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drm/rp1: rp1-dsi: Put all register defines into order
Put particularly the PHY registers into order, bitmasks defined alongside the registers, and Use tabs for indentation. Signed-off-by: Dave Stevenson <[email protected]>
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‎drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c‎

Lines changed: 130 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -15,147 +15,136 @@
1515
#include "rp1_dsi.h"
1616

1717
/* ------------------------------- Synopsis DSI ------------------------ */
18-
#define DSI_VERSION_CFG 0x000
19-
#define DSI_PWR_UP 0x004
20-
#define DSI_CLKMGR_CFG 0x008
21-
#define DSI_DPI_VCID 0x00C
22-
#define DSI_DPI_COLOR_CODING 0x010
23-
#define DSI_DPI_CFG_POL 0x014
24-
#define DSI_DPI_LP_CMD_TIM 0x018
25-
#define DSI_DBI_VCID 0x01C
26-
#define DSI_DBI_CFG 0x020
27-
#define DSI_DBI_PARTITIONING_EN 0x024
28-
#define DSI_DBI_CMDSIZE 0x028
29-
#define DSI_PCKHDL_CFG 0x02C
30-
#define DSI_GEN_VCID 0x030
31-
#define DSI_MODE_CFG 0x034
32-
#define DSI_VID_MODE_CFG 0x038
33-
#define DSI_VID_PKT_SIZE 0x03C
34-
#define DSI_VID_NUM_CHUNKS 0x040
35-
#define DSI_VID_NULL_SIZE 0x044
36-
#define DSI_VID_HSA_TIME 0x048
37-
#define DSI_VID_HBP_TIME 0x04C
38-
#define DSI_VID_HLINE_TIME 0x050
39-
#define DSI_VID_VSA_LINES 0x054
40-
#define DSI_VID_VBP_LINES 0x058
41-
#define DSI_VID_VFP_LINES 0x05C
42-
#define DSI_VID_VACTIVE_LINES 0x060
43-
#define DSI_EDPI_CMD_SIZE 0x064
44-
#define DSI_CMD_MODE_CFG 0x068
45-
#define DSI_GEN_HDR 0x06C
46-
#define DSI_GEN_PLD_DATA 0x070
47-
#define DSI_CMD_PKT_STATUS 0x074
48-
#define DSI_TO_CNT_CFG 0x078
49-
#define DSI_HS_RD_TO_CNT 0x07C
50-
#define DSI_LP_RD_TO_CNT 0x080
51-
#define DSI_HS_WR_TO_CNT 0x084
52-
#define DSI_LP_WR_TO_CNT 0x088
53-
#define DSI_BTA_TO_CNT 0x08C
54-
#define DSI_SDF_3D 0x090
55-
#define DSI_LPCLK_CTRL 0x094
56-
#define DSI_PHY_TMR_LPCLK_CFG 0x098
57-
#define DSI_PHY_TMR_HS2LP_LSB 16
58-
#define DSI_PHY_TMR_LP2HS_LSB 0
59-
#define DSI_PHY_TMR_CFG 0x09C
60-
#define DSI_PHY_TMR_RD_CFG 0x0F4
61-
#define DSI_PHYRSTZ 0x0A0
62-
#define DSI_PHY_IF_CFG 0x0A4
63-
#define DSI_PHY_ULPS_CTRL 0x0A8
64-
#define DSI_PHY_TX_TRIGGERS 0x0AC
65-
#define DSI_PHY_STATUS 0x0B0
66-
67-
#define DSI_PHY_TST_CTRL0 0x0B4
68-
#define DSI_PHY_TST_CTRL1 0x0B8
69-
#define DSI_INT_ST0 0x0BC
70-
#define DSI_INT_ST1 0x0C0
71-
#define DSI_INT_MASK0_CFG 0x0C4
72-
#define DSI_INT_MASK1_CFG 0x0C8
73-
#define DSI_PHY_CAL 0x0CC
74-
#define DSI_HEXP_NPKT_CLR 0x104
75-
#define DSI_HEXP_NPKT_SIZE 0x108
76-
#define DSI_VID_SHADOW_CTRL 0x100
77-
78-
#define DSI_DPI_VCID_ACT 0x10C
79-
#define DSI_DPI_COLOR_CODING_ACT 0x110
80-
#define DSI_DPI_LP_CMD_TIM_ACT 0x118
81-
#define DSI_VID_MODE_CFG_ACT 0x138
82-
#define DSI_VID_PKT_SIZE_ACT 0x13C
83-
#define DSI_VID_NUM_CHUNKS_ACT 0x140
84-
#define DSI_VID_NULL_SIZE_ACT 0x144
85-
#define DSI_VID_HSA_TIME_ACT 0x148
86-
#define DSI_VID_HBP_TIME_ACT 0x14C
87-
#define DSI_VID_HLINE_TIME_ACT 0x150
88-
#define DSI_VID_VSA_LINES_ACT 0x154
89-
#define DSI_VID_VBP_LINES_ACT 0x158
90-
#define DSI_VID_VFP_LINES_ACT 0x15C
91-
#define DSI_VID_VACTIVE_LINES_ACT 0x160
92-
#define DSI_SDF_3D_CFG_ACT 0x190
93-
94-
#define DSI_INT_FORCE0 0x0D8
95-
#define DSI_INT_FORCE1 0x0DC
96-
97-
#define DSI_AUTO_ULPS_MODE 0x0E0
98-
#define DSI_AUTO_ULPS_ENTRY_DELAY 0x0E4
99-
#define DSI_AUTO_ULPS_WAKEUP_TIME 0x0E8
100-
#define DSI_EDPI_ADV_FEATURES 0x0EC
101-
102-
#define DSI_DSC_PARAMETER 0x0F0
103-
104-
/* And some bitfield definitions */
105-
106-
#define DSI_PCKHDL_EOTP_TX_EN BIT(0)
107-
#define DSI_PCKHDL_BTA_EN BIT(2)
108-
109-
#define DSI_VID_MODE_LP_CMD_EN BIT(15)
110-
#define DSI_VID_MODE_FRAME_BTA_ACK_EN BIT(14)
111-
#define DSI_VID_MODE_LP_HFP_EN BIT(13)
112-
#define DSI_VID_MODE_LP_HBP_EN BIT(12)
113-
#define DSI_VID_MODE_LP_VACT_EN BIT(11)
114-
#define DSI_VID_MODE_LP_VFP_EN BIT(10)
115-
#define DSI_VID_MODE_LP_VBP_EN BIT(9)
116-
#define DSI_VID_MODE_LP_VSA_EN BIT(8)
117-
#define DSI_VID_MODE_SYNC_PULSES 0
118-
#define DSI_VID_MODE_SYNC_EVENTS 1
119-
#define DSI_VID_MODE_BURST 2
120-
121-
#define DSI_CMD_MODE_ALL_LP 0x10f7f00
122-
#define DSI_CMD_MODE_ACK_RQST_EN BIT(1)
123-
124-
#define DPHY_PWR_UP_SHUTDOWNZ_LSB 0
125-
#define DPHY_PWR_UP_SHUTDOWNZ_BITS BIT(DPHY_PWR_UP_SHUTDOWNZ_LSB)
126-
127-
#define DPHY_CTRL0_PHY_TESTCLK_LSB 1
128-
#define DPHY_CTRL0_PHY_TESTCLK_BITS BIT(DPHY_CTRL0_PHY_TESTCLK_LSB)
129-
#define DPHY_CTRL0_PHY_TESTCLR_LSB 0
130-
#define DPHY_CTRL0_PHY_TESTCLR_BITS BIT(DPHY_CTRL0_PHY_TESTCLR_LSB)
131-
132-
#define DPHY_CTRL1_PHY_TESTDIN_LSB 0
133-
#define DPHY_CTRL1_PHY_TESTDIN_BITS (0xff << DPHY_CTRL1_PHY_TESTDIN_LSB)
134-
#define DPHY_CTRL1_PHY_TESTDOUT_LSB 8
135-
#define DPHY_CTRL1_PHY_TESTDOUT_BITS (0xff << DPHY_CTRL1_PHY_TESTDOUT_LSB)
136-
#define DPHY_CTRL1_PHY_TESTEN_LSB 16
137-
#define DPHY_CTRL1_PHY_TESTEN_BITS BIT(DPHY_CTRL1_PHY_TESTEN_LSB)
138-
139-
#define DSI_PHYRSTZ_SHUTDOWNZ_LSB 0
140-
#define DSI_PHYRSTZ_SHUTDOWNZ_BITS BIT(DSI_PHYRSTZ_SHUTDOWNZ_LSB)
141-
#define DSI_PHYRSTZ_RSTZ_LSB 1
142-
#define DSI_PHYRSTZ_RSTZ_BITS BIT(DSI_PHYRSTZ_RSTZ_LSB)
143-
#define DSI_PHYRSTZ_ENABLECLK_LSB 2
144-
#define DSI_PHYRSTZ_ENABLECLK_BITS BIT(DSI_PHYRSTZ_ENABLECLK_LSB)
145-
#define DSI_PHYRSTZ_FORCEPLL_LSB 3
146-
#define DSI_PHYRSTZ_FORCEPLL_BITS BIT(DSI_PHYRSTZ_FORCEPLL_LSB)
147-
148-
#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
149-
#define DPHY_PLL_INPUT_DIV_OFFSET 0x17
150-
#define DPHY_PLL_LOOP_DIV_OFFSET 0x18
151-
#define DPHY_PLL_DIV_CTRL_OFFSET 0x19
152-
153-
#define DPHY_PLL_BIAS_OFFSET 0x10
154-
#define DPHY_PLL_BIAS_VCO_RANGE_LSB 3
155-
#define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7)
156-
157-
#define DPHY_PLL_CHARGE_PUMP_OFFSET 0x11
158-
#define DPHY_PLL_LPF_OFFSET 0x12
18+
#define DSI_VERSION_CFG 0x000
19+
#define DSI_PWR_UP 0x004
20+
#define DSI_CLKMGR_CFG 0x008
21+
#define DSI_DPI_VCID 0x00C
22+
#define DSI_DPI_COLOR_CODING 0x010
23+
#define DSI_DPI_CFG_POL 0x014
24+
#define DSI_DPI_LP_CMD_TIM 0x018
25+
#define DSI_DBI_VCID 0x01C
26+
#define DSI_DBI_CFG 0x020
27+
#define DSI_DBI_PARTITIONING_EN 0x024
28+
#define DSI_DBI_CMDSIZE 0x028
29+
#define DSI_PCKHDL_CFG 0x02C
30+
#define DSI_PCKHDL_EOTP_TX_EN BIT(0)
31+
#define DSI_PCKHDL_BTA_EN BIT(2)
32+
#define DSI_GEN_VCID 0x030
33+
#define DSI_MODE_CFG 0x034
34+
#define DSI_VID_MODE_CFG 0x038
35+
#define DSI_VID_MODE_LP_CMD_EN BIT(15)
36+
#define DSI_VID_MODE_FRAME_BTA_ACK_EN BIT(14)
37+
#define DSI_VID_MODE_LP_HFP_EN BIT(13)
38+
#define DSI_VID_MODE_LP_HBP_EN BIT(12)
39+
#define DSI_VID_MODE_LP_VACT_EN BIT(11)
40+
#define DSI_VID_MODE_LP_VFP_EN BIT(10)
41+
#define DSI_VID_MODE_LP_VBP_EN BIT(9)
42+
#define DSI_VID_MODE_LP_VSA_EN BIT(8)
43+
#define DSI_VID_MODE_SYNC_PULSES 0
44+
#define DSI_VID_MODE_SYNC_EVENTS 1
45+
#define DSI_VID_MODE_BURST 2
46+
#define DSI_VID_PKT_SIZE 0x03C
47+
#define DSI_VID_NUM_CHUNKS 0x040
48+
#define DSI_VID_NULL_SIZE 0x044
49+
#define DSI_VID_HSA_TIME 0x048
50+
#define DSI_VID_HBP_TIME 0x04C
51+
#define DSI_VID_HLINE_TIME 0x050
52+
#define DSI_VID_VSA_LINES 0x054
53+
#define DSI_VID_VBP_LINES 0x058
54+
#define DSI_VID_VFP_LINES 0x05C
55+
#define DSI_VID_VACTIVE_LINES 0x060
56+
#define DSI_EDPI_CMD_SIZE 0x064
57+
#define DSI_CMD_MODE_CFG 0x068
58+
#define DSI_CMD_MODE_ALL_LP 0x10f7f00
59+
#define DSI_CMD_MODE_ACK_RQST_EN BIT(1)
60+
#define DSI_GEN_HDR 0x06C
61+
#define DSI_GEN_PLD_DATA 0x070
62+
#define DSI_CMD_PKT_STATUS 0x074
63+
#define DSI_TO_CNT_CFG 0x078
64+
#define DSI_HS_RD_TO_CNT 0x07C
65+
#define DSI_LP_RD_TO_CNT 0x080
66+
#define DSI_HS_WR_TO_CNT 0x084
67+
#define DSI_LP_WR_TO_CNT 0x088
68+
#define DSI_BTA_TO_CNT 0x08C
69+
#define DSI_SDF_3D 0x090
70+
#define DSI_LPCLK_CTRL 0x094
71+
#define DSI_PHY_TMR_LPCLK_CFG 0x098
72+
#define DSI_PHY_TMR_HS2LP_LSB 16
73+
#define DSI_PHY_TMR_LP2HS_LSB 0
74+
#define DSI_PHY_TMR_CFG 0x09C
75+
#define DSI_PHY_TMR_RD_CFG 0x0F4
76+
#define DSI_PHYRSTZ 0x0A0
77+
#define DSI_PHYRSTZ_SHUTDOWNZ_LSB 0
78+
#define DSI_PHYRSTZ_SHUTDOWNZ_BITS BIT(DSI_PHYRSTZ_SHUTDOWNZ_LSB)
79+
#define DSI_PHYRSTZ_RSTZ_LSB 1
80+
#define DSI_PHYRSTZ_RSTZ_BITS BIT(DSI_PHYRSTZ_RSTZ_LSB)
81+
#define DSI_PHYRSTZ_ENABLECLK_LSB 2
82+
#define DSI_PHYRSTZ_ENABLECLK_BITS BIT(DSI_PHYRSTZ_ENABLECLK_LSB)
83+
#define DSI_PHYRSTZ_FORCEPLL_LSB 3
84+
#define DSI_PHYRSTZ_FORCEPLL_BITS BIT(DSI_PHYRSTZ_FORCEPLL_LSB)
85+
#define DSI_PHY_IF_CFG 0x0A4
86+
#define DSI_PHY_ULPS_CTRL 0x0A8
87+
#define DSI_PHY_TX_TRIGGERS 0x0AC
88+
#define DSI_PHY_STATUS 0x0B0
89+
90+
#define DSI_PHY_TST_CTRL0 0x0B4
91+
#define DPHY_CTRL0_PHY_TESTCLK_LSB 1
92+
#define DPHY_CTRL0_PHY_TESTCLK_BITS BIT(DPHY_CTRL0_PHY_TESTCLK_LSB)
93+
#define DPHY_CTRL0_PHY_TESTCLR_LSB 0
94+
#define DPHY_CTRL0_PHY_TESTCLR_BITS BIT(DPHY_CTRL0_PHY_TESTCLR_LSB)
95+
#define DSI_PHY_TST_CTRL1 0x0B8
96+
#define DPHY_CTRL1_PHY_TESTDIN_LSB 0
97+
#define DPHY_CTRL1_PHY_TESTDIN_BITS (0xff << DPHY_CTRL1_PHY_TESTDIN_LSB)
98+
#define DPHY_CTRL1_PHY_TESTDOUT_LSB 8
99+
#define DPHY_CTRL1_PHY_TESTDOUT_BITS (0xff << DPHY_CTRL1_PHY_TESTDOUT_LSB)
100+
#define DPHY_CTRL1_PHY_TESTEN_LSB 16
101+
#define DPHY_CTRL1_PHY_TESTEN_BITS BIT(DPHY_CTRL1_PHY_TESTEN_LSB)
102+
#define DSI_INT_ST0 0x0BC
103+
#define DSI_INT_ST1 0x0C0
104+
#define DSI_INT_MASK0_CFG 0x0C4
105+
#define DSI_INT_MASK1_CFG 0x0C8
106+
#define DSI_PHY_CAL 0x0CC
107+
#define DSI_HEXP_NPKT_CLR 0x104
108+
#define DSI_HEXP_NPKT_SIZE 0x108
109+
#define DSI_VID_SHADOW_CTRL 0x100
110+
111+
#define DSI_DPI_VCID_ACT 0x10C
112+
#define DSI_DPI_COLOR_CODING_ACT 0x110
113+
#define DSI_DPI_LP_CMD_TIM_ACT 0x118
114+
#define DSI_VID_MODE_CFG_ACT 0x138
115+
#define DSI_VID_PKT_SIZE_ACT 0x13C
116+
#define DSI_VID_NUM_CHUNKS_ACT 0x140
117+
#define DSI_VID_NULL_SIZE_ACT 0x144
118+
#define DSI_VID_HSA_TIME_ACT 0x148
119+
#define DSI_VID_HBP_TIME_ACT 0x14C
120+
#define DSI_VID_HLINE_TIME_ACT 0x150
121+
#define DSI_VID_VSA_LINES_ACT 0x154
122+
#define DSI_VID_VBP_LINES_ACT 0x158
123+
#define DSI_VID_VFP_LINES_ACT 0x15C
124+
#define DSI_VID_VACTIVE_LINES_ACT 0x160
125+
#define DSI_SDF_3D_CFG_ACT 0x190
126+
127+
#define DSI_INT_FORCE0 0x0D8
128+
#define DSI_INT_FORCE1 0x0DC
129+
130+
#define DSI_AUTO_ULPS_MODE 0x0E0
131+
#define DSI_AUTO_ULPS_ENTRY_DELAY 0x0E4
132+
#define DSI_AUTO_ULPS_WAKEUP_TIME 0x0E8
133+
#define DSI_EDPI_ADV_FEATURES 0x0EC
134+
135+
#define DSI_DSC_PARAMETER 0x0F0
136+
137+
/* PHY "test and control mode" registers */
138+
#define DPHY_PLL_BIAS_OFFSET 0x10
139+
#define DPHY_PLL_BIAS_VCO_RANGE_LSB 3
140+
#define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7)
141+
#define DPHY_PLL_CHARGE_PUMP_OFFSET 0x11
142+
#define DPHY_PLL_LPF_OFFSET 0x12
143+
#define DPHY_PLL_INPUT_DIV_OFFSET 0x17
144+
#define DPHY_PLL_LOOP_DIV_OFFSET 0x18
145+
#define DPHY_PLL_DIV_CTRL_OFFSET 0x19
146+
#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
147+
159148

160149
#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
161150
#define DSI_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))

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