drm/vc4: Add support for horizontally caled VEC modes

Composite output uses non-square pixels. By allowing horizontally scaled
modes, we can simulate a different pixel clock and thus make it possible
to simulate square pixels at either 4:3 or 16:9 target aspect ratio.

Signed-off-by: Mateusz Kwiatkowski <[email protected]>

Author: Mateusz Kwiatkowski

drivers/gpu/drm/vc4/vc4_vec.c

@@ -687,16 +687,42 @@ static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
 		crtc_state->adjusted_mode.crtc_vtotal /= 2;
 	}
 
-	if (crtc_state->adjusted_mode.crtc_htotal !=
-		    vc4_vec_tv_modes[conn_state->tv.mode].interlaced_mode->htotal ||
-	    crtc_state->adjusted_mode.crtc_hdisplay % 4 != 0 ||
-	    crtc_state->adjusted_mode.crtc_hsync_end -
-		    crtc_state->adjusted_mode.crtc_hsync_start < 1)
+	if (crtc_state->adjusted_mode.hdisplay % 4 != 0 ||
+	    crtc_state->adjusted_mode.hsync_end -
+		    crtc_state->adjusted_mode.hsync_start < 1)
 		return -EINVAL;
 
-	switch (crtc_state->adjusted_mode.crtc_htotal) {
-	case 858:
-		/* 525-line mode */
+	crtc_state->adjusted_mode.htotal =
+		vc4_vec_tv_modes[conn_state->tv.mode].interlaced_mode->htotal;
+	crtc_state->adjusted_mode.hdisplay =
+		DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.hdisplay *
+				  crtc_state->adjusted_mode.htotal,
+				  crtc_state->mode.htotal);
+	crtc_state->adjusted_mode.hsync_start =
+		DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.hsync_start *
+				  crtc_state->adjusted_mode.htotal,
+				  crtc_state->mode.htotal);
+	crtc_state->adjusted_mode.hsync_end =
+		DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.hsync_end *
+				  crtc_state->adjusted_mode.htotal,
+				  crtc_state->mode.htotal);
+	crtc_state->adjusted_mode.clock =
+		DIV_ROUND_CLOSEST(crtc_state->adjusted_mode.clock *
+				  crtc_state->adjusted_mode.htotal,
+				  crtc_state->mode.htotal);
+	if (crtc_state->adjusted_mode.hsync_end -
+	    crtc_state->adjusted_mode.hsync_start < 1)
+		crtc_state->adjusted_mode.hsync_end =
+			crtc_state->adjusted_mode.hsync_start + 1;
+
+	crtc_state->adjusted_mode.crtc_clock = crtc_state->adjusted_mode.clock;
+	crtc_state->adjusted_mode.crtc_hdisplay = crtc_state->adjusted_mode.hdisplay;
+	crtc_state->adjusted_mode.crtc_hsync_start = crtc_state->adjusted_mode.hsync_start;
+	crtc_state->adjusted_mode.crtc_hsync_end = crtc_state->adjusted_mode.hsync_end;
+	crtc_state->adjusted_mode.crtc_htotal = crtc_state->adjusted_mode.htotal;
+
+	switch (vc4_vec_tv_modes[conn_state->tv.mode].interlaced_mode->vtotal) {
+	case 525:
 		if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 		    crtc_state->adjusted_mode.crtc_vdisplay > 253 ||
 		    crtc_state->adjusted_mode.crtc_vsync_start -
@@ -724,8 +750,7 @@ static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
 
 		break;
 
-	case 864:
-		/* 625-line mode */
+	case 625:
 		if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 		    crtc_state->adjusted_mode.crtc_vdisplay > 305 ||
 		    crtc_state->adjusted_mode.crtc_vsync_start -