[mmc: sdhci-brcmstb] Verify DDR200 bus mode

[mirh]

Describe the bug

So.. RPi5 finally supports the full UHS-I, though much as anywhere else it is plateauing at about 90MB/s (SDR104).
This isn't that bad and I can see why it's good enough not to need wasting space for other pcb lines, but in the years since the standard was defined cheats have been designed to keep it cheap yet go faster.

Sandisk and others (with samsung actually being the recommended one at least to prototype) have made these sdcards with a firmware that can run at emmc frequencies, and at least on the tegra X1 controller where it has been re-implemented you can get +50% improvements easy.

CTCaer/switch-l4t-kernel-4.9@c0f1c91
CTCaer/switch-l4t-kernel-4.9@92edf31
Architectural details specific to that are covered here, including a creative workaround for apparent hardware(?) constraints which forced them to go through manual tuning of the normal DDR50 mode.
BCM2712 is certainly more modern given it could even theoretically support sdexpress, but go figure if this means "better potential" (like perhaps even DDR225) or worse.

Steps to reproduce the behaviour

Benchmark a micro sd card.

Device (s)

Raspberry Pi 5

System

Feature request.

Logs

No response

Additional context

No response

[P33M]

This isn't a bug report, it's a feature request.

We are aware of this "bonus speed" of certain SD cards. It is non-standard, there is no publicly available information on the required signal timings, and there is no guarantee that across process and temperature variation there will be a data sampling window wide enough for BCM2712's SD PHY to deliver reliable data transport. I have asked the question of our suppliers' FAEs but no response has yet been forthcoming.

So there won't be any effort spent on implementing this unless the physical layer questions are answered first.