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Added vivado board files for numato Narvi board
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‎FPGA/numatoVivadoBSP/Narvi/1.0/board.xml‎

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<board schema_version="2.0" vendor="numato.com" name="Narvi" display_name="Narvi" url="www.numato.com/" preset_file="preset.xml" >
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<images>
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<image name="" display_name="Narvi Spartan7 BOARD" sub_type="board">
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<description>Narvi Spartan7 Board File Image</description>
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</image>
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</images>
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<compatible_board_revisions>
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<revision id="0">1.0</revision>
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</compatible_board_revisions>
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<file_version>1.0</file_version>
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<description>Narvi</description>
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<components>
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<component name="part0" display_name="Narvi" type="fpga" part_name="xc7s50csga324-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.numato.com/">
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<interfaces>
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<interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
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<description>DDR3 board interface.</description>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
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</preferred_ips>
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</interface>
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<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
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<description>Reset Button</description>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="RESET" physical_port="reset" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="reset"/>
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</pin_maps>
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</port_map>
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</port_maps>
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<parameters>
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<parameter name="rst_polarity" value="1" />
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</parameters>
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</interface>
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<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
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<parameters>
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<parameter name="frequency" value="100000000"/>
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</parameters>
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="clk" physical_port="clk" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="clk"/>
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</pin_maps>
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</port_map>
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</port_maps>
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<parameters>
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<parameter name="frequency" value="100000000" />
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</parameters>
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</interface>
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<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
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<preferred_ips>
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<preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
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</preferred_ips>
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<port_maps>
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<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
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<pin_maps>
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<pin_map port_index="0" component_pin="usb_uart_txd"/>
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</pin_maps>
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</port_map>
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<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
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<pin_maps>
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<pin_map port_index="0" component_pin="usb_uart_rxd"/>
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</pin_maps>
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</port_map>
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</port_maps>
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</interface>
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</interfaces>
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</component>
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<component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
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<description>DDR3 memory</description>
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<parameters>
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<parameter name="ddr_type" value="ddr3"/>
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<parameter name="size" value="256MB"/>
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</parameters>
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</component>
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<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
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<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
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</component>
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<component name="reset" display_name="FPGA Reset" type="chip" sub_type="system_reset" major_group="Reset">
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<description>CPU Reset, Active High</description>
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</component>
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<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
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<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
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</component>
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</components>
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<jtag_chains>
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<jtag_chain name="chain1">
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<position name="0" component="part0"/>
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</jtag_chain>
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</jtag_chains>
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<connections>
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<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
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<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
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</connection>
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<connection name="part0_reset" component1="part0" component2="reset">
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<connection_map name="part0_reset_1" c1_st_index="1" c1_end_index="1" c2_st_index="0" c2_end_index="0"/>
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</connection>
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<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
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<connection_map name="part0_usb_uart_1" c1_st_index="2" c1_end_index="3" c2_st_index="0" c2_end_index="1"/>
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</connection>
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</connections>
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</board>

‎FPGA/numatoVivadoBSP/Narvi/1.0/mig.prj‎

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<?xml version='1.0' encoding='UTF-8'?>
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<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
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<Project NoOfControllers="1" >
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<ModuleName>design_1_mig_7series_0_0</ModuleName>
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<dci_inouts_inputs>1</dci_inouts_inputs>
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<dci_inputs>1</dci_inputs>
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<Debug_En>OFF</Debug_En>
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<DataDepth_En>1024</DataDepth_En>
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<LowPower_En>ON</LowPower_En>
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<XADC_En>Enabled</XADC_En>
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<TargetFPGA>xc7s50-csga324/-1</TargetFPGA>
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<Version>4.1</Version>
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<SystemClock>No Buffer</SystemClock>
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<ReferenceClock>Use System Clock</ReferenceClock>
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<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
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<BankSelectionFlag>FALSE</BankSelectionFlag>
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<InternalVref>1</InternalVref>
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<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
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<dci_cascade>0</dci_cascade>
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<Controller number="0" >
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<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX-125</MemoryDevice>
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<TimePeriod>3000</TimePeriod>
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<VccAuxIO>1.8V</VccAuxIO>
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<PHYRatio>4:1</PHYRatio>
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<InputClkFreq>205.128</InputClkFreq>
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<UIExtraClocks>0</UIExtraClocks>
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<MMCM_VCO>666</MMCM_VCO>
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<MMCMClkOut0> 1.000</MMCMClkOut0>
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<MMCMClkOut1>1</MMCMClkOut1>
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<MMCMClkOut2>1</MMCMClkOut2>
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<MMCMClkOut3>1</MMCMClkOut3>
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<MMCMClkOut4>1</MMCMClkOut4>
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<DataWidth>16</DataWidth>
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<DeepMemory>1</DeepMemory>
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<DataMask>1</DataMask>
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<ECC>Disabled</ECC>
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<Ordering>Normal</Ordering>
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<BankMachineCnt>4</BankMachineCnt>
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<CustomPart></CustomPart>
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<NewPartName></NewPartName>
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<RowAddress>14</RowAddress>
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<ColAddress>10</ColAddress>
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<BankAddress>3</BankAddress>
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<MemoryVoltage>1.5V</MemoryVoltage>
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<C0_MEM_SIZE>268435456</C0_MEM_SIZE>
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<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
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<PinSelection>
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P5" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U1" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T1" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T2" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R3" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T3" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R4" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V4" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V5" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V2" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V3" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U2" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U3" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T6" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V6" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V7" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R7" SLEW="" name="ddr3_cas_n" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="T4" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="R5" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U6" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U7" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L4" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N4" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P2" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P1" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R2" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K2" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L6" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L5" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M6" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="L1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="N2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="K1" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="N3" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P7" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T5" SLEW="" name="ddr3_ras_n" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="M5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
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<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R6" SLEW="" name="ddr3_we_n" IN_TERM="" />
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</PinSelection>
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<System_Control>
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<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
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<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
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<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
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</System_Control>
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<TimingParameters>
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<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="160" trp="13.75" tras="35" trcd="13.75" />
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</TimingParameters>
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<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
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<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
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<mrCasLatency name="CAS Latency" >5</mrCasLatency>
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<mrMode name="Mode" >Normal</mrMode>
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<mrDllReset name="DLL Reset" >No</mrDllReset>
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<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
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<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
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<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
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<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
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<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
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<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
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<emrPosted name="Additive Latency (AL)" >0</emrPosted>
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<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
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<emrDQS name="TDQS enable" >Enabled</emrDQS>
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<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
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<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
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<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
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<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
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<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
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<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
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<PortInterface>AXI</PortInterface>
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<AXIParameters>
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<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
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<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
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<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
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<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
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<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
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</AXIParameters>
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</Controller>
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</Project>

‎FPGA/numatoVivadoBSP/Narvi/1.0/part0_pins.xml‎

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<part_info part_name="xc7s50csga324-1">
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<pins>
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<pin index="0" name ="clk" iostandard="LVCMOS33" loc="D14"/>
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<pin index="1" name ="reset" iostandard="LVCMOS33" loc="T14"/>
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<pin index="2" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="L13"/>
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<pin index="3" name ="usb_uart_txd" iostandard="LVCMOS33" loc="N13"/>
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</pins>
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</part_info>

‎FPGA/numatoVivadoBSP/Narvi/1.0/preset.xml‎

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<ip_presets schema="1.0">
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<ip_preset preset_proc_name="ddr3_sdram_preset">
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<ip vendor="xilinx.com" library="ip" name="mig_7series">
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<user_parameters>
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<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
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</user_parameters>
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</ip>
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</ip_preset>
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<ip_preset preset_proc_name="uart_preset">
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<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
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<user_parameters>
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<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
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<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
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</user_parameters>
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</ip>
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<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
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<user_parameters>
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<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
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<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
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</user_parameters>
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</ip>
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</ip_preset>
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<ip_preset preset_proc_name="sys_clock_preset">
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<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
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<user_parameters>
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<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
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<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
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<user_parameter name="CONFIG.RESET_TYPE" value="Active Low"/>
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<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
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</user_parameters>
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</ip>
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<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
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<user_parameters>
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<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
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<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
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<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
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<user_parameter name="CONFIG.RESET_TYPE" value="Active Low"/>
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<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
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</user_parameters>
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</ip>
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</ip_preset>
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</ip_presets>

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