Skip to content

Commit 9069210

Browse files
rohit-numatorohit-numato
authored
Merge pull request numato#16 from Sridhar-Numato/master
Add AC97AudioExpansionModule demo project for skoll
2 parents 85b3dfd + e3ee3d7 commit 9069210

File tree

5 files changed

+358
-1
lines changed

5 files changed

+358
-1
lines changed

‎FPGA/ExpansionModules/AC97Audio/LM4550AudioExpansionModule.xpr‎

Lines changed: 110 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,110 @@
1+
<?xml version="1.0" encoding="UTF-8"?>
2+
<!-- Product Version: Vivado v2015.2 (64-bit) -->
3+
<!-- -->
4+
<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -->
5+
6+
<Project Version="7" Minor="5" Path="">
7+
<DefaultLaunch Dir="$PRUNDIR"/>
8+
<Configuration>
9+
<Option Name="Id" Val="ae8270595da24391adfd8349a251d131"/>
10+
<Option Name="Part" Val="xc7k70tfbg484-1"/>
11+
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
12+
<Option Name="BoardPart" Val=""/>
13+
<Option Name="ActiveSimSet" Val="sim_1"/>
14+
<Option Name="DefaultLib" Val="xil_defaultlib"/>
15+
<Option Name="EnableCoreContainer" Val="FALSE"/>
16+
<Option Name="EnableCoreContainerForIPI" Val="FALSE"/>
17+
</Configuration>
18+
<FileSets Version="1" Minor="31">
19+
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
20+
<Filter Type="Srcs"/>
21+
<File Path="$PPRDIR/src/series7/AC97Controller.v">
22+
<FileInfo>
23+
<Attr Name="UsedIn" Val="synthesis"/>
24+
<Attr Name="UsedIn" Val="implementation"/>
25+
<Attr Name="UsedIn" Val="simulation"/>
26+
</FileInfo>
27+
</File>
28+
<File Path="$PPRDIR/src/series7/LM4550AudioExpansionModule.v">
29+
<FileInfo>
30+
<Attr Name="UsedIn" Val="synthesis"/>
31+
<Attr Name="UsedIn" Val="implementation"/>
32+
<Attr Name="UsedIn" Val="simulation"/>
33+
</FileInfo>
34+
</File>
35+
<Config>
36+
<Option Name="DesignMode" Val="RTL"/>
37+
<Option Name="TopModule" Val="LM4550AudioExpansionModule"/>
38+
<Option Name="TopAutoSet" Val="TRUE"/>
39+
</Config>
40+
</FileSet>
41+
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
42+
<Filter Type="Constrs"/>
43+
<File Path="$PPRDIR/xdc/skoll.xdc">
44+
<FileInfo>
45+
<Attr Name="UsedIn" Val="synthesis"/>
46+
<Attr Name="UsedIn" Val="implementation"/>
47+
</FileInfo>
48+
</File>
49+
<Config>
50+
<Option Name="ConstrsType" Val="XDC"/>
51+
</Config>
52+
</FileSet>
53+
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
54+
<Filter Type="Srcs"/>
55+
<Config>
56+
<Option Name="DesignMode" Val="RTL"/>
57+
<Option Name="TopModule" Val="LM4550AudioExpansionModule"/>
58+
<Option Name="TopLib" Val="xil_defaultlib"/>
59+
<Option Name="TopAutoSet" Val="TRUE"/>
60+
<Option Name="SrcSet" Val="sources_1"/>
61+
</Config>
62+
</FileSet>
63+
</FileSets>
64+
<Simulators>
65+
<Simulator Name="XSim">
66+
<Option Name="Description" Val="Vivado Simulator"/>
67+
<Option Name="CompiledLib" Val="0"/>
68+
</Simulator>
69+
<Simulator Name="ModelSim">
70+
<Option Name="Description" Val="ModelSim Simulator"/>
71+
</Simulator>
72+
<Simulator Name="Questa">
73+
<Option Name="Description" Val="Questa Advanced Simulator"/>
74+
</Simulator>
75+
<Simulator Name="IES">
76+
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
77+
</Simulator>
78+
<Simulator Name="VCS">
79+
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
80+
</Simulator>
81+
<Simulator Name="Riviera">
82+
<Option Name="Description" Val="Riviera-PRO Simulator"/>
83+
</Simulator>
84+
<Simulator Name="ActiveHDL">
85+
<Option Name="Description" Val="Active-HDL Simulator"/>
86+
</Simulator>
87+
</Simulators>
88+
<Runs Version="1" Minor="9">
89+
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k70tfbg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
90+
<Strategy Version="1" Minor="2">
91+
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
92+
<Step Id="synth_design"/>
93+
</Strategy>
94+
</Run>
95+
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k70tfbg484-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
96+
<Strategy Version="1" Minor="2">
97+
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
98+
<Step Id="init_design"/>
99+
<Step Id="opt_design"/>
100+
<Step Id="power_opt_design"/>
101+
<Step Id="place_design"/>
102+
<Step Id="post_place_power_opt_design"/>
103+
<Step Id="phys_opt_design"/>
104+
<Step Id="route_design"/>
105+
<Step Id="post_route_phys_opt_design"/>
106+
<Step Id="write_bitstream"/>
107+
</Strategy>
108+
</Run>
109+
</Runs>
110+
</Project>

‎FPGA/ExpansionModules/AC97Audio/Readme.txt‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
12
LM4550 AC'97 Stereo Audio Codec Expansion Module demo code
23
Numato Lab
34
http://www.numato.com
@@ -24,6 +25,9 @@ AC'97 Stereo Audio Codec Expansion Module demo for the following boards.
2425
6. Waxwing Spartan 6 FPGA Development Board
2526
http://numato.com/waxwing-spartan-6-fpga-development-board.html
2627

28+
7. Skoll Kintex 7 FPGA Development Board
29+
http://numato.com/skoll-kintex-7-fpga-development-board/
30+
2731
The LM4550 AC'97 Stereo Audio Codec Expansion Module used to test this code is available at
2832
http://numato.com/fpga-boards/expansion-modules/lm4550-ac97-stereo-audio-codec-expansion-module.html
2933

@@ -57,6 +61,12 @@ ISE Webpack software and license is available for free at http://www.xilinx.com
5761
When the build finishes successfully a .bin and a .bit file should be created in
5862
the folder name binary.
5963

64+
----------------------------------------------------------------------------------------------------------------
65+
Kintex 7 Series:
66+
67+
There is a "LM4550AudioExpansionModule.xpr" vivado project file. Just open it by double
68+
clicking. By default the project is configured for Skoll. Click "Generate Bitstream"
69+
and choose Yes in any subsequent dialog windows.
6070
----------------------------------------------------------------------------------------------------------------
6171
Sr No. Numato Lab's FPGA Board Header Used
6272

@@ -67,6 +77,7 @@ Sr No. Numato Lab's FPGA Board Header Used
6777
5 Saturn LX45** P10
6878
6 Waxwing Carrier P5
6979
7 Waxwing Dev Board P4
80+
8 Skoll(IO Expansion on P5) P12-P1
7081

7182
* Mimas Expansion Connector connected to Header P1 of Mimas.
72-
** Saturn Expansion Connector connected to Header P2 of Saturn Spartan 6 Development Board.
83+
** Saturn Expansion Connector connected to Header P2 of Saturn Spartan 6 Development Board.

‎FPGA/ExpansionModules/AC97Audio/src/series7/AC97Controller.v‎

Lines changed: 129 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,129 @@
1+
`timescale 1ns / 1ps
2+
3+
module AC97Controller
4+
// Parameter declared to control the volume.
5+
#(parameter MasterVolume = 5'd11,
6+
HPVolume = 5'd11,
7+
LineInVolume = 5'd11
8+
)(
9+
// Input from the AC97 Audio module and command module.
10+
input AC97SDI,
11+
input AC97BitClock,
12+
input [19:0] Register,
13+
input [19:0] command,
14+
input validate,
15+
16+
// Output for the AC97 Audio module.
17+
output reg AC97SDO,
18+
output reg done,
19+
output reg AC97Sync
20+
);
21+
22+
// Register and wire used for internal purpose.
23+
reg [7:0] counter;
24+
reg [3:0] f_cnt;
25+
reg done;
26+
reg state;
27+
reg previous_done;
28+
reg [23:0] cmd;
29+
30+
wire [4:0] HP_vol;
31+
wire [4:0] Master_vol;
32+
wire [4:0] LineIn_vol;
33+
34+
// Volume control, more the value lesser will be the attenuation so the volume will be more.
35+
assign HP_vol = 31-HPVolume;
36+
assign LineIn_vol = 31-LineInVolume;
37+
assign Master_vol = 31-MasterVolume;
38+
39+
//initial conditions for resting all the internal signals and also the AC97-Serial data out and Synchronization signal pins
40+
initial
41+
begin
42+
done <= 1'b1;
43+
AC97SDO <= 1'b0;
44+
AC97Sync <= 1'b0;
45+
counter <= 8'h00;
46+
f_cnt <=4'h0;
47+
done <=1'b0;
48+
previous_done <=1'b0;
49+
state <=4'h0;
50+
end
51+
52+
// Monitor Bit clock.
53+
always @(posedge AC97BitClock)
54+
begin
55+
// Validate the frame , register and the command for LM4550
56+
if ((counter >= 0) && (counter <= 15))
57+
case (counter[3:0])
58+
4'h0: AC97SDO <= 1'b1;
59+
4'h1: AC97SDO <= done;
60+
4'h2: AC97SDO <= done;
61+
default: AC97SDO <= 1'b0;
62+
endcase
63+
// Serially output the register contained.
64+
else if ((counter >= 16) && (counter <= 35))
65+
AC97SDO <= Register[35-counter];
66+
67+
// Serially output the command for that register.
68+
else if ((counter >= 36) && (counter <= 55))
69+
AC97SDO <= command[55-counter];
70+
71+
// When done PULLDOWN the SDO line
72+
else
73+
AC97SDO <= 1'b0;
74+
75+
// Generate the Sync signal for AC97 at 48 KHz and done signal for fetching next command.
76+
if (counter == 255)
77+
begin
78+
AC97Sync <= 1'b1;
79+
f_cnt<=f_cnt+1;
80+
end
81+
else if (counter == 128)
82+
begin
83+
done <= 1'b1;
84+
end
85+
else if (counter == 15)
86+
begin
87+
AC97Sync <= 1'b0;
88+
end
89+
else if (counter == 2)
90+
begin
91+
done <= 1'b0;
92+
end
93+
counter <= counter+1;
94+
end
95+
96+
//Monitoring the Frame count signal
97+
always @(f_cnt)
98+
begin
99+
// verify whether the all the command is transferred serially to LM4550
100+
if (done && (!previous_done))
101+
begin
102+
previous_done = done;
103+
end
104+
case (f_cnt)
105+
4'h0:
106+
begin
107+
cmd = {8'h02,3'b000,Master_vol,3'b000,Master_vol}; // Control the Master Volume level
108+
end
109+
4'h1:
110+
begin
111+
cmd = {8'h04,3'b000,HP_vol,3'b000,HP_vol}; // Control the volume for the Headphone
112+
end
113+
4'h2:
114+
begin
115+
cmd ={8'h10,3'b000,5'b00000,3'b000,5'b00000}; // Control the volume for Line-in.
116+
end
117+
default:
118+
begin
119+
cmd = 24'hFC_0000; // Read vendor ID
120+
end
121+
endcase
122+
end
123+
124+
// Load the value of Register and the command for the register.
125+
assign Register = {cmd[23:16],12'h000};
126+
assign command = {cmd[15:0],4'h0};
127+
128+
129+
endmodule

‎FPGA/ExpansionModules/AC97Audio/src/series7/LM4550AudioExpansionModule.v‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
`timescale 1ns / 1ps
2+
//////////////////////////////////////////////////////////////////////////////////
3+
// LM4550 Audio Expansion module demo code
4+
// Numato Lab
5+
// http://www.numato.com
6+
// http://www.numato.cc
7+
//////////////////////////////////////////////////////////////////////////////////
8+
module LM4550AudioExpansionModule
9+
// Parameter define to control the volume. More the value more will be the volume.
10+
#(parameter MasterVolume = 5'd22,
11+
HPVolume = 5'd22,
12+
LineInVolume = 5'd22
13+
)
14+
(
15+
// Assume the input clock of 100 MHz with active high reset.
16+
input CLK,
17+
//Interface to LM4550 AC97 CODEC
18+
input AC97SDI, // Serial data line from LM4550 Audio Expansion module.
19+
input AC97BitClock, // Clock from LM4550 Audio Expansion Module. (12.288 MHz)
20+
output reg AC97Rstn, // Active Low reset for LM4550 Audio Expansion Module.
21+
output AC97SDO, // Serial data to LM4550 Audio Expansion Module.
22+
output AC97Sync // Sync signal for LM4550 Audio Expansion Module.(48 KHz)
23+
);
24+
25+
26+
// Implementation:
27+
// LM4550 Audio Expansion module provide high quality sample rate Conversion from 4 kHz to 48kHz in 1 Hz increments.
28+
// It is boarded with two input namely Line-in and Mic-in and two output Headphone out and Line-out. It has the crystal
29+
// of frequency 24.576 MHz which gives the Bit clock of 12.288 MHz. This clock along with the Sync signal is use to synchronize
30+
// the data flow from and to the module.For the purpose of initializing LM4550 command are passed to the register. The command
31+
// with register is better explained in national Semiconductor datasheet for LM4550.
32+
33+
// Register and wire are used for internal purpose.
34+
reg [7:0] rst_count;
35+
wire [19:0] Register;
36+
wire [19:0] command;
37+
wire validate;
38+
wire done;
39+
wire [3:0] f_cnt;
40+
41+
42+
//initial conditions for reseting the AC97Code reset pin and rst_count for calculating the bit count
43+
initial
44+
begin
45+
AC97Rstn = 1'b0;
46+
rst_count = 0;
47+
end
48+
// Monitor input CLK signal. Whenever the CLK is triggered wait for
49+
// 1us or more before the command are send to LM4550.
50+
always @(posedge CLK)
51+
begin
52+
if (rst_count == 255)
53+
AC97Rstn = 1'b1;
54+
else
55+
rst_count = rst_count + 1;
56+
end
57+
58+
59+
// Instantiate the Controller which controls the flow of data from and to the module.
60+
AC97Controller controller(
61+
.AC97SDI(AC97SDI),
62+
.AC97BitClock(AC97BitClock),
63+
.Register(Register),
64+
.command(command),
65+
.validate(validate),
66+
.AC97SDO(AC97SDO),
67+
.done(done),
68+
.AC97Sync(AC97Sync)
69+
);
70+
71+
72+
endmodule
73+

‎FPGA/ExpansionModules/AC97Audio/xdc/skoll.xdc‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# Module is connected to Header P6 of saturn expansion modle.
2+
#
3+
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}];
4+
set_property PACKAGE_PIN E11 [get_ports {CLK}]; # Sch=CLK1
5+
set_property SLEW FAST [get_ports {CLK}]
6+
7+
8+
set_property PACKAGE_PIN U17 [get_ports {AC97SDI}]; #IO_L6P_T0_13 Sch=GPIO-119
9+
set_property IOSTANDARD LVCMOS33 [get_ports {AC97SDI}];
10+
set_property SLEW FAST [get_ports {AC97SDI}]
11+
set_property DRIVE 8 [get_ports {AC97SDI}]
12+
13+
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {AC97BitClock}]
14+
set_property PACKAGE_PIN V18 [get_ports {AC97BitClock}]; #IO_L6N_T0_VREF_13 Sch=GPIO-118
15+
set_property IOSTANDARD LVCMOS33 [get_ports {AC97BitClock}];
16+
set_property SLEW FAST [get_ports {AC97BitClock}]
17+
set_property DRIVE 8 [get_ports {AC97BitClock}]
18+
19+
set_property PACKAGE_PIN AA21 [get_ports {AC97Rstn}]; #IO_L12P_T1_MRCC_13 Sch=GPIO-121
20+
set_property IOSTANDARD LVCMOS33 [get_ports {AC97Rstn}];
21+
set_property SLEW FAST [get_ports {AC97Rstn}]
22+
set_property DRIVE 8 [get_ports {AC97Rstn}]
23+
24+
set_property PACKAGE_PIN U18 [get_ports {AC97SDO}]; #IO_L24N_T3_A00_D16_14 Sch=GPIO-122
25+
set_property IOSTANDARD LVCMOS33 [get_ports {AC97SDO}];
26+
set_property SLEW FAST [get_ports {AC97SDO}]
27+
set_property DRIVE 8 [get_ports {AC97SDO}]
28+
29+
set_property PACKAGE_PIN AB22 [get_ports {AC97Sync}]; #IO_L12N_T1_MRCC_13 Sch=GPIO-120
30+
set_property IOSTANDARD LVCMOS33 [get_ports {AC97Sync}];
31+
set_property SLEW FAST [get_ports {AC97Sync}]
32+
set_property DRIVE 8 [get_ports {AC97Sync}]
33+
34+

0 commit comments

Comments
 (0)