8202379: ARM32 is broken after JDK-8201543 (Modularize C1 GC barriers)

Reviewed-by: aph, eosterlund

Author: shipilev

src/hotspot/cpu/arm/c1_LIRGenerator_arm.cpp

@@ -375,32 +375,17 @@ LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,
 }
 
 
-LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,
-                                              BasicType type, bool needs_card_mark) {
+LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr, BasicType type) {
   int base_offset = arrayOopDesc::base_offset_in_bytes(type);
   int elem_size = type2aelembytes(type);
 
   if (index_opr->is_constant()) {
     int offset = base_offset + index_opr->as_constant_ptr()->as_jint() * elem_size;
-    if (needs_card_mark) {
-      LIR_Opr base_opr = new_pointer_register();
-      add_large_constant(array_opr, offset, base_opr);
-      return new LIR_Address(base_opr, (intx)0, type);
-    } else {
-      return generate_address(array_opr, offset, type);
-    }
+    return generate_address(array_opr, offset, type);
   } else {
     assert(index_opr->is_register(), "must be");
     int scale = exact_log2(elem_size);
-    if (needs_card_mark) {
-      LIR_Opr base_opr = new_pointer_register();
-      LIR_Address* addr = make_address(base_opr, index_opr, (LIR_Address::Scale)scale, type);
-      __ add(array_opr, LIR_OprFact::intptrConst(base_offset), base_opr);
-      __ add(base_opr, LIR_OprFact::address(addr), base_opr); // add with shifted/extended register
-      return new LIR_Address(base_opr, type);
-    } else {
-      return generate_address(array_opr, index_opr, scale, base_offset, type);
-    }
+    return generate_address(array_opr, index_opr, scale, base_offset, type);
   }
 }
 
@@ -1024,7 +1009,7 @@ LIR_Opr LIRGenerator::atomic_xchg(BasicType type, LIR_Opr addr, LIRItem& value)
   value.load_item();
   assert(type == T_INT || is_oop LP64_ONLY( || type == T_LONG ), "unexpected type");
   LIR_Opr tmp = (UseCompressedOops && is_oop) ? new_pointer_register() : LIR_OprFact::illegalOpr;
-  __ xchg(addr_ptr, data, dst, tmp);
+  __ xchg(addr, value.result(), result, tmp);
   return result;
 }
 

src/hotspot/cpu/arm/c1_Runtime1_arm.cpp

@@ -352,11 +352,11 @@ static void restore_live_registers_without_return(StubAssembler* sasm, bool rest
 }
 
 void StubAssembler::save_live_registers() {
-  save_live_registers(this);
+  ::save_live_registers(this);
 }
 
 void StubAssembler::restore_live_registers_without_return() {
-  restore_live_registers_without_return(this);
+  ::restore_live_registers_without_return(this);
 }
 
 void Runtime1::initialize_pd() {

src/hotspot/cpu/arm/gc/g1/g1BarrierSetAssembler_arm.cpp

@@ -26,6 +26,7 @@
 #include "asm/macroAssembler.inline.hpp"
 #include "gc/g1/g1BarrierSet.hpp"
 #include "gc/g1/g1BarrierSetAssembler.hpp"
+#include "gc/g1/g1ThreadLocalData.hpp"
 #include "gc/g1/g1CardTable.hpp"
 #include "gc/g1/heapRegion.hpp"
 #include "interpreter/interp_masm.hpp"
@@ -175,15 +176,7 @@ void G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler*
   // Input:
   // - pre_val pushed on the stack
 
-  __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
-
-  BarrierSet* bs = BarrierSet::barrier_set();
-  if (bs->kind() != BarrierSet::G1BarrierSet) {
-    __ mov(R0, (int)id);
-    __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
-    __ should_not_reach_here();
-    break;
-  }
+  __ set_info("g1_pre_barrier_slow_id", false);
 
   // save at least the registers that need saving if the runtime is called
 #ifdef AARCH64
@@ -251,15 +244,7 @@ void G1BarrierSetAssembler::generate_c1_post_barrier_runtime_stub(StubAssembler*
   // Input:
   // - store_addr, pushed on the stack
 
-  __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
-
-  BarrierSet* bs = BarrierSet::barrier_set();
-  if (bs->kind() != BarrierSet::G1BarrierSet) {
-    __ mov(R0, (int)id);
-    __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
-    __ should_not_reach_here();
-    break;
-  }
+  __ set_info("g1_post_barrier_slow_id", false);
 
   Label done;
   Label recheck;

src/hotspot/cpu/arm/gc/g1/g1BarrierSetAssembler_arm.hpp

@@ -42,6 +42,7 @@ class G1BarrierSetAssembler: public ModRefBarrierSetAssembler {
                                         Register addr, Register count, Register tmp);
 
 #ifdef COMPILER1
+public:
   void gen_pre_barrier_stub(LIR_Assembler* ce, G1PreBarrierStub* stub);
   void gen_post_barrier_stub(LIR_Assembler* ce, G1PostBarrierStub* stub);
 

src/hotspot/share/c1/c1_LIRGenerator.hpp

@@ -302,6 +302,10 @@ class LIRGenerator: public InstructionVisitor, public BlockClosure {
   LIR_Opr atomic_xchg(BasicType type, LIR_Opr addr, LIRItem& new_value);
   LIR_Opr atomic_add(BasicType type, LIR_Opr addr, LIRItem& new_value);
 
+#ifdef CARDTABLEBARRIERSET_POST_BARRIER_HELPER
+  virtual void CardTableBarrierSet_post_barrier_helper(LIR_OprDesc* addr, LIR_Const* card_table_base);
+#endif
+
   // specific implementations
   void array_store_check(LIR_Opr value, LIR_Opr array, CodeEmitInfo* store_check_info, ciMethod* profiled_method, int profiled_bci);