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‎endec8b10b/sim/Sim8b10b.do‎

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vlog ../src/mEnc8b10bMem.v
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vlog ../src/mDec8b10bMem.v
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vlog m8b10bEndecTestbench.v
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‎endec8b10b/sim/Veritil.v‎

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/*
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Include this file after module
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*/
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integer ErrorCnt;
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integer ErrorCode;
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initial begin
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ErrorCnt=0;
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ErrorCode=0;
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end
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`define CheckE(Signal,Value,SignalName) if(Signal!==Value) begin \
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$display("E@(%d): expect %x, actual %x (%s,%s,%d)",$time,Value,Signal,SignalName,`__FILE__,`__LINE__); \
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ErrorCnt=ErrorCnt+1;\
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end
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`define CheckF(Signal,Value,SignalName) if(Signal!==Value) begin \
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$display("F@(%d): expect %x, actual %x (%s,%s,%d)",$time,Value,Signal,SignalName,`__FILE__,`__LINE__); \
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$stop(1);\
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end
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`define CheckW(Signal,Value,SignalName) if(Signal!==Value) begin \
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$display("W@(%d): expect %x, actual %x (%s,%s,%d)",$time,Value,Signal,SignalName,`__FILE__,`__LINE__); \
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end
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`define WaitTil(Signal,Value,Clk,Message) while(Signal!==Value) begin @(posedge Clk);#0.001;end \
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$display(Message);
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`define WaitTilRise(Signal) @(posedge Signal);#0.001;
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`define WaitTilRall(Signal) @(negedge Signal);#0.001;
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‎endec8b10b/sim/m8b10bEndecTestbench.v‎

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`timescale 1ns/10ps
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module m8b10bEndecTestbench;
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`include "Veritil.v"
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wire w_Clk;
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reg [7:0] r8_DataIn;
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reg r_Kin;
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wire [9:0] w10_DataOut;
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reg r_ARst_L;
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wire w_Rd;
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wire [7:0] w8_DecDataOut;
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wire w_Kout;
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reg r_ForceParity,r_Disparity;
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wire w_Err;
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mClkGen u0ClkGen(w_Clk);
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mEnc8b10bMem u0Enc8b10bMem(
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.i8_Din (r8_DataIn),
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.i_Kin (r_Kin),
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.i_ForceDisparity (r_ForceParity),
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.i_Disparity (r_Disparity), //1 positive, 0 is negative
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.o10_Dout (w10_DataOut),
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.o_Rd (w_Rd),
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.o_KErr (w_KErr),
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.i_Clk (w_Clk),
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.i_ARst_L (r_ARst_L));
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mDec8b10bMem u0Dec8b10bMem(
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.o8_Dout (w8_DecDataOut), //HGFEDCBA
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.o_Kout (w_Kout),
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.o_DErr (w_Err),
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.o_KErr (),
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.o_DpErr (),
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.i_ForceDisparity (1'b0),
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.i_Disparity (1'b0), //1 Is negative, 0 is positive
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.i10_Din (w10_DataOut), //abcdeifghj
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.o_Rd (),
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.i_Clk (w_Clk),
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.i_ARst_L (r_ARst_L));
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initial
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begin
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r_ARst_L = 1'b0;
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r_Kin = 1'b0;
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r_ForceParity = 1'b0;
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r_Disparity = 1'b0;
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#100;
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r_ARst_L = 1'b1;
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r8_DataIn = 0;
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//Normal Test no K
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$display("Normal data test, no K");
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repeat(256)
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begin
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@(posedge w_Clk);
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r8_DataIn = r8_DataIn +1;
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end
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#10000;
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//Normal Test with K
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$display("Normal data test, with valid K");
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repeat(100)
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repeat(256)
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begin
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@(posedge w_Clk);
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r8_DataIn = r8_DataIn +1;
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if(r8_DataIn==8'h1C||r8_DataIn==8'h3C||r8_DataIn==8'h5C||r8_DataIn==8'h7C||
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r8_DataIn==8'h9C||r8_DataIn==8'hBC||r8_DataIn==8'hDC||r8_DataIn==8'hFC||
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r8_DataIn==8'hF7||r8_DataIn==8'hFB||r8_DataIn==8'hFD||r8_DataIn==8'hFE)
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r_Kin=$random; else r_Kin=1'b0;
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end
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//Force Parity Error
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$display("Inject Parity Error");
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repeat(256)
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begin
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@(posedge w_Clk);
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r8_DataIn = r8_DataIn +1;
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if(r8_DataIn==8'h1C||r8_DataIn==8'h3C||r8_DataIn==8'h5C||r8_DataIn==8'h7C||
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r8_DataIn==8'h9C||r8_DataIn==8'hBC||r8_DataIn==8'hDC||r8_DataIn==8'hFC||
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r8_DataIn==8'hF7||r8_DataIn==8'hFB||r8_DataIn==8'hFD||r8_DataIn==8'hFE)
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r_Kin=$random; else r_Kin=1'b0;
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if(($random&32'h3F)==0)
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begin
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r_Disparity = ~w_Rd;
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r_ForceParity = 1'b1;
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end
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else
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r_ForceParity = 1'b0;
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end
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r_ForceParity = 1'b0;
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#10000;
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$display("Inject K Error");
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repeat(100)
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repeat(256)
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begin
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@(posedge w_Clk);
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r8_DataIn = r8_DataIn +1;
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if(r8_DataIn==8'h1C||r8_DataIn==8'h3C||r8_DataIn==8'h5C||r8_DataIn==8'h7C||
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r8_DataIn==8'h9C||r8_DataIn==8'hBC||r8_DataIn==8'hDC||r8_DataIn==8'hFC||
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r8_DataIn==8'hF7||r8_DataIn==8'hFB||r8_DataIn==8'hFD||r8_DataIn==8'hFE||
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r8_DataIn==8'h17||r8_DataIn==8'h1B||r8_DataIn==8'h1D||r8_DataIn==8'h1E)//Invalid Ks
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r_Kin=$random; else r_Kin=1'b0;
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end
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#10000;
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$display("Totally Random Test");
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repeat(25600000)
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begin
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@(posedge w_Clk);
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r8_DataIn = $random&8'hFF;
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if(r8_DataIn==8'h1C||r8_DataIn==8'h3C||r8_DataIn==8'h5C||r8_DataIn==8'h7C||
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r8_DataIn==8'h9C||r8_DataIn==8'hBC||r8_DataIn==8'hDC||r8_DataIn==8'hFC||
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r8_DataIn==8'hF7||r8_DataIn==8'hFB||r8_DataIn==8'hFD||r8_DataIn==8'hFE||
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r8_DataIn==8'h17||r8_DataIn==8'h1B||r8_DataIn==8'h1D||r8_DataIn==8'h1E)//Invalid Ks
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r_Kin=$random; else r_Kin=1'b0;
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if(($random&32'h3F)==0)
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begin
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r_Disparity = ~w_Rd;
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r_ForceParity = 1'b1;
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end
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else
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r_ForceParity = 1'b0;
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end
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$display("Done");
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$stop;
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end
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//Checker
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reg [7:0] r8_D[7:0];
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reg [7:0] r_K;
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reg [7:0] r_KEncErr;
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reg [7:0] r_DecErr;
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always@(posedge w_Clk)
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if(~w_Err)
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begin
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r8_D[0] <= r8_DataIn;
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r8_D[1] <= r8_D[0];
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r_K[0] <= r_Kin;
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r_K[1] <= r_K[0];
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r_KEncErr[0] <= w_KErr;
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`CheckW(w8_DecDataOut,r8_D[1],"Data Out Mismatch")
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if(~r_KEncErr[0]) `CheckW(w_Kout,r_K[1],"Data Out Mismatch")
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end
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endmodule
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module mClkGen #(parameter pClkPeriod=10) (output reg o_Clk);
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initial
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forever
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begin
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o_Clk = 1'b0;
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#pClkPeriod;
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o_Clk = 1'b1;
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#pClkPeriod;
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end
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endmodule

‎endec8b10b/src/mDec8b10bMem.v‎

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/*
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Copyright © 2012 [email protected]
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This file is part of SGMII-IP-Core.
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SGMII-IP-Core is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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SGMII-IP-Core is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
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File :
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Description :
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Remarks :
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Revision :
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Date Author Description
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02/09/12 Jefflieu
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*/
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module mDec8b10bMem(
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output reg [7:0] o8_Dout, //HGFEDCBA
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output reg o_Kout,
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output reg o_DErr,
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output reg o_KErr,
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output reg o_DpErr,
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input i_ForceDisparity,
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input i_Disparity, //1 Is negative, 0 is positive
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input [9:0] i10_Din, //abcdeifghj
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output o_Rd,
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input i_Clk,
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input i_ARst_L);
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parameter pNEG = 2'b01;
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parameter pPOS = 2'b10;
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parameter pNEU = 2'b00;
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parameter pERR = 2'b11;
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parameter pD = 2'b01;
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parameter pK = 2'b10;
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parameter pDK = 2'b11;
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reg r_Disp;
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reg [8:0] w9_5bDecode;
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reg [6:0] w7_3bDecode;
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wire w_Disp,w_jDisp,w_iDisp;
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wire w_iDpErr,w_jDpErr;
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wire w_iDErr,w_jDErr;
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wire [7:0] w8_ABCDEFGH;
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wire wa,wb,wc,wd,we,wi,wf,wg,wh,wj;
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wire w_K28;
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reg w_Kx;
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wire w_cdeihj;
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assign w_Disp = i_ForceDisparity?i_Disparity:r_Disp;
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assign {wa,wb,wc,wd,we,wi,wf,wg,wh,wj} = i10_Din;
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always@(*)
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case(i10_Din[9:4])
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6'b011000 : w9_5bDecode <= {5'b00000,pD,pPOS};
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6'b100111 : w9_5bDecode <= {5'b00000,pD,pNEG};
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6'b100010 : w9_5bDecode <= {5'b10000,pD,pPOS};
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6'b011101 : w9_5bDecode <= {5'b10000,pD,pNEG};
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6'b010010 : w9_5bDecode <= {5'b01000,pD,pPOS};
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6'b101101 : w9_5bDecode <= {5'b01000,pD,pNEG};
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6'b110001 : w9_5bDecode <= {5'b11000,pD,pNEU};
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6'b001010 : w9_5bDecode <= {5'b00100,pD,pPOS};
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6'b110101 : w9_5bDecode <= {5'b00100,pD,pNEG};
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6'b101001 : w9_5bDecode <= {5'b10100,pD,pNEU};
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6'b011001 : w9_5bDecode <= {5'b01100,pD,pNEU};
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6'b111000 : w9_5bDecode <= {5'b11100,pD,pNEG};
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6'b000111 : w9_5bDecode <= {5'b11100,pD,pPOS};
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6'b000110 : w9_5bDecode <= {5'b00010,pD,pPOS};
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6'b111001 : w9_5bDecode <= {5'b00010,pD,pNEG};
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6'b100101 : w9_5bDecode <= {5'b10010,pD,pNEU};
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6'b010101 : w9_5bDecode <= {5'b01010,pD,pNEU};
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6'b110100 : w9_5bDecode <= {5'b11010,pD,pNEU};
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6'b001101 : w9_5bDecode <= {5'b00110,pD,pNEU};
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6'b101100 : w9_5bDecode <= {5'b10110,pD,pNEU};
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6'b011100 : w9_5bDecode <= {5'b01110,pD,pNEU};
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6'b101000 : w9_5bDecode <= {5'b11110,pD,pPOS};
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6'b010111 : w9_5bDecode <= {5'b11110,pD,pNEG};
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6'b011011 : w9_5bDecode <= {5'b00001,pD,pNEG};
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6'b100100 : w9_5bDecode <= {5'b00001,pD,pPOS};
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6'b100011 : w9_5bDecode <= {5'b10001,pD,pNEU};
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6'b010011 : w9_5bDecode <= {5'b01001,pD,pNEU};
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6'b110010 : w9_5bDecode <= {5'b11001,pD,pNEU};
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6'b001011 : w9_5bDecode <= {5'b00101,pD,pNEU};
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6'b101010 : w9_5bDecode <= {5'b10101,pD,pNEU};
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6'b011010 : w9_5bDecode <= {5'b01101,pD,pNEU};
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6'b111010 : w9_5bDecode <= {5'b11101,pDK,pNEG};
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6'b000101 : w9_5bDecode <= {5'b11101,pDK,pPOS};
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6'b001100 : w9_5bDecode <= {5'b00011,pD,pPOS};
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6'b110011 : w9_5bDecode <= {5'b00011,pD,pNEG};
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6'b100110 : w9_5bDecode <= {5'b10011,pD,pNEU};
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6'b010110 : w9_5bDecode <= {5'b01011,pD,pNEU};
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6'b110110 : w9_5bDecode <= {5'b11011,pDK,pNEG};
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6'b001001 : w9_5bDecode <= {5'b11011,pDK,pPOS};
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6'b001110 : w9_5bDecode <= {5'b00111,pD,pNEU};
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6'b001111 : w9_5bDecode <= {5'b00111,pK,pNEG};
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6'b110000 : w9_5bDecode <= {5'b00111,pK,pPOS};
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6'b101110 : w9_5bDecode <= {5'b10111,pDK,pNEG};
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6'b010001 : w9_5bDecode <= {5'b10111,pDK,pPOS};
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6'b011110 : w9_5bDecode <= {5'b01111,pDK,pNEG};
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6'b100001 : w9_5bDecode <= {5'b01111,pDK,pPOS};
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6'b101011 : w9_5bDecode <= {5'b11111,pDK,pNEG};
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6'b010100 : w9_5bDecode <= {5'b11111,pDK,pPOS};
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default : w9_5bDecode <= {5'b11111,pERR,pERR};
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endcase
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assign w_iDpErr = (w9_5bDecode[1:0]==pNEG && w_Disp==1'b1) | (w9_5bDecode[1:0]==pPOS && w_Disp==1'b0);
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assign w_iDErr = (w9_5bDecode[1:0]==pERR)?1'b1:1'b0;
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assign w_iDisp = (w9_5bDecode[1:0]==pERR||w9_5bDecode[1:0]==pNEU||i10_Din[9:4]==6'b111000||i10_Din[9:4]==6'b000111)?w_Disp:~w9_5bDecode[1];
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assign w_jDpErr = (w7_3bDecode[1:0]==pNEG && w_iDisp==1'b1) | (w7_3bDecode[1:0]==pPOS && w_iDisp==1'b0);
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assign w_jDisp = (w7_3bDecode[1:0]==pERR||w7_3bDecode[1:0]==pNEU||i10_Din[3:0]==4'b1100||i10_Din[3:0]==4'b0011)?w_iDisp:~w_iDisp;
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assign w_jDErr = (w7_3bDecode[1:0]==pERR)?1'b1:1'b0;
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assign w_cdeihj = (~(|{wc,wd,we,wi}))&(wh^wj);
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always@(*)
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case(i10_Din[3:0])
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4'b0100 : w7_3bDecode <= {3'b000,pDK,pPOS};
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4'b1011 : w7_3bDecode <= {3'b000,pDK,pNEG};
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4'b1001 : if(w_cdeihj)
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w7_3bDecode <= {3'b011,pK,pNEU};
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else
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w7_3bDecode <= {3'b100,pDK,pNEU};
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4'b0110 : if(w_cdeihj)
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w7_3bDecode <= {3'b100,pK,pNEU};
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else
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w7_3bDecode <= {3'b011,pDK,pNEU};
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4'b0101 : if(w_cdeihj)
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w7_3bDecode <= {3'b101,pK,pNEU};
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else
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w7_3bDecode <= {3'b010,pDK,pNEU};
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4'b1010 : if(w_cdeihj)
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w7_3bDecode <= {3'b010,pK,pNEU};
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else
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w7_3bDecode <= {3'b101,pDK,pNEU};
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4'b1100 : w7_3bDecode <= {3'b110,pDK,pNEG};
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4'b0011 : w7_3bDecode <= {3'b110,pDK,pPOS};
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4'b0010 : w7_3bDecode <= {3'b001,pDK,pPOS};
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4'b1101 : w7_3bDecode <= {3'b001,pDK,pNEG};
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//4'b1010 :
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//4'b0101 :
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//4'b0110 :
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//4'b1001 :
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4'b1110 : w7_3bDecode <= {3'b111,pD,pNEG};
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4'b0001 : w7_3bDecode <= {3'b111,pD,pPOS};
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4'b0111 : w7_3bDecode <= {3'b111,pDK,pNEG};
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4'b1000 : w7_3bDecode <= {3'b111,pDK,pPOS};
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default : w7_3bDecode <= {3'b111,pERR,pERR};
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endcase
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assign w8_ABCDEFGH = {w9_5bDecode[8:4],w7_3bDecode[6:4]};
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integer I;
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always@(posedge i_Clk or negedge i_ARst_L)
167+
if(~i_ARst_L)
168+
begin
169+
o_DErr <= 1'b1;
170+
o_DpErr <= 1'b0;
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o_KErr <= 1'b0;
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o_Kout <= 1'b0;
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o8_Dout <= 8'h0;
174+
r_Disp <= 1'b0;
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end
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else
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begin
178+
o_DErr <= w_jDErr|w_iDErr;
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o_DpErr <= w_jDpErr|w_iDpErr;
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o_KErr <= ~(|(w9_5bDecode[3:2]&w7_3bDecode[3:2]));
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o_Kout <= ((w9_5bDecode[3:2]==pK)&(w7_3bDecode[3]))|((w9_5bDecode[3:2]==pDK)&(w7_3bDecode[3])&(w7_3bDecode[6:4]==3'b111));
182+
r_Disp <= w_jDisp;
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for(I=0;I<8;I=I+1)
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o8_Dout[7-I] <= w8_ABCDEFGH[I];
185+
end
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assign o_Rd = r_Disp;
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endmodule

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