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Suchismith RoyVarada M
Suchismith Roy
authored and
Varada M
committed
8331859: [PPC64] Remove support for Power7 and older
Reviewed-by: mdoerr
1 parent a37e826 commit 5cdeef8

25 files changed

+266
-1731
lines changed

‎make/autoconf/flags-cflags.m4

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -732,8 +732,7 @@ AC_DEFUN([FLAGS_SETUP_CFLAGS_CPU_DEP],
732732
$1_CFLAGS_CPU_JVM="-mno-multiple -mno-string"
733733
if test "x$FLAGS_CPU" = xppc64; then
734734
# -mminimal-toc fixes `relocation truncated to fit' error for gcc 4.1.
735-
# Use ppc64 instructions, but schedule for power5
736-
$1_CFLAGS_CPU="-mcpu=powerpc64 -mtune=power5"
735+
$1_CFLAGS_CPU="-mcpu=power8 -mtune=power8"
737736
$1_CFLAGS_CPU_JVM="${$1_CFLAGS_CPU_JVM} -mminimal-toc"
738737
elif test "x$FLAGS_CPU" = xppc64le; then
739738
# Little endian machine uses ELFv2 ABI.

‎src/hotspot/cpu/ppc/assembler_ppc.hpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2008,15 +2008,14 @@ class Assembler : public AbstractAssembler {
20082008

20092009
// Wait instructions for polling. Attention: May result in SIGILL.
20102010
inline void wait();
2011-
inline void waitrsv(); // >=Power7
2011+
inline void waitrsv();
20122012

20132013
// atomics
20142014
inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
20152015
inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
20162016
inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
20172017
inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
20182018
inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
2019-
inline bool lxarx_hint_exclusive_access();
20202019
inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
20212020
inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false);
20222021
inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
@@ -2039,7 +2038,6 @@ class Assembler : public AbstractAssembler {
20392038
inline void smt_prio_low();
20402039
inline void smt_prio_medium_low();
20412040
inline void smt_prio_medium();
2042-
// >= Power7
20432041
inline void smt_yield();
20442042
inline void smt_mdoio();
20452043
inline void smt_mdoom();

‎src/hotspot/cpu/ppc/assembler_ppc.inline.hpp

Lines changed: 18 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -208,8 +208,7 @@ inline void Assembler::cmpldi(ConditionRegister crx, Register a, int ui16) { A
208208
inline void Assembler::cmplw( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 0, a, b); }
209209
inline void Assembler::cmpld( ConditionRegister crx, Register a, Register b) { Assembler::cmpl( crx, 1, a, b); }
210210

211-
inline void Assembler::isel(Register d, Register a, Register b, int c) { guarantee(VM_Version::has_isel(), "opcode not supported on this hardware");
212-
emit_int32(ISEL_OPCODE | rt(d) | ra(a) | rb(b) | bc(c)); }
211+
inline void Assembler::isel(Register d, Register a, Register b, int c) { emit_int32(ISEL_OPCODE | rt(d) | ra(a) | rb(b) | bc(c)); }
213212

214213
// PPC 1, section 3.3.11, Fixed-Point Logical Instructions
215214
inline void Assembler::andi_( Register a, Register s, int ui16) { emit_int32(ANDI_OPCODE | rta(a) | rs(s) | uimm(ui16, 16)); }
@@ -701,12 +700,11 @@ inline void Assembler::lharx_unchecked(Register d, Register a, Register b, int e
701700
inline void Assembler::lwarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LWARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
702701
inline void Assembler::ldarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LDARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
703702
inline void Assembler::lqarx_unchecked(Register d, Register a, Register b, int eh1) { emit_int32( LQARX_OPCODE | rt(d) | ra0mem(a) | rb(b) | eh(eh1)); }
704-
inline bool Assembler::lxarx_hint_exclusive_access() { return VM_Version::has_lxarxeh(); }
705-
inline void Assembler::lbarx( Register d, Register a, Register b, bool hint_exclusive_access) { lbarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
706-
inline void Assembler::lharx( Register d, Register a, Register b, bool hint_exclusive_access) { lharx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
707-
inline void Assembler::lwarx( Register d, Register a, Register b, bool hint_exclusive_access) { lwarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
708-
inline void Assembler::ldarx( Register d, Register a, Register b, bool hint_exclusive_access) { ldarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
709-
inline void Assembler::lqarx( Register d, Register a, Register b, bool hint_exclusive_access) { lqarx_unchecked(d, a, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
703+
inline void Assembler::lbarx( Register d, Register a, Register b, bool hint_exclusive_access) { lbarx_unchecked(d, a, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
704+
inline void Assembler::lharx( Register d, Register a, Register b, bool hint_exclusive_access) { lharx_unchecked(d, a, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
705+
inline void Assembler::lwarx( Register d, Register a, Register b, bool hint_exclusive_access) { lwarx_unchecked(d, a, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
706+
inline void Assembler::ldarx( Register d, Register a, Register b, bool hint_exclusive_access) { ldarx_unchecked(d, a, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
707+
inline void Assembler::lqarx( Register d, Register a, Register b, bool hint_exclusive_access) { lqarx_unchecked(d, a, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
710708
inline void Assembler::stbcx_(Register s, Register a, Register b) { emit_int32( STBCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
711709
inline void Assembler::sthcx_(Register s, Register a, Register b) { emit_int32( STHCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
712710
inline void Assembler::stwcx_(Register s, Register a, Register b) { emit_int32( STWCX_OPCODE | rs(s) | ra0mem(a) | rb(b) | rc(1)); }
@@ -775,12 +773,9 @@ inline void Assembler::frim( FloatRegister d, FloatRegister b) { emit_int32( FRI
775773
//inline void Assembler::mffgpr( FloatRegister d, Register b) { emit_int32( MFFGPR_OPCODE | frt(d) | rb(b) | rc(0)); }
776774
//inline void Assembler::mftgpr( Register d, FloatRegister b) { emit_int32( MFTGPR_OPCODE | rt(d) | frb(b) | rc(0)); }
777775
// add cmpb and popcntb to detect ppc power version.
778-
inline void Assembler::cmpb( Register a, Register s, Register b) { guarantee(VM_Version::has_cmpb(), "opcode not supported on this hardware");
779-
emit_int32( CMPB_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
780-
inline void Assembler::popcntb(Register a, Register s) { guarantee(VM_Version::has_popcntb(), "opcode not supported on this hardware");
781-
emit_int32( POPCNTB_OPCODE | rta(a) | rs(s)); };
782-
inline void Assembler::popcntw(Register a, Register s) { guarantee(VM_Version::has_popcntw(), "opcode not supported on this hardware");
783-
emit_int32( POPCNTW_OPCODE | rta(a) | rs(s)); };
776+
inline void Assembler::cmpb( Register a, Register s, Register b) { emit_int32( CMPB_OPCODE | rta(a) | rs(s) | rb(b) | rc(0)); }
777+
inline void Assembler::popcntb(Register a, Register s) { emit_int32( POPCNTB_OPCODE | rta(a) | rs(s)); };
778+
inline void Assembler::popcntw(Register a, Register s) { emit_int32( POPCNTW_OPCODE | rta(a) | rs(s)); };
784779
inline void Assembler::popcntd(Register a, Register s) { emit_int32( POPCNTD_OPCODE | rta(a) | rs(s)); };
785780

786781
inline void Assembler::fneg( FloatRegister d, FloatRegister b) { emit_int32( FNEG_OPCODE | frt(d) | frb(b) | rc(0)); }
@@ -835,17 +830,14 @@ inline void Assembler::fctidz(FloatRegister d, FloatRegister b) { emit_int32( FC
835830
inline void Assembler::fctiw( FloatRegister d, FloatRegister b) { emit_int32( FCTIW_OPCODE | frt(d) | frb(b) | rc(0)); }
836831
inline void Assembler::fctiwz(FloatRegister d, FloatRegister b) { emit_int32( FCTIWZ_OPCODE | frt(d) | frb(b) | rc(0)); }
837832
inline void Assembler::fcfid( FloatRegister d, FloatRegister b) { emit_int32( FCFID_OPCODE | frt(d) | frb(b) | rc(0)); }
838-
inline void Assembler::fcfids(FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fcfids(), "opcode not supported on this hardware");
839-
emit_int32( FCFIDS_OPCODE | frt(d) | frb(b) | rc(0)); }
833+
inline void Assembler::fcfids(FloatRegister d, FloatRegister b) { emit_int32( FCFIDS_OPCODE | frt(d) | frb(b) | rc(0)); }
840834

841835
// PPC 1, section 4.6.7 Floating-Point Compare Instructions
842836
inline void Assembler::fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b) { emit_int32( FCMPU_OPCODE | bf(crx) | fra(a) | frb(b)); }
843837

844838
// PPC 1, section 5.2.1 Floating-Point Arithmetic Instructions
845-
inline void Assembler::fsqrt( FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fsqrt(), "opcode not supported on this hardware");
846-
emit_int32( FSQRT_OPCODE | frt(d) | frb(b) | rc(0)); }
847-
inline void Assembler::fsqrts(FloatRegister d, FloatRegister b) { guarantee(VM_Version::has_fsqrts(), "opcode not supported on this hardware");
848-
emit_int32( FSQRTS_OPCODE | frt(d) | frb(b) | rc(0)); }
839+
inline void Assembler::fsqrt( FloatRegister d, FloatRegister b) { emit_int32( FSQRT_OPCODE | frt(d) | frb(b) | rc(0)); }
840+
inline void Assembler::fsqrts(FloatRegister d, FloatRegister b) { emit_int32( FSQRTS_OPCODE | frt(d) | frb(b) | rc(0)); }
849841

850842
// Vector instructions for >= Power6.
851843
inline void Assembler::lvebx( VectorRegister d, Register s1, Register s2) { emit_int32( LVEBX_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
@@ -1057,8 +1049,7 @@ inline void Assembler::vcmpgtsw_(VectorRegister d,VectorRegister a, VectorRegist
10571049
inline void Assembler::vcmpgtub_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUB_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
10581050
inline void Assembler::vcmpgtuh_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUH_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
10591051
inline void Assembler::vcmpgtuw_(VectorRegister d,VectorRegister a, VectorRegister b) { emit_int32( VCMPGTUW_OPCODE | vrt(d) | vra(a) | vrb(b) | vcmp_rc(1)); }
1060-
inline void Assembler::vand( VectorRegister d, VectorRegister a, VectorRegister b) { guarantee(VM_Version::has_vand(), "opcode not supported on this hardware");
1061-
emit_int32( VAND_OPCODE | vrt(d) | vra(a) | vrb(b)); }
1052+
inline void Assembler::vand( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VAND_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10621053
inline void Assembler::vandc( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VANDC_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10631054
inline void Assembler::vnor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNOR_OPCODE | vrt(d) | vra(a) | vrb(b)); }
10641055
inline void Assembler::vor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VOR_OPCODE | vrt(d) | vra(a) | vrb(b)); }
@@ -1166,11 +1157,11 @@ inline void Assembler::lharx_unchecked(Register d, Register b, int eh1)
11661157
inline void Assembler::lwarx_unchecked(Register d, Register b, int eh1) { emit_int32( LWARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
11671158
inline void Assembler::ldarx_unchecked(Register d, Register b, int eh1) { emit_int32( LDARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
11681159
inline void Assembler::lqarx_unchecked(Register d, Register b, int eh1) { emit_int32( LQARX_OPCODE | rt(d) | rb(b) | eh(eh1)); }
1169-
inline void Assembler::lbarx( Register d, Register b, bool hint_exclusive_access){ lbarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1170-
inline void Assembler::lharx( Register d, Register b, bool hint_exclusive_access){ lharx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1171-
inline void Assembler::lwarx( Register d, Register b, bool hint_exclusive_access){ lwarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1172-
inline void Assembler::ldarx( Register d, Register b, bool hint_exclusive_access){ ldarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1173-
inline void Assembler::lqarx( Register d, Register b, bool hint_exclusive_access){ lqarx_unchecked(d, b, (hint_exclusive_access && lxarx_hint_exclusive_access() && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1160+
inline void Assembler::lbarx( Register d, Register b, bool hint_exclusive_access){ lbarx_unchecked(d, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1161+
inline void Assembler::lharx( Register d, Register b, bool hint_exclusive_access){ lharx_unchecked(d, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1162+
inline void Assembler::lwarx( Register d, Register b, bool hint_exclusive_access){ lwarx_unchecked(d, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1163+
inline void Assembler::ldarx( Register d, Register b, bool hint_exclusive_access){ ldarx_unchecked(d, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
1164+
inline void Assembler::lqarx( Register d, Register b, bool hint_exclusive_access){ lqarx_unchecked(d, b, (hint_exclusive_access && UseExtendedLoadAndReserveInstructionsPPC64) ? 1 : 0); }
11741165
inline void Assembler::stbcx_(Register s, Register b) { emit_int32( STBCX_OPCODE | rs(s) | rb(b) | rc(1)); }
11751166
inline void Assembler::sthcx_(Register s, Register b) { emit_int32( STHCX_OPCODE | rs(s) | rb(b) | rc(1)); }
11761167
inline void Assembler::stwcx_(Register s, Register b) { emit_int32( STWCX_OPCODE | rs(s) | rb(b) | rc(1)); }

‎src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp

Lines changed: 25 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -538,48 +538,32 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
538538
__ extsh(dst->as_register(), src->as_register());
539539
break;
540540
}
541-
case Bytecodes::_i2d:
541+
case Bytecodes::_i2d:{
542+
FloatRegister rdst = dst->as_double_reg();
543+
// move src to dst register
544+
__ mtfprwa(rdst, src->as_register());
545+
__ fcfid(rdst, rdst);
546+
break;
547+
}
542548
case Bytecodes::_l2d: {
543-
bool src_in_memory = !VM_Version::has_mtfprd();
544549
FloatRegister rdst = dst->as_double_reg();
545-
FloatRegister rsrc;
546-
if (src_in_memory) {
547-
rsrc = src->as_double_reg(); // via mem
548-
} else {
549-
// move src to dst register
550-
if (code == Bytecodes::_i2d) {
551-
__ mtfprwa(rdst, src->as_register());
552-
} else {
553-
__ mtfprd(rdst, src->as_register_lo());
554-
}
555-
rsrc = rdst;
556-
}
557-
__ fcfid(rdst, rsrc);
550+
// move src to dst register
551+
__ mtfprd(rdst, src->as_register_lo());
552+
__ fcfid(rdst, rdst);
553+
break;
554+
}
555+
case Bytecodes::_i2f:{
556+
FloatRegister rdst = dst->as_float_reg();
557+
// move src to dst register
558+
__ mtfprwa(rdst, src->as_register());
559+
__ fcfids(rdst, rdst);
558560
break;
559561
}
560-
case Bytecodes::_i2f:
561562
case Bytecodes::_l2f: {
562-
bool src_in_memory = !VM_Version::has_mtfprd();
563563
FloatRegister rdst = dst->as_float_reg();
564-
FloatRegister rsrc;
565-
if (src_in_memory) {
566-
rsrc = src->as_double_reg(); // via mem
567-
} else {
568-
// move src to dst register
569-
if (code == Bytecodes::_i2f) {
570-
__ mtfprwa(rdst, src->as_register());
571-
} else {
572-
__ mtfprd(rdst, src->as_register_lo());
573-
}
574-
rsrc = rdst;
575-
}
576-
if (VM_Version::has_fcfids()) {
577-
__ fcfids(rdst, rsrc);
578-
} else {
579-
assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
580-
__ fcfid(rdst, rsrc);
581-
__ frsp(rdst, rdst);
582-
}
564+
// move src to dst register
565+
__ mtfprd(rdst, src->as_register_lo());
566+
__ fcfids(rdst, rdst);
583567
break;
584568
}
585569
case Bytecodes::_f2d: {
@@ -592,49 +576,27 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
592576
}
593577
case Bytecodes::_d2i:
594578
case Bytecodes::_f2i: {
595-
bool dst_in_memory = !VM_Version::has_mtfprd();
596579
FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
597-
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
598580
Label L;
599581
// Result must be 0 if value is NaN; test by comparing value to itself.
600582
__ fcmpu(CR0, rsrc, rsrc);
601-
if (dst_in_memory) {
602-
__ li(R0, 0); // 0 in case of NAN
603-
__ std(R0, addr);
604-
} else {
605-
__ li(dst->as_register(), 0);
606-
}
583+
__ li(dst->as_register(), 0);
607584
__ bso(CR0, L);
608585
__ fctiwz(rsrc, rsrc); // USE_KILL
609-
if (dst_in_memory) {
610-
__ stfd(rsrc, addr.disp(), addr.base());
611-
} else {
612-
__ mffprd(dst->as_register(), rsrc);
613-
}
586+
__ mffprd(dst->as_register(), rsrc);
614587
__ bind(L);
615588
break;
616589
}
617590
case Bytecodes::_d2l:
618591
case Bytecodes::_f2l: {
619-
bool dst_in_memory = !VM_Version::has_mtfprd();
620592
FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
621-
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
622593
Label L;
623594
// Result must be 0 if value is NaN; test by comparing value to itself.
624595
__ fcmpu(CR0, rsrc, rsrc);
625-
if (dst_in_memory) {
626-
__ li(R0, 0); // 0 in case of NAN
627-
__ std(R0, addr);
628-
} else {
629-
__ li(dst->as_register_lo(), 0);
630-
}
596+
__ li(dst->as_register_lo(), 0);
631597
__ bso(CR0, L);
632598
__ fctidz(rsrc, rsrc); // USE_KILL
633-
if (dst_in_memory) {
634-
__ stfd(rsrc, addr.disp(), addr.base());
635-
} else {
636-
__ mffprd(dst->as_register_lo(), rsrc);
637-
}
599+
__ mffprd(dst->as_register_lo(), rsrc);
638600
__ bind(L);
639601
break;
640602
}
@@ -1581,8 +1543,7 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L
15811543
default: ShouldNotReachHere();
15821544
}
15831545

1584-
// Try to use isel on >=Power7.
1585-
if (VM_Version::has_isel() && result->is_cpu_register()) {
1546+
if (result->is_cpu_register()) {
15861547
bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
15871548
const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
15881549

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