DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core

00001 /* ==========================================================================
00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
00003  * $Revision: #12 $
00004  * $Date: 2011/10/24 $
00005  * $Change: 1871159 $
00006  *
00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
00009  * otherwise expressly agreed to in writing between Synopsys and you.
00010  *
00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
00012  * any End User Software License Agreement or Agreement for Licensed Product
00013  * with Synopsys or any supplement thereto. You are permitted to use and
00014  * redistribute this Software in source and binary forms, with or without
00015  * modification, provided that redistributions of source code must retain this
00016  * notice. You may not view, use, disclose, copy or distribute this file or
00017  * any information contained herein except pursuant to this license grant from
00018  * Synopsys. If you do not agree with this notice, including the disclaimer
00019  * below, then you are not authorized to use the Software.
00020  *
00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
00031  * DAMAGE.
00032  * ========================================================================== */
00033 #if !defined(__DWC_CORE_IF_H__)
00034 #define __DWC_CORE_IF_H__
00035 
00036 #include "dwc_os.h"
00037 
00042 struct dwc_otg_core_if;
00043 typedef struct dwc_otg_core_if dwc_otg_core_if_t;
00044 
00046 #define MAX_PERIO_FIFOS 15
00047 
00048 #define MAX_TX_FIFOS 15
00049 
00051 #define MAX_EPS_CHANNELS 16
00052 
00053 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
00054 extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
00055 extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
00056 
00057 extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
00058 extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
00059 
00060 extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
00061 extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
00062 
00063 extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
00064 
00066 extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
00067 
00078 extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
00079 extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
00080 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
00081 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
00082 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
00083 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
00084 
00085 extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
00086 extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
00087 #define dwc_param_opt_default 1
00088 
00096 extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
00097                                         int32_t val);
00098 extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
00099 #define dwc_param_dma_enable_default 1
00100 
00109 extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
00110                                              int32_t val);
00111 extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
00112 #define dwc_param_dma_desc_enable_default 1
00113 
00117 extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
00118                                             int32_t val);
00119 extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
00120 #define dwc_param_dma_burst_size_default 32
00121 
00130 extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
00131 extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
00132 #define dwc_param_speed_default 0
00133 #define DWC_SPEED_PARAM_HIGH 0
00134 #define DWC_SPEED_PARAM_FULL 1
00135 
00141 extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
00142                                                           core_if, int32_t val);
00143 extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
00144                                                               * core_if);
00145 #define dwc_param_host_support_fs_ls_low_power_default 0
00146 
00155 extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
00156                                                        core_if, int32_t val);
00157 extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
00158                                                            core_if);
00159 #define dwc_param_host_ls_low_power_phy_clk_default 0
00160 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
00161 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
00162 
00167 extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
00168                                                  int32_t val);
00169 extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
00170                                                      core_if);
00171 #define dwc_param_enable_dynamic_fifo_default 1
00172 
00179 extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
00180                                             int32_t val);
00181 extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
00182 #define dwc_param_data_fifo_size_default 8192
00183 
00188 extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
00189                                               int32_t val);
00190 extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
00191 #define dwc_param_dev_rx_fifo_size_default 1064
00192 
00197 extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
00198                                                      core_if, int32_t val);
00199 extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
00200                                                          core_if);
00201 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
00202 
00207 extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
00208                                                     int32_t val, int fifo_num);
00209 extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
00210                                                         core_if, int fifo_num);
00211 #define dwc_param_dev_perio_tx_fifo_size_default 256
00212 
00217 extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
00218                                                int32_t val);
00219 extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
00220 #define dwc_param_host_rx_fifo_size_default 1024
00221 
00226 extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
00227                                                       core_if, int32_t val);
00228 extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
00229                                                           core_if);
00230 #define dwc_param_host_nperio_tx_fifo_size_default 1024
00231 
00236 extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
00237                                                      core_if, int32_t val);
00238 extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
00239                                                          core_if);
00240 #define dwc_param_host_perio_tx_fifo_size_default 1024
00241 
00245 extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
00246                                                int32_t val);
00247 extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
00248 #define dwc_param_max_transfer_size_default 65535
00249 
00253 extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
00254                                               int32_t val);
00255 extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
00256 #define dwc_param_max_packet_count_default 511
00257 
00262 extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
00263                                            int32_t val);
00264 extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
00265 #define dwc_param_host_channels_default 12
00266 
00273 extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
00274                                            int32_t val);
00275 extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
00276 #define dwc_param_dev_endpoints_default 6
00277 
00286 extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
00287 extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
00288 #define DWC_PHY_TYPE_PARAM_FS 0
00289 #define DWC_PHY_TYPE_PARAM_UTMI 1
00290 #define DWC_PHY_TYPE_PARAM_ULPI 2
00291 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
00292 
00304 extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
00305                                             int32_t val);
00306 extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
00307 #define dwc_param_phy_utmi_width_default 16
00308 
00319 extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
00320                                           int32_t val);
00321 extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
00322 #define dwc_param_phy_ulpi_ddr_default 0
00323 
00328 extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
00329                                                int32_t val);
00330 extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
00331 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
00332 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
00333 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
00334 
00341 extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
00342                                         int32_t val);
00343 extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
00344 #define dwc_param_i2c_enable_default 0
00345 
00346 extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
00347                                         int32_t val);
00348 extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
00349 #define dwc_param_ulpi_fs_ls_default 0
00350 
00351 extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
00352 extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
00353 #define dwc_param_ts_dline_default 0
00354 
00361 extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
00362                                                  int32_t val);
00363 extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
00364                                                      core_if);
00365 #define dwc_param_en_multiple_tx_fifo_default 1
00366 
00371 extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
00372                                               int fifo_num, int32_t val);
00373 extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
00374                                                   int fifo_num);
00375 #define dwc_param_dev_tx_fifo_size_default 768
00376 
00382 extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
00383 extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
00384 #define dwc_param_thr_ctl_default 0
00385 
00389 extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
00390                                            int32_t val);
00391 extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
00392 #define dwc_param_tx_thr_length_default 64
00393 
00397 extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
00398                                            int32_t val);
00399 extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
00400 #define dwc_param_rx_thr_length_default 64
00401 
00405 extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
00406                                         int32_t val);
00407 extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
00408 #define dwc_param_lpm_enable_default 1
00409 
00413 extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
00414                                         int32_t val);
00415 extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
00416 #define dwc_param_pti_enable_default 0
00417 
00421 extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
00422                                         int32_t val);
00423 extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
00424 #define dwc_param_mpi_enable_default 0
00425 
00429 extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
00430                                         int32_t val);
00431 extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
00432 #define dwc_param_adp_enable_default 0
00433 
00438 extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
00439                                         int32_t val);
00440 extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
00441 #define dwc_param_ic_usb_cap_default 0
00442 
00443 extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
00444                                            int32_t val);
00445 extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
00446 #define dwc_param_ahb_thr_ratio_default 0
00447 
00448 extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
00449                                         int32_t val);
00450 extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
00451 #define dwc_param_power_down_default 0
00452 
00453 extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
00454                                         int32_t val);
00455 extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
00456 #define dwc_param_reload_ctl_default 0
00457 
00458 extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
00459                                                                                 int32_t val);
00460 extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
00461 #define dwc_param_dev_out_nak_default 0
00462 
00463 extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
00464                                                                                  int32_t val);
00465 extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
00466 #define dwc_param_cont_on_bna_default 0
00467 
00468 extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
00469                                                                                  int32_t val);
00470 extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
00471 #define dwc_param_ahb_single_default 0
00472 
00473 extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
00474 extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
00475 #define dwc_param_otg_ver_default 0
00476 
00484 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
00485 extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
00486 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
00487 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
00488 
00492 extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
00493 
00497 extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
00498 
00502 extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
00503 
00507 extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
00508 
00513 extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
00514 
00518 extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
00522 extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
00523 
00527 extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
00531 extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
00532 
00536 extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
00540 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
00541 
00545 extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
00546 
00550 extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
00551 
00555 extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
00556 
00560 extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
00561 
00565 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
00566 
00570 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
00574 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
00575 
00579 extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
00583 extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
00584 
00588 extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
00592 extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
00593 
00598 extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
00599 
00603 extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
00604 
00608 extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
00609 
00613 extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
00614 
00618 extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
00622 extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
00623 
00627 extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
00631 extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
00632 
00636 extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
00640 extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
00641 
00642 /*
00643  * Some functions for accessing registers
00644  */
00645 
00649 extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
00650 extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
00651 
00655 extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
00656 extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
00657 
00661 extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
00662 extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
00663 
00667 extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
00668 extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
00669 
00670 extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
00671 extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
00672 
00676 extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
00677 extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
00678 
00682 extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
00683 extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
00684 
00688 extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
00689 extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
00690 
00694 extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
00695 
00698 #endif                          /* __DWC_CORE_IF_H__ */