dwc_otg_core_if.h File Reference

This file defines DWC_OTG Core API. More...

#include "dwc_os.h"

Go to the source code of this file.

OTG Core Parameters
#define	DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE   0
#define	DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE   1
#define	DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE   2
#define	dwc_param_otg_cap_default   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
#define	dwc_param_opt_default   1
#define	dwc_param_dma_enable_default   1
#define	dwc_param_dma_desc_enable_default   1
#define	dwc_param_dma_burst_size_default   32
#define	dwc_param_speed_default   0
#define	DWC_SPEED_PARAM_HIGH   0
#define	DWC_SPEED_PARAM_FULL   1
#define	dwc_param_host_support_fs_ls_low_power_default   0
#define	dwc_param_host_ls_low_power_phy_clk_default   0
#define	DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ   0
#define	DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ   1
#define	dwc_param_enable_dynamic_fifo_default   1
#define	dwc_param_data_fifo_size_default   8192
#define	dwc_param_dev_rx_fifo_size_default   1064
#define	dwc_param_dev_nperio_tx_fifo_size_default   1024
#define	dwc_param_dev_perio_tx_fifo_size_default   256
#define	dwc_param_host_rx_fifo_size_default   1024
#define	dwc_param_host_nperio_tx_fifo_size_default   1024
#define	dwc_param_host_perio_tx_fifo_size_default   1024
#define	dwc_param_max_transfer_size_default   65535
#define	dwc_param_max_packet_count_default   511
#define	dwc_param_host_channels_default   12
#define	dwc_param_dev_endpoints_default   6
#define	DWC_PHY_TYPE_PARAM_FS   0
#define	DWC_PHY_TYPE_PARAM_UTMI   1
#define	DWC_PHY_TYPE_PARAM_ULPI   2
#define	dwc_param_phy_type_default   DWC_PHY_TYPE_PARAM_UTMI
#define	dwc_param_phy_utmi_width_default   16
#define	dwc_param_phy_ulpi_ddr_default   0
#define	DWC_PHY_ULPI_INTERNAL_VBUS   0
#define	DWC_PHY_ULPI_EXTERNAL_VBUS   1
#define	dwc_param_phy_ulpi_ext_vbus_default   DWC_PHY_ULPI_INTERNAL_VBUS
#define	dwc_param_i2c_enable_default   0
#define	dwc_param_ulpi_fs_ls_default   0
#define	dwc_param_ts_dline_default   0
#define	dwc_param_en_multiple_tx_fifo_default   1
#define	dwc_param_dev_tx_fifo_size_default   768
#define	dwc_param_thr_ctl_default   0
#define	dwc_param_tx_thr_length_default   64
#define	dwc_param_rx_thr_length_default   64
#define	dwc_param_lpm_enable_default   1
#define	dwc_param_pti_enable_default   0
#define	dwc_param_mpi_enable_default   0
#define	dwc_param_adp_enable_default   0
#define	dwc_param_ic_usb_cap_default   0
#define	dwc_param_ahb_thr_ratio_default   0
#define	dwc_param_power_down_default   0
#define	dwc_param_reload_ctl_default   0
#define	dwc_param_dev_out_nak_default   0
#define	dwc_param_cont_on_bna_default   0
#define	dwc_param_ahb_single_default   0
#define	dwc_param_otg_ver_default   0
int	dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies the OTG capabilities.
int32_t	dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether to use slave or DMA mode for accessing the data FIFOs.
int32_t	dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
	When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
int32_t	dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
	The DMA Burst size (applicable only for External DMA Mode).
int32_t	dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies the maximum speed of operation in host and device mode.
int32_t	dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
int32_t	dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
int32_t	dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
	0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
int32_t	dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
	Total number of 4-byte words in the data FIFO memory.
int32_t	dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
	Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
int32_t	dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
	Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
int32_t	dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
	Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
int32_t	dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
int	dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
	Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
int32_t	dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
	Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
int32_t	dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
	Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
int32_t	dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
	The maximum transfer size supported in bytes.
int32_t	dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
	The maximum number of packets in a transfer.
int32_t	dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
	The number of host channel registers to use.
int32_t	dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
	The number of endpoints in addition to EP0 available for device mode operations.
int32_t	dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies the type of PHY interface to use.
int32_t	dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies the UTMI+ Data Width.
int32_t	dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether the ULPI operates at double or single data rate.
int32_t	dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
int32_t	dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether to use the I2Cinterface for full speed PHY.
int32_t	dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
int32_t	dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num, int32_t val)
	Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
int32_t	dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
int	dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
	Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
int32_t	dwc_otg_get_thr_ctl (dwc_otg_core_if_t *core_if, int fifo_num)
int	dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
	Thresholding length for Tx FIFOs in 32 bit DWORDs.
int32_t	dwc_otg_get_tx_thr_length (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
	Thresholding length for Rx FIFOs in 32 bit DWORDs.
int32_t	dwc_otg_get_rx_thr_length (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether LPM (Link Power Management) support is enabled.
int32_t	dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether PTI enhancement is enabled.
int32_t	dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether MPI enhancement is enabled.
int32_t	dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_adp_enable (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether ADP capability is enabled.
int32_t	dwc_otg_get_param_adp_enable (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
	Specifies whether IC_USB capability is enabled.
int32_t	dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_power_down (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_power_down (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_reload_ctl (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_reload_ctl (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_dev_out_nak (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_dev_out_nak (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_cont_on_bna (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_cont_on_bna (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_ahb_single (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_ahb_single (dwc_otg_core_if_t *core_if)
int	dwc_otg_set_param_otg_ver (dwc_otg_core_if_t *core_if, int32_t val)
int32_t	dwc_otg_get_param_otg_ver (dwc_otg_core_if_t *core_if)
Access to registers and bit-fields
void	dwc_otg_dump_dev_registers (dwc_otg_core_if_t *_core_if)
	Dump core registers and SPRAM.
void	dwc_otg_dump_spram (dwc_otg_core_if_t *_core_if)
	This functions reads the SPRAM and prints its content.
void	dwc_otg_dump_host_registers (dwc_otg_core_if_t *_core_if)
	This function reads the host registers and prints them.
void	dwc_otg_dump_global_registers (dwc_otg_core_if_t *_core_if)
	This function reads the core global registers and prints them.
uint32_t	dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
	Get host negotiation status.
uint32_t	dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
	Get srp status.
void	dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
	Set hnpreq bit in the GOTGCTL register.
uint32_t	dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
	Get Content of SNPSID register.
uint32_t	dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
	Get current mode.
uint32_t	dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
	Get value of hnpcapable field in the GUSBCFG register.
void	dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of hnpcapable field in the GUSBCFG register.
uint32_t	dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
	Get value of srpcapable field in the GUSBCFG register.
void	dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of srpcapable field in the GUSBCFG register.
uint32_t	dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
	Get value of devspeed field in the DCFG register.
void	dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of devspeed field in the DCFG register.
uint32_t	dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
	Get the value of busconnected field from the HPRT0 register.
uint32_t	dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
	Gets the device enumeration Speed.
uint32_t	dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
	Get value of prtpwr field from the HPRT0 register.
uint32_t	dwc_otg_get_core_state (dwc_otg_core_if_t *core_if)
	Get value of flag indicating core state - hibernated or not.
void	dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of prtpwr field from the HPRT0 register.
uint32_t	dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
	Get value of prtsusp field from the HPRT0 regsiter.
void	dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of prtpwr field from the HPRT0 register.
uint32_t	dwc_otg_get_mode_ch_tim (dwc_otg_core_if_t *core_if)
	Get value of ModeChTimEn field from the HCFG regsiter.
void	dwc_otg_set_mode_ch_tim (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of ModeChTimEn field from the HCFG regsiter.
uint32_t	dwc_otg_get_fr_interval (dwc_otg_core_if_t *core_if)
	Get value of Fram Interval field from the HFIR regsiter.
void	dwc_otg_set_fr_interval (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of Frame Interval field from the HFIR regsiter.
void	dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of prtres field from the HPRT0 register FIXME Remove?
uint32_t	dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
	Get value of rmtwkupsig bit in DCTL register.
uint32_t	dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
	Get value of prt_sleep_sts field from the GLPMCFG register.
uint32_t	dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
	Get value of rem_wkup_en field from the GLPMCFG register.
uint32_t	dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
	Get value of appl_resp field from the GLPMCFG register.
void	dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of appl_resp field from the GLPMCFG register.
uint32_t	dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
	Get value of hsic_connect field from the GLPMCFG register.
void	dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of hsic_connect field from the GLPMCFG register.
uint32_t	dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
	Get value of inv_sel_hsic field from the GLPMCFG register.
void	dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
	Set value of inv_sel_hsic field from the GLPMFG register.
uint32_t	dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
	GOTGCTL register.
void	dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
	GUSBCFG register.
void	dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
	GRXFSIZ register.
void	dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
	GNPTXFSIZ register.
void	dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
void	dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
	GGPIO register.
void	dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
	GUID register.
void	dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
	HPRT0 register.
void	dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
uint32_t	dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
	GHPTXFSIZE.
Defines
#define	__DWC_CORE_IF_H__
#define	MAX_PERIO_FIFOS   15
	Maximum number of Periodic FIFOs.
#define	MAX_TX_FIFOS   15
	Maximum number of Periodic FIFOs.
#define	MAX_EPS_CHANNELS   16
	Maximum number of Endpoints/HostChannels.
Typedefs
typedef dwc_otg_core_if	dwc_otg_core_if_t
Functions
dwc_otg_core_if_t *	dwc_otg_cil_init (const uint32_t *_reg_base_addr)
	This function is called to initialize the DWC_otg CSR data structures.
void	dwc_otg_core_init (dwc_otg_core_if_t *_core_if)
	This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
void	dwc_otg_cil_remove (dwc_otg_core_if_t *_core_if)
	This function frees the structures allocated by dwc_otg_cil_init().
void	dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *_core_if)
	This function enables the controller's Global Interrupt in the AHB Config register.
void	dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *_core_if)
	This function disables the controller's Global Interrupt in the AHB Config register.
uint8_t	dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
uint8_t	dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
uint8_t	dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
int32_t	dwc_otg_handle_common_intr (void *otg_dev)
	This function should be called on every hardware interrupt.

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Detailed Description

This file defines DWC_OTG Core API.

Definition in file dwc_otg_core_if.h.

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Function Documentation

dwc_otg_core_if_t* dwc_otg_cil_init (  const uint32_t *  reg_base_addr  )

This function is called to initialize the DWC_otg CSR data structures. The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured. Parameters: reg_base_addr  Base address of DWC_otg core registers ADP initialization Definition at line 78 of file dwc_otg_cil.c.

void dwc_otg_core_init (  dwc_otg_core_if_t *  core_if  )

This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. Parameters: core_if  Programming view of the DWC_otg controller Definition at line 1199 of file dwc_otg_cil.c.

void dwc_otg_cil_remove (  dwc_otg_core_if_t *  core_if  )

This function frees the structures allocated by dwc_otg_cil_init(). Parameters: core_if  The core interface pointer returned from dwc_otg_cil_init(). Remove ADP Stuff Definition at line 285 of file dwc_otg_cil.c.

void dwc_otg_enable_global_interrupts (  dwc_otg_core_if_t *  core_if  )

This function enables the controller's Global Interrupt in the AHB Config register. Parameters: core_if  Programming view of DWC_otg controller. Definition at line 322 of file dwc_otg_cil.c.

void dwc_otg_disable_global_interrupts (  dwc_otg_core_if_t *  core_if  )

This function disables the controller's Global Interrupt in the AHB Config register. Parameters: core_if  Programming view of DWC_otg controller. Definition at line 335 of file dwc_otg_cil.c.

int32_t dwc_otg_handle_common_intr (  void *  dev  )

This function should be called on every hardware interrupt. The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts: Mode Mismatch Interrupt Disconnect Interrupt OTG Interrupt Connector ID Status Change Interrupt Session Request Interrupt. Resume / Remote Wakeup Detected Interrupt. LPM Transaction Received Interrupt ADP Transaction Received Interrupt Definition at line 1275 of file dwc_otg_cil_intr.c.

int dwc_otg_set_param_otg_cap (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies the OTG capabilities. The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable Definition at line 5361 of file dwc_otg_cil.c.

int dwc_otg_set_param_dma_enable (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies whether to use slave or DMA mode for accessing the data FIFOs. The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) Definition at line 5440 of file dwc_otg_cil.c.

int dwc_otg_set_param_dma_desc_enable (  dwc_otg_core_if_t *  core_if, int32_t  val )

When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) Definition at line 5470 of file dwc_otg_cil.c.

int dwc_otg_set_param_dma_burst_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

The DMA Burst size (applicable only for External DMA Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) Definition at line 6275 of file dwc_otg_cil.c.

int dwc_otg_set_param_speed (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies the maximum speed of operation in host and device mode. The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed Definition at line 5904 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_support_fs_ls_low_power (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. 0 - Don't support low power mode (default) 1 - Support low power mode Definition at line 5500 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_ls_low_power_phy_clk (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ. 0 - 48 MHz 1 - 6 MHz Definition at line 5933 of file dwc_otg_cil.c.

int dwc_otg_set_param_data_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

Total number of 4-byte words in the data FIFO memory. This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. Definition at line 5547 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_rx_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. 16 to 32768 (default 1064) Definition at line 5576 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_nperio_tx_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. 16 to 32768 (default 1024) Definition at line 5602 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_perio_tx_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val, int  fifo_num )

Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 4 to 768 (default 256) Definition at line 6085 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_rx_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. 16 to 32768 (default 1024) Definition at line 5635 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_nperio_tx_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. 16 to 32768 (default 1024) Definition at line 5667 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_perio_tx_fifo_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. 16 to 32768 (default 1024) Definition at line 5700 of file dwc_otg_cil.c.

int dwc_otg_set_param_max_transfer_size (  dwc_otg_core_if_t *  core_if, int32_t  val )

The maximum transfer size supported in bytes. 2047 to 65,535 (default 65,535) Definition at line 5731 of file dwc_otg_cil.c.

int dwc_otg_set_param_max_packet_count (  dwc_otg_core_if_t *  core_if, int32_t  val )

The maximum number of packets in a transfer. 15 to 511 (default 511) Definition at line 5764 of file dwc_otg_cil.c.

int dwc_otg_set_param_host_channels (  dwc_otg_core_if_t *  core_if, int32_t  val )

The number of host channel registers to use. 1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. Definition at line 5795 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_endpoints (  dwc_otg_core_if_t *  core_if, int32_t  val )

The number of endpoints in addition to EP0 available for device mode operations. 1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. Definition at line 5825 of file dwc_otg_cil.c.

int dwc_otg_set_param_phy_type (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies the type of PHY interface to use. By default, the driver will automatically detect the phy_type. 0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI Definition at line 5855 of file dwc_otg_cil.c.

int dwc_otg_set_param_phy_utmi_width (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies the UTMI+ Data Width. This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width. 8 or 16 bits (default 16) Definition at line 6005 of file dwc_otg_cil.c.

int dwc_otg_set_param_phy_ulpi_ddr (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies whether the ULPI operates at double or single data rate. This parameter is only applicable if PHY_TYPE is ULPI. 0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus Definition at line 5970 of file dwc_otg_cil.c.

int dwc_otg_set_param_i2c_enable (  dwc_otg_core_if_t *  core_if, int32_t  val )

Specifies whether to use the I2Cinterface for full speed PHY. This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes Definition at line 6056 of file dwc_otg_cil.c.

int dwc_otg_set_param_dev_tx_fifo_size (  dwc_otg_core_if_t *  core_if, int  fifo_num, int32_t  val )

Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 4 to 768 (default 256)

void dwc_otg_dump_dev_registers (  dwc_otg_core_if_t *  core_if  )

Dump core registers and SPRAM. Parameters: core_if  Programming view of DWC_otg controller. Definition at line 4620 of file dwc_otg_cil.c.

void dwc_otg_dump_spram (  dwc_otg_core_if_t *  core_if  )

This functions reads the SPRAM and prints its content. Parameters: core_if  Programming view of DWC_otg controller. Definition at line 4756 of file dwc_otg_cil.c.

void dwc_otg_dump_host_registers (  dwc_otg_core_if_t *  core_if  )

This function reads the host registers and prints them. Parameters: core_if  Programming view of DWC_otg controller. Definition at line 4784 of file dwc_otg_cil.c.

void dwc_otg_dump_global_registers (  dwc_otg_core_if_t *  core_if  )

This function reads the core global registers and prints them. Parameters: core_if  Programming view of DWC_otg controller. Definition at line 4853 of file dwc_otg_cil.c.

uint32_t dwc_otg_get_mode (  dwc_otg_core_if_t *  core_if  )

Get current mode. Returns 0 if in device mode, and 1 if in host mode. Definition at line 6653 of file dwc_otg_cil.c.

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