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00051 #include "dwc_otg_os_dep.h"
00052 #include "dwc_os.h"
00053 #include "dwc_otg_dbg.h"
00054 #include "dwc_otg_driver.h"
00055 #include "dwc_otg_attr.h"
00056 #include "dwc_otg_core_if.h"
00057 #include "dwc_otg_pcd_if.h"
00058 #include "dwc_otg_hcd_if.h"
00059
00060 #define DWC_DRIVER_VERSION "2.94a 27-OCT-2011"
00061 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
00062
00063 static const char dwc_driver_name[] = "dwc_otg";
00064
00065 extern int pcd_init(
00066 #ifdef LM_INTERFACE
00067 struct lm_device *_dev
00068 #elif defined(PCI_INTERFACE)
00069 struct pci_dev *_dev
00070 #endif
00071 );
00072 extern int hcd_init(
00073 #ifdef LM_INTERFACE
00074 struct lm_device *_dev
00075 #elif defined(PCI_INTERFACE)
00076 struct pci_dev *_dev
00077 #endif
00078 );
00079
00080 extern int pcd_remove(
00081 #ifdef LM_INTERFACE
00082 struct lm_device *_dev
00083 #elif defined(PCI_INTERFACE)
00084 struct pci_dev *_dev
00085 #endif
00086 );
00087
00088 extern void hcd_remove(
00089 #ifdef LM_INTERFACE
00090 struct lm_device *_dev
00091 #elif defined(PCI_INTERFACE)
00092 struct pci_dev *_dev
00093 #endif
00094 );
00095
00096 extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
00097
00098
00099
00100
00101 struct dwc_otg_driver_module_params {
00102 int32_t opt;
00103 int32_t otg_cap;
00104 int32_t dma_enable;
00105 int32_t dma_desc_enable;
00106 int32_t dma_burst_size;
00107 int32_t speed;
00108 int32_t host_support_fs_ls_low_power;
00109 int32_t host_ls_low_power_phy_clk;
00110 int32_t enable_dynamic_fifo;
00111 int32_t data_fifo_size;
00112 int32_t dev_rx_fifo_size;
00113 int32_t dev_nperio_tx_fifo_size;
00114 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
00115 int32_t host_rx_fifo_size;
00116 int32_t host_nperio_tx_fifo_size;
00117 int32_t host_perio_tx_fifo_size;
00118 int32_t max_transfer_size;
00119 int32_t max_packet_count;
00120 int32_t host_channels;
00121 int32_t dev_endpoints;
00122 int32_t phy_type;
00123 int32_t phy_utmi_width;
00124 int32_t phy_ulpi_ddr;
00125 int32_t phy_ulpi_ext_vbus;
00126 int32_t i2c_enable;
00127 int32_t ulpi_fs_ls;
00128 int32_t ts_dline;
00129 int32_t en_multiple_tx_fifo;
00130 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
00131 uint32_t thr_ctl;
00132 uint32_t tx_thr_length;
00133 uint32_t rx_thr_length;
00134 int32_t pti_enable;
00135 int32_t mpi_enable;
00136 int32_t lpm_enable;
00137 int32_t ic_usb_cap;
00138 int32_t ahb_thr_ratio;
00139 int32_t power_down;
00140 int32_t reload_ctl;
00141 int32_t dev_out_nak;
00142 int32_t cont_on_bna;
00143 int32_t ahb_single;
00144 int32_t otg_ver;
00145 int32_t adp_enable;
00146 };
00147
00148 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
00149 .opt = -1,
00150 .otg_cap = -1,
00151 .dma_enable = -1,
00152 .dma_desc_enable = -1,
00153 .dma_burst_size = -1,
00154 .speed = -1,
00155 .host_support_fs_ls_low_power = -1,
00156 .host_ls_low_power_phy_clk = -1,
00157 .enable_dynamic_fifo = -1,
00158 .data_fifo_size = -1,
00159 .dev_rx_fifo_size = -1,
00160 .dev_nperio_tx_fifo_size = -1,
00161 .dev_perio_tx_fifo_size = {
00162
00163 -1,
00164 -1,
00165 -1,
00166 -1,
00167 -1,
00168 -1,
00169 -1,
00170 -1,
00171 -1,
00172 -1,
00173 -1,
00174 -1,
00175 -1,
00176 -1,
00177 -1
00178
00179 },
00180 .host_rx_fifo_size = -1,
00181 .host_nperio_tx_fifo_size = -1,
00182 .host_perio_tx_fifo_size = -1,
00183 .max_transfer_size = -1,
00184 .max_packet_count = -1,
00185 .host_channels = -1,
00186 .dev_endpoints = -1,
00187 .phy_type = -1,
00188 .phy_utmi_width = -1,
00189 .phy_ulpi_ddr = -1,
00190 .phy_ulpi_ext_vbus = -1,
00191 .i2c_enable = -1,
00192 .ulpi_fs_ls = -1,
00193 .ts_dline = -1,
00194 .en_multiple_tx_fifo = -1,
00195 .dev_tx_fifo_size = {
00196
00197 -1,
00198 -1,
00199 -1,
00200 -1,
00201 -1,
00202 -1,
00203 -1,
00204 -1,
00205 -1,
00206 -1,
00207 -1,
00208 -1,
00209 -1,
00210 -1,
00211 -1
00212
00213 },
00214 .thr_ctl = -1,
00215 .tx_thr_length = -1,
00216 .rx_thr_length = -1,
00217 .pti_enable = -1,
00218 .mpi_enable = -1,
00219 .lpm_enable = -1,
00220 .ic_usb_cap = -1,
00221 .ahb_thr_ratio = -1,
00222 .power_down = -1,
00223 .reload_ctl = -1,
00224 .dev_out_nak = -1,
00225 .cont_on_bna = -1,
00226 .ahb_single = -1,
00227 .otg_ver = -1,
00228 .adp_enable = -1,
00229 };
00230
00234 static ssize_t version_show(struct device_driver *dev, char *buf)
00235 {
00236 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
00237 DWC_DRIVER_VERSION);
00238 }
00239
00240 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
00241
00245 uint32_t g_dbg_lvl = 0;
00246
00250 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
00251 {
00252 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
00253 }
00254
00258 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
00259 size_t count)
00260 {
00261 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
00262 return count;
00263 }
00264
00265 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
00266 dbg_level_store);
00267
00272 static int set_parameters(dwc_otg_core_if_t * core_if)
00273 {
00274 int retval = 0;
00275 int i;
00276
00277 if (dwc_otg_module_params.otg_cap != -1) {
00278 retval +=
00279 dwc_otg_set_param_otg_cap(core_if,
00280 dwc_otg_module_params.otg_cap);
00281 }
00282 if (dwc_otg_module_params.dma_enable != -1) {
00283 retval +=
00284 dwc_otg_set_param_dma_enable(core_if,
00285 dwc_otg_module_params.
00286 dma_enable);
00287 }
00288 if (dwc_otg_module_params.dma_desc_enable != -1) {
00289 retval +=
00290 dwc_otg_set_param_dma_desc_enable(core_if,
00291 dwc_otg_module_params.
00292 dma_desc_enable);
00293 }
00294 if (dwc_otg_module_params.opt != -1) {
00295 retval +=
00296 dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
00297 }
00298 if (dwc_otg_module_params.dma_burst_size != -1) {
00299 retval +=
00300 dwc_otg_set_param_dma_burst_size(core_if,
00301 dwc_otg_module_params.
00302 dma_burst_size);
00303 }
00304 if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
00305 retval +=
00306 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
00307 dwc_otg_module_params.
00308 host_support_fs_ls_low_power);
00309 }
00310 if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
00311 retval +=
00312 dwc_otg_set_param_enable_dynamic_fifo(core_if,
00313 dwc_otg_module_params.
00314 enable_dynamic_fifo);
00315 }
00316 if (dwc_otg_module_params.data_fifo_size != -1) {
00317 retval +=
00318 dwc_otg_set_param_data_fifo_size(core_if,
00319 dwc_otg_module_params.
00320 data_fifo_size);
00321 }
00322 if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
00323 retval +=
00324 dwc_otg_set_param_dev_rx_fifo_size(core_if,
00325 dwc_otg_module_params.
00326 dev_rx_fifo_size);
00327 }
00328 if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
00329 retval +=
00330 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
00331 dwc_otg_module_params.
00332 dev_nperio_tx_fifo_size);
00333 }
00334 if (dwc_otg_module_params.host_rx_fifo_size != -1) {
00335 retval +=
00336 dwc_otg_set_param_host_rx_fifo_size(core_if,
00337 dwc_otg_module_params.host_rx_fifo_size);
00338 }
00339 if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
00340 retval +=
00341 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
00342 dwc_otg_module_params.
00343 host_nperio_tx_fifo_size);
00344 }
00345 if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
00346 retval +=
00347 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
00348 dwc_otg_module_params.
00349 host_perio_tx_fifo_size);
00350 }
00351 if (dwc_otg_module_params.max_transfer_size != -1) {
00352 retval +=
00353 dwc_otg_set_param_max_transfer_size(core_if,
00354 dwc_otg_module_params.
00355 max_transfer_size);
00356 }
00357 if (dwc_otg_module_params.max_packet_count != -1) {
00358 retval +=
00359 dwc_otg_set_param_max_packet_count(core_if,
00360 dwc_otg_module_params.
00361 max_packet_count);
00362 }
00363 if (dwc_otg_module_params.host_channels != -1) {
00364 retval +=
00365 dwc_otg_set_param_host_channels(core_if,
00366 dwc_otg_module_params.
00367 host_channels);
00368 }
00369 if (dwc_otg_module_params.dev_endpoints != -1) {
00370 retval +=
00371 dwc_otg_set_param_dev_endpoints(core_if,
00372 dwc_otg_module_params.
00373 dev_endpoints);
00374 }
00375 if (dwc_otg_module_params.phy_type != -1) {
00376 retval +=
00377 dwc_otg_set_param_phy_type(core_if,
00378 dwc_otg_module_params.phy_type);
00379 }
00380 if (dwc_otg_module_params.speed != -1) {
00381 retval +=
00382 dwc_otg_set_param_speed(core_if,
00383 dwc_otg_module_params.speed);
00384 }
00385 if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
00386 retval +=
00387 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
00388 dwc_otg_module_params.
00389 host_ls_low_power_phy_clk);
00390 }
00391 if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
00392 retval +=
00393 dwc_otg_set_param_phy_ulpi_ddr(core_if,
00394 dwc_otg_module_params.
00395 phy_ulpi_ddr);
00396 }
00397 if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
00398 retval +=
00399 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
00400 dwc_otg_module_params.
00401 phy_ulpi_ext_vbus);
00402 }
00403 if (dwc_otg_module_params.phy_utmi_width != -1) {
00404 retval +=
00405 dwc_otg_set_param_phy_utmi_width(core_if,
00406 dwc_otg_module_params.
00407 phy_utmi_width);
00408 }
00409 if (dwc_otg_module_params.ulpi_fs_ls != -1) {
00410 retval +=
00411 dwc_otg_set_param_ulpi_fs_ls(core_if,
00412 dwc_otg_module_params.ulpi_fs_ls);
00413 }
00414 if (dwc_otg_module_params.ts_dline != -1) {
00415 retval +=
00416 dwc_otg_set_param_ts_dline(core_if,
00417 dwc_otg_module_params.ts_dline);
00418 }
00419 if (dwc_otg_module_params.i2c_enable != -1) {
00420 retval +=
00421 dwc_otg_set_param_i2c_enable(core_if,
00422 dwc_otg_module_params.
00423 i2c_enable);
00424 }
00425 if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
00426 retval +=
00427 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
00428 dwc_otg_module_params.
00429 en_multiple_tx_fifo);
00430 }
00431 for (i = 0; i < 15; i++) {
00432 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
00433 retval +=
00434 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
00435 dwc_otg_module_params.
00436 dev_perio_tx_fifo_size
00437 [i], i);
00438 }
00439 }
00440
00441 for (i = 0; i < 15; i++) {
00442 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
00443 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
00444 dwc_otg_module_params.
00445 dev_tx_fifo_size
00446 [i], i);
00447 }
00448 }
00449 if (dwc_otg_module_params.thr_ctl != -1) {
00450 retval +=
00451 dwc_otg_set_param_thr_ctl(core_if,
00452 dwc_otg_module_params.thr_ctl);
00453 }
00454 if (dwc_otg_module_params.mpi_enable != -1) {
00455 retval +=
00456 dwc_otg_set_param_mpi_enable(core_if,
00457 dwc_otg_module_params.
00458 mpi_enable);
00459 }
00460 if (dwc_otg_module_params.pti_enable != -1) {
00461 retval +=
00462 dwc_otg_set_param_pti_enable(core_if,
00463 dwc_otg_module_params.
00464 pti_enable);
00465 }
00466 if (dwc_otg_module_params.lpm_enable != -1) {
00467 retval +=
00468 dwc_otg_set_param_lpm_enable(core_if,
00469 dwc_otg_module_params.
00470 lpm_enable);
00471 }
00472 if (dwc_otg_module_params.ic_usb_cap != -1) {
00473 retval +=
00474 dwc_otg_set_param_ic_usb_cap(core_if,
00475 dwc_otg_module_params.
00476 ic_usb_cap);
00477 }
00478 if (dwc_otg_module_params.tx_thr_length != -1) {
00479 retval +=
00480 dwc_otg_set_param_tx_thr_length(core_if,
00481 dwc_otg_module_params.tx_thr_length);
00482 }
00483 if (dwc_otg_module_params.rx_thr_length != -1) {
00484 retval +=
00485 dwc_otg_set_param_rx_thr_length(core_if,
00486 dwc_otg_module_params.
00487 rx_thr_length);
00488 }
00489 if (dwc_otg_module_params.ahb_thr_ratio != -1) {
00490 retval +=
00491 dwc_otg_set_param_ahb_thr_ratio(core_if,
00492 dwc_otg_module_params.ahb_thr_ratio);
00493 }
00494 if (dwc_otg_module_params.power_down != -1) {
00495 retval +=
00496 dwc_otg_set_param_power_down(core_if,
00497 dwc_otg_module_params.power_down);
00498 }
00499 if (dwc_otg_module_params.reload_ctl != -1) {
00500 retval +=
00501 dwc_otg_set_param_reload_ctl(core_if,
00502 dwc_otg_module_params.reload_ctl);
00503 }
00504
00505 if (dwc_otg_module_params.dev_out_nak != -1) {
00506 retval +=
00507 dwc_otg_set_param_dev_out_nak(core_if,
00508 dwc_otg_module_params.dev_out_nak);
00509 }
00510
00511 if (dwc_otg_module_params.cont_on_bna != -1) {
00512 retval +=
00513 dwc_otg_set_param_cont_on_bna(core_if,
00514 dwc_otg_module_params.cont_on_bna);
00515 }
00516
00517 if (dwc_otg_module_params.ahb_single != -1) {
00518 retval +=
00519 dwc_otg_set_param_ahb_single(core_if,
00520 dwc_otg_module_params.ahb_single);
00521 }
00522
00523 if (dwc_otg_module_params.otg_ver != -1) {
00524 retval +=
00525 dwc_otg_set_param_otg_ver(core_if,
00526 dwc_otg_module_params.otg_ver);
00527 }
00528 if (dwc_otg_module_params.adp_enable != -1) {
00529 retval +=
00530 dwc_otg_set_param_adp_enable(core_if,
00531 dwc_otg_module_params.
00532 adp_enable);
00533 }
00534 return retval;
00535 }
00536
00541 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
00542 {
00543 int32_t retval = IRQ_NONE;
00544
00545 retval = dwc_otg_handle_common_intr(dev);
00546 if (retval != 0) {
00547 S3C2410X_CLEAR_EINTPEND();
00548 }
00549 return IRQ_RETVAL(retval);
00550 }
00551
00561 static void dwc_otg_driver_remove(
00562 #ifdef LM_INTERFACE
00563 struct lm_device *_dev
00564 #elif defined(PCI_INTERFACE)
00565 struct pci_dev *_dev
00566 #endif
00567 )
00568 {
00569 #ifdef LM_INTERFACE
00570 dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
00571 #elif defined(PCI_INTERFACE)
00572 dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
00573 #endif
00574
00575 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
00576
00577 if (!otg_dev) {
00578
00579 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
00580 return;
00581 }
00582 #ifndef DWC_DEVICE_ONLY
00583 if (otg_dev->hcd) {
00584 hcd_remove(_dev);
00585 } else {
00586 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
00587 return;
00588 }
00589 #endif
00590
00591 #ifndef DWC_HOST_ONLY
00592 if (otg_dev->pcd) {
00593 pcd_remove(_dev);
00594 } else {
00595 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
00596 return;
00597 }
00598 #endif
00599
00600
00601
00602 if (otg_dev->common_irq_installed) {
00603 free_irq(_dev->irq, otg_dev);
00604 } else {
00605 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
00606 return;
00607 }
00608
00609 if (otg_dev->core_if) {
00610 dwc_otg_cil_remove(otg_dev->core_if);
00611 } else {
00612 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
00613 return;
00614 }
00615
00616
00617
00618
00619 dwc_otg_attr_remove(_dev);
00620
00621
00622
00623
00624 if (otg_dev->os_dep.base) {
00625 iounmap(otg_dev->os_dep.base);
00626 }
00627 DWC_FREE(otg_dev);
00628
00629
00630
00631
00632 #ifdef LM_INTERFACE
00633 lm_set_drvdata(_dev, 0);
00634 #elif defined(PCI_INTERFACE)
00635 release_mem_region(otg_dev->os_dep.rsrc_start, otg_dev->os_dep.rsrc_len);
00636 pci_set_drvdata(_dev, 0);
00637 #endif
00638 }
00639
00651 static int dwc_otg_driver_probe(
00652 #ifdef LM_INTERFACE
00653 struct lm_device *_dev
00654 #elif defined(PCI_INTERFACE)
00655 struct pci_dev *_dev,
00656 const struct pci_device_id *id
00657 #endif
00658 )
00659 {
00660 int retval = 0;
00661 dwc_otg_device_t *dwc_otg_device;
00662
00663 dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
00664 #ifdef LM_INTERFACE
00665 dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
00666 #elif defined(PCI_INTERFACE)
00667 if (!id) {
00668 DWC_ERROR("Invalid pci_device_id %p", id);
00669 return -EINVAL;
00670 }
00671
00672 if (!_dev || (pci_enable_device(_dev) < 0)) {
00673 DWC_ERROR("Invalid pci_device %p", _dev);
00674 return -ENODEV;
00675 }
00676 dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
00677
00678
00679 #endif
00680
00681 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
00682
00683 if (!dwc_otg_device) {
00684 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
00685 return -ENOMEM;
00686 }
00687
00688 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
00689 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
00690
00691
00692
00693
00694 #ifdef LM_INTERFACE
00695 dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
00696
00697 if (!dwc_otg_device->os_dep.base) {
00698 dev_err(&_dev->dev, "ioremap() failed\n");
00699 DWC_FREE(dwc_otg_device);
00700 return -ENOMEM;
00701 }
00702 dev_dbg(&_dev->dev, "base=0x%08x\n",
00703 (unsigned)dwc_otg_device->os_dep.base);
00704 #elif defined(PCI_INTERFACE)
00705 _dev->current_state = PCI_D0;
00706 _dev->dev.power.power_state = PMSG_ON;
00707
00708 if (!_dev->irq) {
00709 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
00710 pci_name(_dev));
00711 iounmap(dwc_otg_device->os_dep.base);
00712 DWC_FREE(dwc_otg_device);
00713 return -ENODEV;
00714 }
00715
00716 dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
00717 dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
00718 DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
00719 (unsigned)dwc_otg_device->os_dep.rsrc_start,
00720 (unsigned)dwc_otg_device->os_dep.rsrc_len);
00721 if (!request_mem_region
00722 (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
00723 "dwc_otg")) {
00724 dev_dbg(&_dev->dev, "error requesting memory\n");
00725 iounmap(dwc_otg_device->os_dep.base);
00726 DWC_FREE(dwc_otg_device);
00727 return -EFAULT;
00728 }
00729
00730 dwc_otg_device->os_dep.base =
00731 ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
00732 dwc_otg_device->os_dep.rsrc_len);
00733 if (dwc_otg_device->os_dep.base == NULL) {
00734 dev_dbg(&_dev->dev, "error mapping memory\n");
00735 release_mem_region(dwc_otg_device->os_dep.rsrc_start,
00736 dwc_otg_device->os_dep.rsrc_len);
00737 iounmap(dwc_otg_device->os_dep.base);
00738 DWC_FREE(dwc_otg_device);
00739 return -EFAULT;
00740 }
00741 dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
00742 dwc_otg_device->os_dep.base);
00743 dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
00744 dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
00745 dwc_otg_device->os_dep.base);
00746 dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
00747 (unsigned)dwc_otg_device->os_dep.rsrc_start,
00748 dwc_otg_device->os_dep.base);
00749
00750 pci_set_master(_dev);
00751 pci_set_drvdata(_dev, dwc_otg_device);
00752 #endif
00753
00754
00755
00756
00757
00758 #ifdef LM_INTERFACE
00759 lm_set_drvdata(_dev, dwc_otg_device);
00760 #endif
00761 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
00762
00763 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
00764 if (!dwc_otg_device->core_if) {
00765 dev_err(&_dev->dev, "CIL initialization failed!\n");
00766 retval = -ENOMEM;
00767 goto fail;
00768 }
00769
00770
00771
00772
00773
00774
00775
00776 if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
00777 0x4F542000) {
00778 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
00779 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
00780 retval = -EINVAL;
00781 goto fail;
00782 }
00783
00784
00785
00786
00787 if (set_parameters(dwc_otg_device->core_if)) {
00788 retval = -EINVAL;
00789 goto fail;
00790 }
00791
00792
00793
00794
00795 dwc_otg_attr_create(_dev);
00796
00797
00798
00799
00800
00801 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
00802
00803
00804
00805
00806
00807 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
00808 _dev->irq);
00809 retval = request_irq(_dev->irq, dwc_otg_common_irq,
00810 IRQF_SHARED | IRQF_DISABLED | IRQ_LEVEL, "dwc_otg",
00811 dwc_otg_device);
00812 if (retval) {
00813 DWC_ERROR("request of irq%d failed\n", _dev->irq);
00814 retval = -EBUSY;
00815 goto fail;
00816 } else {
00817 dwc_otg_device->common_irq_installed = 1;
00818 }
00819
00820 #ifdef LM_INTERFACE
00821 set_irq_type(_dev->irq, IRQT_LOW);
00822 #endif
00823
00824
00825
00826 dwc_otg_core_init(dwc_otg_device->core_if);
00827
00828 #ifndef DWC_HOST_ONLY
00829
00830
00831
00832 retval = pcd_init(_dev);
00833 if (retval != 0) {
00834 DWC_ERROR("pcd_init failed\n");
00835 dwc_otg_device->pcd = NULL;
00836 goto fail;
00837 }
00838 #endif
00839 #ifndef DWC_DEVICE_ONLY
00840
00841
00842
00843 retval = hcd_init(_dev);
00844 if (retval != 0) {
00845 DWC_ERROR("hcd_init failed\n");
00846 dwc_otg_device->hcd = NULL;
00847 goto fail;
00848 }
00849 #endif
00850 #ifdef PCI_INTERFACE
00851 pci_set_drvdata(_dev, dwc_otg_device);
00852 dwc_otg_device->os_dep.pcidev = _dev;
00853 #endif
00854
00855
00856
00857
00858
00859
00860 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))
00861 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
00862 else
00863 dwc_otg_adp_start(dwc_otg_device->core_if,
00864 dwc_otg_is_host_mode(dwc_otg_device->core_if));
00865
00866 return 0;
00867
00868 fail:
00869 dwc_otg_driver_remove(_dev);
00870 return retval;
00871 }
00872
00884 #ifdef LM_INTERFACE
00885 static struct lm_driver dwc_otg_driver = {
00886 .drv = {.name = (char *)dwc_driver_name,},
00887 .probe = dwc_otg_driver_probe,
00888 .remove = dwc_otg_driver_remove,
00889 };
00890 #elif defined(PCI_INTERFACE)
00891 static const struct pci_device_id pci_ids[] = { {
00892 PCI_DEVICE(0x16c3, 0xabcd),
00893 .driver_data =
00894 (unsigned long)0xdeadbeef,
00895 }, { }
00896 };
00897
00898 MODULE_DEVICE_TABLE(pci, pci_ids);
00899
00900
00901 static struct pci_driver dwc_otg_driver = {
00902 .name = "dwc_otg",
00903 .id_table = pci_ids,
00904
00905 .probe = dwc_otg_driver_probe,
00906 .remove = dwc_otg_driver_remove,
00907
00908 .driver = {
00909 .name = (char *)dwc_driver_name,
00910 },
00911 };
00912 #endif
00913
00924 static int __init dwc_otg_driver_init(void)
00925 {
00926 int retval = 0;
00927 int error;
00928 printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
00929 DWC_DRIVER_VERSION);
00930 #ifdef LM_INTERFACE
00931 retval = lm_driver_register(&dwc_otg_driver);
00932 #elif defined(PCI_INTERFACE)
00933 retval = pci_register_driver(&dwc_otg_driver);
00934 #endif
00935 if (retval < 0) {
00936 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
00937 return retval;
00938 }
00939 #ifdef LM_INTERFACE
00940 error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
00941 error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
00942 #elif defined(PCI_INTERFACE)
00943 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
00944 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
00945 #endif
00946 return retval;
00947 }
00948
00949 module_init(dwc_otg_driver_init);
00950
00957 static void __exit dwc_otg_driver_cleanup(void)
00958 {
00959 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
00960
00961 #ifdef LM_INTERFACE
00962 driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
00963 driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
00964 lm_driver_unregister(&dwc_otg_driver);
00965 #elif defined(PCI_INTERFACE)
00966 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
00967 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
00968 pci_unregister_driver(&dwc_otg_driver);
00969 #endif
00970
00971 printk(KERN_INFO "%s module removed\n", dwc_driver_name);
00972 }
00973
00974 module_exit(dwc_otg_driver_cleanup);
00975
00976 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
00977 MODULE_AUTHOR("Synopsys Inc.");
00978 MODULE_LICENSE("GPL");
00979
00980 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
00981 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
00982 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
00983 MODULE_PARM_DESC(opt, "OPT Mode");
00984 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
00985 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
00986
00987 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
00988 0444);
00989 MODULE_PARM_DESC(dma_desc_enable,
00990 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
00991
00992 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
00993 0444);
00994 MODULE_PARM_DESC(dma_burst_size,
00995 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
00996 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
00997 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
00998 module_param_named(host_support_fs_ls_low_power,
00999 dwc_otg_module_params.host_support_fs_ls_low_power, int,
01000 0444);
01001 MODULE_PARM_DESC(host_support_fs_ls_low_power,
01002 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
01003 module_param_named(host_ls_low_power_phy_clk,
01004 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
01005 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
01006 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
01007 module_param_named(enable_dynamic_fifo,
01008 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
01009 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
01010 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
01011 0444);
01012 MODULE_PARM_DESC(data_fifo_size,
01013 "Total number of words in the data FIFO memory 32-32768");
01014 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
01015 int, 0444);
01016 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
01017 module_param_named(dev_nperio_tx_fifo_size,
01018 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
01019 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
01020 "Number of words in the non-periodic Tx FIFO 16-32768");
01021 module_param_named(dev_perio_tx_fifo_size_1,
01022 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
01023 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
01024 "Number of words in the periodic Tx FIFO 4-768");
01025 module_param_named(dev_perio_tx_fifo_size_2,
01026 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
01027 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
01028 "Number of words in the periodic Tx FIFO 4-768");
01029 module_param_named(dev_perio_tx_fifo_size_3,
01030 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
01031 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
01032 "Number of words in the periodic Tx FIFO 4-768");
01033 module_param_named(dev_perio_tx_fifo_size_4,
01034 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
01035 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
01036 "Number of words in the periodic Tx FIFO 4-768");
01037 module_param_named(dev_perio_tx_fifo_size_5,
01038 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
01039 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
01040 "Number of words in the periodic Tx FIFO 4-768");
01041 module_param_named(dev_perio_tx_fifo_size_6,
01042 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
01043 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
01044 "Number of words in the periodic Tx FIFO 4-768");
01045 module_param_named(dev_perio_tx_fifo_size_7,
01046 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
01047 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
01048 "Number of words in the periodic Tx FIFO 4-768");
01049 module_param_named(dev_perio_tx_fifo_size_8,
01050 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
01051 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
01052 "Number of words in the periodic Tx FIFO 4-768");
01053 module_param_named(dev_perio_tx_fifo_size_9,
01054 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
01055 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
01056 "Number of words in the periodic Tx FIFO 4-768");
01057 module_param_named(dev_perio_tx_fifo_size_10,
01058 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
01059 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
01060 "Number of words in the periodic Tx FIFO 4-768");
01061 module_param_named(dev_perio_tx_fifo_size_11,
01062 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
01063 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
01064 "Number of words in the periodic Tx FIFO 4-768");
01065 module_param_named(dev_perio_tx_fifo_size_12,
01066 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
01067 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
01068 "Number of words in the periodic Tx FIFO 4-768");
01069 module_param_named(dev_perio_tx_fifo_size_13,
01070 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
01071 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
01072 "Number of words in the periodic Tx FIFO 4-768");
01073 module_param_named(dev_perio_tx_fifo_size_14,
01074 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
01075 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
01076 "Number of words in the periodic Tx FIFO 4-768");
01077 module_param_named(dev_perio_tx_fifo_size_15,
01078 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
01079 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
01080 "Number of words in the periodic Tx FIFO 4-768");
01081 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
01082 int, 0444);
01083 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
01084 module_param_named(host_nperio_tx_fifo_size,
01085 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
01086 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
01087 "Number of words in the non-periodic Tx FIFO 16-32768");
01088 module_param_named(host_perio_tx_fifo_size,
01089 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
01090 MODULE_PARM_DESC(host_perio_tx_fifo_size,
01091 "Number of words in the host periodic Tx FIFO 16-32768");
01092 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
01093 int, 0444);
01095 MODULE_PARM_DESC(max_transfer_size,
01096 "The maximum transfer size supported in bytes 2047-65535");
01097 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
01098 int, 0444);
01099 MODULE_PARM_DESC(max_packet_count,
01100 "The maximum number of packets in a transfer 15-511");
01101 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
01102 0444);
01103 MODULE_PARM_DESC(host_channels,
01104 "The number of host channel registers to use 1-16");
01105 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
01106 0444);
01107 MODULE_PARM_DESC(dev_endpoints,
01108 "The number of endpoints in addition to EP0 available for device mode 1-15");
01109 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
01110 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
01111 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
01112 0444);
01113 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
01114 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
01115 MODULE_PARM_DESC(phy_ulpi_ddr,
01116 "ULPI at double or single data rate 0=Single 1=Double");
01117 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
01118 int, 0444);
01119 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
01120 "ULPI PHY using internal or external vbus 0=Internal");
01121 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
01122 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
01123 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
01124 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
01125 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
01126 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
01127 module_param_named(debug, g_dbg_lvl, int, 0444);
01128 MODULE_PARM_DESC(debug, "");
01129
01130 module_param_named(en_multiple_tx_fifo,
01131 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
01132 MODULE_PARM_DESC(en_multiple_tx_fifo,
01133 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
01134 module_param_named(dev_tx_fifo_size_1,
01135 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
01136 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
01137 module_param_named(dev_tx_fifo_size_2,
01138 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
01139 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
01140 module_param_named(dev_tx_fifo_size_3,
01141 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
01142 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
01143 module_param_named(dev_tx_fifo_size_4,
01144 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
01145 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
01146 module_param_named(dev_tx_fifo_size_5,
01147 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
01148 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
01149 module_param_named(dev_tx_fifo_size_6,
01150 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
01151 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
01152 module_param_named(dev_tx_fifo_size_7,
01153 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
01154 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
01155 module_param_named(dev_tx_fifo_size_8,
01156 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
01157 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
01158 module_param_named(dev_tx_fifo_size_9,
01159 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
01160 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
01161 module_param_named(dev_tx_fifo_size_10,
01162 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
01163 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
01164 module_param_named(dev_tx_fifo_size_11,
01165 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
01166 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
01167 module_param_named(dev_tx_fifo_size_12,
01168 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
01169 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
01170 module_param_named(dev_tx_fifo_size_13,
01171 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
01172 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
01173 module_param_named(dev_tx_fifo_size_14,
01174 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
01175 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
01176 module_param_named(dev_tx_fifo_size_15,
01177 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
01178 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
01179
01180 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
01181 MODULE_PARM_DESC(thr_ctl,
01182 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
01183 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
01184 0444);
01185 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
01186 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
01187 0444);
01188 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
01189
01190 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
01191 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
01192 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
01193 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
01194 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
01195 MODULE_PARM_DESC(ic_usb_cap,
01196 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
01197 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
01198 0444);
01199 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
01200 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
01201 MODULE_PARM_DESC(power_down, "Power Down Mode");
01202 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
01203 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
01204 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
01205 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
01206 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
01207 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
01208 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
01209 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
01210 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
01211 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
01212 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
01213 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
01214
