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dwc_otg_pcd_intr.c File Reference

This file contains the implementation of the PCD Interrupt handlers. More...

#include "dwc_otg_pcd.h"

Go to the source code of this file.

Defines

#define DEBUG_EP0
#define CLEAR_IN_EP_INTR(__core_if, __epnum, __intr)
#define CLEAR_OUT_EP_INTR(__core_if, __epnum, __intr)

Functions

void dwc_otg_pcd_update_otg (dwc_otg_pcd_t *pcd, const unsigned reset)
 This function updates OTG.
void print_ep0_state (dwc_otg_pcd_t *pcd)
 This function prints the ep0 state for debug purposes.
void print_memory_payload (dwc_otg_pcd_t *pcd, dwc_ep_t *ep)
 This function calculate the size of the payload in the memory for out endpoints and prints size for debug purposes(used in 2.93a DevOutNak feature).
dwc_otg_pcd_ep_t * get_in_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
 This function returns pointer to in ep struct with number ep_num.
dwc_otg_pcd_ep_t * get_out_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
 This function returns pointer to out ep struct with number ep_num.
dwc_otg_pcd_ep_t * get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
 This functions gets a pointer to an EP from the wIndex address value of the control request.
void start_next_request (dwc_otg_pcd_ep_t *ep)
 Tasklet.
int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *pcd)
 This function handles the SOF Interrupts.
int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
 This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.
int get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
 This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.
int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *pcd)
 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
int32_t write_empty_tx_fifo (dwc_otg_pcd_t *pcd, uint32_t epnum)
 This function is called when dedicated Tx FIFO Empty interrupt occurs.
void dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
 This function is called when the Device is disconnected.
int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that ...
int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that ...
void ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
 This function configures EPO to receive SETUP packets.
int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *pcd)
 This interrupt occurs when a USB Reset is detected.
int get_device_speed (dwc_otg_core_if_t *core_if)
 Get the device speed from the device status register and convert it to USB speed constant.
int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *pcd)
 Read the device status register and set the device speed in the data structure.
int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.
int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates the end of the portion of the micro-frame for periodic transactions.
int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.
int32_t dwc_otg_pcd_handle_ep_fetsusp_intr (dwc_otg_pcd_t *pcd)
 This interrupt is valid only in DMA mode.
void ep0_do_stall (dwc_otg_pcd_t *pcd, const int err_val)
 This funcion stalls EP0.
void do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
 This functions delegates the setup command to the gadget driver.
void do_setup_in_status_phase (dwc_otg_pcd_t *pcd)
 This function starts the Zero-Length Packet for the IN status phase of a 2 stage control transfer.
void do_setup_out_status_phase (dwc_otg_pcd_t *pcd)
 This function starts the Zero-Length Packet for the OUT status phase of a 2 stage control transfer.
void pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
 Clear the EP halt (STALL) and if pending requests start the transfer.
void do_test_mode (void *data)
 This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
void do_get_status (dwc_otg_pcd_t *pcd)
 This function process the GET_STATUS Setup Commands.
void do_set_feature (dwc_otg_pcd_t *pcd)
 This function process the SET_FEATURE Setup Commands.
void do_clear_feature (dwc_otg_pcd_t *pcd)
 This function process the CLEAR_FEATURE Setup Commands.
void do_set_address (dwc_otg_pcd_t *pcd)
 This function process the SET_ADDRESS Setup Commands.
void pcd_setup (dwc_otg_pcd_t *pcd)
 This function processes SETUP commands.
int32_t ep0_complete_request (dwc_otg_pcd_ep_t *ep)
 This function completes the ep0 control transfer.
void complete_ep (dwc_otg_pcd_ep_t *ep)
 This function completes the request for the EP.
void dwc_otg_pcd_handle_iso_bna (dwc_otg_pcd_ep_t *ep)
 This function BNA interrupt for Isochronous EPs.
void set_current_pkt_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function sets latest iso packet information(non-PTI mode).
void set_ddma_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function sets latest iso packet information(DDMA mode).
void reinit_ddma_iso_xfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function reinitialize DMA Descriptors for Isochronous transfer.
uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.
uint32_t set_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function sets iso packets information(PTI mode).
void complete_iso_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
 This function is to handle Iso EP transfer complete interrupt.
void dwc_otg_pcd_handle_noniso_bna (dwc_otg_pcd_ep_t *ep)
 This function handle BNA interrupt for Non Isochronous EPs.
void handle_ep0 (dwc_otg_pcd_t *pcd)
 This function handles EP0 Control transfers.
void restart_transfer (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Restart transfer.
void predict_nextep_seq (dwc_otg_core_if_t *core_if)
void handle_in_ep_disable_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 handle the IN EP disable interrupt.
void handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the IN EP timeout handshake interrupt.
int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the IN EP NAK interrupt.
int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the OUT EP Babble interrupt.
int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the OUT EP NAK interrupt.
int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the OUT EP NYET interrupt.
int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that an IN EP has a pending Interrupt.
int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that an OUT EP has a pending Interrupt.
int drop_transfer (uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *pcd)
 Incomplete ISO IN Transfer Interrupt.
int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *pcd)
 Incomplete ISO OUT Transfer Interrupt.
int32_t dwc_otg_pcd_handle_in_nak_effective (dwc_otg_pcd_t *pcd)
 This function handles the Global IN NAK Effective interrupt.
int32_t dwc_otg_pcd_handle_out_nak_effective (dwc_otg_pcd_t *pcd)
 OUT NAK Effective.
int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
 This function should be called on every hardware interrupt.

Detailed Description

This file contains the implementation of the PCD Interrupt handlers.

The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below. All interrupt registers are processed from LSB to MSB.

Definition in file dwc_otg_pcd_intr.c.

Define Documentation

#define CLEAR_IN_EP_INTR (  __core_if,
__epnum,
__intr   ) 
 

Value:

do { \
                diepint_data_t diepint = {.d32=0}; \
                diepint.b.__intr = 1; \
                DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
                diepint.d32); \
} while (0)

#define CLEAR_OUT_EP_INTR (  __core_if,
__epnum,
__intr   ) 
 

Value:

do { \
                doepint_data_t doepint = {.d32=0}; \
                doepint.b.__intr = 1; \
                DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
                doepint.d32); \
} while (0)

Function Documentation

int32_t dwc_otg_pcd_handle_sof_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This function handles the SOF Interrupts.

At this time the SOF Interrupt is disabled.

Definition at line 298 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.

The packets are moved from the FIFO to memory, where they will be processed when the Endpoint Interrupt Register indicates Transfer Complete or SETUP Phase Done.

Repeat the following until the Rx Status Queue is empty:

  1. Read the Receive Status Pop Register (GRXSTSP) to get Packet info
  2. If Receive FIFO is empty then skip to step Clear the interrupt and exit
  3. If SETUP Packet call dwc_otg_read_setup_packet to copy the SETUP data to the buffer
  4. If OUT Data Packet call dwc_otg_read_packet to copy the data to the destination buffer

Todo:
NGS Check for buffer overflow?

Definition at line 331 of file dwc_otg_pcd_intr.c.

int get_ep_of_last_in_token (  dwc_otg_core_if_t *  core_if  )  [inline, static]
 

This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.

This implementation is for the Mass Storage device where there are only 2 IN EPs (Control-IN and BULK-IN).

The EP numbers for the first six IN Tokens are in DTKNQR1 and there are 8 EP Numbers in each of the other possible DTKNQ Registers.

Parameters:
core_if Programming view of DWC_otg controller.

Todo:
Find a simpler way to calculate the max queue position.

Definition at line 424 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This interrupt occurs when the non-periodic Tx FIFO is half-empty.

The active request is checked for the next packet to be loaded into the non-periodic Tx FIFO.

Definition at line 497 of file dwc_otg_pcd_intr.c.

int32_t write_empty_tx_fifo (  dwc_otg_pcd_t *  pcd,
uint32_t  epnum
)  [static]
 

This function is called when dedicated Tx FIFO Empty interrupt occurs.

The active request is checked for the next packet to be loaded into apropriate Tx FIFO.

Definition at line 561 of file dwc_otg_pcd_intr.c.

void dwc_otg_pcd_stop (  dwc_otg_pcd_t *  pcd  ) 
 

This function is called when the Device is disconnected.

It stops any active requests and informs the Gadget driver of the disconnect.

Todo:
NGS Flush Periodic FIFOs

Definition at line 619 of file dwc_otg_pcd_intr.c.

void ep0_out_start (  dwc_otg_core_if_t *  core_if,
dwc_otg_pcd_t *  pcd
)  [inline, static]
 

This function configures EPO to receive SETUP packets.

Todo:
NGS: Update the comments from the HW FS.
  1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
  • DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
  • DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)
    • In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received

Parameters:
core_if Programming view of DWC_otg controller.
pcd Programming view of the PCD.

put here as for Hermes mode deptisz register should not be written

Todo:
dma needs to handle multiple setup packets (up to 3)

DMA Descriptor Setup

DOEPDMA0 Register write

put here as for Hermes mode deptisz register should not be written

DOEPCTL0 Register write

Definition at line 732 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_usb_reset_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This interrupt occurs when a USB Reset is detected.

When the USB Reset Interrupt occurs the device state is set to DEFAULT and the EP0 state is set to IDLE.

  1. Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
  2. Unmask the following interrupt bits
    • DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
  • DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
  • DOEPMSK.SETUP = 1
  • DOEPMSK.XferCompl = 1
  • DIEPMSK.XferCompl = 1
  • DIEPMSK.TimeOut = 1
  1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
  • DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
  • DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)
    • In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received At this point, all the required initialization, except for enabling the control 0 OUT endpoint is done, for receiving SETUP packets.

Definition at line 822 of file dwc_otg_pcd_intr.c.

int get_device_speed (  dwc_otg_core_if_t *  core_if  )  [static]
 

Get the device speed from the device status register and convert it to USB speed constant.

Parameters:
core_if Programming view of DWC_otg controller.

Definition at line 1007 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_enum_done_intr (  dwc_otg_pcd_t *  pcd  ) 
 

Read the device status register and set the device speed in the data structure.

Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.

Definition at line 1035 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.

If this interrupt occurs read all the data from the Rx FIFO.

Definition at line 1130 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This interrupt indicates the end of the portion of the micro-frame for periodic transactions.

If there is a periodic transaction for the next frame, load the packets into the EP periodic Tx FIFO.

Definition at line 1156 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_ep_mismatch_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.

The "Device IN Token Queue" Registers are read to determine the order the IN Tokens have been received. The non-periodic Tx FIFO is flushed, so it can be reloaded in the order seen in the IN Token Queue.

Definition at line 1184 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_ep_fetsusp_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This interrupt is valid only in DMA mode.

This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.

Parameters:
pcd The PCD

Definition at line 1232 of file dwc_otg_pcd_intr.c.

void do_gadget_setup (  dwc_otg_pcd_t *  pcd,
usb_device_request_t *  ctrl
)  [inline, static]
 

This functions delegates the setup command to the gadget driver.

Todo:
This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.

Definition at line 1277 of file dwc_otg_pcd_intr.c.

void pcd_clear_halt (  dwc_otg_pcd_t *  pcd,
dwc_otg_pcd_ep_t *  ep
)  [inline, static]
 

Clear the EP halt (STALL) and if pending requests start the transfer.

Todo:
FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.

Definition at line 1384 of file dwc_otg_pcd_intr.c.

void do_test_mode (  void *  data  ) 
 

This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.

The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

Todo:
This has not been tested since the tasklet struct was put into the PCD struct!

Definition at line 1423 of file dwc_otg_pcd_intr.c.

void do_get_status (  dwc_otg_pcd_t *  pcd  )  [inline, static]
 

This function process the GET_STATUS Setup Commands.

Todo:
check for EP stall

Definition at line 1460 of file dwc_otg_pcd_intr.c.

void do_set_feature (  dwc_otg_pcd_t *  pcd  )  [inline, static]
 

This function process the SET_FEATURE Setup Commands.

Todo:
This has not been tested since the tasklet struct was put into the PCD struct!

Is the gotgctl.devhnpen cleared by a USB Reset?

Definition at line 1533 of file dwc_otg_pcd_intr.c.

void do_clear_feature (  dwc_otg_pcd_t *  pcd  )  [inline, static]
 

This function process the CLEAR_FEATURE Setup Commands.

Todo:
Add CLEAR_FEATURE for TEST modes.

Definition at line 1644 of file dwc_otg_pcd_intr.c.

void pcd_setup (  dwc_otg_pcd_t *  pcd  )  [inline, static]
 

This function processes SETUP commands.

In Linux, the USB Command processing is done in two places - the first being the PCD and the second in the Gadget Driver (for example, the File-Backed Storage Gadget Driver).

Command Driver Description

GET_STATUS PCD Command is processed as defined in chapter 9 of the USB 2.0 Specification chapter 9

CLEAR_FEATURE PCD The Device and Endpoint requests are the ENDPOINT_HALT feature is procesed, all others the interface requests are ignored.

SET_FEATURE PCD The Device and Endpoint requests are processed by the PCD. Interface requests are passed to the Gadget Driver.

SET_ADDRESS PCD Program the DCFG reg, with device address received

GET_DESCRIPTOR Gadget Driver Return the requested descriptor

SET_DESCRIPTOR Gadget Driver Optional - not implemented by any of the existing Gadget Drivers.

SET_CONFIGURATION Gadget Driver Disable all EPs and enable EPs for new configuration.

GET_CONFIGURATION Gadget Driver Return the current configuration

SET_INTERFACE Gadget Driver Disable all EPs and enable EPs for new configuration.

GET_INTERFACE Gadget Driver Return the current interface.

SYNC_FRAME PCD Display debug message.

When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are processed by pcd_setup. Calling the Function Driver's setup function from pcd_setup processes the gadget SETUP commands.

Todo:
handle > 1 setup packet , assert error for now

NGS: Handle bad setup packet?

Definition at line 1756 of file dwc_otg_pcd_intr.c.

void complete_ep (  dwc_otg_pcd_ep_t *  ep  )  [static]
 

This function completes the request for the EP.

If there are additional requests for the EP in the queue they will be started.

Definition at line 2088 of file dwc_otg_pcd_intr.c.

void set_current_pkt_info (  dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep
) 
 

This function sets latest iso packet information(non-PTI mode).

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Definition at line 2490 of file dwc_otg_pcd_intr.c.

void set_ddma_iso_pkts_info (  dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep
)  [static]
 

This function sets latest iso packet information(DDMA mode).

Parameters:
core_if Programming view of DWC_otg controller.
dwc_ep The EP to start the transfer on.

Reinit closed DMA Descriptors

ISO OUT EP

ISO IN EP

Definition at line 2538 of file dwc_otg_pcd_intr.c.

void reinit_ddma_iso_xfer (  dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep
)  [static]
 

This function reinitialize DMA Descriptors for Isochronous transfer.

Parameters:
core_if Programming view of DWC_otg controller.
dwc_ep The EP to start the transfer on.

Buffer 0 descriptors setup

Buffer 1 descriptors setup

Reinit closed DMA Descriptors

ISO OUT EP

ISO IN EP

Definition at line 2701 of file dwc_otg_pcd_intr.c.

uint32_t handle_iso_out_pkt_dropped (  dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep
)  [static]
 

This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.

Parameters:
core_if Programming view of DWC_otg controller.
dwc_ep The EP for wihich transfer complete was asserted

Re-enable endpoint, clear nak

Definition at line 2835 of file dwc_otg_pcd_intr.c.

uint32_t set_iso_pkts_info (  dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep
)  [static]
 

This function sets iso packets information(PTI mode).

Parameters:
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.

Buffer 0 descriptors setup

Buffer 1 descriptors setup

Definition at line 2906 of file dwc_otg_pcd_intr.c.

void complete_iso_ep (  dwc_otg_pcd_t *  pcd,
dwc_otg_pcd_ep_t *  ep
)  [static]
 

This function is to handle Iso EP transfer complete interrupt.

Parameters:
pcd The PCD
ep The EP for which transfer complete was asserted

Definition at line 2982 of file dwc_otg_pcd_intr.c.

void handle_ep0 (  dwc_otg_pcd_t *  pcd  )  [static]
 

This function handles EP0 Control transfers.

The state of the control tranfers are tracked in ep0state.

Definition at line 3110 of file dwc_otg_pcd_intr.c.

void handle_in_ep_timeout_intr (  dwc_otg_pcd_t *  pcd,
const uint32_t  epnum
)  [inline, static]
 

Handler for the IN EP timeout handshake interrupt.

Todo:
NGS Check EP type. Implement for Periodic EPs

Definition at line 3611 of file dwc_otg_pcd_intr.c.

int32_t handle_in_ep_nak_intr (  dwc_otg_pcd_t *  pcd,
const uint32_t  epnum
)  [inline, static]
 

Handler for the IN EP NAK interrupt.

Todo:
implement ISR

Definition at line 3672 of file dwc_otg_pcd_intr.c.

int32_t handle_out_ep_babble_intr (  dwc_otg_pcd_t *  pcd,
const uint32_t  epnum
)  [inline, static]
 

Handler for the OUT EP Babble interrupt.

Todo:
implement ISR

Definition at line 3697 of file dwc_otg_pcd_intr.c.

int32_t handle_out_ep_nak_intr (  dwc_otg_pcd_t *  pcd,
const uint32_t  epnum
)  [inline, static]
 

Handler for the OUT EP NAK interrupt.

Todo:
implement ISR

Definition at line 3723 of file dwc_otg_pcd_intr.c.

int32_t handle_out_ep_nyet_intr (  dwc_otg_pcd_t *  pcd,
const uint32_t  epnum
)  [inline, static]
 

Handler for the OUT EP NYET interrupt.

Todo:
implement ISR

Definition at line 3748 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_in_ep_intr (  dwc_otg_pcd_t *  pcd  )  [static]
 

This interrupt indicates that an IN EP has a pending Interrupt.

The sequence for handling the IN EP interrupt is shown below:

  1. Read the Device All Endpoint Interrupt register
  2. Repeat the following for each IN EP interrupt bit set (from LSB to MSB).
  3. Read the Device Endpoint Interrupt (DIEPINTn) register
  4. If "Transfer Complete" call the request complete function
  5. If "Endpoint Disabled" complete the EP disable procedure.
  6. If "AHB Error Interrupt" log error
  7. If "Time-out Handshake" log error
  8. If "IN Token Received when TxFIFO Empty" write packet to Tx FIFO.
  9. If "IN Token EP Mismatch" (disable, this is handled by EP Mismatch Interrupt)

IN Token received with TxF Empty

IN Token Received with EP mismatch

IN Endpoint NAK Effective

IN EP Tx FIFO Empty Intr

IN EP BNA Intr

Definition at line 3786 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_out_ep_intr (  dwc_otg_pcd_t *  pcd  )  [static]
 

This interrupt indicates that an OUT EP has a pending Interrupt.

The sequence for handling the OUT EP interrupt is shown below:

  1. Read the Device All Endpoint Interrupt register
  2. Repeat the following for each OUT EP interrupt bit set (from LSB to MSB).
  3. Read the Device Endpoint Interrupt (DOEPINTn) register
  4. If "Transfer Complete" call the request complete function
  5. If "Endpoint Disabled" complete the EP disable procedure.
  6. If "AHB Error Interrupt" log error
  7. If "Setup Phase Done" process Setup Packet (See Standard USB Command Processing)

OUT EP BNA Intr

Definition at line 4068 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (  dwc_otg_pcd_t *  pcd  ) 
 

Incomplete ISO IN Transfer Interrupt.

This interrupt indicates one of the following conditions occurred while transmitting an ISOC transaction.

  • Corrupted IN Token for ISOC EP.
  • Packet not complete in FIFO. The follow actions will be taken:
    1. Determine the EP
    2. Set incomplete flag in dwc_ep structure
    3. Disable EP; when "Endpoint Disabled" interrupt is received Flush FIFO

Definition at line 4348 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (  dwc_otg_pcd_t *  pcd  ) 
 

Incomplete ISO OUT Transfer Interrupt.

This interrupt indicates that the core has dropped an ISO OUT packet. The following conditions can be the cause:

  • FIFO Full, the entire packet would not fit in the FIFO.
  • CRC Error
  • Corrupted Token The follow actions will be taken:
    1. Determine the EP
    2. Set incomplete flag in dwc_ep structure
    3. Read any data from the FIFO
    4. Disable EP. When "Endpoint Disabled" interrupt is received re-enable EP.

Definition at line 4458 of file dwc_otg_pcd_intr.c.

int32_t dwc_otg_pcd_handle_intr (  dwc_otg_pcd_t *  pcd  ) 
 

This function should be called on every hardware interrupt.

The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

All interrupt registers are processed from LSB to MSB.

Definition at line 4702 of file dwc_otg_pcd_intr.c.

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