dwc_hc Struct Reference

Host channel descriptor. More...

#include <dwc_otg_cil.h>

Public Member Functions
	DWC_CIRCLEQ_ENTRY (dwc_hc) hc_list_entry
	Entry in list of host channels.
Data Fields
uint8_t	hc_num
	Host channel number used for register address lookup.
unsigned	dev_addr:7
	Device to access.
unsigned	ep_num:4
	EP to access.
unsigned	ep_is_in:1
	EP direction.
unsigned	speed:2
	EP speed.
unsigned	ep_type:2
	Endpoint type.
unsigned	max_packet:11
	Max packet size in bytes.
unsigned	data_pid_start:2
	PID for initial transaction.
unsigned	multi_count:2
	Number of periodic transactions per (micro)frame.
Transfer State
uint8_t *	xfer_buff
	Pointer to the current transfer buffer position.
dwc_dma_t	align_buff
	In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned.
uint32_t	xfer_len
	Total number of bytes to transfer.
uint32_t	xfer_count
	Number of bytes transferred so far.
uint16_t	start_pkt_count
	Packet count at start of transfer.
uint8_t	xfer_started
	Flag to indicate whether the transfer has been started.
uint8_t	do_ping
	Set to 1 to indicate that a PING request should be issued on this channel.
uint8_t	error_state
	Set to 1 to indicate that the error count for this transaction is non-zero.
uint8_t	halt_on_queue
	Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel.
uint8_t	halt_pending
	Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests.
dwc_otg_halt_status_e	halt_status
	Reason for halting the host channel.
uint8_t	do_split
	Enable split for the channel.
uint8_t	complete_split
	Enable complete split.
uint8_t	hub_addr
	Address of high speed hub.
uint8_t	port_addr
	Port of the low/full speed device.
uint8_t	xact_pos
	Split transaction position One of the following values: DWC_HCSPLIT_XACTPOS_MID DWC_HCSPLIT_XACTPOS_BEGIN DWC_HCSPLIT_XACTPOS_END DWC_HCSPLIT_XACTPOS_ALL.
uint8_t	short_read
	Set when the host channel does a short read.
uint8_t	requests
	Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs).
dwc_otg_qh *	qh
	Queue Head for the transfer being processed by this channel.
Descriptor DMA support
uint16_t	ntd
	Number of Transfer Descriptors.
dwc_dma_t	desc_list_addr
	Descriptor List DMA address.
uint8_t	schinfo
	Scheduling micro-frame bitmap.

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Detailed Description

Host channel descriptor.

This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel.

Definition at line 260 of file dwc_otg_cil.h.

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Field Documentation

unsigned dwc_hc::ep_is_in

EP direction. 0: OUT, 1: IN Definition at line 271 of file dwc_otg_cil.h.

unsigned dwc_hc::speed

EP speed. One of the following values: DWC_OTG_EP_SPEED_LOW DWC_OTG_EP_SPEED_FULL DWC_OTG_EP_SPEED_HIGH Definition at line 280 of file dwc_otg_cil.h.

unsigned dwc_hc::ep_type

Endpoint type. One of the following values: DWC_OTG_EP_TYPE_CONTROL: 0 DWC_OTG_EP_TYPE_ISOC: 1 DWC_OTG_EP_TYPE_BULK: 2 DWC_OTG_EP_TYPE_INTR: 3 Definition at line 293 of file dwc_otg_cil.h.

unsigned dwc_hc::data_pid_start

PID for initial transaction. 0: DATA0, 1: DATA2, 2: DATA1, 3: MDATA (non-Control EP), SETUP (Control EP) Definition at line 306 of file dwc_otg_cil.h.

dwc_dma_t dwc_hc::align_buff

In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned. Definition at line 325 of file dwc_otg_cil.h.

uint8_t dwc_hc::xfer_started

Flag to indicate whether the transfer has been started. Set to 1 if it has been started, 0 otherwise. Definition at line 337 of file dwc_otg_cil.h.

uint8_t dwc_hc::do_ping

Set to 1 to indicate that a PING request should be issued on this channel. If 0, process normally. Definition at line 343 of file dwc_otg_cil.h.

uint8_t dwc_hc::error_state

Set to 1 to indicate that the error count for this transaction is non-zero. Set to 0 if the error count is 0. Definition at line 349 of file dwc_otg_cil.h.

uint8_t dwc_hc::halt_on_queue

Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel. This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel. Definition at line 357 of file dwc_otg_cil.h.

uint8_t dwc_hc::halt_pending

Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests. Otherwise 0. Definition at line 363 of file dwc_otg_cil.h.

dwc_otg_halt_status_e dwc_hc::halt_status

Reason for halting the host channel. Definition at line 368 of file dwc_otg_cil.h.

uint8_t dwc_hc::xact_pos

Split transaction position One of the following values: DWC_HCSPLIT_XACTPOS_MID DWC_HCSPLIT_XACTPOS_BEGIN DWC_HCSPLIT_XACTPOS_END DWC_HCSPLIT_XACTPOS_ALL. * - * - * - Definition at line 384 of file dwc_otg_cil.h.

uint8_t dwc_hc::requests

Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs). Definition at line 393 of file dwc_otg_cil.h.

struct dwc_otg_qh* dwc_hc::qh

Queue Head for the transfer being processed by this channel. Definition at line 398 of file dwc_otg_cil.h.

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The documentation for this struct was generated from the following file:

• dwc_otg_cil.h

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