dwc_otg_core_global_regs Struct Reference

DWC_otg Core registers . More...

#include <dwc_otg_regs.h>

Data Fields
volatile uint32_t	gotgctl
	OTG Control and Status Register.
volatile uint32_t	gotgint
	OTG Interrupt Register.
volatile uint32_t	gahbcfg
	Core AHB Configuration Register.
volatile uint32_t	gusbcfg
	Core USB Configuration Register.
volatile uint32_t	grstctl
	Core Reset Register.
volatile uint32_t	gintsts
	Core Interrupt Register.
volatile uint32_t	gintmsk
	Core Interrupt Mask Register.
volatile uint32_t	grxstsr
	Receive Status Queue Read Register (Read Only).
volatile uint32_t	grxstsp
	Receive Status Queue Read & POP Register (Read Only).
volatile uint32_t	grxfsiz
	Receive FIFO Size Register.
volatile uint32_t	gnptxfsiz
	Non Periodic Transmit FIFO Size Register.
volatile uint32_t	gnptxsts
	Non Periodic Transmit FIFO/Queue Status Register (Read Only).
volatile uint32_t	gi2cctl
	I2C Access Register.
volatile uint32_t	gpvndctl
	PHY Vendor Control Register.
volatile uint32_t	ggpio
	General Purpose Input/Output Register.
volatile uint32_t	guid
	User ID Register.
volatile uint32_t	gsnpsid
	Synopsys ID Register (Read Only).
volatile uint32_t	ghwcfg1
	User HW Config1 Register (Read Only).
volatile uint32_t	ghwcfg2
	User HW Config2 Register (Read Only).
volatile uint32_t	ghwcfg3
	User HW Config3 Register (Read Only).
volatile uint32_t	ghwcfg4
	User HW Config4 Register (Read Only).
volatile uint32_t	glpmcfg
	Core LPM Configuration register Offset: 054h.
volatile uint32_t	gpwrdn
	Global PowerDn Register Offset: 058h.
volatile uint32_t	gdfifocfg
	Global DFIFO SW Config Register Offset: 05Ch.
volatile uint32_t	adpctl
	ADP Control Register Offset: 060h.
volatile uint32_t	reserved39 [39]
	Reserved Offset: 064h-0FFh.
volatile uint32_t	hptxfsiz
	Host Periodic Transmit FIFO Size Register.
volatile uint32_t	dtxfsiz [15]
	Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO#n Register.

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Detailed Description

DWC_otg Core registers .

The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers.

Definition at line 71 of file dwc_otg_regs.h.

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Field Documentation

volatile uint32_t dwc_otg_core_global_regs::gotgctl

OTG Control and Status Register. Offset: 000h Definition at line 73 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gotgint

OTG Interrupt Register. Offset: 004h Definition at line 75 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gahbcfg

Core AHB Configuration Register. Offset: 008h Definition at line 77 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gusbcfg

Core USB Configuration Register. Offset: 00Ch Definition at line 87 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::grstctl

Core Reset Register. Offset: 010h Definition at line 89 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gintsts

Core Interrupt Register. Offset: 014h Definition at line 91 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gintmsk

Core Interrupt Mask Register. Offset: 018h Definition at line 93 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::grxstsr

Receive Status Queue Read Register (Read Only). Offset: 01Ch Definition at line 95 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::grxstsp

Receive Status Queue Read & POP Register (Read Only). Offset: 020h Definition at line 97 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::grxfsiz

Receive FIFO Size Register. Offset: 024h Definition at line 99 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gnptxfsiz

Non Periodic Transmit FIFO Size Register. Offset: 028h Definition at line 101 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gnptxsts

Non Periodic Transmit FIFO/Queue Status Register (Read Only). Offset: 02Ch Definition at line 104 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gi2cctl

I2C Access Register. Offset: 030h Definition at line 106 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gpvndctl

PHY Vendor Control Register. Offset: 034h Definition at line 108 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::ggpio

General Purpose Input/Output Register. Offset: 038h Definition at line 110 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::guid

User ID Register. Offset: 03Ch Definition at line 112 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::gsnpsid

Synopsys ID Register (Read Only). Offset: 040h Definition at line 114 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::ghwcfg1

User HW Config1 Register (Read Only). Offset: 044h Definition at line 116 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::ghwcfg2

User HW Config2 Register (Read Only). Offset: 048h Definition at line 118 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::ghwcfg3

User HW Config3 Register (Read Only). Offset: 04Ch Definition at line 132 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::ghwcfg4

User HW Config4 Register (Read Only). Offset: 050h Definition at line 134 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::hptxfsiz

Host Periodic Transmit FIFO Size Register. Offset: 100h Definition at line 146 of file dwc_otg_regs.h.

volatile uint32_t dwc_otg_core_global_regs::dtxfsiz[15]

Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO#n Register. Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). Definition at line 150 of file dwc_otg_regs.h.

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The documentation for this struct was generated from the following file:

• dwc_otg_regs.h

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