dwc_otg_core_if Struct Reference

The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. More...

#include <dwc_otg_cil.h>

Data Fields
dwc_otg_core_params_t *	core_params
	Parameters that define how the core should be configured.
dwc_otg_core_global_regs_t *	core_global_regs
	Core Global registers starting at offset 000h.
dwc_otg_dev_if_t *	dev_if
	Device-specific information.
dwc_otg_host_if_t *	host_if
	Host-specific information.
uint32_t	snpsid
	Value from SNPSID register.
uint8_t	phy_init_done
uint8_t	srp_success
uint8_t	srp_timer_started
dwc_timer_t *	srp_timer
	Timer for SRP.
volatile uint32_t *	pcgcctl
	Power and Clock Gating Control Register.
uint32_t *	data_fifo [MAX_EPS_CHANNELS]
	Push/pop addresses for endpoints or host channels.
uint16_t	total_fifo_size
	Total RAM for FIFOs (Bytes).
uint16_t	rx_fifo_size
	Size of Rx FIFO (Bytes).
uint16_t	nperio_tx_fifo_size
	Size of Non-periodic Tx FIFO (Bytes).
uint8_t	dma_enable
	1 if DMA is enabled, 0 otherwise.
uint8_t	dma_desc_enable
	1 if DMA descriptor is enabled, 0 otherwise.
uint8_t	pti_enh_enable
	1 if PTI Enhancement mode is enabled, 0 otherwise.
uint8_t	multiproc_int_enable
	1 if MPI Enhancement mode is enabled, 0 otherwise.
uint8_t	en_multiple_tx_fifo
	1 if dedicated Tx FIFOs are enabled, 0 otherwise.
uint8_t	queuing_high_bandwidth
	Set to 1 if multiple packets of a high-bandwidth transfer is in process of being queued.
hwcfg1_data_t	hwcfg1
	Hardware Configuration -- stored here for convenience.
hwcfg2_data_t	hwcfg2
hwcfg3_data_t	hwcfg3
hwcfg4_data_t	hwcfg4
fifosize_data_t	hptxfsiz
hcfg_data_t	hcfg
	Host and Device Configuration -- stored here for convenience.
dcfg_data_t	dcfg
uint8_t	op_state
	The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions.
uint8_t	restart_hcd_on_session_req
	Set to 1 if the HCD needs to be restarted on a session request interrupt.
dwc_otg_cil_callbacks *	hcd_cb
	HCD callbacks.
dwc_otg_cil_callbacks *	pcd_cb
	PCD callbacks.
uint32_t	p_tx_msk
	Device mode Periodic Tx FIFO Mask.
uint32_t	tx_msk
	Device mode Periodic Tx FIFO Mask.
dwc_workq_t *	wq_otg
	Workqueue object used for handling several interrupts.
dwc_timer_t *	wkp_timer
	Timer object used for handling "Wakeup Detected" Interrupt.
uint32_t	start_doeptsiz_val [MAX_EPS_CHANNELS]
	This arrays used for debug purposes for DEV OUT NAK enhancement.
ep_xfer_info_t	ep_xfer_info [MAX_EPS_CHANNELS]
dwc_timer_t *	ep_xfer_timer [MAX_EPS_CHANNELS]
dwc_otg_lx_state_e	lx_state
	Lx state of device.
dwc_otg_global_regs_backup *	gr_backup
	Saved Core Global registers.
dwc_otg_host_regs_backup *	hr_backup
	Saved Host registers.
dwc_otg_dev_regs_backup *	dr_backup
	Saved Device registers.
uint32_t	power_down
	Power Down Enable.
uint32_t	adp_enable
	ADP support Enable.
dwc_otg_adp_t	adp
	ADP structure object.
int	hibernation_suspend
	hibernation/suspend flag
uint32_t	otg_ver
	OTG revision supported.
uint8_t	otg_sts
	OTG status flag used for HNP polling.
dwc_spinlock_t *	lock
	Pointer to either hcd->lock or pcd->lock.
uint8_t	start_predict
	Start predict NextEP based on Learning Queue if equal 1, also used as counter of disabled NP IN EP's.
uint8_t	nextep_seq [MAX_EPS_CHANNELS]
	NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and active, 0xff otherwise.
uint8_t	first_in_nextep_seq
	Index of fisrt EP in nextep_seq array which should be re-enabled *.
uint32_t	frame_num
	Frame number while entering to ISR - needed for ISOCs *.

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Detailed Description

The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode.

It represents the programming view of the controller as a whole.

Definition at line 792 of file dwc_otg_cil.h.

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Field Documentation

dwc_timer_t* dwc_otg_core_if::srp_timer

Timer for SRP. If it expires before SRP is successful clear the SRP. Definition at line 820 of file dwc_otg_cil.h.

uint8_t dwc_otg_core_if::op_state

The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions. Definition at line 881 of file dwc_otg_cil.h.

uint8_t dwc_otg_core_if::restart_hcd_on_session_req

Set to 1 if the HCD needs to be restarted on a session request interrupt. This is required if no connector ID status change has occurred since the HCD was last disconnected. Definition at line 888 of file dwc_otg_cil.h.

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The documentation for this struct was generated from the following file:

• dwc_otg_cil.h

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