#include <dwc_otg_cil.h>
Data Fields | |
| int32_t | opt |
| int32_t | otg_cap |
| Specifies the OTG capabilities. | |
| int32_t | dma_enable |
| Specifies whether to use slave or DMA mode for accessing the data FIFOs. | |
| int32_t | dma_desc_enable |
| When DMA mode is enabled specifies whether to use address DMA or DMA Descriptor mode for accessing the data FIFOs in device mode. | |
| int32_t | dma_burst_size |
| The DMA Burst size (applicable only for External DMA Mode). | |
| int32_t | speed |
| Specifies the maximum speed of operation in host and device mode. | |
| int32_t | host_support_fs_ls_low_power |
| Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. | |
| int32_t | host_ls_low_power_phy_clk |
| Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. | |
| int32_t | enable_dynamic_fifo |
| 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default) | |
| int32_t | data_fifo_size |
| Total number of 4-byte words in the data FIFO memory. | |
| int32_t | dev_rx_fifo_size |
| Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. | |
| int32_t | dev_nperio_tx_fifo_size |
| Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. | |
| uint32_t | dev_perio_tx_fifo_size [MAX_PERIO_FIFOS] |
| Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. | |
| int32_t | host_rx_fifo_size |
| Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. | |
| int32_t | host_nperio_tx_fifo_size |
| Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. | |
| int32_t | host_perio_tx_fifo_size |
| Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. | |
| int32_t | max_transfer_size |
| The maximum transfer size supported in bytes. | |
| int32_t | max_packet_count |
| The maximum number of packets in a transfer. | |
| int32_t | host_channels |
| The number of host channel registers to use. | |
| int32_t | dev_endpoints |
| The number of endpoints in addition to EP0 available for device mode operations. | |
| int32_t | phy_type |
| Specifies the type of PHY interface to use. | |
| int32_t | phy_utmi_width |
| Specifies the UTMI+ Data Width. | |
| int32_t | phy_ulpi_ddr |
| Specifies whether the ULPI operates at double or single data rate. | |
| int32_t | phy_ulpi_ext_vbus |
| Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy. | |
| int32_t | i2c_enable |
| Specifies whether to use the I2Cinterface for full speed PHY. | |
| int32_t | ulpi_fs_ls |
| int32_t | ts_dline |
| int32_t | en_multiple_tx_fifo |
| Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes. | |
| uint32_t | dev_tx_fifo_size [MAX_TX_FIFOS] |
| Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. | |
| uint32_t | thr_ctl |
| Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding. | |
| uint32_t | tx_thr_length |
| Thresholding length for Tx FIFOs in 32 bit DWORDs. | |
| uint32_t | rx_thr_length |
| Thresholding length for Rx FIFOs in 32 bit DWORDs. | |
| int32_t | lpm_enable |
| Specifies whether LPM (Link Power Management) support is enabled. | |
| int32_t | pti_enable |
| Per Transfer Interrupt mode enable flag 1 - Enabled 0 - Disabled. | |
| int32_t | mpi_enable |
| Multi Processor Interrupt mode enable flag 1 - Enabled 0 - Disabled. | |
| int32_t | ic_usb_cap |
| IS_USB Capability 1 - Enabled 0 - Disabled. | |
| int32_t | ahb_thr_ratio |
| AHB Threshold Ratio 2'b00 AHB Threshold = MAC Threshold 2'b01 AHB Threshold = 1/2 MAC Threshold 2'b10 AHB Threshold = 1/4 MAC Threshold 2'b11 AHB Threshold = 1/8 MAC Threshold. | |
| int32_t | adp_supp_enable |
| ADP Support 1 - Enabled 0 - Disabled. | |
| int32_t | reload_ctl |
| HFIR Reload Control 0 - The HFIR cannot be reloaded dynamically. | |
| int32_t | dev_out_nak |
| DCFG: Enable device Out NAK 0 - The core does not set NAK after Bulk Out transfer complete. | |
| int32_t | cont_on_bna |
| DCFG: Enable Continue on BNA After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the core starts processing 0 - from the DOEPDMA descriptor 1 - from the descriptor which received the BNA. | |
| int32_t | ahb_single |
| GAHBCFG: AHB Single Support This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation. | |
| int32_t | power_down |
| Core Power down mode 0 - No Power Down is enabled 1 - Reserved 2 - Complete Power Down (Hibernation). | |
| int32_t | otg_ver |
| OTG revision supported 0 - OTG 1.3 revision 1 - OTG 2.0 revision. | |
These parameters define how the DWC_otg controller should be configured.
Definition at line 424 of file dwc_otg_cil.h.
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Specifies the OTG capabilities. The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable Definition at line 434 of file dwc_otg_cil.h. |
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Specifies whether to use slave or DMA mode for accessing the data FIFOs. The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) Definition at line 443 of file dwc_otg_cil.h. |
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When DMA mode is enabled specifies whether to use address DMA or DMA Descriptor mode for accessing the data FIFOs in device mode. The driver will automatically detect the value for this if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) Definition at line 452 of file dwc_otg_cil.h. |
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The DMA Burst size (applicable only for External DMA Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) Definition at line 456 of file dwc_otg_cil.h. |
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Specifies the maximum speed of operation in host and device mode. The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed Definition at line 466 of file dwc_otg_cil.h. |
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Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. 0 - Don't support low power mode (default) 1 - Support low power mode Definition at line 472 of file dwc_otg_cil.h. |
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Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ. 0 - 48 MHz 1 - 6 MHz Definition at line 482 of file dwc_otg_cil.h. |
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Total number of 4-byte words in the data FIFO memory. This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. Definition at line 496 of file dwc_otg_cil.h. |
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Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. 16 to 32768 (default 1064) Definition at line 502 of file dwc_otg_cil.h. |
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Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. 16 to 32768 (default 1024) Definition at line 508 of file dwc_otg_cil.h. |
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Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 4 to 768 (default 256) Definition at line 514 of file dwc_otg_cil.h. |
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Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. 16 to 32768 (default 1024) Definition at line 520 of file dwc_otg_cil.h. |
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Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. 16 to 32768 (default 1024) Definition at line 526 of file dwc_otg_cil.h. |
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Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. 16 to 32768 (default 1024) Definition at line 532 of file dwc_otg_cil.h. |
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The maximum transfer size supported in bytes. 2047 to 65,535 (default 65,535) Definition at line 537 of file dwc_otg_cil.h. |
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The maximum number of packets in a transfer. 15 to 511 (default 511) Definition at line 542 of file dwc_otg_cil.h. |
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The number of host channel registers to use. 1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. Definition at line 548 of file dwc_otg_cil.h. |
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The number of endpoints in addition to EP0 available for device mode operations. 1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. Definition at line 556 of file dwc_otg_cil.h. |
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Specifies the type of PHY interface to use. By default, the driver will automatically detect the phy_type. 0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI Definition at line 566 of file dwc_otg_cil.h. |
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Specifies the UTMI+ Data Width. This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width. 8 or 16 bits (default 16) Definition at line 579 of file dwc_otg_cil.h. |
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Specifies whether the ULPI operates at double or single data rate. This parameter is only applicable if PHY_TYPE is ULPI. 0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus Definition at line 591 of file dwc_otg_cil.h. |
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Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
Definition at line 597 of file dwc_otg_cil.h. |
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Specifies whether to use the I2Cinterface for full speed PHY. This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes Definition at line 605 of file dwc_otg_cil.h. |
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Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. 4 to 768 (default 256) Definition at line 623 of file dwc_otg_cil.h. |
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HFIR Reload Control 0 - The HFIR cannot be reloaded dynamically. 1 - Allow dynamic reloading of the HFIR register during runtime. Definition at line 685 of file dwc_otg_cil.h. |
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DCFG: Enable device Out NAK 0 - The core does not set NAK after Bulk Out transfer complete. 1 - The core sets NAK after Bulk OUT transfer complete. Definition at line 691 of file dwc_otg_cil.h. |
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DCFG: Enable Continue on BNA After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the core starts processing 0 - from the DOEPDMA descriptor 1 - from the descriptor which received the BNA.
Definition at line 699 of file dwc_otg_cil.h. |
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GAHBCFG: AHB Single Support This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation. 0 - in this case the remainder data will be sent using INCR burst size. 1 - in this case the remainder data will be sent using SINGLE burst size. Definition at line 707 of file dwc_otg_cil.h. |
1.3.9.1