#include <dwc_otg_regs.h>
Data Fields | |
| volatile uint32_t | doepctl |
| Device OUT Endpoint Control Register. | |
| uint32_t | reserved04 |
| Reserved. | |
| volatile uint32_t | doepint |
| Device OUT Endpoint Interrupt Register. | |
| uint32_t | reserved0C |
| Reserved. | |
| volatile uint32_t | doeptsiz |
| Device OUT Endpoint Transfer Size Register. | |
| volatile uint32_t | doepdma |
| Device OUT Endpoint DMA Address Register. | |
| uint32_t | unused |
| Reserved. | |
| uint32_t | doepdmab |
| Device OUT Endpoint DMA Buffer Register. | |
Offsets: B00h-CFCh
There will be one set of endpoint registers per logical endpoint implemented.
These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.
Definition at line 1497 of file dwc_otg_regs.h.
|
|
Device OUT Endpoint Control Register. Offset:B00h + (ep_num * 20h) + 00h Definition at line 1500 of file dwc_otg_regs.h. |
|
|
Reserved. Offset:B00h + (ep_num * 20h) + 04h Definition at line 1502 of file dwc_otg_regs.h. |
|
|
Device OUT Endpoint Interrupt Register. Offset:B00h + (ep_num * 20h) + 08h Definition at line 1505 of file dwc_otg_regs.h. |
|
|
Reserved. Offset:B00h + (ep_num * 20h) + 0Ch Definition at line 1507 of file dwc_otg_regs.h. |
|
|
Device OUT Endpoint Transfer Size Register. Offset: B00h + (ep_num * 20h) + 10h Definition at line 1510 of file dwc_otg_regs.h. |
|
|
Device OUT Endpoint DMA Address Register. Offset:B00h + (ep_num * 20h) + 14h Definition at line 1513 of file dwc_otg_regs.h. |
|
|
Reserved. Offset:B00h + * (ep_num * 20h) + 18h Definition at line 1515 of file dwc_otg_regs.h. |
|
|
Device OUT Endpoint DMA Buffer Register. Offset:B00h + (ep_num * 20h) + 1Ch Definition at line 1518 of file dwc_otg_regs.h. |
1.3.9.1