Todo List

Global srp_show (struct device *_dev, struct device_attribute *attr, char *buf)

Add code to initiate the SRP.

Global buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)

Need to do more for power on/off?

Global bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)

Need to do more for suspend?

Global dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)

NGS: Should this be a module parameter?

Global dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)

NGS: Fix Periodic FIFO Sizing!

Finish debug of this

- if the condition needed to be checked or in any case all pending interrutps should be cleared?

Global dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)

Should there be check for room in the Tx Status Queue. If not remove the code above this comment.

Global dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)

NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?

Global dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)

Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.

Global dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)

Consolidate this if statement.

Global dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)

: The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!

Global MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")

Set the max to 512K, modify checks

Global dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)

- check how sw can wait for 1 sec to check asesvld???

Global dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)

Implement i2cintr handler.

Global dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)

- check if steps performed in 'else' block should be perfromed regardles adp

Global dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)

add memflags argument

Global dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)

Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.

Global handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)

add support for isoc release

Global handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)

This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.

Global qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)

Account for split transfers in the bus time.

File dwc_otg_pcd.c

Add Device Mode test modes (Test J mode, Test K mode, etc).

Does it work when the request size is greater than DEPTSIZ transfer size

Global dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)

- pattern data support is to be implemented in the future

Global dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)

NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

Global dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)

NGS Create a function for this.

Global do_test_mode (void *data)

This has not been tested since the tasklet struct was put into the PCD struct!

Global dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)

NGS Check for buffer overflow?

Global get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)

Find a simpler way to calculate the max queue position.

Global dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)

NGS Flush Periodic FIFOs

Global ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)

NGS: Update the comments from the HW FS.

Global ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)

dma needs to handle multiple setup packets (up to 3)

Global do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)

This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.

Global pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)

FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.

Global do_get_status (dwc_otg_pcd_t *pcd)

check for EP stall

Global do_set_feature (dwc_otg_pcd_t *pcd)

This has not been tested since the tasklet struct was put into the PCD struct!

Is the gotgctl.devhnpen cleared by a USB Reset?

Global do_clear_feature (dwc_otg_pcd_t *pcd)

Add CLEAR_FEATURE for TEST modes.

Global pcd_setup (dwc_otg_pcd_t *pcd)

handle > 1 setup packet , assert error for now

NGS: Handle bad setup packet?

Global handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)

NGS Check EP type. Implement for Periodic EPs

Global handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)

implement ISR

Global handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)

implement ISR

Global handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)

implement ISR

Global handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)

implement ISR

Global gadget_add_eps (struct gadget_wrapper *d)

NGS: What should the max packet size be set to here? Before EP type is set?

NGS: What should the max packet size be set to here? Before EP type is set?

NGS: What should the max packet size be set to here? Before EP type is set?

Global dwc_otg_pcd_gadget_release (struct device *dev)

Should this do something? Should it free the PCD?

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