#include <dwc_otg_regs.h>
Data Fields | |
| uint32_t | d32 |
| raw register data | |
| struct { | |
| unsigned prb_dschg:2 | |
| Probe Discharge (PRB_DSCHG) These bits set the times for TADP_DSCHG. | |
| unsigned prb_delta:2 | |
| Probe Delta (PRB_DELTA) These bits set the resolution for RTIM value. | |
| unsigned prb_per:2 | |
| Probe Period (PRB_PER) These bits sets the TADP_PRD as shown in Figure 4 as follows: 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) 2'b11 - Reserved. | |
| unsigned rtim:11 | |
| These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. | |
| unsigned enaprb:1 | |
| Enable Probe (EnaPrb) When programmed to 1'b1, the core performs a probe operation. | |
| unsigned enasns:1 | |
| Enable Sense (EnaSns) When programmed to 1'b1, the core performs a Sense operation. | |
| unsigned adpres:1 | |
| ADP Reset (ADPRes) When set, ADP controller is reset. | |
| unsigned adpen:1 | |
| ADP Enable (ADPEn) When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns. | |
| unsigned adp_prb_int:1 | |
| ADP Probe Interrupt (ADP_PRB_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VADP_PRB is reached. | |
| unsigned adp_sns_int:1 | |
| ADP Sense Interrupt (ADP_SNS_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_SNS value or VADP_SNS is reached. | |
| unsigned adp_tmout_int:1 | |
| ADP Tomeout Interrupt (ADP_TMOUT_INT) This bit is relevant only for an ADP probe. | |
| unsigned adp_prb_int_msk:1 | |
| ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. | |
| unsigned adp_sns_int_msk:1 | |
| ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. | |
| unsigned adp_tmout_int_msk:1 | |
| ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. | |
| unsigned ar:2 | |
| Access Request 2'b00 - Read/Write Valid (updated by the core) 2'b01 - Read 2'b00 - Write 2'b00 - Reserved. | |
| unsigned reserved29_31:3 | |
| Reserved. | |
| } | b |
| register bits | |
Set the bits using bit fields then write the d32 value to the register.
Definition at line 955 of file dwc_otg_regs.h.
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Probe Discharge (PRB_DSCHG) These bits set the times for TADP_DSCHG. These bits are defined as follows: 2'b00 - 4 msec 2'b01 - 8 msec 2'b10 - 16 msec 2'b11 - 32 msec Definition at line 968 of file dwc_otg_regs.h. |
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Probe Delta (PRB_DELTA) These bits set the resolution for RTIM value. The bits are defined in units of 32 kHz clock cycles as follows: 2'b00 - 1 cycles 2'b01 - 2 cycles 2'b10 - 3 cycles 2'b11 - 4 cycles For example if this value is chosen to 2'b01, it means that RTIM increments for every 3(three) 32Khz clock cycles. Definition at line 979 of file dwc_otg_regs.h. |
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These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. 0x000 - 1 cycles 0x001 - 2 cycles 0x002 - 3 cycles etc 0x7FF - 2048 cycles A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. Definition at line 997 of file dwc_otg_regs.h. |
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Enable Probe (EnaPrb) When programmed to 1'b1, the core performs a probe operation. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1002 of file dwc_otg_regs.h. |
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Enable Sense (EnaSns) When programmed to 1'b1, the core performs a Sense operation. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1007 of file dwc_otg_regs.h. |
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ADP Reset (ADPRes) When set, ADP controller is reset. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1012 of file dwc_otg_regs.h. |
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ADP Enable (ADPEn) When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1018 of file dwc_otg_regs.h. |
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ADP Probe Interrupt (ADP_PRB_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VADP_PRB is reached. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1024 of file dwc_otg_regs.h. |
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ADP Sense Interrupt (ADP_SNS_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_SNS value or VADP_SNS is reached. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1031 of file dwc_otg_regs.h. |
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ADP Tomeout Interrupt (ADP_TMOUT_INT) This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed ie ADPCTL.RTIM has reached its terminal value of 0x7FF. This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1040 of file dwc_otg_regs.h. |
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ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1045 of file dwc_otg_regs.h. |
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ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1050 of file dwc_otg_regs.h. |
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ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. This bit is valid only if OTG_Ver = 1'b1. Definition at line 1055 of file dwc_otg_regs.h. |
1.3.9.1