diff --git a/boards.txt b/boards.txt
index 402b120b98..4d6940f7b7 100644
--- a/boards.txt
+++ b/boards.txt
@@ -64,7 +64,7 @@ Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.cmsis_lib_gcc=arm_cortexM7l_math
Nucleo_144.menu.pnum.NUCLEO_H743ZI=Nucleo H743ZI
Nucleo_144.menu.pnum.NUCLEO_H743ZI.node=NODE_H743ZI
Nucleo_144.menu.pnum.NUCLEO_H743ZI.upload.maximum_size=2097152
-Nucleo_144.menu.pnum.NUCLEO_H743ZI.upload.maximum_data_size=131072
+Nucleo_144.menu.pnum.NUCLEO_H743ZI.upload.maximum_data_size=524288
Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.mcu=cortex-m7
Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.board=NUCLEO_H743ZI
@@ -74,9 +74,9 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.variant=NUCLEO_H743ZI
Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.cmsis_lib_gcc=arm_cortexM7l_math
Nucleo_144.menu.pnum.NUCLEO_H743ZI2=Nucleo H743ZI2
-Nucleo_144.menu.pnum.NUCLEO_H743ZI2.node=NODE_H743ZI
+Nucleo_144.menu.pnum.NUCLEO_H743ZI2.node="NODE_H743ZI,NOD_H743ZI2"
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.upload.maximum_size=2097152
-Nucleo_144.menu.pnum.NUCLEO_H743ZI2.upload.maximum_data_size=131072
+Nucleo_144.menu.pnum.NUCLEO_H743ZI2.upload.maximum_data_size=524288
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.mcu=cortex-m7
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.board=NUCLEO_H743ZI2
diff --git a/variants/NUCLEO_H743ZI/ldscript.ld b/variants/NUCLEO_H743ZI/ldscript.ld
index 7cc3325995..410c85d653 100644
--- a/variants/NUCLEO_H743ZI/ldscript.ld
+++ b/variants/NUCLEO_H743ZI/ldscript.ld
@@ -1,11 +1,17 @@
/*
-*****************************************************************************
+******************************************************************************
**
-
** File : LinkerScript.ld
**
-** Abstract : Linker script for STM32H743ZI Device with
-** 2048KByte FLASH, 1056KByte RAM
+** Author : Auto-generated by STM32CubeIDE
+**
+** Abstract : Linker script for NUCLEO-H743ZI(2) Board embedding STM32H743ZITx Device from STM32H7 series
+** 2048Kbytes FLASH
+** 128Kbytes DTCMRAM
+** 64Kbytes ITCMRAM
+** 512Kbytes RAM_D1
+** 288Kbytes RAM_D2
+** 64Kbytes RAM_D3
**
** Set heap size, stack size and stack location according
** to application requirements.
@@ -14,14 +20,13 @@
**
** Target : STMicroelectronics STM32
**
-**
-** Distribution: The file is distributed as is, without any warranty
+** Distribution: The file is distributed as is without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
-** © COPYRIGHT(c) 2014 Ac6
+** © COPYRIGHT(c) 2019 STMicroelectronics
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
@@ -30,7 +35,7 @@
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
-** 3. Neither the name of Ac6 nor the names of its contributors
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
@@ -52,26 +57,26 @@
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
-_estack = 0x20020000; /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_estack = 0x24080000; /* end of "RAM_D1" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
-/* Specify the memory areas */
+/* Memories definition */
MEMORY
{
-DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
+ DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
+ ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
+ RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
+ RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
}
-/* Define output sections */
+/* Sections */
SECTIONS
{
- /* The startup code goes first into FLASH */
+ /* The startup code into "FLASH" Rom type memory */
.isr_vector :
{
. = ALIGN(4);
@@ -79,8 +84,8 @@ SECTIONS
. = ALIGN(4);
} >FLASH
- /* The program code and other data goes into FLASH */
- .text ALIGN(4):
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
@@ -96,7 +101,7 @@ SECTIONS
_etext = .; /* define a global symbols at end of code */
} >FLASH
- /* Constant data goes into FLASH */
+ /* Constant data into "FLASH" Rom type memory */
.rodata :
{
. = ALIGN(4);
@@ -105,39 +110,54 @@ SECTIONS
. = ALIGN(4);
} >FLASH
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
.ARM : {
+ . = ALIGN(4);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
+ . = ALIGN(4);
} >FLASH
.preinit_array :
{
+ . = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
} >FLASH
+
.init_array :
{
+ . = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
} >FLASH
+
.fini_array :
{
+ . = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
} >FLASH
- /* used by the startup to initialize data */
+ /* Used by the startup to initialize data */
_sidata = LOADADDR(.data);
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
+ /* Initialized data sections into "RAM_D1" Ram type memory */
+ .data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@@ -146,10 +166,10 @@ SECTIONS
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
- } >DTCMRAM AT> FLASH
-
-
- /* Uninitialized data section */
+
+ } >RAM_D1 AT> FLASH
+
+ /* Uninitialized data section into "RAM_D1" Ram type memory */
. = ALIGN(4);
.bss :
{
@@ -163,9 +183,9 @@ SECTIONS
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
- } >DTCMRAM
+ } >RAM_D1
- /* User_heap_stack section, used to check that there is enough RAM left */
+ /* User_heap_stack section, used to check that there is enough "RAM_D1" Ram type memory left */
._user_heap_stack :
{
. = ALIGN(8);
@@ -174,11 +194,9 @@ SECTIONS
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
- } >DTCMRAM
-
-
+ } >RAM_D1
- /* Remove information from the standard libraries */
+ /* Remove information from the compiler libraries */
/DISCARD/ :
{
libc.a ( * )
@@ -188,5 +206,3 @@ SECTIONS
.ARM.attributes 0 : { *(.ARM.attributes) }
}
-
-
diff --git a/variants/NUCLEO_H743ZI/variant.cpp b/variants/NUCLEO_H743ZI/variant.cpp
index 84ae81e772..56740eafa2 100644
--- a/variants/NUCLEO_H743ZI/variant.cpp
+++ b/variants/NUCLEO_H743ZI/variant.cpp
@@ -184,39 +184,33 @@ extern "C" {
*/
WEAK void SystemClock_Config(void)
{
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
/* Supply configuration update enable */
- MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
-
+ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/* Configure the main internal regulator output voltage */
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
- while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {
- }
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
- /* Initializes the CPU, AHB and APB buses clocks */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI;
- RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
- RCC_OscInitStruct.CSIState = RCC_CSI_ON;
- RCC_OscInitStruct.CSICalibrationValue = 16;
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+ /* Initializes the CPU, AHB and APB busses clocks */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_CSI;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 1;
- RCC_OscInitStruct.PLL.PLLN = 200;
+ RCC_OscInitStruct.PLL.PLLN = 120;
RCC_OscInitStruct.PLL.PLLP = 2;
- RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLQ = 20;
RCC_OscInitStruct.PLL.PLLR = 2;
- RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
}
-
- /* Initializes the CPU, AHB and APB buses clocks */
+ /* Initializes the CPU, AHB and APB busses clocks */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
@@ -228,24 +222,25 @@ WEAK void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
Error_Handler();
}
-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
PeriphClkInitStruct.PLL2.PLL2M = 1;
- PeriphClkInitStruct.PLL2.PLL2N = 129;
+ PeriphClkInitStruct.PLL2.PLL2N = 120;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 2;
PeriphClkInitStruct.PLL2.PLL2R = 2;
- PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
- PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
Error_Handler();
}
+ /* Enable USB Voltage detector */
+ HAL_PWREx_EnableUSBVoltageDetector();
}
#ifdef __cplusplus
diff --git a/variants/NUCLEO_H743ZI/variant.h b/variants/NUCLEO_H743ZI/variant.h
index 07c5c9ebd0..6df67e501e 100644
--- a/variants/NUCLEO_H743ZI/variant.h
+++ b/variants/NUCLEO_H743ZI/variant.h
@@ -205,6 +205,12 @@ extern "C" {
#define PIN_SERIAL_RX PD9
#define PIN_SERIAL_TX PD8
+// HSE default value is 25MHz in HAL
+// HSE_BYPASS is 8MHz
+#ifndef HSE_BYPASS_NOT_USED
+#define HSE_VALUE 8000000
+#endif
+
/* Extra HAL modules */
#define HAL_DAC_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED