diff --git a/lib/stm32wba/CMakeLists.txt b/lib/stm32wba/CMakeLists.txt index a7a8114c1..c8d7a6665 100644 --- a/lib/stm32wba/CMakeLists.txt +++ b/lib/stm32wba/CMakeLists.txt @@ -30,6 +30,7 @@ if(CONFIG_IEEE802154_STM32WBA) zephyr_sources(Common/WPAN/Modules/BasicAES/baes_ccm.c) zephyr_sources(Common/WPAN/Modules/BasicAES/baes_cmac.c) zephyr_sources(Common/WPAN/Modules/BasicAES/baes_ecb.c) + zephyr_sources(Common/WPAN/Interfaces/hw_aes.c) endif() set(STM32WBA_LIB_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../zephyr/blobs/stm32wba/lib) @@ -86,7 +87,12 @@ endif() # Selecting the proper version of link layer lib if(CONFIG_BT_STM32WBA) - # Checking all the soc variants and not simply relying on board name + if(BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") + zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/ble_basic) + elseif(BLE_LIB_TYPE STREQUAL "BLE_LIB_FULL") + zephyr_include_directories(STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full) + endif() + # Checking all the soc variants and not simply relying on board name if(CONFIG_SOC_STM32WBA65XX) message(STATUS "STM32WBA6 link layer lib selected") if (BLE_LIB_TYPE STREQUAL "BLE_LIB_BASIC") diff --git a/lib/stm32wba/Common/WPAN/Interfaces/hw.h b/lib/stm32wba/Common/WPAN/Interfaces/hw.h index 8129950ed..642415016 100644 --- a/lib/stm32wba/Common/WPAN/Interfaces/hw.h +++ b/lib/stm32wba/Common/WPAN/Interfaces/hw.h @@ -20,6 +20,7 @@ #define HW_H__ #include "stm32wbaxx.h" +#include "app_conf.h" /* --------------------------------------------------------------------------- * General @@ -360,7 +361,7 @@ extern void HW_PKA_P256_ReadEccScalarMul( uint32_t* p_x, * Thus, the function HW_RNG_Process() must be called regularly in background * loop to generate a pool of random numbers. The function HW_RNG_Get() reads * the random numbers from the pool. - * The size of the pool must be configured with CFG_HW_RNG_POOL_SIZE. + * The size of the pool must be configured with HW_RNG_POOL_SIZE. */ /* Error codes definition for HW_RNG return values */ @@ -371,6 +372,11 @@ enum HW_RNG_UFLOW_ERROR = CFG_HW_ERROR_OFFSET + 0x103, }; +/* RNG pool size */ +#define HW_RNG_POOL_SIZE (CFG_HW_RNG_POOL_SIZE) +/* Default threshold to refill RNG pool */ +#define HW_RNG_POOL_DEFAULT_THRESHOLD (12) + /* RNG_KERNEL_CLK_ON * * Enable RNG kernel clock. @@ -441,6 +447,20 @@ extern void HW_RNG_DisableClock( uint8_t user_mask ); extern void HWCB_RNG_Process( void ); +/* + * HW_RNG_Init + * + * This function initializes RNG (clock, configuration ...) + */ +extern void HW_RNG_Init(void); + +/* + * HW_RNG_Init + * + * Sets RNG pool threshold (for refill) + */ +extern void HW_RNG_SetPoolThreshold(uint8_t threshold); + /* --------------------------------------------------------------------------- * GPIO * --------------------------------------------------------------------------- diff --git a/lib/stm32wba/Common/WPAN/Modules/BasicAES/baes.h b/lib/stm32wba/Common/WPAN/Modules/BasicAES/baes.h index d126478dc..a6343c891 100644 --- a/lib/stm32wba/Common/WPAN/Modules/BasicAES/baes.h +++ b/lib/stm32wba/Common/WPAN/Modules/BasicAES/baes.h @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file baes.h + * @file baes.h * @author MCD Application Team * @brief This file contains the interface of the basic AES software module. ****************************************************************************** diff --git a/lib/stm32wba/Common/WPAN/Modules/RTDebug/RTDebug.h b/lib/stm32wba/Common/WPAN/Modules/RTDebug/RTDebug.h index e819c6225..4f0406bc5 100644 --- a/lib/stm32wba/Common/WPAN/Modules/RTDebug/RTDebug.h +++ b/lib/stm32wba/Common/WPAN/Modules/RTDebug/RTDebug.h @@ -28,48 +28,46 @@ /** and global signal table GPIO manipulation **/ /**************************************************************/ -#define GENERIC_DEBUG_GPIO_SET(signal, table) do { \ - uint32_t debug_table_idx = 0; \ - if(signal >= sizeof(table)) \ - { \ - return; \ - } \ - debug_table_idx = table[signal]; \ - if(debug_table_idx != RT_DEBUG_SIGNAL_UNUSED) \ - { \ - HAL_GPIO_WritePin(general_debug_table[debug_table_idx].GPIO_port, \ - general_debug_table[debug_table_idx].GPIO_pin, \ - GPIO_PIN_SET); \ - } \ +#define GENERIC_DEBUG_GPIO_SET(signal, table) do { \ + uint32_t debug_table_idx = 0; \ + if(signal >= sizeof(table)) \ + { \ + return; \ + } \ + debug_table_idx = table[signal]; \ + if(debug_table_idx != RT_DEBUG_SIGNAL_UNUSED) \ + { \ + LL_GPIO_SetOutputPin(general_debug_table[debug_table_idx].GPIO_port, \ + general_debug_table[debug_table_idx].GPIO_pin); \ + } \ } while(0) -#define GENERIC_DEBUG_GPIO_RESET(signal, table) do { \ - uint32_t debug_table_idx = 0; \ - if(signal >= sizeof(table)) \ - { \ - return; \ - } \ - debug_table_idx = table[signal]; \ - if(debug_table_idx != RT_DEBUG_SIGNAL_UNUSED) \ - { \ - HAL_GPIO_WritePin(general_debug_table[debug_table_idx].GPIO_port, \ - general_debug_table[debug_table_idx].GPIO_pin, \ - GPIO_PIN_RESET); \ - } \ +#define GENERIC_DEBUG_GPIO_RESET(signal, table) do { \ + uint32_t debug_table_idx = 0; \ + if(signal >= sizeof(table)) \ + { \ + return; \ + } \ + debug_table_idx = table[signal]; \ + if(debug_table_idx != RT_DEBUG_SIGNAL_UNUSED) \ + { \ + LL_GPIO_ResetOutputPin(general_debug_table[debug_table_idx].GPIO_port, \ + general_debug_table[debug_table_idx].GPIO_pin); \ + } \ } while(0) -#define GENERIC_DEBUG_GPIO_TOGGLE(signal, table) do { \ - uint32_t debug_table_idx = 0; \ - if(signal >= sizeof(table)) \ - { \ - return; \ - } \ - debug_table_idx = table[signal]; \ - if(debug_table_idx != RT_DEBUG_SIGNAL_UNUSED) \ - { \ - HAL_GPIO_TogglePin(general_debug_table[debug_table_idx].GPIO_port, \ - general_debug_table[debug_table_idx].GPIO_pin); \ - } \ +#define GENERIC_DEBUG_GPIO_TOGGLE(signal, table) do { \ + uint32_t debug_table_idx = 0; \ + if(signal >= sizeof(table)) \ + { \ + return; \ + } \ + debug_table_idx = table[signal]; \ + if(debug_table_idx != RT_DEBUG_SIGNAL_UNUSED) \ + { \ + LL_GPIO_TogglePin(general_debug_table[debug_table_idx].GPIO_port, \ + general_debug_table[debug_table_idx].GPIO_pin); \ + } \ } while(0) #endif /* CFG_RT_DEBUG_GPIO_MODULE */ diff --git a/lib/stm32wba/Common/WPAN/Modules/RTDebug/debug_signals.h b/lib/stm32wba/Common/WPAN/Modules/RTDebug/debug_signals.h index 5f3fba4b1..14d1fc33d 100644 --- a/lib/stm32wba/Common/WPAN/Modules/RTDebug/debug_signals.h +++ b/lib/stm32wba/Common/WPAN/Modules/RTDebug/debug_signals.h @@ -811,6 +811,10 @@ typedef enum { RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2, #endif /* USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 */ +#if (USE_RT_DEBUG_BACK_FROM_DEEP_SLEEP == 1) + RT_DEBUG_BACK_FROM_DEEP_SLEEP, +#endif /* USE_RT_DEBUG_BACK_FROM_DEEP_SLEEP */ + #include "app_debug_signal_def.h" RT_DEBUG_SIGNALS_TOTAL_NUM diff --git a/lib/stm32wba/Common/WPAN/Modules/RTDebug/local_debug_tables.h b/lib/stm32wba/Common/WPAN/Modules/RTDebug/local_debug_tables.h index 1afa50791..b790b5d07 100644 --- a/lib/stm32wba/Common/WPAN/Modules/RTDebug/local_debug_tables.h +++ b/lib/stm32wba/Common/WPAN/Modules/RTDebug/local_debug_tables.h @@ -1149,6 +1149,12 @@ static const rt_debug_signal_t linklayer_debug_table[] = { #else [DBG_IO_LLHWC_GET_CH_IDX_ALGO_2] = RT_DEBUG_SIGNAL_UNUSED, #endif /* USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 */ + +#if (USE_RT_DEBUG_BACK_FROM_DEEP_SLEEP == 1) + [DBG_IO_BACK_FROM_DEEP_SLEEP] = RT_DEBUG_BACK_FROM_DEEP_SLEEP, +#else + [DBG_IO_BACK_FROM_DEEP_SLEEP] = RT_DEBUG_SIGNAL_UNUSED, +#endif /* USE_RT_DEBUG_BACK_FROM_DEEP_SLEEP */ }; #endif /* CFG_RT_DEBUG_GPIO_MODULE */ diff --git a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/linklayer_plat.c b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/linklayer_plat.c index bfe0d8e65..21a361637 100644 --- a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/linklayer_plat.c +++ b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/linklayer_plat.c @@ -498,37 +498,40 @@ void LINKLAYER_PLAT_RequestTemperature(void) { } -#ifndef __ZEPHYR__ + /** - * @brief Enable RTOS context switch. + * @brief PHY Start calibration. * @param None * @retval None */ -void LINKLAYER_PLAT_EnableOSContextSwitch(void) +void LINKLAYER_PLAT_PhyStartClbr(void) { - /* USER CODE BEGIN LINKLAYER_PLAT_EnableOSContextSwitch_0 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_0 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_0 */ - /* USER CODE END LINKLAYER_PLAT_EnableOSContextSwitch_0 */ - /* USER CODE BEGIN LINKLAYER_PLAT_EnableOSContextSwitch_1 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_1 */ - /* USER CODE END LINKLAYER_PLAT_EnableOSContextSwitch_1 */ + /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_1 */ } /** - * @brief Disable RTOS context switch. + * @brief PHY Stop calibration. * @param None * @retval None */ -void LINKLAYER_PLAT_DisableOSContextSwitch(void) +void LINKLAYER_PLAT_PhyStopClbr(void) { - /* USER CODE BEGIN LINKLAYER_PLAT_DisableOSContextSwitch_0 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_0 */ - /* USER CODE END LINKLAYER_PLAT_DisableOSContextSwitch_0 */ - /* USER CODE BEGIN LINKLAYER_PLAT_DisableOSContextSwitch_1 */ + /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_0 */ - /* USER CODE END LINKLAYER_PLAT_DisableOSContextSwitch_1 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_1 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_1 */ } +#ifndef __ZEPHYR__ /** * @brief Notify the upper layer that new Link Layer timings have been applied. * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time diff --git a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c index fb4ac4851..2f93e95e9 100644 --- a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c +++ b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -17,17 +17,17 @@ ****************************************************************************** */ /* USER CODE END Header */ -#include -#include "ll_intf.h" + +#include "main.h" +#include "app_common.h" +#include "app_conf.h" +#include "log_module.h" #include "ll_intf_cmn.h" #include "ll_sys.h" #include "ll_sys_if.h" +#include "platform.h" #include "utilities_common.h" -#ifndef __ZEPHYR__ -#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) -#include "temp_measurement.h" -#endif /* (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) */ -#endif /*__ZEPHYR__*/ + /* Private defines -----------------------------------------------------------*/ /* Radio event scheduling method - must be set at 1 */ #define USE_RADIO_LOW_ISR (1) @@ -53,7 +53,6 @@ /* USER CODE END PV */ /* Global variables ----------------------------------------------------------*/ - /* USER CODE BEGIN GV */ /* USER CODE END GV */ @@ -211,4 +210,8 @@ void ll_sys_sleep_clock_source_selection(void) ll_intf_cmn_le_select_slp_clk_src((uint8_t)linklayer_slp_clk_src, &freq_value); } - +void ll_sys_set_rtl_polling_time(uint8_t rtl_polling_time) +{ + /* first parameter otInstance *aInstance is unused */ + radio_set_rtl_polling_time(NULL, rtl_polling_time); +} diff --git a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.h b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.h index 9af998921..3b8db9d76 100644 --- a/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.h +++ b/lib/stm32wba/IEEE802154/STM32_WPAN/Target/ll_sys_if.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -39,7 +39,6 @@ extern "C" { /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ - /* USER CODE BEGIN EC */ /* USER CODE END EC */ @@ -55,9 +54,7 @@ extern "C" { /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ -#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) -void ll_sys_bg_temperature_measurement(void); -#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ +void ll_sys_set_rtl_polling_time(uint8_t rtl_polling_time); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/lib/stm32wba/README.rst b/lib/stm32wba/README.rst index a600fc0e6..eb1f4ac33 100644 --- a/lib/stm32wba/README.rst +++ b/lib/stm32wba/README.rst @@ -6,7 +6,7 @@ Origin: https://github.com/STMicroelectronics/STM32CubeWBA Status: - version v1.6.0 + version v1.7.0 Purpose: This library is used on STM32WBA series to port BLE and IEEE802154 controller libraries in @@ -48,6 +48,7 @@ Description: Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/ot_inc/toolchain.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/ot_inc/types.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/ll_fw_config.h + Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_basic/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/ll_fw_config.h Middlewares/ST/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h @@ -103,12 +104,12 @@ Description: Projects/NUCLEO-WBA65RI/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/linklayer_plat.c Projects/NUCLEO-WBA65RI/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/ll_sys_if.c Projects/NUCLEO-WBA65RI/Applications/BLE/BLE_TransparentMode/STM32_WPAN/Target/ll_sys_if.h - Projects/NUCLEO-WBA65RI/Applications/BLE/Zigbee_OnOff_Client_SED/System/Config/Debug_GPIO/debug_config.h - Projects/NUCLEO-WBA65RI/Applications/BLE/Zigbee_OnOff_Client_SED/System/Config/Log/log_module_conf.h - Projects/NUCLEO-WBA65RI/Applications/BLE/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/power_table.c - Projects/NUCLEO-WBA65RI/Applications/BLE/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/linklayer_plat.c - Projects/NUCLEO-WBA65RI/Applications/BLE/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/ll_sys_if.c - Projects/NUCLEO-WBA65RI/Applications/BLE/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/ll_sys_if.h + Projects/NUCLEO-WBA65RI/Applications/Zigbee/Zigbee_OnOff_Client_SED/System/Config/Debug_GPIO/debug_config.h + Projects/NUCLEO-WBA65RI/Applications/Zigbee/Zigbee_OnOff_Client_SED/System/Config/Log/log_module_conf.h + Projects/NUCLEO-WBA65RI/Applications/Zigbee/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/power_table.c + Projects/NUCLEO-WBA65RI/Applications/Zigbee/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/linklayer_plat.c + Projects/NUCLEO-WBA65RI/Applications/Zigbee/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/ll_sys_if.c + Projects/NUCLEO-WBA65RI/Applications/Zigbee/Zigbee_OnOff_Client_SED/STM32_WPAN/Target/ll_sys_if.h Utilities/trace/adv_trace/stm32_adv_trace.h Utilities/misc/stm32_mem.h Utilities/tim_serv/stm32_timer.h @@ -122,7 +123,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeWBA Commit: - e7d27c496416aae8f4ba8b3e84f963f0c5a0b69f + f5b281ba4ca4d00aba59215728265f1d2cc80715 Maintained-by: External @@ -136,9 +137,10 @@ License Link: opensource.org/license/mit Patch List: - * Discard "static" implementation of ll_sys_bg_temperature_measurement_init to allow specific zephyr implementation - Impacted file: ll_sys_if.c - ll_sys.h + + * Discard "static" implementation of ll_sys_bg_temperature_measurement_init to allow specific zephyr implementation + Impacted file: ll_sys_if.c + ll_sys.h * Enabled extended advertising in CFG_BLE_OPTIONS: Impacted file: app_conf.h @@ -153,7 +155,6 @@ Patch List: Impacted files: stm_list.h main.h app_conf.h - scm.c ll_intf_cmn.h ll_sys_if.c linklayer_plat.c @@ -170,8 +171,7 @@ Patch List: Impacted files: ll_sys_if.c * SCM_HSE_WaitUntilReady Cube mechanism not used - Impacted files: scm.c - linklayer_plat.c + Impacted files: linklayer_plat.c * Changes from official delivery: - dos2unix applied diff --git a/lib/stm32wba/STM32_WPAN/CMakeLists.txt b/lib/stm32wba/STM32_WPAN/CMakeLists.txt index c5f66263b..1df662c9d 100644 --- a/lib/stm32wba/STM32_WPAN/CMakeLists.txt +++ b/lib/stm32wba/STM32_WPAN/CMakeLists.txt @@ -6,12 +6,12 @@ if(CONFIG_BT_STM32WBA) endif() if(CONFIG_IEEE802154_STM32WBA) zephyr_compile_definitions( -DMAC ) + zephyr_compile_definitions( -DMAC_LAYER ) endif() if(CONFIG_BT_STM32WBA) zephyr_include_directories(ble/stack/include) zephyr_include_directories(ble/stack/include/auto) - zephyr_include_directories(link_layer/ll_cmd_lib/config/ble_full) endif() if(CONFIG_IEEE802154_STM32WBA) zephyr_include_directories(ieee802154) diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/auto/ble_types.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/auto/ble_types.h index 437e2e463..05ee9940e 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/auto/ble_types.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/auto/ble_types.h @@ -29,7 +29,7 @@ typedef uint8_t tBleStatus; typedef __PACKED_STRUCT { /** - * Connection_Handle[i] + * Connection_Handle[i]. * Values: * - 0x0000 ... 0x0EFF */ @@ -88,16 +88,14 @@ typedef __PACKED_STRUCT * begins the subsequent scan on the primary advertising physical channel. * Time = N * 0.625 ms. * Values: - * - 0x0004 (2.500 ms) ... 0x5DC0 (15000.000 ms) : STM32WB - * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : STM32WBA + * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : full supported range */ uint16_t Scan_Interval; /** * Duration of the scan on the primary advertising physical channel. * Time = N * 0.625 ms. * Values: - * - 0x0004 (2.500 ms) ... 0x5DC0 (15000.000 ms) : STM32WB - * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : STM32WBA + * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : full supported range */ uint16_t Scan_Window; } Scan_Param_Phy_t; @@ -110,16 +108,14 @@ typedef __PACKED_STRUCT * begins the subsequent scan on the primary advertising physical channel. * Time = N * 0.625 ms. * Values: - * - 0x0004 (2.500 ms) ... 0x5DC0 (15000.000 ms) : STM32WB - * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : STM32WBA + * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : full supported range */ uint16_t Scan_Interval; /** * Duration of the scan on the primary advertising physical channel. * Time = N * 0.625 ms. * Values: - * - 0x0004 (2.500 ms) ... 0x5DC0 (15000.000 ms) : STM32WB - * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : STM32WBA + * - 0x0004 (2.500 ms) ... 0xFFFF (40959.375 ms) : full supported range */ uint16_t Scan_Window; /** @@ -182,13 +178,13 @@ typedef __PACKED_STRUCT /** * Maximum size, in octets, of the payload from the Central's Host. * Values: - * - 0x0000 ... 0x0FFF + * - 0 ... 310 */ uint16_t Max_SDU_C_To_P; /** * Maximum size, in octets, of the payload from the Peripheral's Host. * Values: - * - 0x0000 ... 0x0FFF + * - 0 ... 310 */ uint16_t Max_SDU_P_To_C; /** @@ -231,33 +227,33 @@ typedef __PACKED_STRUCT /** * Number of subevents in each interval of each BIS in the BIG. * Values: - * - 0x01 ... 0x1F + * - 1 ... 31 */ uint8_t NSE; /** * Maximum size, in octets, of the payload from the Central's Host. * Values: - * - 0x0000 ... 0x0FFF + * - 0 ... 310 */ uint16_t Max_SDU_C_To_P; /** * Maximum size, in octets, of the payload from the Peripheral's Host. * Values: - * - 0x0000 ... 0x0FFF + * - 0 ... 310 */ uint16_t Max_SDU_P_To_C; /** * Maximum size, in octets, of the payload from the Central to the * Peripheral. * Values: - * - 0x0000 ... 0x00FB + * - 0 ... 251 */ uint16_t Max_PDU_C_To_P; /** * Maximum size, in octets, of the payload from the Peripheral to the * Central. * Values: - * - 0x0000 ... 0x00FB + * - 0 ... 251 */ uint16_t Max_PDU_P_To_C; /** @@ -341,22 +337,6 @@ typedef __PACKED_STRUCT uint8_t Address[6]; } Bonded_Device_Entry_t; -/* Definition of Identity_Entry_t */ -typedef __PACKED_STRUCT -{ - /** - * Identity address type - * Values: - * - 0x00: Public Identity Address - * - 0x01: Random (static) Identity Address - */ - uint8_t Peer_Identity_Address_Type; - /** - * Public or Random (static) Identity Address of the peer device - */ - uint8_t Peer_Identity_Address[6]; -} Identity_Entry_t; - /* Definition of List_Entry_t */ typedef __PACKED_STRUCT { @@ -481,17 +461,14 @@ typedef __PACKED_STRUCT */ uint8_t Event_Type; /** - * Address type - * 0x00 Public Device Address - * 0x01 Random Device Address - * 0x02 Public Identity Address (Corresponds to Resolved Private Address) - * 0x03 Random (Static) Identity Address (Corresponds to Resolved Private - * Address) + * Address type. * Values: * - 0x00: Public Device Address * - 0x01: Random Device Address - * - 0x02: Public Identity Address - * - 0x03: Random (Static) Identity Address + * - 0x02: Public Identity Address (corresponds to the Resolved Private + * Address) + * - 0x03: Random (static) Identity Address (corresponds to the Resolved + * Private Address) */ uint8_t Address_Type; /** @@ -506,8 +483,8 @@ typedef __PACKED_STRUCT */ uint8_t Length_Data; /** - * Octets of advertising or scan response data formatted as defined in - * Bluetooth spec. [Vol 3, Part C, 11]. + * Octets of advertising or scan response data formatted as defined in Core + * Specification [Vol 3, Part C, 11]. */ const uint8_t* Data; /** @@ -530,17 +507,14 @@ typedef __PACKED_STRUCT */ uint8_t Event_Type; /** - * Address type - * 0x00 Public Device Address - * 0x01 Random Device Address - * 0x02 Public Identity Address (Corresponds to Resolved Private Address) - * 0x03 Random (Static) Identity Address (Corresponds to Resolved Private - * Address) + * Address type. * Values: * - 0x00: Public Device Address * - 0x01: Random Device Address - * - 0x02: Public Identity Address - * - 0x03: Random (Static) Identity Address + * - 0x02: Public Identity Address (corresponds to the Resolved Private + * Address) + * - 0x03: Random (static) Identity Address (corresponds to the Resolved + * Private Address) */ uint8_t Address_Type; /** @@ -878,7 +852,7 @@ typedef __PACKED_STRUCT { uint8_t Status; uint8_t LE_Features[8]; -} hci_le_read_local_supported_features_rp0; +} hci_le_read_local_supported_features_page_0_rp0; typedef __PACKED_STRUCT { @@ -1070,12 +1044,12 @@ typedef __PACKED_STRUCT typedef __PACKED_STRUCT { uint16_t Connection_Handle; -} hci_le_read_remote_features_cp0; +} hci_le_read_remote_features_page_0_cp0; typedef __PACKED_STRUCT { uint8_t Status; -} hci_le_read_remote_features_rp0; +} hci_le_read_remote_features_page_0_rp0; typedef __PACKED_STRUCT { @@ -2366,11 +2340,399 @@ typedef __PACKED_STRUCT uint8_t Selected_TX_Power; } hci_le_set_extended_advertising_parameters_v2_rp0; +typedef __PACKED_STRUCT +{ + uint8_t Advertising_Handle; + uint8_t Num_Subevents; + uint8_t Subevent_Param[252]; +} hci_le_set_periodic_advertising_subevent_data_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint8_t Advertising_Handle; +} hci_le_set_periodic_advertising_subevent_data_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Sync_Handle; + uint16_t Request_Event; + uint8_t Request_Subevent; + uint8_t Response_Subevent; + uint8_t Response_Slot; + uint8_t Response_Data_Length; + uint8_t Response_Data[BLE_CMD_MAX_PARAM_LEN - 8]; +} hci_le_set_periodic_advertising_response_data_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Sync_Handle; +} hci_le_set_periodic_advertising_response_data_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Sync_Handle; + uint16_t Periodic_Advertising_Properties; + uint8_t Num_Subevents; + uint8_t Subevent[BLE_CMD_MAX_PARAM_LEN - 5]; +} hci_le_set_periodic_sync_subevent_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Sync_Handle; +} hci_le_set_periodic_sync_subevent_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Advertising_Handle; + uint8_t Subevent; + uint8_t Initiator_Filter_Policy; + uint8_t Own_Address_Type; + uint8_t Peer_Address_Type; + uint8_t Peer_Address[6]; + uint8_t Initiating_PHYs; + Init_Param_Phy_t Init_Param_Phy[3]; +} hci_le_extended_create_connection_v2_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_extended_create_connection_v2_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Advertising_Handle; + uint16_t Periodic_Adv_Interval_Min; + uint16_t Periodic_Adv_Interval_Max; + uint16_t Periodic_Adv_Properties; + uint8_t Num_Subevents; + uint8_t Subevent_Interval; + uint8_t Response_Slot_Delay; + uint8_t Response_Slot_Spacing; + uint8_t Num_Response_Slots; +} hci_le_set_periodic_advertising_parameters_v2_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint8_t Advertising_Handle; +} hci_le_set_periodic_advertising_parameters_v2_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint8_t Max_Page; + uint8_t LE_Features[248]; +} hci_le_read_all_local_supported_features_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Pages_Requested; +} hci_le_read_all_remote_features_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_read_all_remote_features_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint8_t Num_Config_Supported; + uint16_t Max_Consecutive_Procedures_Supported; + uint8_t Num_Antennas_Supported; + uint8_t Max_Antenna_Paths_Supported; + uint8_t Roles_Supported; + uint8_t Optional_Modes_Supported; + uint8_t RTT_Capability; + uint8_t RTT_AA_Only_N; + uint8_t RTT_Sounding_N; + uint8_t RTT_Random_Payload_N; + uint16_t NADM_Sounding_Capability; + uint16_t NADM_Random_Capability; + uint8_t CS_SYNC_PHYs_Supported; + uint16_t Subfeatures_Supported; + uint16_t T_IP1_Times_Supported; + uint16_t T_IP2_Times_Supported; + uint16_t T_FCS_Times_Supported; + uint16_t T_PM_Times_Supported; + uint8_t T_SW_Time_Supported; + uint8_t TX_SNR_Capability; +} hci_le_cs_read_local_supported_capabilities_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; +} hci_le_cs_read_remote_supported_capabilities_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_read_remote_supported_capabilities_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Num_Config_Supported; + uint16_t Max_Consecutive_Procedures_Supported; + uint8_t Num_Antennas_Supported; + uint8_t Max_Antenna_Paths_Supported; + uint8_t Roles_Supported; + uint8_t Modes_Supported; + uint8_t RTT_Capability; + uint8_t RTT_AA_Only_N; + uint8_t RTT_Sounding_N; + uint8_t RTT_Random_Payload_N; + uint16_t NADM_Sounding_Capability; + uint16_t NADM_Random_Capability; + uint8_t CS_SYNC_PHYs_Supported; + uint16_t Subfeatures_Supported; + uint16_t T_IP1_Times_Supported; + uint16_t T_IP2_Times_Supported; + uint16_t T_FCS_Times_Supported; + uint16_t T_PM_Times_Supported; + uint8_t T_SW_Time_Supported; + uint8_t TX_SNR_Capability; +} hci_le_cs_write_cached_remote_supported_capabilities_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_cs_write_cached_remote_supported_capabilities_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; +} hci_le_cs_security_enable_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_security_enable_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Role_Enable; + uint8_t CS_SYNC_Antenna_Selection; + uint8_t Max_TX_Power; +} hci_le_cs_set_default_settings_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_cs_set_default_settings_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; +} hci_le_cs_read_remote_fae_table_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_read_remote_fae_table_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Remote_FAE_Table[72]; +} hci_le_cs_write_cached_remote_fae_table_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_cs_write_cached_remote_fae_table_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Config_ID; + uint8_t Create_Context; + uint8_t Main_Mode_Type; + uint8_t Sub_Mode_Type; + uint8_t Min_Main_Mode_Steps; + uint8_t Max_Main_Mode_Steps; + uint8_t Main_Mode_Repetition; + uint8_t Mode_0_Steps; + uint8_t Role; + uint8_t RTT_Type; + uint8_t CS_SYNC_PHY; + uint8_t Channel_Map[10]; + uint8_t Channel_Map_Repetition; + uint8_t Channel_Selection_Type; + uint8_t Ch3c_Shape; + uint8_t Ch3c_Jump; + uint8_t Reserved; +} hci_le_cs_create_config_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_create_config_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Config_ID; +} hci_le_cs_remove_config_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_remove_config_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Channel_Classification[10]; +} hci_le_cs_set_channel_classification_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_set_channel_classification_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Config_ID; + uint16_t Max_Procedure_Len; + uint16_t Min_Procedure_Interval; + uint16_t Max_Procedure_Interval; + uint16_t Max_Procedure_Count; + uint8_t Min_Subevent_Len[3]; + uint8_t Max_Subevent_Len[3]; + uint8_t Tone_Antenna_Config_Selection; + uint8_t PHY; + uint8_t Tx_Power_Delta; + uint8_t Preferred_Peer_Antenna; + uint8_t SNR_Control_Initiator; + uint8_t SNR_Control_Reflector; +} hci_le_cs_set_procedure_parameters_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_cs_set_procedure_parameters_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Config_ID; + uint8_t Enable; +} hci_le_cs_procedure_enable_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_procedure_enable_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Main_Mode_Type; + uint8_t Sub_Mode_Type; + uint8_t Main_Mode_Repetition; + uint8_t Mode_0_Steps; + uint8_t Role; + uint8_t RTT_Type; + uint8_t CS_SYNC_PHY; + uint8_t CS_SYNC_Antenna_Selection; + uint8_t Subevent_Len[3]; + uint16_t Subevent_Interval; + uint8_t Max_Num_Subevents; + uint8_t Transmit_Power_Level; + uint8_t T_IP1_Time; + uint8_t T_IP2_Time; + uint8_t T_FCS_Time; + uint8_t T_PM_Time; + uint8_t T_SW_Time; + uint8_t Tone_Antenna_Config_Selection; + uint8_t Reserved; + uint8_t SNR_Control_Initiator; + uint8_t SNR_Control_Reflector; + uint16_t DRBG_Nonce; + uint8_t Channel_Map_Repetition; + uint16_t Override_Config; + uint8_t Override_Parameters_Length; + uint8_t Override_Parameters_Data[BLE_CMD_MAX_PARAM_LEN - 30]; +} hci_le_cs_test_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_test_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_test_end_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Address_Type; + uint8_t Address[6]; + uint8_t RSSI_Threshold_Low; + uint8_t RSSI_Threshold_High; + uint8_t Timeout; +} hci_le_add_device_to_monitored_advertisers_list_cp0; + typedef __PACKED_STRUCT { uint8_t Status; - uint16_t Build_Number; -} aci_hal_get_fw_build_number_rp0; +} hci_le_add_device_to_monitored_advertisers_list_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Address_Type; + uint8_t Address[6]; +} hci_le_remove_device_from_monitored_advertisers_list_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_remove_device_from_monitored_advertisers_list_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_clear_monitored_advertisers_list_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint8_t Number; +} hci_le_read_monitored_advertisers_list_size_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Enable; +} hci_le_enable_monitoring_advertisers_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_enable_monitoring_advertisers_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint16_t Frame_Space_Min; + uint16_t Frame_Space_Max; + uint8_t PHYS; + uint16_t Spacing_Types; +} hci_le_frame_space_update_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_frame_space_update_rp0; typedef __PACKED_STRUCT { @@ -2456,14 +2818,6 @@ typedef __PACKED_STRUCT uint16_t Link_Connection_Handle[22]; } aci_hal_get_link_status_v2_rp0; -typedef __PACKED_STRUCT -{ - uint8_t Status; - uint16_t Allocated_For_TX; - uint16_t Allocated_For_RX; - uint16_t Allocated_MBlocks; -} aci_hal_get_pm_debug_info_v2_rp0; - typedef __PACKED_STRUCT { uint8_t Enable; @@ -3024,22 +3378,6 @@ typedef __PACKED_STRUCT uint8_t Status; } aci_gap_set_oob_data_rp0; -typedef __PACKED_STRUCT -{ - uint8_t Num_of_Resolving_list_Entries; - Identity_Entry_t Identity_Entry[(BLE_CMD_MAX_PARAM_LEN - 2)/sizeof(Identity_Entry_t)]; -} aci_gap_add_devices_to_resolving_list_cp0; - -typedef __PACKED_STRUCT -{ - uint8_t Clear_Resolving_List; -} aci_gap_add_devices_to_resolving_list_cp1; - -typedef __PACKED_STRUCT -{ - uint8_t Status; -} aci_gap_add_devices_to_resolving_list_rp0; - typedef __PACKED_STRUCT { uint8_t Peer_Identity_Address_Type; @@ -3949,6 +4287,7 @@ typedef __PACKED_STRUCT uint16_t MPS; uint16_t Initial_Credits; uint16_t Result; + uint8_t Max_Channel_Number; } aci_l2cap_coc_connect_confirm_cp0; typedef __PACKED_STRUCT @@ -4016,6 +4355,49 @@ typedef __PACKED_STRUCT uint8_t Status; } aci_l2cap_coc_tx_data_rp0; +typedef __PACKED_STRUCT +{ + uint8_t Mode; + uint32_t Options; +} aci_reset_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} aci_reset_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint32_t Version[2]; + uint32_t Options; + uint32_t Debug_Info[3]; +} aci_get_information_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Offset; + uint8_t Length; + uint8_t Value[BLE_CMD_MAX_PARAM_LEN - 2]; +} aci_write_config_data_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} aci_write_config_data_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Offset; +} aci_read_config_data_cp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint8_t Data_Length; + uint8_t Data[(BLE_EVT_MAX_PARAM_LEN - 3) - 2]; +} aci_read_config_data_rp0; + typedef __PACKED_STRUCT { uint8_t Status; @@ -4099,7 +4481,7 @@ typedef __PACKED_STRUCT uint8_t Status; uint16_t Connection_Handle; uint8_t LE_Features[8]; -} hci_le_read_remote_features_complete_event_rp0; +} hci_le_read_remote_features_page_0_complete_event_rp0; typedef __PACKED_STRUCT { @@ -4407,6 +4789,86 @@ typedef __PACKED_STRUCT uint16_t Supervision_Timeout; } hci_le_subrate_change_event_rp0; +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Sync_Handle; + uint8_t Advertising_SID; + uint8_t Advertiser_Address_Type; + uint8_t Advertiser_Address[6]; + uint8_t Advertiser_PHY; + uint16_t Periodic_Advertising_Interval; + uint8_t Advertiser_Clock_Accuracy; + uint8_t Num_Subevents; + uint8_t Subevent_Interval; + uint8_t Response_Slot_Delay; + uint8_t Response_Slot_Spacing; +} hci_le_periodic_advertising_sync_established_v2_event_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Sync_Handle; + uint8_t Tx_Power; + uint8_t RSSI; + uint8_t CTE_Type; + uint16_t Periodic_Event_Counter; + uint8_t Subevent; + uint8_t Data_Status; + uint8_t Data_Length; + uint8_t Data[(BLE_EVT_MAX_PARAM_LEN - 1) - 10]; +} hci_le_periodic_advertising_report_v2_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint16_t Service_Data; + uint16_t Sync_Handle; + uint8_t Advertising_SID; + uint8_t Advertiser_Address_Type; + uint8_t Advertiser_Address[6]; + uint8_t Advertiser_PHY; + uint16_t Periodic_Advertising_Interval; + uint8_t Advertiser_Clock_Accuracy; + uint8_t Num_Subevents; + uint8_t Subevent_Interval; + uint8_t Response_Slot_Delay; + uint8_t Response_Slot_Spacing; +} hci_le_periodic_advertising_sync_transfer_received_v2_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Advertising_Handle; + uint8_t Subevent_Start; + uint8_t Subevent_Data_Count; +} hci_le_periodic_advertising_subevent_data_request_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Advertising_Handle; + uint8_t Subevent; + uint8_t Tx_Status; + uint8_t Num_Responses; + uint8_t Responses[250]; +} hci_le_periodic_advertising_response_report_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Role; + uint8_t Peer_Address_Type; + uint8_t Peer_Address[6]; + uint8_t Local_Resolvable_Private_Address[6]; + uint8_t Peer_Resolvable_Private_Address[6]; + uint16_t Conn_Interval; + uint16_t Conn_Latency; + uint16_t Supervision_Timeout; + uint8_t Central_Clock_Accuracy; + uint8_t Advertising_Handle; + uint16_t Sync_Handle; +} hci_le_enhanced_connection_complete_v2_event_rp0; + typedef __PACKED_STRUCT { uint8_t Status; @@ -4433,6 +4895,148 @@ typedef __PACKED_STRUCT uint8_t Framing; } hci_le_cis_established_v2_event_rp0; +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Max_Remote_Page; + uint8_t Max_Valid_Page; + uint8_t LE_Features[248]; +} hci_le_read_all_remote_features_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Num_Config_Supported; + uint16_t Max_Consecutive_Procedures_Supported; + uint8_t Num_Antennas_Supported; + uint8_t Max_Antenna_Paths_Supported; + uint8_t Roles_Supported; + uint8_t Optional_Modes_Supported; + uint8_t RTT_Capability; + uint8_t RTT_AA_Only_N; + uint8_t RTT_Sounding_N; + uint8_t RTT_Random_Payload_N; + uint16_t NADM_Sounding_Capability; + uint16_t NADM_Random_Capability; + uint8_t CS_SYNC_PHYs_Supported; + uint16_t Subfeatures_Supported; + uint16_t T_IP1_Times_Supported; + uint16_t T_IP2_Times_Supported; + uint16_t T_FCS_Times_Supported; + uint16_t T_PM_Times_Supported; + uint8_t T_SW_Time_Supported; + uint8_t TX_SNR_Capability; +} hci_le_cs_read_remote_supported_capabilities_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Remote_FAE_Table[72]; +} hci_le_cs_read_remote_fae_table_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_cs_security_enable_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Config_ID; + uint8_t Action; + uint8_t Main_Mode_Type; + uint8_t Sub_Mode_Type; + uint8_t Min_Main_Mode_Steps; + uint8_t Max_Main_Mode_Steps; + uint8_t Main_Mode_Repetition; + uint8_t Mode_0_Steps; + uint8_t Role; + uint8_t RTT_Type; + uint8_t CS_SYNC_PHY; + uint8_t Channel_Map[10]; + uint8_t Channel_Map_Repetition; + uint8_t Channel_Selection_Type; + uint8_t Ch3c_Shape; + uint8_t Ch3c_Jump; + uint8_t Reserved; + uint8_t T_IP1_Time; + uint8_t T_IP2_Time; + uint8_t T_FCS_Time; + uint8_t T_PM_Time; +} hci_le_cs_config_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Config_ID; + uint8_t State; + uint8_t Tone_Antenna_Config_Selection; + uint8_t Selected_TX_Power; + uint8_t Subevent_Len[3]; + uint8_t Subevents_Per_Event; + uint16_t Subevent_Interval; + uint16_t Event_Interval; + uint16_t Procedure_Interval; + uint16_t Procedure_Count; + uint16_t Max_Procedure_Len; +} hci_le_cs_procedure_enable_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Config_ID; + uint16_t Start_ACL_Conn_Event_Counter; + uint16_t Procedure_Counter; + uint16_t Frequency_Compensation; + uint8_t Reference_Power_Level; + uint8_t Procedure_Done_Status; + uint8_t Subevent_Done_Status; + uint8_t Abort_Reason; + uint8_t Num_Antenna_Paths; + uint8_t Num_Steps_Reported; + uint8_t Step_Param[239]; +} hci_le_cs_subevent_result_event_rp0; + +typedef __PACKED_STRUCT +{ + uint16_t Connection_Handle; + uint8_t Config_ID; + uint8_t Procedure_Done_Status; + uint8_t Subevent_Done_Status; + uint8_t Abort_Reason; + uint8_t Num_Antenna_Paths; + uint8_t Num_Steps_Reported; + uint8_t Step_Param[246]; +} hci_le_cs_subevent_result_continue_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; +} hci_le_cs_test_end_complete_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Address_Type; + uint8_t Address[6]; + uint8_t Condition; +} hci_le_monitored_advertisers_report_event_rp0; + +typedef __PACKED_STRUCT +{ + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Initiator; + uint16_t Frame_Space; + uint8_t PHYS; + uint16_t Spacing_Types; +} hci_le_frame_space_update_complete_event_rp0; + typedef __PACKED_STRUCT { uint8_t Last_State; @@ -4447,7 +5051,7 @@ typedef __PACKED_STRUCT uint8_t Warning_Type; uint8_t Data_Length; uint8_t Data[(BLE_EVT_MAX_PARAM_LEN - 2) - 2]; -} aci_hal_warning_event_rp0; +} aci_warning_event_rp0; typedef __PACKED_STRUCT { @@ -4766,9 +5370,10 @@ typedef __PACKED_STRUCT typedef __PACKED_STRUCT { + uint16_t Connection_Handle; uint8_t Channel_Index; uint8_t EAB_State; - uint8_t Status; + uint16_t MTU; } aci_gatt_eatt_bearer_event_rp0; typedef __PACKED_STRUCT diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_bufsize.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_bufsize.h index 70862c568..0ad932a05 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_bufsize.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_bufsize.h @@ -97,23 +97,32 @@ * mentioned parameters. */ #if (PERIPHERAL_ONLY != 0) -#define BLE_FIXED_BUFFER_SIZE_BYTES 4 /* Peripheral Only */ +#define BLE_FIXED_BUFFER_SIZE_BYTES 4 /* Peripheral Only */ #elif (BASIC_FEATURES != 0) -#define BLE_FIXED_BUFFER_SIZE_BYTES 260 /* Basic Features */ +#define BLE_FIXED_BUFFER_SIZE_BYTES 260 /* Basic Features */ #else -#define BLE_FIXED_BUFFER_SIZE_BYTES 676 /* Full stack / Basic Plus */ +#define BLE_FIXED_BUFFER_SIZE_BYTES 516 /* Full stack / Basic Plus */ #endif /* * BLE_PER_LINK_SIZE_BYTES: additional memory size used per link */ - #if (PERIPHERAL_ONLY != 0) #define BLE_PER_LINK_SIZE_BYTES 148 /* Peripheral Only */ #elif (BASIC_FEATURES != 0) #define BLE_PER_LINK_SIZE_BYTES 176 /* Basic Features */ #else -#define BLE_PER_LINK_SIZE_BYTES 188 /* Full stack / Basic Plus */ +#define BLE_PER_LINK_SIZE_BYTES 192 /* Full stack / Basic Plus */ +#endif + +/* + * BLE_PER_ADD_BEARER_SIZE_BYTES: additional memory size used per add. bearer + */ + +#if (BASIC_FEATURES | PERIPHERAL_ONLY | LL_ONLY | LL_ONLY_BASIC) +#define BLE_PER_ADD_BEARER_SIZE_BYTES 0 +#else +#define BLE_PER_ADD_BEARER_SIZE_BYTES 40 /* Full stack / Basic Plus */ #endif /* @@ -122,13 +131,16 @@ * whose size depends on the number of supported connections. * * @param n_link: Maximum number of simultaneous connections that the device - * will support. Valid values are from 1 to 8. + * will support. Valid values are from 1 to 20. * * @param mblocks_count: Number of memory blocks allocated for packets. + * + * @param n_add_bearer: Number of additional EATT bearers */ -#define BLE_TOTAL_BUFFER_SIZE(n_link, mblocks_count) \ +#define BLE_TOTAL_BUFFER_SIZE(n_link, mblocks_count, n_add_bearer) \ (16 + BLE_FIXED_BUFFER_SIZE_BYTES + \ (BLE_PER_LINK_SIZE_BYTES * (n_link)) + \ + (BLE_PER_ADD_BEARER_SIZE_BYTES * (n_add_bearer)) + \ ((BLE_MEM_BLOCK_SIZE + 8) * (mblocks_count))) /* diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_const.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_const.h index aea40af02..4e06339cd 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_const.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_const.h @@ -25,13 +25,14 @@ #include "ble_defs.h" -/* Default BLE variant */ -#ifndef BASIC_FEATURES -#define BASIC_FEATURES 0 -#endif +/* Default BLE variant + */ #ifndef BASIC_PLUS #define BASIC_PLUS 0 #endif +#ifndef BASIC_FEATURES +#define BASIC_FEATURES 0 +#endif #ifndef PERIPHERAL_ONLY #define PERIPHERAL_ONLY 0 #endif @@ -42,55 +43,13 @@ #define LL_ONLY_BASIC 0 #endif -/* Size of command/events buffers: - * - * To change the size of commands and events parameters used in the - * auto-generated files, you need to update 2 defines: - * - * - BLE_CMD_MAX_PARAM_LEN - * - BLE_EVT_MAX_PARAM_LEN - * - * These 2 defines are set below with default values and can be changed. - * - * To compute the value to support a characteristic of 512 bytes for a specific - * command or an event, you need to look in "ble_types.h". - * - * Here are 2 examples, one with a command and one with an event: - * - * - aci_gatt_update_char_value_ext_cp0 - * ---------------------------------- - * - * we have in the structure: - * - * uint8_t Value[(BLE_CMD_MAX_PARAM_LEN- 12)/sizeof(uint8_t)]; - * - * so to support a 512 byte value, we need to have - * - * BLE_CMD_MAX_PARAM_LEN at least equal to: 512 + 12 = 524 - * - * - aci_gatt_read_handle_value_rp0 - * ------------------------------ - * - * we have in the structure: - * - * uint8_t Value[((BLE_EVT_MAX_PARAM_LEN - 3) - 5)/sizeof(uint8_t)]; - * - * so to support a 512 byte value, we need to have - * - * BLE_EVT_MAX_PARAM_LEN at least equal to: 512 + 3 + 5 = 520 - * - * If you need several events or commands with 512-size values, you need to - * take the maximum values for BLE_EVT_MAX_PARAM_LEN and BLE_CMD_MAX_PARAM_LEN. - * - */ - /* Maximum parameter size of BLE commands. - * Change this value if needed. */ -#define BLE_CMD_MAX_PARAM_LEN HCI_COMMAND_MAX_PARAM_LEN + */ +#define BLE_CMD_MAX_PARAM_LEN HCI_COMMAND_MAX_PARAM_LEN /* Maximum parameter size of BLE responses/events. - * Change this value if needed. */ -#define BLE_EVT_MAX_PARAM_LEN HCI_EVENT_MAX_PARAM_LEN + */ +#define BLE_EVT_MAX_PARAM_LEN HCI_EVENT_MAX_PARAM_LEN #endif /* BLE_CONST_H__ */ diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_defs.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_defs.h index c08056544..76dc75b10 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_defs.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_defs.h @@ -147,6 +147,22 @@ /* ------------------------------------------------------------------------- */ +/* BLE stack options (Options) + * (ACI_RESET) + */ +#define BLE_OPTIONS_LL_ONLY 0x00000001UL +#define BLE_OPTIONS_NO_SVC_CHANGE_DESC 0x00000002UL +#define BLE_OPTIONS_DEV_NAME_READ_ONLY 0x00000004UL +#define BLE_OPTIONS_EXTENDED_ADV 0x00000008UL +#define BLE_OPTIONS_CS_ALGO_2 0x00000010UL +#define BLE_OPTIONS_REDUCED_DB_IN_NVM 0x00000020UL +#define BLE_OPTIONS_GATT_CACHING 0x00000040UL +#define BLE_OPTIONS_POWER_CLASS_1 0x00000080UL +#define BLE_OPTIONS_APPEARANCE_WRITABLE 0x00000100UL +#define BLE_OPTIONS_ENHANCED_ATT 0x00000200UL + +/* ------------------------------------------------------------------------- */ + /* Characteristic value lengths */ #define DEVICE_NAME_CHARACTERISTIC_LEN 8 @@ -288,6 +304,7 @@ #define REASON_DHKEY_CHECK_FAILED 0x0BU #define REASON_NUM_COMPARISON_FAILED 0x0CU #define REASON_KEY_REJECTED 0x0FU +#define REASON_BUSY 0x10U /* Passkey input type detected * (ACI_GAP_PASSKEY_INPUT) @@ -440,7 +457,7 @@ /* ------------------------------------------------------------------------- */ /* Definitions for Warning_Type - * (ACI_HAL_WARNING_EVENT) + * (ACI_WARNING_EVENT) */ #define WARNING_L2CAP_RECOMBINATION_FAILURE 0x01U #define WARNING_GATT_UNEXPECTED_PEER_MESSAGE 0x02U @@ -448,6 +465,7 @@ #define WARNING_COC_RX_DATA_LENGTH_TOO_LARGE 0x04U #define WARNING_COC_ALREADY_ASSIGNED_DCID 0x05U #define WARNING_SMP_UNEXPECTED_LTK_REQUEST 0x06U +#define WARNING_GATT_BEARER_NOT_ALLOCATED 0x07U /* ------------------------------------------------------------------------- */ diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_std.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_std.h index ea281f115..a39c23393 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_std.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/ble_std.h @@ -62,42 +62,59 @@ #define HCI_VENDOR_SPECIFIC_DEBUG_EVT_CODE 0xFFU /* HCI LE subevent code */ -#define HCI_LE_CONNECTION_COMPLETE_SUBEVT_CODE 0x01U -#define HCI_LE_ADVERTISING_REPORT_SUBEVT_CODE 0x02U -#define HCI_LE_CONNECTION_UPDATE_COMPLETE_SUBEVT_CODE 0x03U -#define HCI_LE_READ_REMOTE_FEATURES_COMPLETE_SUBEVT_CODE 0x04U -#define HCI_LE_LONG_TERM_KEY_REQUEST_SUBEVT_CODE 0x05U -#define HCI_LE_REMOTE_CONNECTION_PARAMETER_REQUEST_SUBEVT_CODE 0x06U -#define HCI_LE_DATA_LENGTH_CHANGE_SUBEVT_CODE 0x07U -#define HCI_LE_READ_LOCAL_P256_PUBLIC_KEY_COMPLETE_SUBEVT_CODE 0x08U -#define HCI_LE_GENERATE_DHKEY_COMPLETE_SUBEVT_CODE 0x09U -#define HCI_LE_ENHANCED_CONNECTION_COMPLETE_SUBEVT_CODE 0x0AU -#define HCI_LE_DIRECTED_ADVERTISING_REPORT_SUBEVT_CODE 0x0BU -#define HCI_LE_PHY_UPDATE_COMPLETE_SUBEVT_CODE 0x0CU -#define HCI_LE_EXTENDED_ADVERTISING_REPORT_SUBEVT_CODE 0x0DU -#define HCI_LE_PERIODIC_ADVERTISING_SYNC_ESTABLISHED_SUBEVT_CODE 0x0EU -#define HCI_LE_PERIODIC_ADVERTISING_REPORT_SUBEVT_CODE 0x0FU -#define HCI_LE_PERIODIC_ADVERTISING_SYNC_LOST_SUBEVT_CODE 0x10U -#define HCI_LE_SCAN_TIMEOUT_SUBEVT_CODE 0x11U -#define HCI_LE_ADVERTISING_SET_TERMINATED_SUBEVT_CODE 0x12U -#define HCI_LE_SCAN_REQUEST_RECEIVED_SUBEVT_CODE 0x13U -#define HCI_LE_CHANNEL_SELECTION_ALGORITHM_SUBEVT_CODE 0x14U -#define HCI_LE_CONNECTIONLESS_IQ_REPORT_SUBEVT_CODE 0x15U -#define HCI_LE_CONNECTION_IQ_REPORT_SUBEVT_CODE 0x16U -#define HCI_LE_CTE_REQUEST_FAILED_SUBEVT_CODE 0x17U -#define HCI_LE_PERIODIC_ADVERTISING_SYNC_TRANSFER_RECEIVED_SUBEVT_CODE 0x18U -#define HCI_LE_CIS_ESTABLISHED_SUBEVT_CODE 0x19U -#define HCI_LE_CIS_REQUEST_SUBEVT_CODE 0x1AU -#define HCI_LE_CREATE_BIG_COMPLETE_SUBEVT_CODE 0x1BU -#define HCI_LE_TERMINATE_BIG_COMPLETE_SUBEVT_CODE 0x1CU -#define HCI_LE_BIG_SYNC_ESTABLISHED_SUBEVT_CODE 0x1DU -#define HCI_LE_BIG_SYNC_LOST_SUBEVT_CODE 0x1EU -#define HCI_LE_REQUEST_PEER_SCA_COMPLETE_SUBEVT_CODE 0x1FU -#define HCI_LE_PATH_LOSS_THRESHOLD_SUBEVT_CODE 0x20U -#define HCI_LE_TRANSMIT_POWER_REPORTING_SUBEVT_CODE 0x21U -#define HCI_LE_BIGINFO_ADVERTISING_REPORT_SUBEVT_CODE 0x22U -#define HCI_LE_SUBRATE_CHANGE_SUBEVT_CODE 0x23U -#define HCI_LE_CIS_ESTABLISHED_V2_SUBEVT_CODE 0x2AU +#define HCI_LE_CONNECTION_COMPLETE_SUBEVT_CODE 0x01U +#define HCI_LE_ADVERTISING_REPORT_SUBEVT_CODE 0x02U +#define HCI_LE_CONNECTION_UPDATE_COMPLETE_SUBEVT_CODE 0x03U +#define HCI_LE_READ_REMOTE_FEATURES_PAGE_0_COMPLETE_SUBEVT_CODE 0x04U +#define HCI_LE_LONG_TERM_KEY_REQUEST_SUBEVT_CODE 0x05U +#define HCI_LE_REMOTE_CONNECTION_PARAMETER_REQUEST_SUBEVT_CODE 0x06U +#define HCI_LE_DATA_LENGTH_CHANGE_SUBEVT_CODE 0x07U +#define HCI_LE_READ_LOCAL_P256_PUBLIC_KEY_COMPLETE_SUBEVT_CODE 0x08U +#define HCI_LE_GENERATE_DHKEY_COMPLETE_SUBEVT_CODE 0x09U +#define HCI_LE_ENHANCED_CONNECTION_COMPLETE_SUBEVT_CODE 0x0AU +#define HCI_LE_DIRECTED_ADVERTISING_REPORT_SUBEVT_CODE 0x0BU +#define HCI_LE_PHY_UPDATE_COMPLETE_SUBEVT_CODE 0x0CU +#define HCI_LE_EXTENDED_ADVERTISING_REPORT_SUBEVT_CODE 0x0DU +#define HCI_LE_PERIODIC_ADVERTISING_SYNC_ESTABLISHED_SUBEVT_CODE 0x0EU +#define HCI_LE_PERIODIC_ADVERTISING_REPORT_SUBEVT_CODE 0x0FU +#define HCI_LE_PERIODIC_ADVERTISING_SYNC_LOST_SUBEVT_CODE 0x10U +#define HCI_LE_SCAN_TIMEOUT_SUBEVT_CODE 0x11U +#define HCI_LE_ADVERTISING_SET_TERMINATED_SUBEVT_CODE 0x12U +#define HCI_LE_SCAN_REQUEST_RECEIVED_SUBEVT_CODE 0x13U +#define HCI_LE_CHANNEL_SELECTION_ALGORITHM_SUBEVT_CODE 0x14U +#define HCI_LE_CONNECTIONLESS_IQ_REPORT_SUBEVT_CODE 0x15U +#define HCI_LE_CONNECTION_IQ_REPORT_SUBEVT_CODE 0x16U +#define HCI_LE_CTE_REQUEST_FAILED_SUBEVT_CODE 0x17U +#define HCI_LE_PERIODIC_ADVERTISING_SYNC_TRANSFER_RECEIVED_SUBEVT_CODE 0x18U +#define HCI_LE_CIS_ESTABLISHED_SUBEVT_CODE 0x19U +#define HCI_LE_CIS_REQUEST_SUBEVT_CODE 0x1AU +#define HCI_LE_CREATE_BIG_COMPLETE_SUBEVT_CODE 0x1BU +#define HCI_LE_TERMINATE_BIG_COMPLETE_SUBEVT_CODE 0x1CU +#define HCI_LE_BIG_SYNC_ESTABLISHED_SUBEVT_CODE 0x1DU +#define HCI_LE_BIG_SYNC_LOST_SUBEVT_CODE 0x1EU +#define HCI_LE_REQUEST_PEER_SCA_COMPLETE_SUBEVT_CODE 0x1FU +#define HCI_LE_PATH_LOSS_THRESHOLD_SUBEVT_CODE 0x20U +#define HCI_LE_TRANSMIT_POWER_REPORTING_SUBEVT_CODE 0x21U +#define HCI_LE_BIGINFO_ADVERTISING_REPORT_SUBEVT_CODE 0x22U +#define HCI_LE_SUBRATE_CHANGE_SUBEVT_CODE 0x23U +#define HCI_LE_PERIODIC_ADVERTISING_SYNC_ESTABLISHED_V2_SUBEVT_CODE 0x24U +#define HCI_LE_PERIODIC_ADVERTISING_REPORT_V2_SUBEVT_CODE 0x25U +#define HCI_LE_PERIODIC_ADVERTISING_SYNC_TRANSFER_RECEIVED_V2_SUBEVT_CODE 0x26U +#define HCI_LE_PERIODIC_ADVERTISING_SUBEVENT_DATA_REQUEST_SUBEVT_CODE 0x27U +#define HCI_LE_PERIODIC_ADVERTISING_RESPONSE_REPORT_SUBEVT_CODE 0x28U +#define HCI_LE_ENHANCED_CONNECTION_COMPLETE_V2_SUBEVT_CODE 0x29U +#define HCI_LE_CIS_ESTABLISHED_V2_SUBEVT_CODE 0x2AU +#define HCI_LE_READ_ALL_REMOTE_FEATURES_COMPLETE_SUBEVT_CODE 0x2BU +#define HCI_LE_CS_READ_REMOTE_SUPPORTED_CAPABILITIES_COMPLETE_SUBEVT_CODE 0x2CU +#define HCI_LE_CS_READ_REMOTE_FAE_TABLE_COMPLETE_SUBEVT_CODE 0x2DU +#define HCI_LE_CS_SECURITY_ENABLE_COMPLETE_SUBEVT_CODE 0x2EU +#define HCI_LE_CS_CONFIG_COMPLETE_SUBEVT_CODE 0x2FU +#define HCI_LE_CS_PROCEDURE_ENABLE_COMPLETE_SUBEVT_CODE 0x30U +#define HCI_LE_CS_SUBEVENT_RESULT_SUBEVT_CODE 0x31U +#define HCI_LE_CS_SUBEVENT_RESULT_CONTINUE_SUBEVT_CODE 0x32U +#define HCI_LE_CS_TEST_END_COMPLETE_SUBEVT_CODE 0x33U +#define HCI_LE_MONITORED_ADVERTISERS_REPORT_SUBEVT_CODE 0x34U +#define HCI_LE_FRAME_SPACE_UPDATE_COMPLETE_SUBEVT_CODE 0x35U /* HCI error code */ #define HCI_SUCCESS_ERR_CODE 0x00U @@ -248,6 +265,7 @@ #define BLE_CORE_5_3 12 #define BLE_CORE_5_4 13 #define BLE_CORE_6_0 14 +#define BLE_CORE_6_1 15 /* AD types for advertising data and scan response data */ diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/bleplat.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/bleplat.h index c87b35d0b..0a9860c7a 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/bleplat.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/bleplat.h @@ -33,38 +33,17 @@ enum requested operation */ BLEPLAT_EOF = -3, /* The function exits and notifies the HW resource (memory for example) reached the end */ - BLEPLAT_WARN = -4, /* The function runs the asked operation and notifies - that the HW resource is near to be full */ BLEPLAT_ERROR = -5 /* The function exits due to some issue (memory corruption or buffer overflow for example) */ }; -/* Enumerated values used for the 'type' of NVM functions: - */ -enum -{ - BLEPLAT_NVM_TYPE_SEC = 0, - BLEPLAT_NVM_TYPE_GATT = 1, -}; - -/* Enumerated values used for the 'mode' of NVM functions: - */ -enum -{ - BLEPLAT_NVM_FIRST = 0, - BLEPLAT_NVM_NEXT = 1, - BLEPLAT_NVM_CURRENT = 2, - BLEPLAT_NVM_ALL = 3 -}; - /* General functions: */ /** - * @brief This function is called by the Bluetooth LE stack when it is - * initialized or reset (via hci_reset). The user shall call here the - * functions to reset the Timer, AES, PKA, NVM and RNG needed for the - * Bluetooth LE stack. + * @brief This function is called by the BLE stack when it is initialized + * or reset (via hci_reset). The user shall call here the functions + * to reset the Timer, AES, PKA and RNG needed for the BLE stack. * @param None * @retval None */ @@ -74,69 +53,18 @@ extern void BLEPLAT_Init( void ); */ /** - * @brief Store data in the NVM - * @param type: The type of data to be stored either security data - * (BLEPLAT_NVM_TYPE_SEC) or GATT data (BLEPLAT_NVM_TYPE_GATT) - * @param data: The data buffer to be stored - * @param size: The size of data to be stored - * @param extra_data: If there is extra data to be stored too. If not, this - * parameter shall be passed with "NULL" value - * @param extra_size: The size of extra data - * @retval status (BLEPLAT_XX) - */ -extern int BLEPLAT_NvmAdd( uint8_t type, - const uint8_t* data, - uint16_t size, - const uint8_t* extra_data, - uint16_t extra_size ); - -/** - * @brief Read data from the NVM - * @param mode: The mode of NVM reading: - * - BLEPLAT_NVM_FIRST - * used to read the first record of NVM - * - BLEPLAT_NVM_NEXT - * used to read the next record (after a previous call to - * BLEPLAT_NvmGet) - * - BLEPLAT_NVM_CURRENT - * used to read the same record again (after a previous call to - * BLEPLAT_NvmGet) - * @param type: The type of data to be read, either security data - * (BLEPLAT_NVM_TYPE_SEC) or GATT data (BLEPLAT_NVM_TYPE_GATT) - * @param offset: The offset from which the NVM starts the read an operation. - * @param data: The pointer to data read by the function - * @param size: The size of data to be read - * @retval - if positive or zero, it is the number of copied bytes - * - if negative, it is an error status (BLEPLAT_XX) - */ -extern int BLEPLAT_NvmGet( uint8_t mode, - uint8_t type, - uint16_t offset, - uint8_t* data, - uint16_t size ); - -/** - * @brief Compare passed data as parameter with data stored in the NVM - * @param offset: The offset from which the NVM starts the comparison - * @param data: The data to be compared with stored data in the NVM - * @param size: The size of data to be compared - * @retval - if zero, the comparison was successful (BLEPLAT_OK) - * - if positive, the comparison failed - * - if negative, it is an error status (BLEPLAT_XX) - */ -extern int BLEPLAT_NvmCompare( uint16_t offset, - const uint8_t* data, - uint16_t size ); - -/** - * @brief Clear a block from the NVM or the whole NVM, storing the security - * database (security and GATT records) - * @param mode: Mode of deleting data from the NVM, either clear all the - * security database (BLEPLAT_NVM_ALL) or the current read NVM block - * (BLEPLAT_NVM_CURRENT) + * @brief Store data in the NVM. + * This functions indicates the portion of NVM cache buffer that needs + * to be written in NVM. + * @param ptr: Pointer to the start of the data portion to be stored + * (it points inside the NVM cache buffer) + * @param size: Size of valid data in NVM cache buffer (in 64-bit words) + * Note: valid data always starts at the beginning of the NVM + * cache buffer. * @retval None */ -extern void BLEPLAT_NvmDiscard( uint8_t mode ); +extern void BLEPLAT_NvmStore( const uint64_t* ptr, + uint16_t size ); /* Public Key Algorithms (PKA) interface: */ diff --git a/lib/stm32wba/STM32_WPAN/ble/stack/include/blestack.h b/lib/stm32wba/STM32_WPAN/ble/stack/include/blestack.h index 14b28a93e..4adbc851c 100644 --- a/lib/stm32wba/STM32_WPAN/ble/stack/include/blestack.h +++ b/lib/stm32wba/STM32_WPAN/ble/stack/include/blestack.h @@ -34,22 +34,6 @@ enum BLE_SLEEPMODE_NOTIMER = 3, }; -/* - * Definitions for 'options' parameter - */ -enum -{ - BLE_OPTIONS_LL_ONLY = 0x0001U, - BLE_OPTIONS_NO_SVC_CHANGE_DESC = 0x0002U, - BLE_OPTIONS_DEV_NAME_READ_ONLY = 0x0004U, - BLE_OPTIONS_EXTENDED_ADV = 0x0008U, - BLE_OPTIONS_REDUCED_DB_IN_NVM = 0x0020U, - BLE_OPTIONS_GATT_CACHING = 0x0040U, - BLE_OPTIONS_POWER_CLASS_1 = 0x0080U, - BLE_OPTIONS_APPEARANCE_WRITABLE = 0x0100U, - BLE_OPTIONS_ENHANCED_ATT = 0x0200U, -}; - /* * Definitions for 'debug' parameter */ @@ -74,6 +58,20 @@ typedef struct */ uint32_t total_buffer_size; + /* Start address of the RAM buffer allocated for BLE NVM cache. + */ + uint64_t* nvm_cache_buffer; + + /* Size of actual data in BLE NVM cache (in 64-bit words). + * Range: 0 .. (nvm_cache_max_size - 1) + */ + uint16_t nvm_cache_size; + + /* Maximum size of BLE NVM cache (in 64-bit words). + * Range: 1 .. 1024 + */ + uint16_t nvm_cache_max_size; + /* Start address of the RAM buffer allocated for GATT database. * It must be a 32bit aligned RAM area. */ @@ -130,6 +128,12 @@ typedef struct */ uint16_t mblockCount; + /* Maximum number of bearers that can be created for Enhanced ATT + * in addition to the number of links + * Range: 0 .. 64 + */ + uint8_t max_add_eatt_bearers; + /* Maximum supported ATT_MTU size */ uint16_t attMtu; @@ -150,7 +154,7 @@ typedef struct uint8_t max_coc_initiator_nbr; /* Options flags - * Bitmap of the "BLE_OPTIONS_..." definitions (see above). + * Bitmap of the "BLE_OPTIONS_..." definitions (see ble_defs.h). * - bit 0: 1: LL only 0: LL + host * - bit 1: 1: no service change desc. 0: with service change desc. * - bit 2: 1: device name Read-Only 0: device name R/W diff --git a/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154.h b/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154.h index 9986aa911..a1fd4cba4 100644 --- a/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154.h +++ b/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154.h @@ -279,10 +279,10 @@ stm32wba_802154_ral_error_t stm32wba_802154_ral_energy_detection(uint16_t aScanD /** * @brief Changes the radio state to @ref RADIO_STATE_CCA. * - * @note @ref stm32wba_802154_cca_done can be called before this function returns a result. + * @note @ref st_ral_cca_done can be called before this function returns a result. * * In the CCA state, the radio verifies if the channel is clear. The result of the verification is - * reported to the higher layer by @ref stm32wba_802154_cca_done. + * reported to the higher layer by @ref st_ral_cca_done. * * @returns STM32WBA_802154_RAL_ERROR_NONE on success, or an error code on failure. */ @@ -487,12 +487,21 @@ stm32wba_802154_ral_error_t stm32wba_802154_ral_mac_gen_rnd_num(uint8_t *ptr_rnd * * @brief enable/disable antenna diversity * - * @param enable[in] : enable:1 / disable:0 + * @param[in] enable : enable:1 / disable:0 * * @returns STM32WBA_802154_RAL_ERROR_NONE on success, or an error code on failure. */ stm32wba_802154_ral_error_t stm32wba_802154_ral_set_ant_div_enable(uint8_t enable); +/** + * + * @brief A wrapper function to set configurable library parameters + * + * @param[in] support_openthread_1_2 : support_openthread_1_2: true / false + * @param[in] mac_layer_build : mac_layer_build: true / false + * @retval Error code + */ +stm32wba_802154_ral_error_t stm32wba_802154_ral_set_config_lib_params(bool support_openthread_1_2, bool mac_layer_build); /** @} */ @@ -503,4 +512,3 @@ stm32wba_802154_ral_error_t stm32wba_802154_ral_set_ant_div_enable(uint8_t enabl #endif /* STM32WBA_802154_H_ */ /** @} */ - diff --git a/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154_callbacks.h b/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154_callbacks.h index 5e053251c..666083e9d 100644 --- a/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154_callbacks.h +++ b/lib/stm32wba/STM32_WPAN/ieee802154/stm32wba_802154_callbacks.h @@ -61,7 +61,7 @@ struct stm32wba_802154_ral_cbk_dispatch_tbl{ * @retval none */ void (*stm32wba_802154_ral_cbk_ed_scan_done)(int8_t rssiResult); - + /** * @brief callback function called after the end of transmission operation * @@ -69,13 +69,13 @@ struct stm32wba_802154_ral_cbk_dispatch_tbl{ * @param error Transmission error status of type stm32wba_802154_tx_error_t. * Indicates whether the transmission was successful or if an * error occurred. - * @param p_metadata Pointer to metadata of type stm32wba_802154_transmit_done_metadata_t, + * @param p_metadata Pointer to metadata of type stm32wba_802154_transmit_done_metadata_t, * containing additional information about the transmission. * * @retval none */ void (*stm32wba_802154_ral_cbk_tx_done)(uint8_t * p_frame, stm32wba_802154_ral_tx_error_t error, const stm32wba_802154_ral_transmit_done_metadata_t *p_metadata); - + /** * @brief callback function called after the end of Reception operation * @@ -94,7 +94,7 @@ struct stm32wba_802154_ral_cbk_dispatch_tbl{ * @retval none */ void (*stm32wba_802154_ral_cbk_cca_done)(uint8_t error); - + /** * @brief callback function notifies about the start of the ACK frame transmission. * @@ -122,4 +122,3 @@ void stm32wba_802154_ral_call_back_funcs_init(struct stm32wba_802154_ral_cbk_dis #endif /* STM32WBA_802154_CALLBACKS_H_ */ /** @} */ - diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/ll_fw_config.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/ll_fw_config.h index 2c328949c..fdf24a89c 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/ll_fw_config.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/ll_fw_config.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -119,31 +119,55 @@ #endif /* SUPPORT_CSSA */ #ifndef SUPPORT_LE_PAWR_ADVERTISER_ROLE +#ifdef STM32WBA25xx +#define SUPPORT_LE_PAWR_ADVERTISER_ROLE 1 /* Enable\Disable PAwR Advertiser role. Enable:1 - Disable:0 */ +#else #define SUPPORT_LE_PAWR_ADVERTISER_ROLE 0 /* Enable\Disable PAwR Advertiser role. Enable:1 - Disable:0 */ +#endif #endif /* SUPPORT_LE_PAWR_ADVERTISER_ROLE */ #ifndef SUPPORT_LE_PAWR_SYNC_ROLE +#ifdef STM32WBA25xx +#define SUPPORT_LE_PAWR_SYNC_ROLE 1 /* Enable\Disable PAwR Synchronizer role. Enable:1 - Disable:0 */ +#else #define SUPPORT_LE_PAWR_SYNC_ROLE 0 /* Enable\Disable PAwR Synchronizer role. Enable:1 - Disable:0 */ +#endif #endif /* SUPPORT_LE_PAWR_SYNC_ROLE */ #ifndef SUPPORT_CHANNEL_SOUNDING -#define SUPPORT_CHANNEL_SOUNDING 0 /* Enable\Disable Channel Sounding Feature. Enable:1 - Disable:0 */ +#define SUPPORT_CHANNEL_SOUNDING 0 /* Enable\Disable Channel Sounding Feature. Enable:1 - Disable:0 */ #endif /* SUPPORT_CHANNEL_SOUNDING */ #ifndef SUPPORT_FRAME_SPACE_UPDATE -#define SUPPORT_FRAME_SPACE_UPDATE 0 /* Enable\Disable Frame Space Update Feature. Enable:1 - Disable:0 */ +#ifdef STM32WBA25xx +#define SUPPORT_FRAME_SPACE_UPDATE 1 /* Enable\Disable Frame Space Update Feature. Enable:1 - Disable:0 */ +#else +#define SUPPORT_FRAME_SPACE_UPDATE 0 /* Enable\Disable Frame Space Update Feature. Enable:1 - Disable:0 */ +#endif #endif /* SUPPORT_FRAME_SPACE_UPDATE */ #ifndef SUPPORT_EXT_FEATURE_SET -#define SUPPORT_EXT_FEATURE_SET 0 /* Enable\Disable Extended Feature Set Exchange. Enable:1 - Disable:0 */ +#ifdef STM32WBA25xx +#define SUPPORT_EXT_FEATURE_SET 1 /* Enable\Disable Extended Feature Set Exchange. Enable:1 - Disable:0 */ +#else +#define SUPPORT_EXT_FEATURE_SET 0 /* Enable\Disable Extended Feature Set Exchange. Enable:1 - Disable:0 */ +#endif #endif /* SUPPORT_EXT_FEATURE_SET */ #ifndef SUPPORT_ISO_UNSEG_MODE -#define SUPPORT_ISO_UNSEG_MODE 0 /* Enable\Disable Unsegmented Mode for Framed ISO PDUs. Enable: 1 - Disable: 0*/ +#ifdef STM32WBA25xx +#define SUPPORT_ISO_UNSEG_MODE 1 /* Enable\Disable Unsegmented Mode for Framed ISO PDUs. Enable: 1 - Disable: 0*/ +#else +#define SUPPORT_ISO_UNSEG_MODE 0 /* Enable\Disable Unsegmented Mode for Framed ISO PDUs. Enable: 1 - Disable: 0*/ +#endif #endif /* SUPPORT_ISO_UNSEG_MODE */ #ifndef SUPPORT_LE_ADVERTISERS_MONITORING -#define SUPPORT_LE_ADVERTISERS_MONITORING 0 /* Enable\Disable Advertisers Monitoring Feature. Enable:1 - Disable:0 */ +#ifdef STM32WBA25xx +#define SUPPORT_LE_ADVERTISERS_MONITORING 1 /* Enable\Disable Advertisers Monitoring Feature. Enable:1 - Disable:0 */ +#else +#define SUPPORT_LE_ADVERTISERS_MONITORING 0 /* Enable\Disable Advertisers Monitoring Feature. Enable:1 - Disable:0 */ +#endif #endif /* SUPPORT_LE_ADVERTISERS_MONITORING */ /* Capabilities configurations */ @@ -156,6 +180,10 @@ /*LL can use crystal oscillator or RTC or RCO to drive the sleep clock.This selection is done via "DEFAULT_SLEEP_CLOCK_SOURCE" macro. */ #endif /* USE_NON_ACCURATE_32K_SLEEP_CLK */ +#ifndef SUPPORT_CTE_DEGRADATION_API +#define SUPPORT_CTE_DEGRADATION_API 1 /* Enable\Disable CTE degradation API. Enable:1 - Disable:0 */ +#endif /* SUPPORT_CTE_DEGRADATION_API */ + /* Non-standard features configurations */ #ifndef NUM_OF_CTSM_EMNGR_HNDLS #define NUM_OF_CTSM_EMNGR_HNDLS 1 /* Number of custom handles in event manager to be used for app specific needs */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/ll_fw_config.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/ll_fw_config.h index b86618434..81a239f7c 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/ll_fw_config.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/ll_fw_config.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -129,19 +129,19 @@ #ifndef SUPPORT_CHANNEL_SOUNDING #define SUPPORT_CHANNEL_SOUNDING 0 /* Enable\Disable Channel Sounding Feature. Enable:1 - Disable:0 */ #endif /* SUPPORT_CHANNEL_SOUNDING */ - + #ifndef SUPPORT_FRAME_SPACE_UPDATE #define SUPPORT_FRAME_SPACE_UPDATE 0 /* Enable\Disable Frame Space Update Feature. Enable:1 - Disable:0 */ #endif /* SUPPORT_FRAME_SPACE_UPDATE */ - + #ifndef SUPPORT_EXT_FEATURE_SET #define SUPPORT_EXT_FEATURE_SET 0 /* Enable\Disable Extended Feature Set Exchange. Enable:1 - Disable:0 */ #endif /* SUPPORT_EXT_FEATURE_SET */ - + #ifndef SUPPORT_ISO_UNSEG_MODE #define SUPPORT_ISO_UNSEG_MODE 0 /* Enable\Disable Unsegmented Mode for Framed ISO PDUs. Enable: 1 - Disable: 0*/ #endif /* SUPPORT_ISO_UNSEG_MODE */ - + #ifndef SUPPORT_LE_ADVERTISERS_MONITORING #define SUPPORT_LE_ADVERTISERS_MONITORING 0 /* Enable\Disable Advertisers Monitoring Feature. Enable:1 - Disable:0 */ #endif /* SUPPORT_LE_ADVERTISERS_MONITORING */ @@ -201,11 +201,11 @@ #endif /* MAX_NUMBER_OF_INDIRECT_DATA */ #ifndef SUPPORT_OPENTHREAD_1_2 -#define SUPPORT_OPENTHREAD_1_2 0 /* Enable / disable FW parts related to new features introduced in openthread 1.2*/ +#define SUPPORT_OPENTHREAD_1_2 1 /* Enable / disable FW parts related to new features introduced in openthread 1.2*/ #endif /* SUPPORT_OPENTHREAD_1_2 */ #ifndef SUPPORT_SEC -#define SUPPORT_SEC 0 /* The MAC Security Supported : 1 - Not Supported:0 */ +#define SUPPORT_SEC 1 /* The MAC Security Supported : 1 - Not Supported:0 */ #endif /* SUPPORT_SEC */ #ifndef RADIO_CSMA @@ -219,6 +219,11 @@ #ifndef SUPPORT_A_MAC #define SUPPORT_A_MAC 1 #endif /* SUPPORT_A_MAC */ + +#ifndef SUPPORT_CONFIG_LIB +#define SUPPORT_CONFIG_LIB 1 /* Enable\Disable Configurable Library feature */ +#endif /* SUPPORT_CONFIG_LIB */ + #ifndef SMPL_PRTCL_TEST_ENABLE #define SMPL_PRTCL_TEST_ENABLE 0 #endif /* SMPL_PRTCL_TEST_ENABLE */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/ll_fw_config.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/ll_fw_config.h index 07d98acfa..fc52a8c49 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/ll_fw_config.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/ll_fw_config.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -186,9 +186,16 @@ #ifndef FFD_DEVICE_CONFIG #define FFD_DEVICE_CONFIG 1 /* Enable\Disable FFD:1 - RFD:0 */ #endif /* FFD_DEVICE_CONFIG */ + +#ifdef RFD_DEVICE_CONFIG +#undef FFD_DEVICE_CONFIG +#define FFD_DEVICE_CONFIG 0 /* Enable\Disable FFD:1 - RFD:0 */ +#endif + #ifndef RAL_NUMBER_OF_INSTANCE #define RAL_NUMBER_OF_INSTANCE 1 /* The Number of RAL instances supported */ #endif /* RAL_NUMBER_OF_INSTANCE */ + #ifndef MAX_NUMBER_OF_INDIRECT_DATA #define MAX_NUMBER_OF_INDIRECT_DATA 10 /* The maximum number of supported indirect data buffers */ #endif /* MAX_NUMBER_OF_INDIRECT_DATA */ @@ -213,6 +220,10 @@ #define SUPPORT_A_MAC 1 #endif /* SUPPORT_A_MAC */ +#ifndef SUPPORT_CONFIG_LIB +#define SUPPORT_CONFIG_LIB 1 /* Enable\Disable Configurable Library feature */ +#endif /* SUPPORT_CONFIG_LIB */ + #ifndef SMPL_PRTCL_TEST_ENABLE #define SMPL_PRTCL_TEST_ENABLE 0 #endif /* SMPL_PRTCL_TEST_ENABLE */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/_40nm_reg_files/DWC_ble154combo.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/_40nm_reg_files/DWC_ble154combo.h index 98fba5515..faca9e6cd 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/_40nm_reg_files/DWC_ble154combo.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/_40nm_reg_files/DWC_ble154combo.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/_40nm_reg_files/DWC_ble154combo.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/_40nm_reg_files/DWC_ble154combo.h#1 $*/ /** ******************************************************************************** * @brief @@ -14,10 +14,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/bsp.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/bsp.h index 48d04cedd..4c37276ae 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/bsp.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/bsp.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/bsp.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/bsp.h#1 $*/ /** ******************************************************************************** @@ -14,10 +14,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -104,10 +104,20 @@ typedef struct _ble_ll_bus { /* Structure holding the Event timing */ typedef struct Evnt_timing_s{ - uint32_t drift_time; /* The total drift time between the software timer value and the start execution of the function evnt_schdlr_timer_callback */ - uint32_t exec_time; /* The time to get the event ready for air transmission */ + uint32_t drift_time; /* The total drift time between the software timer value and the start execution of the function evnt_schdlr_timer_callback */ + uint32_t exec_time; /* The time to get the event ready for air transmission. + * When passed from the host, it indicates the profiled execution time. It will be replaced + * by the actual execution time using the CALCULATE_EXEC_TIME directive + * after calling ll_intf_config_schdling_time and this new value will be reported through bsp_evnt_schldr_timing_update_not */ uint32_t schdling_time; /* The total time to server the completed event and start new cycle of it, the time from longest time of the state machine done isr to till the debug dio DBG_IO_PROFILE_END_DRIFT_TIME is raised */ }Evnt_timing_t; + +typedef enum _profiling_state_e { + PROFILE_STATE_START, + PROFILE_STATE_CLEAR, + PROFILE_STATE_END, +} profiling_state_e; + /** * @brief enum holding all debugging gpio * @@ -334,6 +344,8 @@ typedef enum Debug_GPIO_e{ DBG_IO_RAL_AD_SET_MEASUREMENT_STATE , DBG_IO_PROFILE_CS_GEN , DBG_IO_PROFILE_CS_CHNL_SHUFFLING , + DBG_IO_SET_DEEP_SLEEP_MODE , + DBG_IO_BACK_FROM_DEEP_SLEEP , Debug_GPIO_num }Debug_GPIO_t; @@ -646,7 +658,7 @@ void bsp_set_phy_clbr_state(PhyClbrState state); /** * @brief a function to notify the upper layer to switch the clock. * - * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time + * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time. For the execution time, it shall follow this equation MAX(EXEC_TIME_PROFILED, PHY_WAKEUP_TIME) - PHY_WAKEUP_TIME + EXEC_TIME_MARGIN * * @retval None. */ @@ -665,6 +677,19 @@ int logUart(void* devHandle, char* logStr); void bsp_assert_log(uint8_t condition, uint8_t severity, const char *ptr_func_name, const int line); void bsp_assert(uint8_t condition, uint8_t severity); +/** + * @brief Communicates the state of the execution time profiling + * + * @param[in] state: Signals the start, end or clearance of the execution time + */ +void bsp_exec_time_profiling(const profiling_state_e state); + +/** + * @brief Communicates the profiled value for the drift time + * + * @param[in] value: Profiled value in HW Cycles + */ +void bsp_drift_time_profiling(const uint32_t value); #endif /* LL_BSP_H_ */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/common_types.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/common_types.h index f6583bcdb..a40c398c3 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/common_types.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/common_types.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/common_types.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/common_types.h#1 $*/ /** ******************************************************************************** * @file common_types.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -83,6 +83,7 @@ #else #define SUPPORT_AUG_MAC_HCI_UART 0 #endif +#define SUPPORT_RADIO_HCI_UART 0 #if((!SUPPORT_BLE)&&(SUPPORT_MAC || SUPPORT_AUG_MAC_HCI_UART)&&(RAL_NUMBER_OF_INSTANCE>1)) #error "BLE controller must be enabled to support MAC multiple Instances" @@ -95,12 +96,25 @@ #if((!SUPPORT_BLE)&&(SUPPORT_MAC)&&(SUPPORT_ANT)) #error "BLE controller must be enabled to support MAC and ANT Coexistence" #endif - +#if(SUPPORT_MAC && SUPPORT_CONFIG_LIB && (!MAC_LAYER_BUILD || !SUPPORT_OPENTHREAD_1_2)) +#error "BUILD_MAC and SUPPORT_OPENTHREAD_1_2 must be TRUE to support configurable library feature" +#endif #define SUPPORT_COEXISTENCE ((SUPPORT_BLE&&SUPPORT_MAC) || (SUPPORT_BLE&&SUPPORT_ANT)) #define SUPPORT_ANT_COEXISTENCE (SUPPORT_BLE&&SUPPORT_ANT) /****************** User configuration **********************************/ #define CS_TESTING TRUE +#define PROFILE_DISABLED 0 +#define PROFILE_DETAILED 1 +#define PROFILE_LIGHTWEIGHT 2 +#define PROFILE_BSP 3 + +#ifndef SUPPORT_PROFILE +#define SUPPORT_PROFILE PROFILE_DISABLED +#endif /* SUPPORT_PROFILE */ + +#define IS_INTERNAL_PROFILED_ENABLED ((SUPPORT_PROFILE == PROFILE_DETAILED) || (SUPPORT_PROFILE == PROFILE_LIGHTWEIGHT)) + /********************* Macros **********************************/ #ifndef SUCCESS @@ -135,14 +149,10 @@ #define MEMCPY_N_BYTES(ptr_dest, ptr_src,no_bytes ,keep_endian) ble_memcpy_n_bytes(ptr_dest,ptr_src ,no_bytes ,keep_endian) - extern os_mutex_id g_ll_lock; #define LL_LOCK() os_rcrsv_mutex_wait(g_ll_lock,0xffffffff) #define LL_UNLOCK() os_rcrsv_mutex_release(g_ll_lock) -#ifndef SUPPORT_ANT_DIV -#define SUPPORT_ANT_DIV 0 -#endif #if SUPPORT_MAC #define RADIO_MAC_TX_DONE_EVENT_MAX 1 @@ -154,6 +164,8 @@ extern os_mutex_id g_ll_lock; #define PRDC_CLBR_TMR_EVENT_MAX 1 #define CSL_RCV_TMR_EVENT_MAX 1 +#define OQPSK_RECEIVER_SENSTIVITY -85 + /* Size in octets of extended address used in security processing */ #define EXT_ADDRESS_LENGTH 8 #endif /* SUPPORT_MAC */ @@ -178,9 +190,24 @@ extern os_mutex_id g_ll_lock; #define SUPPORT_TIME_SYNC_OT_1_2 0 #endif /*SUPPORT_MAC && SUPPORT_OPENTHREAD_1_2 */ +#ifndef SUPPORT_ANT_DIV +#define SUPPORT_ANT_DIV 0 +#endif + +#ifndef SUPPORT_CONFIG_LIB +#define SUPPORT_CONFIG_LIB 0 +#endif + /* end of radio activity custom command flag */ #define END_OF_RADIO_ACTIVITY_REPORTING 1 /* Enable\Disable end of radio activity reporting feature. Enable:1 - Disable:0 */ +/** + * @brief Global error definition across different components. + * refer the error codes defined in @ref ll_error.h for more information about the values that this type should set + */ +typedef uint32_t ble_stat_t; + + /* Supported PHYs*/ typedef enum { LE_NO_CHANGE = 0x00, @@ -317,6 +344,15 @@ typedef struct _antenna_diversity_st{ uint8_t max_rx_ack_retries; /* max number of retries to receive ack in case of ack error reception*/ } antenna_diversity_st; #endif /* SUPPORT_MAC && SUPPORT_ANT_DIV */ +#if SUPPORT_MAC && SUPPORT_CONFIG_LIB +typedef struct _config_lib_st{ + uint8_t mac_layer_build; /* Disable/Enable MAC layer build */ + uint8_t support_openthread_1_2; /* Disable/Enable FW parts related to new features introduced in OpenThread 1.2. */ + uint8_t ack_all_received_frames_with_ar_bit_set; /* Disable/Enable sending ACK for all received frames with AR bit set */ +} config_lib_st; + +extern config_lib_st g_config_lib_params; +#endif /* SUPPORT_MAC && SUPPORT_CONFIG_LIB */ /* * @brief structure that hold some information about the data transmitted across layers. @@ -362,6 +398,7 @@ typedef struct _sdu_buf_hdr_st { uint32_t time_offset; /* Time Offset used only in framed SDUs */ uint16_t pkt_sqnc_num; /* Packet Sequence Number */ uint16_t iso_sdu_len; /* ISO SDU data real length */ + uint16_t total_sdu_len; /* total sdu length for all sdu fragments */ uint8_t pkt_status_flag; uint8_t pb_flag; /* PB_flag used in rx */ /* @@ -407,7 +444,6 @@ typedef enum { AUG_HCI_MAC_REQ = 0x0C, AUG_HCI_MAC_CFM = 0x0D, #endif /* SUPPORT_AUG_MAC_HCI_UART */ - } event_t; @@ -435,12 +471,12 @@ typedef enum { #define BLE_BUFF_HDR_MAC_CMD_PCK (1<<6) #define BLE_BUFF_HDR_MAC_KEY_TBL_CMD_PCK ((1<<7)|(1<<4)) #endif /* (SUPPORT_MAC && SUPPORT_MAC_HCI_UART) */ +#if (SUPPORT_AUG_MAC_HCI_UART) +#define BLE_BUFF_HDR_AUG_MAC_CMD_PCK ((1<<7)|(1<<6)) +#endif /* SUPPORT_AUG_MAC_HCI_UART */ #if (SUPPORT_ANT_HCI_UART) #define BLE_BUFF_HDR_ANT_CMD_PCK (1<<7) #endif /* SUPPORT_ANT_HCI_UART */ -#if (SUPPORT_AUG_MAC_HCI_UART) -#define BLE_BUFF_HDR_AUG_MAC_CMD_PCK ((1<<7)|(1<<6)) -#endif /** @@ -450,14 +486,15 @@ typedef enum { #define DEFAULT_PHY_CALIBRATION_PERIOD 10 /* Time period for PHY calibration = 10s */ #endif /* DEFAULT_PHY_CALIBRATION_PERIOD */ -#if defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) -#define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 1 +#ifndef SUPPORT_MAC_PHY_CONT_TESTING_CMDS +#define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 1 +#endif /* SUPPORT_MAC_PHY_CONT_TESTING_CMDS */ + +#if (defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) || defined(PHY_40nm_6_00_a)) +#define SUPPORT_MAC_CONT_TESTING_CMDS_PHY_SUPPORT SUPPORT_MAC_PHY_CONT_TESTING_CMDS #else -#define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 0 -#if(SUPPORT_MAC_PHY_CONT_TESTING_CMDS) -#error "SUPPORT_MAC_PHY_CONT_TESTING_CMDS must be enabled for PHY_40nm_3_00_a or PHY_40nm_3_40_a only" -#endif/*end of (SUPPORT_MAC_PHY_CONT_TESTING_CMDS) */ -#endif /*end of defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) */ +#define SUPPORT_MAC_CONT_TESTING_CMDS_PHY_SUPPORT 0 +#endif /*end of defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) || defined(PHY_40nm_6_00_a) */ #ifndef EXTERNAL_CUSTOM_CMDS #define EXTERNAL_CUSTOM_CMDS 0 /* Indicates that an external custom HCI commands module exists */ @@ -523,33 +560,58 @@ typedef enum { #endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ #if SUPPORT_CONFIGURABLE_GAIN_FIX +#define SUPPORT_DYNAMIC_PREEMPH_COEFF 1 /* Enable\Disable dynamic preemphasis coefficients support */ #define PREEMPH_GAIN_COEFF_STEP_SIZE 10 /* percentage margin of single step */ #define GAIN_FIX_WAKEUP_TIME_OVERHEAD 4 /* in sleep timer units, the added time overhead from patching all pre-emphasis coefficients */ #else +#define SUPPORT_DYNAMIC_PREEMPH_COEFF 0 #define GAIN_FIX_WAKEUP_TIME_OVERHEAD 0 #endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ #ifndef SUPPORT_PHY_SHUTDOWN_MODE -#if defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) #define SUPPORT_PHY_SHUTDOWN_MODE 1 /* Enable\Disable phpy shutdown mode support */ -#else -#define SUPPORT_PHY_SHUTDOWN_MODE 0 -#endif /* defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) */ #endif /* SUPPORT_PHY_SHUTDOWN_MODE */ -#if SUPPORT_PHY_SHUTDOWN_MODE +#if (defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) || defined(PHY_40nm_6_00_a)) +#define PHY_SHUTDOWN_MODE_PHY_SUPPORT SUPPORT_PHY_SHUTDOWN_MODE +#else +#define PHY_SHUTDOWN_MODE_PHY_SUPPORT 0 +#endif /* defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) || defined(PHY_40nm_6_00_a) */ + +#if PHY_SHUTDOWN_MODE_PHY_SUPPORT #define PHY_SHUTDOWN_WAKEUP_TIME_OVERHEAD 2 /* in sleep timer units, the added time overhead from executing override seqeuences needed in phy shutdown mode */ #else #define PHY_SHUTDOWN_WAKEUP_TIME_OVERHEAD 0 -#endif /* SUPPORT_PHY_SHUTDOWN_MODE */ +#endif /* PHY_SHUTDOWN_MODE_PHY_SUPPORT */ + +#ifndef SUPPORT_CTE_DEGRADATION_API +#define SUPPORT_CTE_DEGRADATION_API 0 /* Enable\Disable CTE PHY Degradation fix support */ +#endif /* SUPPORT_CTE_DEGRADATION_API */ + +#if (defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a)) +#define CTE_DEGRADATION_API_PHY_SUPPORT SUPPORT_CTE_DEGRADATION_API +#else +#define CTE_DEGRADATION_API_PHY_SUPPORT 0 +#endif /* defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) */ #ifndef SUPPORT_GNRC_SCHDLR_IF #define SUPPORT_GNRC_SCHDLR_IF 1 -#endif +#endif /* SUPPORT_GNRC_SCHDLR_IF */ + #ifndef NEAR_AUX_AFTER_EXT_SLEEP_TIMER_SCHEDULING #define NEAR_AUX_AFTER_EXT_SLEEP_TIMER_SCHEDULING 0 #endif /* NEAR_AUX_AFTER_EXT_SLEEP_TIMER_SCHEDULING */ +#ifndef SUPPORT_LE_ENHANCED_CONN_UPDATE +#define SUPPORT_LE_ENHANCED_CONN_UPDATE 0 +#endif /* SUPPORT_LE_ENHANCED_CONN_UPDATE */ + +#if defined(PHY_40nm_6_00_a) +#define PHY_USE_APB_TRANSPORT 1 +#else +#define PHY_USE_APB_TRANSPORT 0 +#endif /*PHY_40nm_6_00_a */ + #if (SUPPORT_CHANNEL_SOUNDING &&( SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) /** * @brief holds the possible values for cs roles @@ -581,4 +643,18 @@ typedef struct _cs_host_buffer { #endif /*SUPPORT_CHANNEL_SOUNDING &&( SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)*/ +#ifndef ENABLE_AUTOMOUS_SCHEDULING_TIMING_UPDATE +/** + * Compiler flag to enable autonomous link layer timing updates, which increases EXEC_TIME when some event fails to execute multiple times. + * This serves as a recovery mechanism for misconfigured EXEC_TIME values. However, enabling this flag may introduce conflicts in some multi-role scenarios. + * The recommended approach is to set EXEC_TIME correctly based on the worst-case scenario, in which case this flag is not needed. + * If EXEC_TIME is not set properly, enabling this flag may cause conflicts and degrade scheduling performance, which is expected. + * If conflicts arise due to the autonomous link layer timing introduced by this flag, EXEC_TIME should be re-profiled and the new profiled value should be set in EXEC_TIME_PROFILED. + * If @ref SUPPORT_TIM_UPDT is set to 0, this flag has no meaning + */ +#define ENABLE_AUTOMOUS_SCHEDULING_TIMING_UPDATE 0 +#endif /*ENABLE_AUTOMOUS_SCHEDULING_TIMING_UPDATE*/ + + + #endif /*COMMON_TYPES_H_*/ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/dtm.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/dtm.h index 06a7c9bdd..b5440bf52 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/dtm.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/dtm.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/dtm.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/dtm.h#1 $*/ /** ******************************************************************************** * @file dtm.h @@ -15,10 +15,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/event_manager.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/event_manager.h index 17d69182e..3b397c02d 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/event_manager.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/event_manager.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/event_manager.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/event_manager.h#1 $*/ /** ******************************************************************************** * @file event_manager.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -96,18 +96,15 @@ typedef enum { #endif /* SUPPORT_LE_PAWR_ADVERTISER_ROLE */ #endif /* SUPPORT_LE_EXTENDED_ADVERTISING */ #endif /*SUPPORT_BLE*/ -#if SUPPORT_COEXISTENCE - COEX_TIMER_EVENT, -#endif #if SUPPORT_MAC RADIO_MAC_TX_DONE_EVENT, RAL_SM_DONE_EVENT, MAC_SM_DONE_EVENT, ED_TMR_EVENT, #endif /*SUPPORT_MAC*/ -#if ((SUPPORT_BLE)||(SUPPORT_MAC_HCI_UART)||(SUPPORT_ANT_HCI_UART) || (SUPPORT_AUG_MAC_HCI_UART)) +#if ((SUPPORT_BLE)||(SUPPORT_MAC_HCI_UART)||(SUPPORT_ANT_HCI_UART) || (SUPPORT_AUG_MAC_HCI_UART) || (SUPPORT_RADIO_HCI_UART)) HCI_TRANSPORT_HANDLER, /* handler for the HCI transport events; handling events from HCI to Host */ -#endif /*SUPPORT_BLE*/ +#endif /* ((SUPPORT_BLE)||(SUPPORT_MAC_HCI_UART)||(SUPPORT_ANT_HCI_UART) || (SUPPORT_AUG_MAC_HCI_UART) || (SUPPORT_RADIO_HCI_UART)) */ #if (SUPPORT_HCI_EVENT_ONLY) GENERIC_EVENT, #if SUPPORT_SYNC_ISOCHRONOUS || SUPPORT_CONNECTED_ISOCHRONOUS diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/evnt_schdlr_gnrc_if.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/evnt_schdlr_gnrc_if.h index 2189fe178..0ee37af4e 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/evnt_schdlr_gnrc_if.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/evnt_schdlr_gnrc_if.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/evnt_schdlr_gnrc_if.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/evnt_schdlr_gnrc_if.h#1 $*/ /** ******************************************************************************** * @file evnt_schdlr_gnrc_if.h @@ -14,10 +14,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/hci.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/hci.h index 8947c4342..a6a4f6f3c 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/hci.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/hci.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/hci.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/hci.h#1 $*/ /** ******************************************************************************** * @file hci.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_error.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_error.h index 330c2c8ca..74d3d1949 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_error.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_error.h @@ -1,4 +1,5 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/ll_error.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/ll_error.h#1 $*/ + /** ******************************************************************************** * @file error.h @@ -13,10 +14,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -211,9 +212,13 @@ typedef enum _HW_ERROR_CODES #error Advertisers Monitoring feature can be enabled when the device is an observer. #endif /* ((SUPPORT_LE_ADVERTISERS_MONITORING) && (!SUPPORT_EXPLCT_OBSERVER_ROLE)) */ -#if ((SUPPORT_PHY_SHUTDOWN_MODE) && !(defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a))) -#error Phy Shutdown feature is only supported on PHY_40nm_3_60_a_tc, PHY_40nm_3_00_a and PHY_40nm_3_40_a -#endif /* ((SUPPORT_PHY_SHUTDOWN_MODE) && !(defined(PHY_40nm_3_60_a_tc) || defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a))) */ +#if defined(PHY_40nm_2_00_a_tc) +#error "PHY_40nm_2_00_a_tc is not supported by the current FW version" +#endif /* PHY_40nm_2_00_a_tc */ + +#if (SUPPORT_DYNAMIC_PREEMPH_COEFF && CTE_DEGRADATION_API_PHY_SUPPORT) +#error "Dynamic Preemphasis coefficients feature cannot be enabled while the CTE degradation API is enabled" +#endif /* SUPPORT_DYNAMIC_PREEMPH_COEFF && CTE_DEGRADATION_API_PHY_SUPPORT */ /* Exported macros ------------------------------------------------------------*/ @@ -223,4 +228,4 @@ typedef enum _HW_ERROR_CODES #endif /* SUPPORT_BLE */ #endif /* ERROR_H_ */ -/******************* (C) (C) COPYRIGHT 2024 SYNOPSYS, INC. *****END OF FILE****/ +/******************* (C) (C) COPYRIGHT 2025 SYNOPSYS, INC. *****END OF FILE****/ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf.h index 18228cdc9..cef1fa744 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/ll_intf.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/ll_intf.h#1 $*/ /** ******************************************************************************** * @file ll_intf_cmds.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -35,11 +35,7 @@ #if SUPPORT_PTA #include "pta.h" #endif /* SUPPORT_PTA */ -/** - * @brief Global error definition across different components. - * refer the error codes defined in @ref ll_error.h for more information about the values that this type should set - */ -typedef uint32_t ble_stat_t; + #if (SUPPORT_CHANNEL_SOUNDING && \ (SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) @@ -2474,7 +2470,7 @@ ble_stat_t ll_intf_read_local_supported_features(uint8_t lmp_features[8]); * * @retval None. */ -ble_stat_t ll_intf_read_local_extended_features(uint8_t* page_number, uint8_t lmp_features[8], uint8_t* max_page_number); +ble_stat_t ll_intf_read_local_extended_features(uint8_t page_number, uint8_t lmp_features[8], uint8_t* max_page_number); #endif /* SUPPORT_EXT_FEATURE_SET */ /** @@ -5461,11 +5457,12 @@ ble_stat_t ll_intf_set_dtm_with_spcfc_pckt_count(uint16_t pckt_count); /** * @brief used to update the event timing. * - * @param p_evnt_timing[in]: pointer to structure containing the new Event timing requested from the Upper layer. + * @param p_evnt_timing[in]: pointer to structure containing the new Event timing requested from the Upper layer. All the values passed within should be the worst case timings. The acutal time for each timing is calculated by the link layer. + * @param effective_exec_time[out]: Execution time calculated by the controller. * * @retval None */ -void ll_intf_config_schdling_time(Evnt_timing_t * p_evnt_timing); +void ll_intf_config_schdling_time(Evnt_timing_t * p_evnt_timing, uint32_t* effective_exec_time); #endif /* SUPPORT_TIM_UPDT */ @@ -5511,6 +5508,25 @@ void ll_intf_gain_fix_init( #endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ +#if CTE_DEGRADATION_API_PHY_SUPPORT +/** + * @brief replace the contents of the wakeup and interpacket + * sequences to apply the CTE Degradation fix. + * + * @retval None. + */ +void ll_intf_apply_cte_degrad_change(void); +#endif /* CTE_DEGRADATION_API_PHY_SUPPORT */ + +#if IS_INTERNAL_PROFILED_ENABLED +/** + * @brief Gets the maximum times for the execution time and drift time + * @param exec_time [out]: Max Execution Time + * @param drift_time [out]: Max Drift Time + */ +void ll_intf_get_profile_statistics(uint32_t* exec_time, uint32_t* drift_time); +#endif /* IS_INTERNAL_PROFILED_ENABLED */ + /**@} */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf_cmn.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf_cmn.h index fa65f4f81..dc088f308 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf_cmn.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ll_intf_cmn.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/ll_intf_cmn.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/ll_intf_cmn.h#1 $*/ /** ******************************************************************************** * @file ll_intf_cmn.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -165,6 +165,16 @@ void ll_intf_cmn_gain_fix_init( uint8_t region_0x0b_val, uint8_t region_0x09_val, uint8_t r_msur_percent); #endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ +/*=============== Set PHY Calibration Period =================*/ + /** + * @brief set PHY calibration period. + * + * @param phy_clbr_evnt_period : [in] Indicate the periodicity of the PHY calibration event. Periodicity = phy_clbr_evnt_period * 1s. + * @param phy_clbr_evnt_count : [in] Indicate the number of the PHY calibration events to be executed. + * + * @retval None + */ +void ll_intf_cmn_set_phy_clbr_period(uint32_t phy_clbr_evnt_period, uint32_t phy_clbr_evnt_count); /** @} */ diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mac_host_intf.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mac_host_intf.h index 812b586c2..1ab60da4a 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mac_host_intf.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mac_host_intf.h @@ -15,10 +15,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mem_intf.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mem_intf.h index 26a94e23b..2fe3efd6a 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mem_intf.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/mem_intf.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/mem_intf.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/mem_intf.h#1 $*/ /** ******************************************************************************** * @file mem_intf.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/os_wrapper.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/os_wrapper.h index 230f6f5bb..401389be6 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/os_wrapper.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/os_wrapper.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/os_wrapper.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/os_wrapper.h#1 $*/ /** ******************************************************************************** * @file os_wrapper.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/platform.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/platform.h index a893acac3..be5c1736d 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/platform.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/platform.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/platform.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/platform.h#1 $*/ /** ******************************************************************************** * @file platform.h @@ -15,10 +15,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -464,7 +464,7 @@ void radio_run_phy_clbr_on_temp_change(void); */ otError radio_set_dp_slp_mode(dpslp_state_e dp_slp_mode); #endif /*end of (!SUPPORT_COEXISTENCE)*/ -#if SUPPORT_MAC_PHY_CONT_TESTING_CMDS +#if SUPPORT_MAC_CONT_TESTING_CMDS_PHY_SUPPORT /** * * @brief set the phy continuous modulation and continuous wave modes upon enable @@ -476,7 +476,7 @@ otError radio_set_dp_slp_mode(dpslp_state_e dp_slp_mode); * @retval Status */ otError platform_zigbee_set_phy_cont_modul_mode(uint8_t type, uint8_t enable_mode, uint8_t chnl_num, int8_t pwr); -#endif /*end of SUPPORT_MAC_PHY_CONT_TESTING_CMDS */ +#endif /*end of SUPPORT_MAC_CONT_TESTING_CMDS_PHY_SUPPORT */ #if SUPPORT_ANT_DIV /** * @@ -528,6 +528,35 @@ otError radio_set_default_ant_id(otInstance *aInstance, uint8_t default_ant_id); */ otError radio_set_ant_div_rssi_threshold(otInstance *aInstance, int8_t rssi_threshold); #endif /* SUPPORT_ANT_DIV */ +/** + * + * @brief set bus latency between thread core and radio platform + * + * @param aInstance[in] : radio instance + * @param bus_latency[in] : Time in Us for latency between thread core and radio platform + * @retval None + */ +void otPlatRadioSetBusLatency(otInstance *aInstance, uint32_t bus_latency); +#if SUPPORT_OPENTHREAD_1_2 +/** + * + * @brief Set clock accuracy + * + * @param clk_acc: [in] Value for clock accuracy in PPM + * + * @retval None . + */ +void radio_set_clk_accuracy(uint8_t clk_acc); +/** + * + * @brief Set clock uncertainty + * + * @param clk_uncer: [in] Value for clock uncertainty in units of 10 us. + * + * @retval None . + */ +void radio_set_clk_uncertainty(uint8_t clk_uncer); +#endif /*SUPPORT_OPENTHREAD_1_2*/ #if SUPPORT_CONFIGURABLE_GAIN_FIX /** @@ -548,6 +577,62 @@ void radio_gain_fix_init( uint8_t r_msur_percent); #endif /* SUPPORT_CONFIGURABLE_GAIN_FIX */ +#if SUPPORT_CONFIG_LIB +/** + * + * @brief set configurable library parameters + * + * @param ptr_config_lib_params[in] : pointer to configurable library parameters structure + * @retval Status + */ +otError radio_set_config_lib_params(otInstance *aInstance, config_lib_st* ptr_config_lib_params); +/** + * + * @brief get current configurable library parameters + * + * @param aInstance[in] : radio instance + * @param ptr_config_lib_params[out] : pointer to configurable library parameters structure + * @retval None + */ +void radio_get_config_lib_params(otInstance *aInstance, config_lib_st* ptr_config_lib_params); + +/** + * + * @brief set RTL polling time + * + * @param aInstance[in] : radio instance + * @param rtl_polling_time[in] : RTL polling time value + * @retval None + */ +void radio_set_rtl_polling_time(otInstance *aInstance, uint8_t rtl_polling_time); + +/** + * + * @brief get current RTL polling time + * + * @param aInstance[in] : radio instance + * @retval current RTL polling time + */ +uint8_t radio_get_rtl_polling_time(otInstance *aInstance); +#endif /* SUPPORT_CONFIG_LIB */ +#if !SUPPORT_COEXISTENCE && DEFAULT_PHY_CALIBRATION_PERIOD +/** + * + * @brief set phy calibration period + * + * @param phy_clbr_evnt_period[in] : phy calibration period + * @retval None + */ +void radio_set_phy_clbr_period(uint32_t phy_clbr_evnt_period); +#endif /* !SUPPORT_COEXISTENCE && DEFAULT_PHY_CALIBRATION_PERIOD */ +#if SUPPORT_COEXISTENCE && RADIO_CSMA +/** + * @brief get minimum block counter of TX packet to increase priority to critical. + * + * @retval minimum block number of TX packets to be critical + */ +uint8_t radio_get_min_blck_cnt_to_be_critical(void); +#endif /* SUPPORT_COEXISTENCE && RADIO_CSMA */ #endif /* INCLUDE_PLATFORM_H_ */ /** diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/power_table.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/power_table.h index 5bc292556..5477adcc2 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/power_table.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/power_table.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/power_table.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/power_table.h#1 $*/ /** ****************************************************************************** * @file power_table.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/pta.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/pta.h index 6453309dc..2a348f234 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/pta.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/pta.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/pta.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/pta.h#1 $*/ /** ****************************************************************************** * @file pta.h @@ -13,10 +13,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ral.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ral.h index afc029237..9da708694 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ral.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/ral.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/ral.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/ral.h#1 $*/ /** ******************************************************************************** * @file ral.h @@ -9,28 +9,36 @@ * ****************************************************************************** * @copy + * This Synopsys DWC Bluetooth Low Energy Combo Link Layer/MAC software and + * associated documentation ( hereinafter the "Software") is an unsupported + * proprietary work of Synopsys, Inc. unless otherwise expressly agreed to in + * writing between Synopsys and you. The Software IS NOT an item of Licensed + * Software or a Licensed Product under any End User Software License Agreement + * or Agreement for Licensed Products with Synopsys or any supplement thereto. + * Synopsys is a registered trademark of Synopsys, Inc. Other names included in + * the SOFTWARE may be the trademarks of their respective owners. + * * Synopsys MIT License: * Copyright (c) 2020-Present Synopsys, Inc * - * Permission is hereby granted, free of charge, to any person obtaining a copy of the software and - * associated documentation files (the “Software”), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the - * following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or substantial - * portions of the Software. - * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * the Software), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, + * sublicense, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE - * ARISING FROM, OUT OF, OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE ARISING FROM, + * OUT OF, OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * */ - + #ifndef INCLUDE_RAL_H_ #define INCLUDE_RAL_H_ @@ -122,6 +130,9 @@ typedef enum ral_error_enum { #if SUPPORT_ANT_DIV RAL_ERROR_AD_NOT_IN_CONFIG_STATE, #endif /* SUPPORT_ANT_DIV */ +#if SUPPORT_CONFIG_LIB + RAL_ERROR_CONFIG_LIB_NOT_IN_CONFIG_STATE, +#endif /* SUPPORT_CONFIG_LIB */ RAL_ERROR_GENERIC = 255 } ral_error_enum_t; @@ -167,6 +178,18 @@ typedef enum ral_ack_type_enum { #endif RAL_ACK_MAC } ral_ack_type_enum_t; +#if SUPPORT_CONFIG_LIB +/* @brief: Define configurable library states: + * + * CONFIGURABLE : includes pre-initialization and post-reset states. + * NOT_CONIFUGRABLE: includes post-initialization and running states. + * */ +typedef enum config_lib_state_enum { + NOT_CONFIGURED_NOT_INITIALIZED, // initial state + CONFIGURED_NOT_INITIALIZED, // the state of post-reset or configuring using API + CONFIGURED_INITIALIZED // post-initialization state +} config_lib_state_enum_t; +#endif /* SUPPORT_CONFIG_LIB */ /* @brief: Define ral time structure that contains fine and base */ typedef ble_time_t ral_time_st; @@ -180,6 +203,7 @@ typedef ble_time_t ral_time_st; typedef struct _ral_pkt_st { uint8_t * ptr_pyld; /* pointer to packet */ ral_time_st time_stamp; /* exact time in which the packet transmitted/received */ + uint16_t num_ov_cycles; /* variable to store the number of cycles the overflow when packet is received*/ uint16_t pyld_len; /* packet length */ uint8_t channel; /* channel at which the packet will be transmitted */ uint8_t rxchannelaftertxdone; /* The RX channel after frame TX is done (after all frame retries - ack received, or timeout, or abort).*/ @@ -194,7 +218,8 @@ typedef struct _ral_pkt_st { #endif int8_t tx_power; /* power of transmitted packet */ uint8_t last_tx_pkt; /* last transmitted packet flag */ - uint8_t csl_frame; /* True only if the current TX frame is a CSL frame */ + uint8_t csl_frame; /* True only if the current TX frame is a CSL frame */ + uint8_t is_poll_req; /* True only if the current TX frame is a Poll reuest frame */ } tx_info; struct @@ -603,6 +628,16 @@ extern llhwc_mac_evnt_info_mem_t* g_mac_event_info; * @retval ral instance associated to this context that should be used with any ral interface */ ral_instance_t ral_init(ral_cbk_dispatch_tbl_st * ptr_cbk_dispatch_tbl); +/** + * + * + * @brief radio abstraction layer reset + * + * @param ral_instance : [in] current RAL instance + * + * @retval None + */ +void ral_reset(ral_instance_t ral_instance); /** * @@ -781,7 +816,7 @@ ral_error_enum_t ral_set_ifs(ral_instance_t ral_instance, uint16_t ifs); * @param ral_instance : [in] ral instance * @param pkt_src : [in] transmission packet source, FIFO based or Packet based * @param ptr_pkt : [in] pointer to transmitted packet if packet source is Packet based only - * @param ptr_start_time : [in] pointer to start time structure which contains start time of transmission + * @param ptr_start_time : [in] pointer to start time structure which contains start time of transmission (SFD of packet) * if NULL function will use the current time get from llhwc_slptmr_get * @param periodic_interval : [in] periodic interval in microsecond, 0 means not periodic * @param ptr_coex_info : [in] pointer to current coexistence parameters @@ -926,7 +961,7 @@ ral_error_enum_t ral_set_cont_recp_state(ral_instance_t ral_instance, ral_state_ */ ral_error_enum_t ral_set_auto_sleep_state(ral_instance_t ral_instance, ral_state_enum_t auto_sleep_state); /** - * @brief This function used to get the state of automatic switching to sleep mode + * @brief This function used to get the state of automatic switching to sleep mode * * @param ral_instance : [in] ral instance * @@ -1275,12 +1310,13 @@ void ral_set_ot_base_slp_time_value(uint32_t time); uint64_t ral_get_ot_base_slp_time_value(void); /** * @brief Convert the value of sleep timer to openthread time - * @param time [in] : sleep timer value to be converted to openthread time + * @param time [in] : sleep timer value to be converted to openthread time + * @param num_of_overflow [in] : number of overflow cycles to be added * @note if openthread is not integrated, @ref ral_ot_base_slp_time is set to zero, no conversion will take place * @retval uint64_t. the converted time value */ -uint64_t ral_cnvert_slp_tim_to_ot_tim(uint32_t time); +uint64_t ral_cnvert_slp_tim_to_ot_tim(uint32_t time, uint16_t num_of_overflow); /** * @brief Convert the value of openthread time to sleep timer value * @param time [in] : openthread time value to be converted to sleep timer @@ -1448,10 +1484,11 @@ uint8_t radio_get_cca_en(void); * * @param evnt_type : [in] type of new retry (CONTINUE_CSMA_RETRY , START_NEW_FULL_TX_RETRY) * @param radio_error : [in] error returned from previous TX trial + * @param is_tx_blocked : [in] flag to indicate that TX event is blocked * * @retval None . */ -void radio_set_tx_retry_pending(tx_new_retry_enum_t evnt_type, otError radio_error); +void radio_set_tx_retry_pending(tx_new_retry_enum_t evnt_type, otError radio_error, uint8_t is_tx_blocked); /** * * @brief handle pending tx retry event @@ -1498,8 +1535,50 @@ void ral_set_implicitbroadcast(ral_instance_t ral_instance, uint8_t ImplicitBroa * @retval void */ void ed_timer_hndl(void* ptr_info); +#if SUPPORT_CONFIG_LIB +/** + * @fn ral_set_config_lib_params + * + * @brief set configurable library parameters + * + * @param ptr_config_lib_params : [in] pointer to configurable library parameters structure + * + * @retval RAL_ERROR_NONE if configurable library parameters are set correctly + */ +ral_error_enum_t ral_set_config_lib_params(config_lib_st* ptr_config_lib_params); +/** + * @fn ral_get_config_lib_params + * + * @brief get configurable library parameters + * + * @param ptr_config_lib_params : [out] pointer to configurable library parameters structure + * + * @retval void + */ +void ral_get_config_lib_params(config_lib_st* ptr_config_lib_params); +/** + * @fn ral_set_rtl_polling_time + * + * @brief set RTL polling time + * + * @param rtl_polling_time : [in] RTL polling time + * + * @retval void + */ +void ral_set_rtl_polling_time(uint8_t rtl_polling_time); -#if SUPPORT_MAC_PHY_CONT_TESTING_CMDS +/** + * @fn ral_get_rtl_polling_time + * + * @brief get current RTL polling time + * + * @param None + * + * @retval current RTL polling time + */ +uint8_t ral_get_rtl_polling_time(void); +#endif /* SUPPORT_CONFIG_LIB */ +#if SUPPORT_MAC_CONT_TESTING_CMDS_PHY_SUPPORT /** * * @brief set the phy continuous modulation and continuous wave modes @@ -1519,7 +1598,8 @@ void ed_timer_hndl(void* ptr_info); * @retval Status */ void ral_phy_set_zigbee_phy_cont_test_mode(ral_instance_t instance, uint8_t type, uint8_t enable_mode, uint8_t chnl_num, int8_t tx_pwr); -#endif /*end of SUPPORT_MAC_PHY_CONT_TESTING_CMDS */ +#endif /*end of SUPPORT_MAC_CONT_TESTING_CMDS_PHY_SUPPORT */ + #if SUPPORT_A_MAC /** @@ -1536,6 +1616,19 @@ void ral_phy_set_zigbee_phy_cont_test_mode(ral_instance_t instance, uint8_t type */ ral_error_enum_t ral_get_a_mac_params(ral_instance_t ral_instance,ral_a_mac_params_st* a_mac_params); #endif /*SUPPORT_A_MAC*/ +/** + * + * @fn ral_set_drop_on_error + * + * @brief set value for drop on error flag + * + * @param ral_instance : [in] ral instance + * + * @param drop_on_error : [in] value for drop on error flag + * + * @retval None + */ +void ral_set_drop_on_error(ral_instance_t ral_instance, uint8_t drop_on_error); #endif /* INCLUDE_RAL_H_ */ /** diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/rfd_dev_config.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/rfd_dev_config.h index e91073abc..839c24563 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/rfd_dev_config.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_cmd_lib/inc/rfd_dev_config.h @@ -1,4 +1,4 @@ -/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca01/firmware/public_inc/rfd_dev_config.h#1 $*/ +/*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/2.00a-lca03/firmware/public_inc/rfd_dev_config.h#1 $*/ /** ******************************************************************************** * @file rfd_dev_config.h @@ -15,10 +15,10 @@ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies * of the Software, and to permit persons to whom the Software is furnished to do so, subject to the * following conditions: - * + * * The above copyright notice and this permission notice shall be included in all copies or substantial * portions of the Software. - * + * * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h index 4e5949120..697192788 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/linklayer_plat.h @@ -212,14 +212,14 @@ extern void LINKLAYER_PLAT_RequestTemperature(void); * @param None * @retval None */ -extern void LINKLAYER_PLAT_EnableOSContextSwitch(void); +extern void LINKLAYER_PLAT_PhyStartClbr(void); /** * @brief Disable RTOS context switch. * @param None * @retval None */ -extern void LINKLAYER_PLAT_DisableOSContextSwitch(void); +extern void LINKLAYER_PLAT_PhyStopClbr(void); /** * @brief Notify the upper layer that new Link Layer timings have been applied. diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/ll_sys.h b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/ll_sys.h index ff83ef2e4..210b6cccf 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/ll_sys.h +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/inc/ll_sys.h @@ -19,7 +19,6 @@ #ifndef LL_SYS_H #define LL_SYS_H -#include "app_conf.h" #include "ll_intf.h" #include "hci.h" #include "cmsis_compiler.h" @@ -90,8 +89,8 @@ void ll_sys_enable_irq(void); void ll_sys_disable_irq(void); void ll_sys_enable_specific_irq(uint8_t isr_type); void ll_sys_disable_specific_irq(uint8_t isr_type); -void ll_sys_enable_os_context_switch(void); -void ll_sys_disable_os_context_switch(void); +void ll_sys_phy_start_clbr(void); +void ll_sys_phy_stop_clbr(void); /* Link Layer system interface deep sleep module functions ************************************************/ ll_sys_status_t ll_sys_dp_slp_init(void); @@ -120,9 +119,9 @@ uint8_t ll_sys_get_concurrent_state_machines_num(void); * @param exec_time[in]: number of Link Layer sleep timer cycles (1 cycle = 31us) for the EXEC TIME timing. * @note This interface needs to be called after system initialization * and before starting any radio activity. - * @retval None + * @retval uint32_t : Effective EXEC_Time value computed from the exec_time value profiled and given in parameter. */ -void ll_sys_config_BLE_schldr_timings(uint8_t drift_time, uint8_t exec_time); +uint32_t ll_sys_config_BLE_schldr_timings(uint8_t drift_time, uint8_t exec_time); #endif /* BLE */ uint32_t ll_intf_cmn_get_slptmr_value(void); diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_cs.c b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_cs.c index 93f424d95..4f002220a 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_cs.c +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_cs.c @@ -59,12 +59,12 @@ void ll_sys_disable_specific_irq(uint8_t isr_type) LINKLAYER_PLAT_DisableSpecificIRQ(isr_type); } -void ll_sys_enable_os_context_switch(void) +void ll_sys_phy_start_clbr(void) { - LINKLAYER_PLAT_EnableOSContextSwitch(); + LINKLAYER_PLAT_PhyStartClbr(); } -void ll_sys_disable_os_context_switch(void) +void ll_sys_phy_stop_clbr(void) { - LINKLAYER_PLAT_DisableOSContextSwitch(); + LINKLAYER_PLAT_PhyStopClbr(); } \ No newline at end of file diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_dp_slp.c b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_dp_slp.c index 8d4e27ec9..e68815e63 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_dp_slp.c +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_dp_slp.c @@ -143,6 +143,6 @@ ll_sys_status_t ll_sys_dp_slp_exit(void){ void ll_sys_dp_slp_wakeup_evt_clbk(void const *ptr_arg){ /* Link Layer IP exits from DEEP SLEEP mode */ - ll_sys_dp_slp_exit(); + (void)ll_sys_dp_slp_exit(); } diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_intf.c b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_intf.c index e8151693d..4065d902e 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_intf.c +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_intf.c @@ -167,7 +167,7 @@ void ll_sys_bg_process(void) { if(emngr_can_mcu_sleep() == 0) { - ll_sys_dp_slp_exit(); + (void)ll_sys_dp_slp_exit(); emngr_handle_all_events(); HostStack_Process(); diff --git a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c index 09828ba5a..1a056414a 100644 --- a/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c +++ b/lib/stm32wba/STM32_WPAN/link_layer/ll_sys/src/ll_sys_startup.c @@ -22,9 +22,11 @@ #include "ll_sys_startup.h" #include "common_types.h" #if defined(CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA) -#if defined(MAC) && (SUPPORT_OPENTHREAD_1_2 == 0) +#if defined(MAC) +#ifndef OPENTHREAD_CONFIG_FILE /* Projects with MAC Layer (i.e. 15.4 except Thread) */ #include "st_mac_802_15_4_sap.h" +#endif /* OPENTHREAD_CONFIG_FILE */ #endif /* MAC */ #endif /* CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA */ /** @@ -60,7 +62,8 @@ void ll_sys_ble_cntrl_init(hst_cbk hostCallback) } #endif /* BLE */ #if defined(CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA) -#if defined(MAC) && (SUPPORT_OPENTHREAD_1_2 == 0) +#if defined(MAC) +#ifndef OPENTHREAD_CONFIG_FILE /** * @brief Initialize the Link Layer IP 802.15.4 MAC controller * @param None @@ -71,6 +74,7 @@ void ll_sys_mac_cntrl_init(void) ST_MAC_preInit(); ll_sys_dependencies_init(); } +#endif /* OPENTHREAD_CONFIG_FILE */ #endif /* MAC */ #endif /* CONFIG_NET_L2_CUSTOM_IEEE802154_STM32WBA */ /** diff --git a/lib/stm32wba/ble/Core/Inc/app_conf.h b/lib/stm32wba/ble/Core/Inc/app_conf.h index c832b2c2a..1dfc4e75f 100644 --- a/lib/stm32wba/ble/Core/Inc/app_conf.h +++ b/lib/stm32wba/ble/Core/Inc/app_conf.h @@ -38,12 +38,12 @@ /** * Identity root key used to derive IRK and DHK(Legacy) */ -#define CFG_BLE_IR {0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0} +#define CFG_BLE_IR {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /** * Encryption root key used to derive LTK(Legacy) and CSRK */ -#define CFG_BLE_ER {0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21, 0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21} +#define CFG_BLE_ER {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /* USER CODE BEGIN Generic_Parameters */ @@ -109,7 +109,12 @@ * - 2, if extended properties is used * The total amount of memory needed is the sum of the above quantities for each attribute. */ -#define CFG_BLE_ATT_VALUE_ARRAY_SIZE (1344) +#define CFG_BLE_ATT_VALUE_ARRAY_SIZE (1344) + +/** + * Maximum numbers of bearers that can be created for Enhanced ATT per ACL links + */ +#define CFG_BLE_EATT_BEARER_PER_LINK (0) /** * depth of the PREPARE WRITE queue when PREPARE WRITE REQUEST @@ -167,7 +172,16 @@ #define CFG_LPM_LEVEL (1) #define CFG_LPM_STDBY_SUPPORTED (1) -/* Defines time to wake up from standby before radio event to meet timings */ +/** + * Defines to use dynamic low power wakeup time profilling. + * With this option at boot wake up time is profiled and then is used. + */ +#define CFG_LPM_WAKEUP_TIME_PROFILING (1) + +/** + * Defines time to wake up from standby before radio event to meet timings + * This value will be dynamically updated when using CFG_LPM_WAKEUP_TIME_PROFILING + */ #define CFG_LPM_STDBY_WAKEUP_TIME (1500) /* USER CODE BEGIN Low_Power 0 */ @@ -219,6 +233,9 @@ typedef enum */ #define CFG_LOG_SUPPORTED (0U) +extern UART_HandleTypeDef huart1; +#define LOG_UART_HANDLER huart1 + /* Configure Log display settings */ #define CFG_LOG_INSERT_COLOR_INSIDE_THE_TRACE (0U) #define CFG_LOG_INSERT_TIME_STAMP_INSIDE_THE_TRACE (0U) @@ -227,10 +244,6 @@ typedef enum #define CFG_LOG_TRACE_FIFO_SIZE (4096U) #define CFG_LOG_TRACE_BUF_SIZE (256U) -/* macro ensuring retrocompatibility with old applications */ -#define APP_DBG LOG_INFO_APP -#define APP_DBG_MSG LOG_INFO_APP - /* USER CODE BEGIN Logs */ /* USER CODE END Logs */ @@ -334,19 +347,12 @@ typedef enum #define CFG_SNVMA_START_ADDRESS (FLASH_BASE + (FLASH_PAGE_SIZE * (CFG_SNVMA_START_SECTOR_ID))) -/* USER CODE BEGIN NVM_Configuration */ - -/* USER CODE END NVM_Configuration */ - -/****************************************************************************** - * BLEPLAT configuration - ******************************************************************************/ /* Number of 64-bit words in NVM flash area */ -#define CFG_BLEPLAT_NVM_MAX_SIZE ((2048/8)-4) +#define CFG_BLE_NVM_SIZE_MAX ((2048/8)-4) -/* USER CODE BEGIN BLEPLAT_Configuration */ +/* USER CODE BEGIN NVM_Configuration */ -/* USER CODE END BLEPLAT_Configuration */ +/* USER CODE END NVM_Configuration */ /****************************************************************************** * Debugger @@ -368,8 +374,15 @@ typedef enum /****************************************************************************** * System Clock Manager module configuration + * + * When CFG_SCM_SUPPORTED is set to: + * - 0 : System Clock Manager is disabled and user must handle himself + * all clock management, taking care of radio requirements. + * (radio operation requires HSE 32MHz with Voltage Scaling Range 1) + * - 1 : System Clock Manager ensures proper clock settings and switchings + * according to radio requirements and user preferences + * ******************************************************************************/ - #define CFG_SCM_SUPPORTED (0) /****************************************************************************** @@ -398,7 +411,7 @@ typedef enum #define CFG_EXTERNAL_PA_ENABLE (0) -#define CFG_BLE_AOA_AOD_ENABLE (1) +#define CFG_BLE_AOA_AOD_ENABLE (0) #define CFG_RADIO_NUM_OF_ANTENNAS (8) /* Link Layer supported number of antennas */ /* Radio sleep clock LSE accuracy configuration */ @@ -412,9 +425,12 @@ typedef enum * HW_RNG configuration ******************************************************************************/ -/* Number of 32-bit random values stored in internal pool */ +/* Number of 32-bit random numbers stored in internal pool */ #define CFG_HW_RNG_POOL_SIZE (32) +/* Threshold of random numbers available before triggering pool refill */ +#define CFG_HW_RNG_POOL_THRESHOLD (16) + /* USER CODE BEGIN HW_RNG_Configuration */ /* USER CODE END HW_RNG_Configuration */ @@ -472,13 +488,6 @@ typedef enum #endif /* CFG_DEBUGGER_LEVEL */ #endif /* CFG_LPM_LEVEL */ -#if (CFG_LPM_STDBY_SUPPORTED != 0) && (CFG_LPM_LEVEL != 0) - #if CFG_LOG_SUPPORTED - #undef CFG_LOG_SUPPORTED - #define CFG_LOG_SUPPORTED (0) - #endif /* CFG_LOG_SUPPORTED */ -#endif /* (CFG_LPM_STDBY_SUPPORTED > 0) && (CFG_LPM_LEVEL != 0) */ - /* USER CODE BEGIN Defines_2 */ /* USER CODE END Defines_2 */ diff --git a/lib/stm32wba/ble/Core/Inc/main.h b/lib/stm32wba/ble/Core/Inc/main.h index ce6bbfa06..d45421b94 100644 --- a/lib/stm32wba/ble/Core/Inc/main.h +++ b/lib/stm32wba/ble/Core/Inc/main.h @@ -72,7 +72,6 @@ void MX_RAMCFG_Init(void); void MX_RTC_Init(void); void MX_USART1_UART_Init(void); void MX_ADC4_Init(void); -void MX_RNG_Init(void); void MX_CRC_Init(void); void MX_ICACHE_Init(void); diff --git a/lib/stm32wba/ble/Core/Inc/utilities_conf.h b/lib/stm32wba/ble/Core/Inc/utilities_conf.h index 8365e3bdb..05d320779 100644 --- a/lib/stm32wba/ble/Core/Inc/utilities_conf.h +++ b/lib/stm32wba/ble/Core/Inc/utilities_conf.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -154,6 +154,14 @@ extern "C" { #define UTIL_ADV_TRACE_MEMSET8( dest, value, size) UTIL_MEM_set_8((dest),(value),(size)) /*!< memset utilities interface to trace feature */ #define UTIL_ADV_TRACE_VSNPRINTF(...) vsnprintf(__VA_ARGS__) /*!< vsnprintf utilities interface to trace feature */ +/****************************************************************************** + * tiny low power manager + ******************************************************************************/ +/* Maximum number of supported LPM drivers */ +#define UTIL_LPM_DRIVER_MAX_NUM (10) +/* Enables LPM legacy APIs */ +#define UTIL_LPM_LEGACY_ENABLED (1) + /* USER CODE BEGIN EM */ /* USER CODE END EM */ diff --git a/lib/stm32wba/ble/STM32_WPAN/Target/linklayer_plat.c b/lib/stm32wba/ble/STM32_WPAN/Target/linklayer_plat.c index 2a6feee0f..c926bbbde 100644 --- a/lib/stm32wba/ble/STM32_WPAN/Target/linklayer_plat.c +++ b/lib/stm32wba/ble/STM32_WPAN/Target/linklayer_plat.c @@ -18,7 +18,6 @@ */ /* USER CODE END Header */ - #include "stm32wbaxx_hal.h" #include "stm32wbaxx_hal_conf.h" #include "stm32wbaxx_ll_rcc.h" @@ -38,6 +37,9 @@ #endif /* (CFG_LPM_LEVEL != 0) */ #endif +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ #ifndef __ZEPHYR__ #define max(a,b) ((a) > (b) ? a : b) @@ -503,37 +505,40 @@ void LINKLAYER_PLAT_RequestTemperature(void) ll_sys_bg_temperature_measurement(); #endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ } -#ifndef __ZEPHYR__ + /** - * @brief Enable RTOS context switch. + * @brief PHY Start calibration. * @param None * @retval None */ -void LINKLAYER_PLAT_EnableOSContextSwitch(void) +void LINKLAYER_PLAT_PhyStartClbr(void) { - /* USER CODE BEGIN LINKLAYER_PLAT_EnableOSContextSwitch_0 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_0 */ - /* USER CODE END LINKLAYER_PLAT_EnableOSContextSwitch_0 */ - /* USER CODE BEGIN LINKLAYER_PLAT_EnableOSContextSwitch_1 */ + /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_0 */ - /* USER CODE END LINKLAYER_PLAT_EnableOSContextSwitch_1 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStartClbr_1 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStartClbr_1 */ } /** - * @brief Disable RTOS context switch. + * @brief PHY Stop calibration. * @param None * @retval None */ -void LINKLAYER_PLAT_DisableOSContextSwitch(void) +void LINKLAYER_PLAT_PhyStopClbr(void) { - /* USER CODE BEGIN LINKLAYER_PLAT_DisableOSContextSwitch_0 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_0 */ + + /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_0 */ - /* USER CODE END LINKLAYER_PLAT_DisableOSContextSwitch_0 */ - /* USER CODE BEGIN LINKLAYER_PLAT_DisableOSContextSwitch_1 */ + /* USER CODE BEGIN LINKLAYER_PLAT_PhyStopClbr_1 */ - /* USER CODE END LINKLAYER_PLAT_DisableOSContextSwitch_1 */ + /* USER CODE END LINKLAYER_PLAT_PhyStopClbr_1 */ } +#ifndef __ZEPHYR__ /** * @brief Notify the upper layer that new Link Layer timings have been applied. * @param evnt_timing[in]: Evnt_timing_t pointer to structure contains drift time , execution time and scheduling time diff --git a/lib/stm32wba/ble/STM32_WPAN/Target/ll_sys_if.c b/lib/stm32wba/ble/STM32_WPAN/Target/ll_sys_if.c index 8b272878c..fbfc97c1a 100644 --- a/lib/stm32wba/ble/STM32_WPAN/Target/ll_sys_if.c +++ b/lib/stm32wba/ble/STM32_WPAN/Target/ll_sys_if.c @@ -59,6 +59,9 @@ /* USER CODE END GV */ /* Private functions prototypes-----------------------------------------------*/ +#if (USE_TEMPERATURE_BASED_RADIO_CALIBRATION == 1) +void ll_sys_bg_temperature_measurement_init(void); +#endif /* USE_TEMPERATURE_BASED_RADIO_CALIBRATION */ static void ll_sys_sleep_clock_source_selection(void); static uint8_t ll_sys_BLE_sleep_clock_accuracy_selection(void); void ll_sys_reset(void); diff --git a/lib/stm32wba/ble/System/Config/Debug_GPIO/debug_config.h b/lib/stm32wba/ble/System/Config/Debug_GPIO/debug_config.h index e8a83448c..ab9959336 100644 --- a/lib/stm32wba/ble/System/Config/Debug_GPIO/debug_config.h +++ b/lib/stm32wba/ble/System/Config/Debug_GPIO/debug_config.h @@ -49,570 +49,573 @@ extern "C" { /* System clock manager - System clock config */ #define USE_RT_DEBUG_SCM_SYSTEM_CLOCK_CONFIG (0) -#define GPIO_DEBUG_SCM_SYSTEM_CLOCK_CONFIG {GPIOA, GPIO_PIN_12} +#define GPIO_DEBUG_SCM_SYSTEM_CLOCK_CONFIG {GPIOA, LL_PWR_GPIO_PIN_12} /* System clock manager - Setup */ #define USE_RT_DEBUG_SCM_SETUP (0) -#define GPIO_DEBUG_SCM_SETUP {GPIOA, GPIO_PIN_5} +#define GPIO_DEBUG_SCM_SETUP {GPIOA, LL_PWR_GPIO_PIN_5} /* System clock manager - HSE RDY interrupt handling */ #define USE_RT_DEBUG_SCM_HSERDY_ISR (0) -#define GPIO_DEBUG_SCM_HSERDY_ISR {GPIOA, GPIO_PIN_15} +#define GPIO_DEBUG_SCM_HSERDY_ISR {GPIOA, LL_PWR_GPIO_PIN_15} #define USE_RT_DEBUG_ADC_ACTIVATION (0) -#define GPIO_DEBUG_ADC_ACTIVATION {GPIOB, GPIO_PIN_4} +#define GPIO_DEBUG_ADC_ACTIVATION {GPIOB, LL_PWR_GPIO_PIN_4} #define USE_RT_DEBUG_ADC_DEACTIVATION (0) -#define GPIO_DEBUG_ADC_DEACTIVATION {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADC_DEACTIVATION {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADC_TEMPERATURE_ACQUISITION (0) -#define GPIO_DEBUG_ADC_TEMPERATURE_ACQUISITION {GPIOB, GPIO_PIN_8} +#define GPIO_DEBUG_ADC_TEMPERATURE_ACQUISITION {GPIOB, LL_PWR_GPIO_PIN_8} #define USE_RT_DEBUG_RNG_ENABLE (0) -#define GPIO_DEBUG_RNG_ENABLE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RNG_ENABLE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RNG_DISABLE (0) -#define GPIO_DEBUG_RNG_DISABLE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RNG_DISABLE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RNG_GEN_RAND_NUM (0) -#define GPIO_DEBUG_RNG_GEN_RAND_NUM {GPIOB, GPIO_PIN_12} +#define GPIO_DEBUG_RNG_GEN_RAND_NUM {GPIOB, LL_PWR_GPIO_PIN_12} #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ENTER (0) -#define GPIO_DEBUG_LOW_POWER_STOP_MODE_ENTER {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STOP_MODE_ENTER {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_EXIT (0) -#define GPIO_DEBUG_LOW_POWER_STOP_MODE_EXIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STOP_MODE_EXIT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STOP_MODE_ACTIVE (0) -#define GPIO_DEBUG_LOW_POWER_STOP_MODE_ACTIVE {GPIOB, GPIO_PIN_3} +#define GPIO_DEBUG_LOW_POWER_STOP_MODE_ACTIVE {GPIOB, LL_PWR_GPIO_PIN_3} #define USE_RT_DEBUG_LOW_POWER_STOP2_MODE_ENTER (0) -#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_ENTER {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_ENTER {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STOP2_MODE_EXIT (0) -#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_EXIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_EXIT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STOP2_MODE_ACTIVE (0) -#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_ACTIVE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STOP2_MODE_ACTIVE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ENTER (0) -#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ENTER {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ENTER {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_EXIT (0) -#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_EXIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_EXIT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE (0) -#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE {GPIOB, GPIO_PIN_15} +#define GPIO_DEBUG_LOW_POWER_STANDBY_MODE_ACTIVE {GPIOB, LL_PWR_GPIO_PIN_15} #define USE_RT_DEBUG_HCI_READ_DONE (0) -#define GPIO_DEBUG_HCI_READ_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_HCI_READ_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_HCI_RCVD_CMD (0) -#define GPIO_DEBUG_HCI_RCVD_CMD {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_HCI_RCVD_CMD {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_HCI_WRITE_DONE (0) -#define GPIO_DEBUG_HCI_WRITE_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_HCI_WRITE_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_EVNT_UPDATE (0) -#define GPIO_DEBUG_SCHDLR_EVNT_UPDATE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_EVNT_UPDATE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_TIMER_SET (0) -#define GPIO_DEBUG_SCHDLR_TIMER_SET {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_TIMER_SET {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_PHY_CLBR_TIMER (0) -#define GPIO_DEBUG_SCHDLR_PHY_CLBR_TIMER {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_PHY_CLBR_TIMER {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_EVNT_SKIPPED (0) -#define GPIO_DEBUG_SCHDLR_EVNT_SKIPPED {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_EVNT_SKIPPED {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_HNDL_NXT_TRACE (0) -#define GPIO_DEBUG_SCHDLR_HNDL_NXT_TRACE {GPIOA, GPIO_PIN_12} +#define GPIO_DEBUG_SCHDLR_HNDL_NXT_TRACE {GPIOA, LL_PWR_GPIO_PIN_12} #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED (0) -#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_DETEDTED {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK (0) -#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_GAP_CHECK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK (0) -#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TIME_CHECK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE (0) -#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ACTIVE_SCHDLR_NEAR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_EVNT_RGSTR (0) -#define GPIO_DEBUG_SCHDLR_EVNT_RGSTR {GPIOB, GPIO_PIN_8} +#define GPIO_DEBUG_SCHDLR_EVNT_RGSTR {GPIOB, LL_PWR_GPIO_PIN_8} #define USE_RT_DEBUG_SCHDLR_ADD_CONFLICT_Q (0) -#define GPIO_DEBUG_SCHDLR_ADD_CONFLICT_Q {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_ADD_CONFLICT_Q {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_HNDL_MISSED_EVNT (0) -#define GPIO_DEBUG_SCHDLR_HNDL_MISSED_EVNT {GPIOA, GPIO_PIN_5} +#define GPIO_DEBUG_SCHDLR_HNDL_MISSED_EVNT {GPIOA, LL_PWR_GPIO_PIN_5} #define USE_RT_DEBUG_SCHDLR_UNRGSTR_EVNT (0) -#define GPIO_DEBUG_SCHDLR_UNRGSTR_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_UNRGSTR_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_TRACE (0) -#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_TRACE {GPIOA, GPIO_PIN_15} +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_TRACE {GPIOA, LL_PWR_GPIO_PIN_15} #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_PROFILE (0) -#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_PROFILE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_PROFILE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_ERROR (0) -#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_ERROR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_ERROR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING (0) -#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_SCHDLR_EXEC_EVNT_WINDOW_WIDENING {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_CMN_CLR_ISR (0) -#define GPIO_DEBUG_LLHWC_CMN_CLR_ISR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_CMN_CLR_ISR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLWCC_CMN_HG_ISR (0) -#define GPIO_DEBUG_LLWCC_CMN_HG_ISR {GPIOA, GPIO_PIN_15} +#define GPIO_DEBUG_LLWCC_CMN_HG_ISR {GPIOA, LL_PWR_GPIO_PIN_15} #define USE_RT_DEBUG_LLHWC_CMN_LW_ISR (0) -#define GPIO_DEBUG_LLHWC_CMN_LW_ISR {GPIOA, GPIO_PIN_12} +#define GPIO_DEBUG_LLHWC_CMN_LW_ISR {GPIOA, LL_PWR_GPIO_PIN_12} #define USE_RT_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR (0) -#define GPIO_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_CMN_CLR_TIMER_ERROR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_LL_ISR (0) -#define GPIO_DEBUG_LLHWC_LL_ISR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_LL_ISR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_SPLTMR_SET (0) -#define GPIO_DEBUG_LLHWC_SPLTMR_SET {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_SPLTMR_SET {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_SPLTMR_GET (0) -#define GPIO_DEBUG_LLHWC_SPLTMR_GET {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_SPLTMR_GET {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_LOW_ISR (0) -#define GPIO_DEBUG_LLHWC_LOW_ISR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_LOW_ISR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_STOP_SCN (0) -#define GPIO_DEBUG_LLHWC_STOP_SCN {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_STOP_SCN {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_WAIT_ENVT_ON_AIR (0) -#define GPIO_DEBUG_LLHWC_WAIT_ENVT_ON_AIR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_WAIT_ENVT_ON_AIR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_SET_CONN_EVNT_PARAM (0) -#define GPIO_DEBUG_LLHWC_SET_CONN_EVNT_PARAM {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_SET_CONN_EVNT_PARAM {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_POST_EVNT (0) -#define GPIO_DEBUG_POST_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_POST_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_HNDL_ALL_EVNTS (0) -#define GPIO_DEBUG_HNDL_ALL_EVNTS {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_HNDL_ALL_EVNTS {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PROCESS_EVNT (0) -#define GPIO_DEBUG_PROCESS_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PROCESS_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PROCESS_ISO_DATA (0) -#define GPIO_DEBUG_PROCESS_ISO_DATA {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PROCESS_ISO_DATA {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ALLOC_TX_ISO_EMPTY_PKT (0) -#define GPIO_DEBUG_ALLOC_TX_ISO_EMPTY_PKT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ALLOC_TX_ISO_EMPTY_PKT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIG_FREE_EMPTY_PKTS (0) -#define GPIO_DEBUG_BIG_FREE_EMPTY_PKTS {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIG_FREE_EMPTY_PKTS {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_OK (0) -#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_OK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_OK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_CRC (0) -#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_CRC {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_CRC {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX (0) -#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_NoRX {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE (0) -#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RECOMBINE_UNFRMD_DATA_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISO_HNDL_SDU (0) -#define GPIO_DEBUG_ISO_HNDL_SDU {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISO_HNDL_SDU {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LL_INTF_INIT (0) -#define GPIO_DEBUG_LL_INTF_INIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LL_INTF_INIT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_DATA_TO_CNTRLR (0) -#define GPIO_DEBUG_DATA_TO_CNTRLR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_DATA_TO_CNTRLR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_FREE_LL_PKT_HNDLR (0) -#define GPIO_DEBUG_FREE_LL_PKT_HNDLR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_FREE_LL_PKT_HNDLR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PHY_INIT_CLBR_TRACE (0) -#define GPIO_DEBUG_PHY_INIT_CLBR_TRACE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PHY_INIT_CLBR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PHY_RUNTIME_CLBR_TRACE (0) -#define GPIO_DEBUG_PHY_RUNTIME_CLBR_TRACE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PHY_RUNTIME_CLBR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PHY_CLBR_ISR (0) -#define GPIO_DEBUG_PHY_CLBR_ISR {GPIOB, GPIO_PIN_3} +#define GPIO_DEBUG_PHY_CLBR_ISR {GPIOB, LL_PWR_GPIO_PIN_3} #define USE_RT_DEBUG_PHY_INIT_CLBR_SINGLE_CH (0) -#define GPIO_DEBUG_PHY_INIT_CLBR_SINGLE_CH {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PHY_INIT_CLBR_SINGLE_CH {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PHY_CLBR_STRTD (0) -#define GPIO_DEBUG_PHY_CLBR_STRTD {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PHY_CLBR_STRTD {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PHY_CLBR_EXEC (0) -#define GPIO_DEBUG_PHY_CLBR_EXEC {GPIOB, GPIO_PIN_4} +#define GPIO_DEBUG_PHY_CLBR_EXEC {GPIOB, LL_PWR_GPIO_PIN_4} #define USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV (0) -#define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_CLBR_ACTV {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR (0) -#define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RCO_STRT_STOP_RUNTIME_RCO_CLBR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT (0) -#define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_SWT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE (0) -#define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_STRT_STOP_RUNTIME_RCO_CLBR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RCO_ISR_TRACE (0) -#define GPIO_DEBUG_RCO_ISR_TRACE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RCO_ISR_TRACE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RCO_ISR_COMPENDATE (0) -#define GPIO_DEBUG_RCO_ISR_COMPENDATE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RCO_ISR_COMPENDATE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_STRT_TX (0) -#define GPIO_DEBUG_RAL_STRT_TX {GPIOA, GPIO_PIN_5} +#define GPIO_DEBUG_RAL_STRT_TX {GPIOA, LL_PWR_GPIO_PIN_5} #define USE_RT_DEBUG_RAL_ISR_TIMER_ERROR (0) -#define GPIO_DEBUG_RAL_ISR_TIMER_ERROR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_ISR_TIMER_ERROR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_ISR_TRACE (0) -#define GPIO_DEBUG_RAL_ISR_TRACE {GPIOB, GPIO_PIN_3} +#define GPIO_DEBUG_RAL_ISR_TRACE {GPIOB, LL_PWR_GPIO_PIN_3} #define USE_RT_DEBUG_RAL_STOP_OPRTN (0) -#define GPIO_DEBUG_RAL_STOP_OPRTN {GPIOB, GPIO_PIN_8} +#define GPIO_DEBUG_RAL_STOP_OPRTN {GPIOB, LL_PWR_GPIO_PIN_8} #define USE_RT_DEBUG_RAL_STRT_RX (0) -#define GPIO_DEBUG_RAL_STRT_RX {GPIOB, GPIO_PIN_12} +#define GPIO_DEBUG_RAL_STRT_RX {GPIOB, LL_PWR_GPIO_PIN_12} #define USE_RT_DEBUG_RAL_DONE_CLBK_TX (0) -#define GPIO_DEBUG_RAL_DONE_CLBK_TX {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_DONE_CLBK_TX {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_DONE_CLBK_RX (0) -#define GPIO_DEBUG_RAL_DONE_CLBK_RX {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_DONE_CLBK_RX {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_DONE_CLBK_ED (0) -#define GPIO_DEBUG_RAL_DONE_CLBK_ED {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_DONE_CLBK_ED {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_ED_SCAN (0) -#define GPIO_DEBUG_RAL_ED_SCAN {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_ED_SCAN {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ERROR_MEM_CAP_EXCED (0) -#define GPIO_DEBUG_ERROR_MEM_CAP_EXCED {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ERROR_MEM_CAP_EXCED {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ERROR_COMMAND_DISALLOWED (0) -#define GPIO_DEBUG_ERROR_COMMAND_DISALLOWED {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ERROR_COMMAND_DISALLOWED {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PTA_INIT (0) -#define GPIO_DEBUG_PTA_INIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PTA_INIT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PTA_EN (0) -#define GPIO_DEBUG_PTA_EN {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PTA_EN {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_PTA_SET_EN (0) -#define GPIO_DEBUG_LLHWC_PTA_SET_EN {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_PTA_SET_EN {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_PTA_SET_PARAMS (0) -#define GPIO_DEBUG_LLHWC_PTA_SET_PARAMS {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_PTA_SET_PARAMS {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_COEX_STRT_ON_IDLE (0) -#define GPIO_DEBUG_COEX_STRT_ON_IDLE {GPIOB, GPIO_PIN_15} +#define GPIO_DEBUG_COEX_STRT_ON_IDLE {GPIOB, LL_PWR_GPIO_PIN_15} #define USE_RT_DEBUG_COEX_ASK_FOR_AIR (0) -#define GPIO_DEBUG_COEX_ASK_FOR_AIR {GPIOB, GPIO_PIN_3} +#define GPIO_DEBUG_COEX_ASK_FOR_AIR {GPIOB, LL_PWR_GPIO_PIN_3} #define USE_RT_DEBUG_COEX_TIMER_EVNT_CLBK (0) -#define GPIO_DEBUG_COEX_TIMER_EVNT_CLBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_COEX_TIMER_EVNT_CLBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_COEX_STRT_ONE_SHOT (0) -#define GPIO_DEBUG_COEX_STRT_ONE_SHOT {GPIOA, GPIO_PIN_5} +#define GPIO_DEBUG_COEX_STRT_ONE_SHOT {GPIOA, LL_PWR_GPIO_PIN_5} #define USE_RT_DEBUG_COEX_FORCE_STOP_RX (0) -#define GPIO_DEBUG_COEX_FORCE_STOP_RX {GPIOB, GPIO_PIN_12} +#define GPIO_DEBUG_COEX_FORCE_STOP_RX {GPIOB, LL_PWR_GPIO_PIN_12} #define USE_RT_DEBUG_LLHWC_ADV_DONE (0) -#define GPIO_DEBUG_LLHWC_ADV_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_ADV_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_SCN_DONE (0) -#define GPIO_DEBUG_LLHWC_SCN_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_SCN_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_INIT_DONE (0) -#define GPIO_DEBUG_LLHWC_INIT_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_INIT_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_CONN_DONE (0) -#define GPIO_DEBUG_LLHWC_CONN_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_CONN_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_CIG_DONE (0) -#define GPIO_DEBUG_LLHWC_CIG_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_CIG_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_BIG_DONE (0) -#define GPIO_DEBUG_LLHWC_BIG_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_BIG_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_OS_TMR_CREATE (0) -#define GPIO_DEBUG_OS_TMR_CREATE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_OS_TMR_CREATE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_TIMEOUT_CBK (0) -#define GPIO_DEBUG_ADV_EXT_TIMEOUT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_TIMEOUT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_SCN_DUR_CBK (0) -#define GPIO_DEBUG_ADV_EXT_SCN_DUR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_SCN_DUR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_SCN_PERIOD_CBK (0) -#define GPIO_DEBUG_ADV_EXT_SCN_PERIOD_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_SCN_PERIOD_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK (0) -#define GPIO_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_PRDC_SCN_TIMEOUT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK (0) -#define GPIO_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIS_SYNC_TIMEOUT_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIS_TERM_TMR_CBK (0) -#define GPIO_DEBUG_BIS_TERM_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIS_TERM_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIS_TST_MODE_CBK (0) -#define GPIO_DEBUG_BIS_TST_MODE_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIS_TST_MODE_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIS_TST_MODE_TMR_CBK (0) -#define GPIO_DEBUG_BIS_TST_MODE_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIS_TST_MODE_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISO_POST_TMR_CBK (0) -#define GPIO_DEBUG_ISO_POST_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISO_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISO_TST_MODE_TMR_CBK (0) -#define GPIO_DEBUG_ISO_TST_MODE_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISO_TST_MODE_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_CONN_POST_TMR_CBK (0) -#define GPIO_DEBUG_CONN_POST_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_CONN_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_EVNT_SCHDLR_TMR_CBK (0) -#define GPIO_DEBUG_EVNT_SCHDLR_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_EVNT_SCHDLR_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_HCI_POST_TMR_CBK (0) -#define GPIO_DEBUG_HCI_POST_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_HCI_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLCP_POST_TMR_CBK (0) -#define GPIO_DEBUG_LLCP_POST_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLCP_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_ENRGY_DETECT_CBK (0) -#define GPIO_DEBUG_LLHWC_ENRGY_DETECT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_ENRGY_DETECT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PRVCY_POST_TMR_CBK (0) -#define GPIO_DEBUG_PRVCY_POST_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PRVCY_POST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ANT_PRPR_TMR_CBK (0) -#define GPIO_DEBUG_ANT_PRPR_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ANT_PRPR_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK (0) -#define GPIO_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_COEX_TMR_FRC_STOP_AIR_GRANT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MLME_RX_EN_TMR_CBK (0) -#define GPIO_DEBUG_MLME_RX_EN_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MLME_RX_EN_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MLME_GNRC_TMR_CBK (0) -#define GPIO_DEBUG_MLME_GNRC_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MLME_GNRC_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MIB_JOIN_LST_TMR_CBK (0) -#define GPIO_DEBUG_MIB_JOIN_LST_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MIB_JOIN_LST_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MLME_PWR_PRES_TMR_CBK (0) -#define GPIO_DEBUG_MLME_PWR_PRES_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MLME_PWR_PRES_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PRESISTENCE_TMR_CBK (0) -#define GPIO_DEBUG_PRESISTENCE_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PRESISTENCE_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK (0) -#define GPIO_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RADIO_PHY_PRDC_CLBK_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RADIO_CSMA_TMR_CBK (0) -#define GPIO_DEBUG_RADIO_CSMA_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RADIO_CSMA_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RADIO_CSL_RCV_TMR_CBK (0) -#define GPIO_DEBUG_RADIO_CSL_RCV_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RADIO_CSL_RCV_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ED_TMR_CBK (0) -#define GPIO_DEBUG_ED_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ED_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_DIO_EXT_TMR_CBK (0) -#define GPIO_DEBUG_DIO_EXT_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_DIO_EXT_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RCO_CLBR_TMR_CBK (0) -#define GPIO_DEBUG_RCO_CLBR_TMR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RCO_CLBR_TMR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_ADV_CBK (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_ADV_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_ADV_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_CBK (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIG_ADV_CBK (0) -#define GPIO_DEBUG_BIG_ADV_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIG_ADV_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIG_ADV_ERR_CBK (0) -#define GPIO_DEBUG_BIG_ADV_ERR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIG_ADV_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIG_SYNC_CBK (0) -#define GPIO_DEBUG_BIG_SYNC_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIG_SYNC_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIG_SYNC_ERR_CBK (0) -#define GPIO_DEBUG_BIG_SYNC_ERR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIG_SYNC_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK (0) -#define GPIO_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISO_CIS_PKT_TRNSM_RECEIVED_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISO_CIG_ERR_CBK (0) -#define GPIO_DEBUG_ISO_CIG_ERR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISO_CIG_ERR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK (0) -#define GPIO_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_CONN_PKT_TRNSM_RECEIVED_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PRDC_CLBR_EXTRL_CBK (0) -#define GPIO_DEBUG_PRDC_CLBR_EXTRL_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PRDC_CLBR_EXTRL_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PTR_PRDC_ADV_SYNC_CBK (0) -#define GPIO_DEBUG_PTR_PRDC_ADV_SYNC_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PTR_PRDC_ADV_SYNC_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_NCONN_SCN_CBK (0) -#define GPIO_DEBUG_NCONN_SCN_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_NCONN_SCN_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_NCONN_ADV_CBK (0) -#define GPIO_DEBUG_NCONN_ADV_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_NCONN_ADV_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_NCONN_INIT_CBK (0) -#define GPIO_DEBUG_NCONN_INIT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_NCONN_INIT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK (0) -#define GPIO_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ANT_RADIO_CMPLT_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ANT_STACK_EVNT_CBK (0) -#define GPIO_DEBUG_ANT_STACK_EVNT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ANT_STACK_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK (0) -#define GPIO_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_PROCESS_TMOUT_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_DUR_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_SCN_PERIODIC_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_TMOUT_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT (0) -#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ADV_EXT_MNGR_PRDC_SCN_CNCEL_EVNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIS_MNGR_BIG_TERM_CBK (0) -#define GPIO_DEBUG_BIS_MNGR_BIG_TERM_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIS_MNGR_BIG_TERM_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK (0) -#define GPIO_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_BIS_MNGR_SYNC_TMOUT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISOAL_MNGR_SDU_GEN (0) -#define GPIO_DEBUG_ISOAL_MNGR_SDU_GEN {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISOAL_MNGR_SDU_GEN {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK (0) -#define GPIO_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ISO_MNGR_CIS_PROCESS_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK (0) -#define GPIO_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_CONN_MNGR_PROCESS_EVNT_CLBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK (0) -#define GPIO_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_CONN_MNGR_UPDT_CONN_PARAM_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT (0) -#define GPIO_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_EVNT_SCHDLR_HW_EVNT_CMPLT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_HCI_EVENT_HNDLR (0) -#define GPIO_DEBUG_HCI_EVENT_HNDLR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_HCI_EVENT_HNDLR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MLME_TMRS_CBK (0) -#define GPIO_DEBUG_MLME_TMRS_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MLME_TMRS_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_DIRECT_TX_EVNT_CBK (0) -#define GPIO_DEBUG_DIRECT_TX_EVNT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_DIRECT_TX_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_INDIRECT_PKT_TOUR_CBK (0) -#define GPIO_DEBUG_INDIRECT_PKT_TOUR_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_INDIRECT_PKT_TOUR_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RADIO_CSMA_TMR (0) -#define GPIO_DEBUG_RADIO_CSMA_TMR {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RADIO_CSMA_TMR {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_SM_DONE_EVNT_CBK (0) -#define GPIO_DEBUG_RAL_SM_DONE_EVNT_CBK {GPIOB, GPIO_PIN_4} +#define GPIO_DEBUG_RAL_SM_DONE_EVNT_CBK {GPIOB, LL_PWR_GPIO_PIN_4} #define USE_RT_DEBUG_ED_TMR_HNDL (0) -#define GPIO_DEBUG_ED_TMR_HNDL {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_ED_TMR_HNDL {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_OS_TMR_EVNT_CBK (0) -#define GPIO_DEBUG_OS_TMR_EVNT_CBK {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_OS_TMR_EVNT_CBK {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME (0) -#define GPIO_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PROFILE_MARKER_PHY_WAKEUP_TIME {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PROFILE_END_DRIFT_TIME (0) -#define GPIO_DEBUG_PROFILE_END_DRIFT_TIME {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PROFILE_END_DRIFT_TIME {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PROC_RADIO_RCV (0) -#define GPIO_DEBUG_PROC_RADIO_RCV {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PROC_RADIO_RCV {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_EVNT_TIME_UPDT (0) -#define GPIO_DEBUG_EVNT_TIME_UPDT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_EVNT_TIME_UPDT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MAC_RECEIVE_DONE (0) -#define GPIO_DEBUG_MAC_RECEIVE_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MAC_RECEIVE_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_MAC_TX_DONE (0) -#define GPIO_DEBUG_MAC_TX_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_MAC_TX_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RADIO_APPLY_CSMA (0) -#define GPIO_DEBUG_RADIO_APPLY_CSMA {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RADIO_APPLY_CSMA {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RADIO_TRANSMIT (0) -#define GPIO_DEBUG_RADIO_TRANSMIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RADIO_TRANSMIT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_PROC_RADIO_TX (0) -#define GPIO_DEBUG_PROC_RADIO_TX {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_PROC_RADIO_TX {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_TX_DONE (0) -#define GPIO_DEBUG_RAL_TX_DONE {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_TX_DONE {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT (0) -#define GPIO_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_TX_DONE_INCREMENT_BACKOFF_COUNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT (0) -#define GPIO_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_TX_DONE_RST_BACKOFF_COUNT {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_CONTINUE_RX (0) -#define GPIO_DEBUG_RAL_CONTINUE_RX {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_CONTINUE_RX {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_PERFORM_CCA (0) -#define GPIO_DEBUG_RAL_PERFORM_CCA {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_PERFORM_CCA {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_RAL_ENABLE_TRANSMITTER (0) -#define GPIO_DEBUG_RAL_ENABLE_TRANSMITTER {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_RAL_ENABLE_TRANSMITTER {GPIOA, LL_PWR_GPIO_PIN_0} #define USE_RT_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 (0) -#define GPIO_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_LLHWC_GET_CH_IDX_ALGO_2 {GPIOA, LL_PWR_GPIO_PIN_0} + +#define USE_RT_DEBUG_BACK_FROM_DEEP_SLEEP (0) +#define GPIO_DEBUG_BACK_FROM_DEEP_SLEEP {GPIOA, LL_PWR_GPIO_PIN_0} /* Application signal selection and GPIO assignment. CAN BE MODIFIED BY USER */ #define USE_RT_DEBUG_APP_APPE_INIT (0) -#define GPIO_DEBUG_APP_APPE_INIT {GPIOA, GPIO_PIN_0} +#define GPIO_DEBUG_APP_APPE_INIT {GPIOA, LL_PWR_GPIO_PIN_0} /********************************/ /** Debug configuration setup **/ diff --git a/lib/stm32wba/ble/System/Config/Log/log_module_conf.h b/lib/stm32wba/ble/System/Config/Log/log_module_conf.h index 67134f788..a09f19ba9 100644 --- a/lib/stm32wba/ble/System/Config/Log/log_module_conf.h +++ b/lib/stm32wba/ble/System/Config/Log/log_module_conf.h @@ -177,6 +177,10 @@ typedef enum #define LOG_DEBUG_BLE(...) do {} while(0) #endif /* (CFG_LOG_SUPPORTED != 0) */ +/* macro ensuring retrocompatibility with old applications */ +#define APP_DBG LOG_INFO_APP +#define APP_DBG_MSG LOG_INFO_APP + /* USER CODE BEGIN LOG_REGION_BLE */ /** * Add inside this user section your defines to match the new verbose levels you diff --git a/scripts/ble_library.py b/scripts/ble_library.py index cfd259fca..6dc8f8b76 100644 --- a/scripts/ble_library.py +++ b/scripts/ble_library.py @@ -41,7 +41,7 @@ ble_transparent_mode_app_path = "Projects/NUCLEO-WBA65RI/Applications/BLE/" \ + "BLE_TransparentMode" -zgbee_onoff_client_sed_app_path = "Projects/NUCLEO-WBA65RI/Applications/BLE/" \ +zigbee_onoff_client_sed_app_path = "Projects/NUCLEO-WBA65RI/Applications/Zigbee/" \ + "Zigbee_OnOff_Client_SED" file_list_wba = { "STM32_WPAN": [ @@ -66,6 +66,12 @@ "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/inc/rfd_dev_config.h", "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_full/" + "ll_fw_config.h", + "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ble_basic/" + + "ll_fw_config.h", + "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/ieee_15_4_basic/" + + "ll_fw_config.h", + "Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/config/thread/" + + "ll_fw_config.h", "Middlewares/ST/STM32_WPAN/ble/stack/include/ble_bufsize.h", "Middlewares/ST/STM32_WPAN/ble/stack/include/ble_const.h", "Middlewares/ST/STM32_WPAN/ble/stack/include/ble_defs.h", @@ -97,17 +103,17 @@ ble_transparent_mode_app_path + "/STM32_WPAN/Target/ll_sys_if.h", ], "IEEE802154": [ - zgbee_onoff_client_sed_app_path + "/Core/Inc/app_common.h", - zgbee_onoff_client_sed_app_path + "/Core/Inc/app_conf.h", - zgbee_onoff_client_sed_app_path + "/Core/Inc/app_entry.h", - zgbee_onoff_client_sed_app_path + "/Core/Inc/utilities_conf.h", - zgbee_onoff_client_sed_app_path + "/Core/Inc/main.h", - zgbee_onoff_client_sed_app_path + "/System/Config/Debug_GPIO/debug_config.h", - zgbee_onoff_client_sed_app_path + "/System/Config/Log/log_module_conf.h", - zgbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/power_table.c", - zgbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/linklayer_plat.c", - zgbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/ll_sys_if.c", - zgbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/ll_sys_if.h", + zigbee_onoff_client_sed_app_path + "/Core/Inc/app_common.h", + zigbee_onoff_client_sed_app_path + "/Core/Inc/app_conf.h", + zigbee_onoff_client_sed_app_path + "/Core/Inc/app_entry.h", + zigbee_onoff_client_sed_app_path + "/Core/Inc/utilities_conf.h", + zigbee_onoff_client_sed_app_path + "/Core/Inc/main.h", + zigbee_onoff_client_sed_app_path + "/System/Config/Debug_GPIO/debug_config.h", + zigbee_onoff_client_sed_app_path + "/System/Config/Log/log_module_conf.h", + zigbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/power_table.c", + zigbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/linklayer_plat.c", + zigbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/ll_sys_if.c", + zigbee_onoff_client_sed_app_path + "/STM32_WPAN/Target/ll_sys_if.h", ], "Common": [ "Projects/Common/WPAN/Modules/Flash/rf_timing_synchro.c", diff --git a/stm32cube/common_ll/README.rst b/stm32cube/common_ll/README.rst index 606d96e3d..2622c1e77 100644 --- a/stm32cube/common_ll/README.rst +++ b/stm32cube/common_ll/README.rst @@ -34,7 +34,7 @@ stm32u0xx 1.3.0 stm32u3xx 1.2.0 stm32u5xx 1.8.0 stm32wb0x 1.0.0 -stm32wbaxx 1.6.0 +stm32wbaxx 1.7.0 stm32wbxx 1.23.0 stm32wlxx 1.3.1 -=============== =============== +=============== =============== \ No newline at end of file diff --git a/stm32cube/stm32wbaxx/README b/stm32cube/stm32wbaxx/README index b3c2fe9f7..ea64eb5c0 100644 --- a/stm32cube/stm32wbaxx/README +++ b/stm32cube/stm32wbaxx/README @@ -6,7 +6,7 @@ Origin: http://www.st.com/en/embedded-software/stm32cubewba.html Status: - version v1.6.0 + version v1.7.0 Purpose: ST Microelectronics official MCU package for STM32WBA series. @@ -23,7 +23,7 @@ URL: https://github.com/STMicroelectronics/STM32CubeWBA Commit: - e7d27c496416aae8f4ba8b3e84f963f0c5a0b69f + f5b281ba4ca4d00aba59215728265f1d2cc80715 Maintained-by: External @@ -48,4 +48,8 @@ Patch List: Impacted files: drivers/include/Legacy/stm32_hal_legacy.h + *Fix to remove XSPI HAL support as not present in WBAXX + Impacted files: + drivers/include/stm32wbaxx_hal_conf.h + See release_note.html from STM32Cube diff --git a/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h b/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h index d7aad3204..8eed03404 100644 --- a/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/stm32cube/stm32wbaxx/drivers/include/Legacy/stm32_hal_legacy.h @@ -564,6 +564,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -1283,10 +1286,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1298,10 +1301,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1485,7 +1488,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -2033,12 +2036,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -3699,7 +3702,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3950,7 +3953,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h index d3bd1543c..f98d3691a 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal.h @@ -78,10 +78,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** * @brief STM32WBAxx HAL Driver version number */ -#define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBAxx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WBAxx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x07UL) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32WBAxx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ |(__STM32WBAxx_HAL_VERSION_SUB1 << 16U)\ |(__STM32WBAxx_HAL_VERSION_SUB2 << 8U )\ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_conf.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_conf.h index 82b834a94..c48764d11 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_conf.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_conf.h @@ -180,6 +180,7 @@ extern "C" { #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ /* ################## SPI peripheral configuration ########################## */ @@ -205,6 +206,10 @@ extern "C" { #include "stm32wbaxx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32wbaxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + #ifdef HAL_ADC_MODULE_ENABLED #include "stm32wbaxx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ @@ -289,10 +294,6 @@ extern "C" { #include "stm32wbaxx_hal_ramcfg.h" #endif /* HAL_RAMCFG_MODULE_ENABLED */ -#ifdef HAL_RCC_MODULE_ENABLED -#include "stm32wbaxx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - #ifdef HAL_RNG_MODULE_ENABLED #include "stm32wbaxx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ @@ -337,6 +338,9 @@ extern "C" { #include "stm32wbaxx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32wbaxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h index 2c6ff0507..504a1aa8b 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cortex.h @@ -114,6 +114,9 @@ typedef struct #define SYSTICK_CLKSOURCE_LSI 0x00000001U /*!< LSI clock selected as SysTick clock source */ #define SYSTICK_CLKSOURCE_LSE 0x00000002U /*!< LSE clock selected as SysTick clock source */ #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /*!< AHB clock selected as SysTick clock source */ +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define SYSTICK_CLKSOURCE_HSI_DIV4 0x00000008U /*!< HSI clock divided by 4 selected as SysTick clock source */ +#endif /** * @} */ @@ -333,10 +336,18 @@ void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_Attribute #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)|| \ + ((SOURCE) == SYSTICK_CLKSOURCE_HSI_DIV4)) +#else #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +#endif #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cryp.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cryp.h index b862c06d5..6288f6089 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cryp.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_cryp.h @@ -484,25 +484,25 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg @ref CRYP_FLAG_KEIF Key error flag * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (FlagStatus). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\ - ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ - ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ - ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ - ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ - (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + (CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h index f82abcc93..c26656a2a 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_dma_ex.h @@ -540,12 +540,12 @@ typedef struct #define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ #define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ -#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ -#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ -#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ -#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ -#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ -#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ +#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_exti.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_exti.h index a14a2cc5e..8e8b2ad2d 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_exti.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_exti.h @@ -192,19 +192,19 @@ typedef struct /** * @brief EXTI Line property definition */ -#define EXTI_PROPERTY_SHIFT 24U -#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT) -#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ #define EXTI_REG_SHIFT 16U -#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT) -#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT) +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) #define EXTI_PIN_MASK 0x0000001FU @@ -355,8 +355,8 @@ typedef struct * @{ */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h index bb3d280a0..149fd2c8e 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_flash_ex.h @@ -316,12 +316,12 @@ typedef struct /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); #if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) -HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(const FLASH_BBAttributesTypeDef *pBBAttributes); void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); #endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h index c937b0d82..0295cc129 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio.h @@ -352,10 +352,10 @@ GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) */ +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h index a2f15826f..c9839b490 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gpio_ex.h @@ -117,6 +117,11 @@ extern "C" { */ #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_PTA ((uint8_t)0x0A) /*!< PTA Alternate Function mapping */ + /** * @brief AF 11 selection */ @@ -127,6 +132,7 @@ extern "C" { */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_PTA ((uint8_t)0x0C) /*!< PTA Alternate Function mapping */ /** * @brief AF 13 selection @@ -321,7 +327,7 @@ extern "C" { #endif /* defined(STM32WBA50xx) */ -#if defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) /** * @brief AF 0 selection */ @@ -403,6 +409,7 @@ extern "C" { /** * @brief AF 10 selection */ +#define GPIO_AF10_PTA ((uint8_t)0x0A) /*!< PTA Alternate Function mapping */ #define GPIO_AF10_USB_OTG_HS ((uint8_t)0x0A) /*!< USB OTG-HS Alternate Function mapping */ /** @@ -415,6 +422,7 @@ extern "C" { */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_PTA ((uint8_t)0x0C) /*!< PTA Alternate Function mapping */ #define GPIO_AF12_TIM4 ((uint8_t)0x0C) /*!< TIM4 Alternate Function mapping */ /** @@ -439,7 +447,7 @@ extern "C" { #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) -#endif /* defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#endif /* defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ #if defined(STM32WBA63xx) /** @@ -510,6 +518,11 @@ extern "C" { */ #define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_PTA ((uint8_t)0x0A) /*!< PTA Alternate Function mapping */ + /** * @brief AF 11 selection */ @@ -520,6 +533,7 @@ extern "C" { */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF12_PTA ((uint8_t)0x0C) /*!< PTA Alternate Function mapping */ /** * @brief AF 13 selection diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h index 55792cffb..e49e1fe21 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_gtzc.h @@ -45,7 +45,7 @@ extern "C" { /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ #if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx) #define GTZC_MPCBB_NB_VCTR_REG_MAX 4U /*!< Maximum number of superblocks */ -#elif defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#elif defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) #define GTZC_MPCBB_NB_VCTR_REG_MAX 28U /*!< Maximum number of superblocks */ #endif #define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 1U /*!< Maximum number of 32-bit registers to lock superblocks */ @@ -70,6 +70,7 @@ typedef struct MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ } MPCBB_ConfigTypeDef; + /** * @} */ @@ -149,6 +150,7 @@ typedef struct * @} */ + /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values * @{ */ @@ -185,13 +187,18 @@ typedef struct #if defined (TIM1) #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) #endif /* TIM1 */ +#if defined (SPI1) #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) +#endif /* SPI1 */ #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) #if defined (SAI1) #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) #endif /* SAI1 */ +#if defined (USB_DRD_FS) +#define GTZC_PERIPH_USB1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USB1_Pos) +#endif /* USB_DRD_FS */ #if defined (SPI3) #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) #endif /* SPI3 */ @@ -242,7 +249,7 @@ typedef struct #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) #if defined (OTFDEC1) -#define GTZC_PERIPH_OTFDEC1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_PERIPH_OTFDEC1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) #endif /* OTFDEC1 */ #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) #define GTZC_PERIPH_RTC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) @@ -259,10 +266,10 @@ typedef struct #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) -#if defined (SRAM6_BASE) +#if defined (GTZC_MPCBB6) #define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) #define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) -#endif /* SRAM6 */ +#endif /* MPCBB6 */ #define GTZC_PERIPH_ALL (0x00000020U) @@ -437,6 +444,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * @} */ + #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @addtogroup GTZC_Exported_Functions_Group3 diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_hcd.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_hcd.h index 8d78c8259..f2e387118 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_hcd.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_hcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wbaxx_ll_usb.h" -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32WBAxx_HAL_Driver * @{ */ @@ -53,11 +53,35 @@ typedef enum HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; +#if defined (USB_DRD_FS) +typedef USB_DRD_TypeDef HCD_TypeDef; +typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; +typedef USB_DRD_HCTypeDef HCD_HCTypeDef; +typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef; +#else typedef USB_OTG_GlobalTypeDef HCD_TypeDef; typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; typedef USB_OTG_HCTypeDef HCD_HCTypeDef; typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +#endif /* defined (USB_DRD_FS) */ +#if defined (USB_DRD_FS) +typedef enum +{ + HCD_HCD_STATE_DISCONNECTED = 0x00U, + HCD_HCD_STATE_CONNECTED = 0x01U, + HCD_HCD_STATE_RESETED = 0x02U, + HCD_HCD_STATE_RUN = 0x03U, + HCD_HCD_STATE_SUSPEND = 0x04U, + HCD_HCD_STATE_RESUME = 0x05U, +} HCD_HostStateTypeDef; + +/* PMA lookup Table size depending on PMA Size + * 8Bytes each Block 32Bit in each word + */ +#define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U)) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -74,6 +98,13 @@ typedef struct HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ +#if defined (USB_DRD_FS) + uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */ + uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */ + uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/ + uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */ + HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */ +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO uint32_t ErrorCode; /*!< HCD Error code */ @@ -103,6 +134,9 @@ typedef struct /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ */ +#ifndef HAL_HCD_CHANNEL_NAK_COUNT +#define HAL_HCD_CHANNEL_NAK_COUNT 2U +#endif /* HAL_HCD_CHANNEL_NAK_COUNT */ /** @defgroup HCD_Speed HCD Speed * @{ @@ -159,13 +193,20 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) - +#if defined (USB_DRD_FS) +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#else #define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#endif /* defined (USB_DRD_FS) */ #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#if defined (USB_DRD_FS) +#define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN) +#define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR) +#else #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) #define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) @@ -174,6 +215,7 @@ typedef struct #define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) #define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) #define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -193,6 +235,10 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); @@ -267,6 +313,10 @@ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd); +#endif /* defined (USB_DRD_FS) */ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state); /** @@ -280,6 +330,11 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd); +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -295,6 +350,21 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, u uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); +#if defined (USB_DRD_FS) +/* PMA Allocation functions **********************************************/ +/** @addtogroup PMA Allocation + * @{ + */ +HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint16_t ch_kind, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); + +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -304,6 +374,242 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** @defgroup HCD_Private_Macros HCD Private Macros * @{ */ +#if defined (USB_DRD_FS) +#define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +/** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel + * @{ + */ +#define HCD_LOGICAL_CH_NOT_OPENED 0xFFU +#define HCD_FREE_CH_NOT_FOUND 0xFFU +/** + * @} + */ + +/** @defgroup HCD_ENDP_Kind HCD Endpoint Kind + * @{ + */ +#define HCD_SNG_BUF 0U +#define HCD_DBL_BUF 1U +/** + * @} + */ + +/* Powerdown exit count */ +#define HCD_PDWN_EXIT_CNT 0x100U + +/* Set Channel */ +#define HCD_SET_CHANNEL USB_DRD_SET_CHEP + +/* Get Channel Register */ +#define HCD_GET_CHANNEL USB_DRD_GET_CHEP + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bChNum, bDir + * @retval None + */ +#define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER + +/** + * @brief Set the Setup bit in the corresponding channel, when a Setup + transaction is needed. + * @param USBx USB device. + * @param bChNum + * @retval None + */ +#define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval status + */ +#define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS +#define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS +/** + * @brief Sets/clears CH_KIND bit in the Channel register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND +#define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND +#define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND +#define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND + +/** + * @brief Clears bit ERR_RX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR + +/** + * @brief Clears bit ERR_TX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR +#define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_RX_DTOG USB_DRD_RX_DTOG +#define HCD_TX_DTOG USB_DRD_TX_DTOG +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG +#define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT +#define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +#define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) +{ + uint32_t HostCoreSpeed; + uint32_t ep_reg = USB_DRD_GET_CHEP(Instance, bChNum); + __IO uint32_t count = 10U; + + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(Instance); + + /* Count depends on device LS */ + if ((HostCoreSpeed == USB_DRD_SPEED_LS) || ((ep_reg & USB_CHEP_LSEP) == USB_CHEP_LSEP)) + { + count = (70U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U; + } + + if (count > 15U) + { + count = HCD_MAX(10U, (count - 15U)); + } + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum)); +} + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT +#define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT +#define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + + +/** + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); +} +#endif /* defined (USB_DRD_FS) */ + /** * @} */ @@ -318,7 +624,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ -#endif /* defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h index b7d5f1740..90f2f2505 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_i2c_ex.h @@ -107,59 +107,59 @@ typedef struct #if defined(I2C_TRIG_GRP1) #define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ #if defined(COMP1) -#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ #endif /* I2C_TRIG_GRP1 */ #define I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ #if defined(COMP1) -#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_icache.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_icache.h index 83e18ee7d..a39a60652 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_icache.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_icache.h @@ -101,13 +101,13 @@ typedef struct /** @defgroup ICACHE_Region_Size Remapped Region size * @{ */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd.h index ced072559..30ed7cc90 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wbaxx_ll_usb.h" -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32WBAxx_HAL_Driver * @{ @@ -85,6 +85,11 @@ typedef USB_OTG_GlobalTypeDef PCD_TypeDef; typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; typedef USB_OTG_EPTypeDef PCD_EPTypeDef; #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +typedef USB_DRD_TypeDef PCD_TypeDef; +typedef USB_DRD_CfgTypeDef PCD_InitTypeDef; +typedef USB_DRD_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_DRD_FS) */ /** * @brief PCD Handle Structure definition @@ -98,8 +103,14 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ +#if defined (USB_OTG_HS) PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ +#endif /* defined (USB_DRD_FS) */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ __IO uint32_t ErrorCode; /*!< PCD Error code */ @@ -210,6 +221,10 @@ typedef struct ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -372,6 +387,42 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** @defgroup PCD_Private_Constants PCD Private Constants * @{ */ +#if defined (USB_DRD_FS) +/** @defgroup PCD_EP0_MPS PCD EP0 MPS + * @{ + */ +#define PCD_EP0MPS_64 EP_MPS_64 +#define PCD_EP0MPS_32 EP_MPS_32 +#define PCD_EP0MPS_16 EP_MPS_16 +#define PCD_EP0MPS_08 EP_MPS_8 +/** + * @} + */ + +/** @defgroup PCD_ENDP PCD ENDP + * @{ + */ +#define PCD_ENDP0 0U +#define PCD_ENDP1 1U +#define PCD_ENDP2 2U +#define PCD_ENDP3 3U +#define PCD_ENDP4 4U +#define PCD_ENDP5 5U +#define PCD_ENDP6 6U +#define PCD_ENDP7 7U +/** + * @} + */ + +/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind + * @{ + */ +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -406,6 +457,211 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** @defgroup PCD_Private_Macros PCD Private Macros * @{ */ +#if defined (USB_DRD_FS) +/* PMA RX counter */ +#ifndef PCD_RX_PMA_CNT +#define PCD_RX_PMA_CNT 10U +#endif /* PCD_RX_PMA_CNT */ + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT USB_DRD_SET_CHEP + +/* GetENDPOINT Register value*/ +#define PCD_GET_ENDPOINT USB_DRD_GET_CHEP + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND +#define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND +#define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR +#define PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG USB_DRD_RX_DTOG +#define PCD_TX_DTOG USB_DRD_TX_DTOG +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG +#define PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS +#define PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT +#define PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum)); +} + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT +#define PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT +#define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + +/** + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = PCD_RX_PMA_CNT; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); +} +#endif /* defined (USB_DRD_FS) */ /** * @} @@ -418,7 +674,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ -#endif /* defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd_ex.h index b8999c69a..aeddde2c0 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pcd_ex.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wbaxx_hal_def.h" -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32WBAxx_HAL_Driver * @{ */ @@ -45,12 +45,15 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress); +#endif /* defined (USB_DRD_FS) */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); @@ -78,7 +81,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /** * @} */ -#endif /* defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h index 0d804a431..598058ef4 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr.h @@ -1103,7 +1103,7 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN8)) #endif /* defined (STM32WBA55xx) */ #endif /* defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) */ -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\ ((PIN) == PWR_WAKEUP_PIN1_HIGH_1) ||\ ((PIN) == PWR_WAKEUP_PIN2_HIGH_0) ||\ @@ -1150,7 +1150,7 @@ typedef struct ((PIN) == PWR_WAKEUP_PIN6) ||\ ((PIN) == PWR_WAKEUP_PIN7) ||\ ((PIN) == PWR_WAKEUP_PIN8)) -#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) */ +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ /* PVD level check macro */ #if defined(PWR_STOP3_SUPPORT) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h index 34e8b63d4..1f924a6f4 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_pwr_ex.h @@ -290,9 +290,13 @@ extern "C" { #endif /* defined(USB_OTG_HS) */ #else #if defined(PWR_STOP3_SUPPORT) +#if defined (PWR_USB_SRAM_STOP_RETENTION) +#define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ + PWR_USB_SRAM_STOP_RETENTION | PWR_PKA_SRAM_STOP_RETENTION) +#else /* defined (PWR_USB_SRAM_STOP_RETENTION) */ #define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ - PWR_ICACHE_FULL_STOP_RETENTION | PWR_USB_SRAM_STOP_RETENTION | \ PWR_PKA_SRAM_STOP_RETENTION) +#endif /* defined (PWR_USB_SRAM_STOP_RETENTION) */ #else #define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ PWR_ICACHE_FULL_STOP_RETENTION ) @@ -418,7 +422,6 @@ extern "C" { ((RAMCONTENT) == PWR_SRAM2_PAGE1_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_SRAM2_PAGE2_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ - ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_PKA_SRAM_STOP_RETENTION)) #else #define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_PAGE1_STOP_RETENTION) ||\ @@ -430,7 +433,7 @@ extern "C" { ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION) ||\ ((RAMCONTENT) == PWR_PKA_SRAM_STOP_RETENTION)) -#endif /* defined(PWR_STOP3_SUPPORT) && (defined (STM32WBA24xx) || defined (STM32WBA25xx)) */ +#endif /* defined(PWR_STOP3_SUPPORT) */ #endif /* defined(USB_OTG_HS) */ #else #define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_ramcfg.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_ramcfg.h index 9fd41ed68..924d8f8d7 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_ramcfg.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_ramcfg.h @@ -393,8 +393,11 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg) ((WAITSTATE) == RAMCFG_WAITSTATE_4) || ((WAITSTATE) == RAMCFG_WAITSTATE_5) || \ ((WAITSTATE) == RAMCFG_WAITSTATE_6) || ((WAITSTATE) == RAMCFG_WAITSTATE_7)) -#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) - +#if defined(RAMCFG_WPR2_P32WP) +#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) < 64U) +#else /* defined(RAMCFG_WPR2_P32WP) */ +#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) < 32U) +#endif /* defined(RAMCFG_WPR2_P32WP) */ /** diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h index ddbcb054f..f5d6e283c 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc.h @@ -413,20 +413,20 @@ typedef struct * @{ */ /* Flags in the CIFR register */ -#define RCC_IT_LSI1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI1RDYF_Pos) /*!< LSI1 Ready Interrupt flag */ -#define RCC_IT_LSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSERDYF_Pos) /*!< LSE Ready Interrupt flag */ -#define RCC_IT_HSIRDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSIRDYF_Pos) /*!< HSI16 Ready Interrupt flag */ -#define RCC_IT_HSERDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSERDYF_Pos) /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLL1RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_PLL1RDYF_Pos) /*!< PLL1 Ready Interrupt flag */ -#define RCC_IT_CSS ((CIFR_REG_INDEX << 5U) | RCC_CIFR_HSECSSF_Pos) /*!< HSE32 Clock Security System Interrupt flag */ +#define RCC_IT_LSI1RDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_LSI1RDYF_Pos) /*!< LSI1 Ready Interrupt flag */ +#define RCC_IT_LSERDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_LSERDYF_Pos) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_HSIRDYF_Pos) /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_HSERDYF_Pos) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLL1RDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_PLL1RDYF_Pos) /*!< PLL1 Ready Interrupt flag */ +#define RCC_IT_CSS ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_HSECSSF_Pos) /*!< HSE32 Clock Security System Interrupt flag */ #if defined(RCC_LSI2_SUPPORT) -#define RCC_IT_LSI2RDY ((CIFR_REG_INDEX << 5U) | RCC_CIFR_LSI2RDYF_Pos) /*!< LSI2 Ready Interrupt flag */ +#define RCC_IT_LSI2RDY ((CIFR_REG_INDEX << 5UL) | RCC_CIFR_LSI2RDYF_Pos) /*!< LSI2 Ready Interrupt flag */ #endif /* RCC_BDCR1_LSI2ON */ /* Flags in the ASSR register */ -#define RCC_IT_CAPTURE_ERROR ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAEF_Pos) /*!< Capture Error Interrupt flag */ -#define RCC_IT_COMPARER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_COF_Pos) /*!< Comparer Interrupt flag */ -#define RCC_IT_CAPTURE_TRIGGER ((ASSR_REG_INDEX << 5U) | RCC_ASSR_CAF_Pos) /*!< Capture Trigger Interrupt flag */ +#define RCC_IT_CAPTURE_ERROR ((ASSR_REG_INDEX << 5UL) | RCC_ASSR_CAEF_Pos) /*!< Capture Error Interrupt flag */ +#define RCC_IT_COMPARER ((ASSR_REG_INDEX << 5UL) | RCC_ASSR_COF_Pos) /*!< Comparer Interrupt flag */ +#define RCC_IT_CAPTURE_TRIGGER ((ASSR_REG_INDEX << 5UL) | RCC_ASSR_CAF_Pos) /*!< Capture Trigger Interrupt flag */ /** * @} */ @@ -1134,7 +1134,7 @@ typedef struct } while(0) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ @@ -1142,7 +1142,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ UNUSED(tmpreg); \ } while(0) -#endif /* USB */ +#endif /* USB_DRD_FS */ #if defined(TIM1) #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) @@ -1158,9 +1158,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) -#endif /* USB */ +#endif /* USB_DRD_FS */ /** * @} */ @@ -1395,9 +1395,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) -#endif /* USB */ +#endif /* USB_DRD_FS */ /** * @} */ @@ -1645,9 +1645,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) -#endif /* SAI1 */ +#endif /* USB_DRD_FS */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) @@ -1662,9 +1662,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) -#endif /* USB */ +#endif /* USB_DRD_FS */ /** * @} */ @@ -1955,9 +1955,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) -#endif /* USB */ +#endif /* USB_DRD_FS */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #if defined(SPI1) @@ -1971,9 +1971,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) -#endif /* USB */ +#endif /* USB_DRD_FS */ /** * @} */ @@ -2153,9 +2153,9 @@ typedef struct #if defined(SAI1) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) #endif /* SAI1 */ -#if defined(USB) +#if defined(USB_DRD_FS) #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) != 0U) -#endif /* USB */ +#endif /* USB_DRD_FS */ /** * @} */ @@ -2676,8 +2676,8 @@ typedef struct */ #if defined(RCC_CCIPR2_ASSEL) #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ - WRITE_REG(RCC->CICR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ - CLEAR_BIT(RCC->ASSR,1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) + WRITE_REG(RCC->CICR,1UL << ((__INTERRUPT__) & RCC_FLAG_MASK)) : \ + CLEAR_BIT(RCC->ASSR,1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) #else #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) #endif /* RCC_CCIPR2_ASSEL */ @@ -2702,8 +2702,8 @@ typedef struct */ #if defined(RCC_CCIPR2_ASSEL) #define __HAL_RCC_GET_IT(__INTERRUPT__) ((((__INTERRUPT__) >> 5U) == 0U) ? \ - ((RCC->CIFR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) : \ - ((RCC->ASSR & (1U << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1U << ((__INTERRUPT__) & RCC_FLAG_MASK)))) + ((RCC->CIFR & (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) : \ + ((RCC->ASSR & (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK))) == (1UL << ((__INTERRUPT__) & RCC_FLAG_MASK)))) #else #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) #endif /* RCC_CCIPR2_ASSEL */ @@ -2759,13 +2759,13 @@ typedef struct /* Defines used for Flags */ -#define CR_REG_INDEX (1U) -#define BDCR1_REG_INDEX (2U) -#define CSR_REG_INDEX (3U) +#define CR_REG_INDEX (1UL) +#define BDCR1_REG_INDEX (2UL) +#define CSR_REG_INDEX (3UL) #if defined(RCC_CCIPR2_ASSEL) /* Defines used for Interrupt Flags */ -#define CIFR_REG_INDEX (0U) -#define ASSR_REG_INDEX (1U) +#define CIFR_REG_INDEX (0UL) +#define ASSR_REG_INDEX (1UL) #endif /* RCC_CCIPR2_ASSEL */ #define RCC_FLAG_MASK (0x1FU) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h index 8e1926761..12d74f885 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rcc_ex.h @@ -342,7 +342,7 @@ uint32_t CompareValue; /*!< Compare value. #define RCC_SYSTICKCLKSOURCE_HCLK_DIV8 0x00000000U #define RCC_SYSTICKCLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 #define RCC_SYSTICKCLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) #define RCC_SYSTICKCLKSOURCE_HSI_DIV4 (RCC_CCIPR1_SYSTICKSEL_1 | RCC_CCIPR1_SYSTICKSEL_0) #endif /** @@ -731,10 +731,8 @@ uint32_t CompareValue; /*!< Compare value. * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) - * @arg RCC_SYSTICKCLKSOURCE_HSI_DIV4 : HSI Clock selected as SYSTICK clock (1) + * @arg RCC_SYSTICKCLKSOURCE_HSI_DIV4 : HSI divided by 4 Clock selected as SYSTICK clock (1) * @note (1) Source is not available on all devices -#endif */ #define __HAL_RCC_SYSTICK_CONFIG(__SYSTICK_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (__SYSTICK_CLKSOURCE__)) @@ -744,10 +742,8 @@ uint32_t CompareValue; /*!< Compare value. * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) - * @arg RCC_SYSTICKCLKSOURCE_HSI_DIV4 : LSI Clock selected as SYSTICK clock (1) + * @arg RCC_SYSTICKCLKSOURCE_HSI_DIV4 : HSI divided by 4 Clock selected as SYSTICK clock (1) * @note (1) Source is not available on all devices -#endif */ #define __HAL_RCC_GET_SYSTICK_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL) @@ -1081,7 +1077,7 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_RADIOST) -#elif defined (STM32WBA62xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#elif defined (STM32WBA62xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) #define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ @@ -1170,7 +1166,7 @@ uint32_t HAL_RCCEx_GetAudioSyncCaptureValue(void); ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)) #endif -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) #define IS_RCC_SYSTICKCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSTICKCLKSOURCE_HCLK_DIV8) || \ ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSE) || \ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rng.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rng.h index 0b66c1272..4098f2096 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rng.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rtc_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rtc_ex.h index 4b99399a4..5d6fe5fe3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rtc_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_rtc_ex.h @@ -354,14 +354,19 @@ typedef struct #define RTC_TAMPER_3 TAMP_CR1_TAMP3E #ifdef TAMP_CR1_TAMP4E #define RTC_TAMPER_4 TAMP_CR1_TAMP4E +#endif /* TAMP_CR1_TAMP4E */ +#ifdef TAMP_CR1_TAMP5E #define RTC_TAMPER_5 TAMP_CR1_TAMP5E #define RTC_TAMPER_6 TAMP_CR1_TAMP6E -#endif /* TAMP_CR1_TAMP4E */ +#endif /* TAMP_CR1_TAMP5E */ -#ifdef TAMP_CR1_TAMP4E +#ifdef TAMP_CR1_TAMP5E #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ RTC_TAMPER_3 | RTC_TAMPER_4 |\ RTC_TAMPER_5 | RTC_TAMPER_6) +#elif defined(TAMP_CR1_TAMP4E) +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ + RTC_TAMPER_3 | RTC_TAMPER_4) #else #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ RTC_TAMPER_3) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai.h index a6625bcc7..030c78d0b 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai.h @@ -47,14 +47,14 @@ extern "C" { typedef struct { FunctionalState Activation; /*!< Enable/disable PDM interface */ -#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 3 for STM32WBA6xxx devices, Max_Data = 2 for other devices. */ -#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. This parameter must be a number between Min_Data = 1 and Max_Data = 2. */ -#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t ClockEnable; /*!< Specifies which clock must be enabled. This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ } SAI_PdmInitTypeDef; @@ -859,11 +859,11 @@ uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) -#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) -#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 2U)) -#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai_ex.h index 6ec92bdec..830d292ee 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_sai_ex.h @@ -45,14 +45,14 @@ extern "C" { */ typedef struct { -#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) uint32_t MicPair; /*!< Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 3 for STM32WBA6xxx devices, Max_Data = 2 for other devices. */ -#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#else /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t MicPair; /*!< Specifies which pair of microphones is selected. This parameter must be a number between Min_Data = 1 and Max_Data = 2. */ -#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) */ +#endif /* defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) */ uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone. This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smartcard.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smartcard.h index 7e2ee7038..2d359c163 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smartcard.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smartcard.h @@ -726,13 +726,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h index adb43d004..76150a820 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_smbus_ex.h @@ -99,59 +99,59 @@ typedef struct #if defined(SMBUS_TRIG_GRP1) #define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ #if defined(COMP1) -#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ #endif /* SMBUS_TRIG_GRP1 */ #define SMBUS_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define SMBUS_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define SMBUS_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define SMBUS_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ #if defined(COMP1) -#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ #endif /* COMP1 */ #if defined(COMP2) -#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ #endif /* COMP2 */ -#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h index 7537de2d3..c0e7db099 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_spi_ex.h @@ -87,57 +87,57 @@ typedef struct /* HW Trigger signal is GPDMA_CH0_TRG */ #define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) /* HW Trigger signal is GPDMA_CH1_TRG */ -#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH2_TRG */ -#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH3_TRG */ -#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI9_TRG */ -#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) #if defined(LPTIM2) /* HW Trigger signal is LPTIM2_CH1_TRG */ -#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* LPTIM2 */ #if defined(COMP1) /* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* COMP1 */ #if defined(COMP2) /* HW Trigger signal is COMP2_TRG */ -#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* (COMP2) */ /* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* SPI_TRIG_GRP1 */ /* HW Trigger signal is GPDMA_CH0_TRG */ #define SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) /* HW Trigger signal is GPDMA_CH1_TRG */ -#define SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH2_TRG */ -#define SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH3_TRG */ -#define SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI8_TRG */ -#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) #if defined(COMP1) /* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* COMP1 */ /* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h index aad5fc89f..c7be9984e 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim.h @@ -244,8 +244,10 @@ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ +#if defined(TIM_CR2_MMS2) uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ +#endif /* TIM_CR2_MMS2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of @@ -296,6 +298,7 @@ typedef struct uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ +#if defined(TIM_BDTR_BK2E) uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ @@ -303,6 +306,7 @@ typedef struct uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ +#endif /*TIM_BDTR_BK2E */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ @@ -349,8 +353,12 @@ typedef enum HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ +#if defined(TIM_CCER_CC5E) HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ +#endif /* TIM_CCER_CC6E */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; @@ -370,8 +378,13 @@ typedef struct This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ +#if defined(TIM1) __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ +#else + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[1]; /*!< TIM complementary channel operation state */ +#endif /* TIM1 */ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) @@ -402,7 +415,9 @@ typedef struct void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#if defined(TIM_BDTR_BK2E) void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* TIM_BDTR_BK2E */ void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ @@ -443,7 +458,9 @@ typedef enum , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +#if defined(TIM_BDTR_BK2E) , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +#endif /* TIM_BDTR_BK2E */ , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ @@ -472,8 +489,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#if defined(COMP1) && defined(COMP2) #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ #define TIM_CLEARINPUTSOURCE_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -499,9 +518,13 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U +#if defined(TIM_CCER_CC5E) #define TIM_DMABASE_CCR5 0x00000012U +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define TIM_DMABASE_CCR6 0x00000013U #define TIM_DMABASE_CCMR3 0x00000014U +#endif /* TIM_CCER_CC6E */ #define TIM_DMABASE_DTR2 0x00000015U #define TIM_DMABASE_ECR 0x00000016U #define TIM_DMABASE_TISEL 0x00000017U @@ -523,7 +546,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#if defined(TIM_EGR_B2G) #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +#endif /* TIM_EGR_B2G */ /** * @} */ @@ -786,12 +811,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#if defined(TIM_SR_CC5IF) #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#endif /* TIM_SR_CC5IF */ +#if defined(TIM_SR_CC6IF) #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#endif /* TIM_SR_CC6IF */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#if defined(TIM_SR_B2IF) #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#endif /* TIM_SR_B2IF */ #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ @@ -812,8 +843,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#if defined(TIM_CCER_CC5E) #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#endif /* TIM_CCER_CC6E */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} @@ -828,20 +863,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#if defined(TIM1) #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#endif /* TIM1 */ +#if defined(TIM3) || defined(TIM2) #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#endif /* TIM3 */ #if defined(TIM4) #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #endif /* TIM4 */ -#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ -#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ -#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ -#if defined(USB_OTG_HS) +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ -#endif /* USB_OTG_HS */ +#endif /* USB_OTG_HS || USB_DRD_FS */ /** * @} */ @@ -944,6 +980,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_BDTR_BK2E) /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ @@ -970,6 +1007,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#endif /* TIM_BDTR_BK2E */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ @@ -980,6 +1018,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_CCR5_CCR5) /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ @@ -990,6 +1029,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#endif /* TIM_CCR5_CCR5 */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ @@ -1007,6 +1047,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +#if defined(TIM_CR2_MMS2) /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ @@ -1029,6 +1070,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#endif /* TIM_CR2_MMS2 */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ @@ -1079,17 +1121,21 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ +#if defined(TIM1) #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#endif /* TIM1 */ +#if defined(TIM3) || defined(TIM2) #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#endif /* TIM3 */ #if defined(TIM4) #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ #endif /* TIM4 */ #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ -#if defined(USB_OTG_HS) +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ -#endif /* USB_OTG_HS */ +#endif /* USB_OTG_HS || USB_DRD_FS */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ @@ -1215,6 +1261,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#if defined(TIM1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ @@ -1244,6 +1291,32 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#endif /* TIM1 */ +#else +#if defined(TIM1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ @@ -1258,6 +1331,17 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* TIM1 */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1395,12 +1479,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1410,6 +1494,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag + * (*) Value not defined for all devices * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) @@ -1423,12 +1508,12 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag @@ -1438,6 +1523,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag + * (*) Value not defined for all devices * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) @@ -1645,11 +1731,13 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ @@ -1657,6 +1745,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) +#else +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Get the TIM Capture Compare Register value on runtime. @@ -1667,10 +1762,12 @@ mode. * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @arg TIM_CHANNEL_5: get capture/compare 5 register value - * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value (*) + * @arg TIM_CHANNEL_6: get capture/compare 6 register value (*) + * (*) Value not defined for all devices * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ @@ -1678,6 +1775,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) +#else +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Set the TIM Output compare preload. @@ -1688,10 +1792,12 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ @@ -1699,6 +1805,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) +#else +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Reset the TIM Output compare preload. @@ -1709,10 +1822,12 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ @@ -1720,6 +1835,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) +#else +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Enable fast mode for a given channel. @@ -1730,14 +1852,16 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ @@ -1745,6 +1869,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) +#else +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Disable fast mode for a given channel. @@ -1755,14 +1886,16 @@ mode. * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ @@ -1770,6 +1903,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) +#else +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1837,8 +1977,14 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) +#else +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @} */ @@ -1848,11 +1994,17 @@ mode. /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ +#if defined(COMP1) && defined(COMP2) #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#endif /* COMP1 && COMP2 */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ ((__BASE__) == TIM_DMABASE_SMCR) || \ @@ -1878,10 +2030,40 @@ mode. ((__BASE__) == TIM_DMABASE_AF2) || \ ((__BASE__) == TIM_DMABASE_TISEL) || \ ((__BASE__) == TIM_DMABASE_DTR2) || \ - ((__BASE__) == TIM_DMABASE_ECR) || \ + ((__BASE__) == TIM_DMABASE_ECR) || \ + ((__BASE__) == TIM_DMABASE_OR)) +#else +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL) || \ + ((__BASE__) == TIM_DMABASE_DTR2) || \ + ((__BASE__) == TIM_DMABASE_ECR) || \ ((__BASE__) == TIM_DMABASE_OR)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ +#if defined(TIM_EGR_B2G) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#else +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#endif /* TIM_EGR_B2G */ #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ @@ -1930,9 +2112,13 @@ mode. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ ((__CHANNEL__) != (TIM_CHANNEL_6))) +#else +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -1949,6 +2135,7 @@ mode. #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ @@ -1956,13 +2143,22 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) || \ ((__CHANNEL__) == TIM_CHANNEL_6) || \ ((__CHANNEL__) == TIM_CHANNEL_ALL)) +#else +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) +#endif /* TIM_CCER_CC5E &&TIM_CCER_CC6E */ #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ + ((__PERIOD__) > 0U )) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1983,7 +2179,7 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) -#else +#elif defined(TIM1) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ @@ -1995,6 +2191,27 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) +#else /* (USB_OTG_HS) || (USB_DRD_FS) */ +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)) +#endif #endif /* TIM4 */ #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ @@ -2043,6 +2260,7 @@ mode. ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) +#if defined(TIM_BDTR_BK2E) #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) @@ -2052,11 +2270,14 @@ mode. #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) +#endif /* TIM_BDTR_BK2E */ #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) +#if defined(TIM_CCR5_CCR5) #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) +#endif /* TIM_CCR5_CCR5 */ #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ @@ -2068,6 +2289,7 @@ mode. ((__SOURCE__) == TIM_TRGO_OC4REF) || \ ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) +#if defined(TIM_CR2_MMS2) #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ @@ -2085,6 +2307,7 @@ mode. ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) +#endif /* TIM_CR2_MMS2 */ #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) @@ -2124,13 +2347,24 @@ mode. ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11) || \ ((__SELECTION__) == TIM_TS_NONE)) +#elif defined(TIM1) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)) #else -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE)) +#else /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM4 */ #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ @@ -2214,6 +2448,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ @@ -2230,21 +2465,38 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) +#else +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);\ + } while(0) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ @@ -2257,16 +2509,24 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) +#else +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + HAL_TIM_CHANNEL_STATE_READY) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) \ + (((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__))) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h index 4b7420c07..37e8c1100 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_tim_ex.h @@ -106,6 +106,7 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ +#if defined(TIM1) #define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ #define TIM_TIM1_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ @@ -113,17 +114,28 @@ typedef struct #define TIM_TIM1_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */ #define TIM_TIM1_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */ #define TIM_TIM1_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */ +#endif /* TIM1 */ #define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ #define TIM_TIM2_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ +#if defined(TIM3) #define TIM_TIM2_ETR_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ +#endif /* TIM3 */ #if defined(TIM4) #define TIM_TIM2_ETR_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ #endif /* TIM4 */ #define TIM_TIM2_ETR_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ +#if defined(TIM2_ETR_ADC4_SUPPORT) +#define TIM_TIM2_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM2_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM2_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to ADC4 AWD3 */ +#endif /* TIM2_ETR_ADC4_SUPPORT */ +#if defined(TIM3) #define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ #define TIM_TIM3_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ #define TIM_TIM3_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ @@ -135,8 +147,9 @@ typedef struct #define TIM_TIM3_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1| TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC4 AWD1 */ #define TIM_TIM3_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC4 AWD2 */ #define TIM_TIM3_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC4 AWD3 */ -#if defined(TIM4) +#endif /* TIM3 */ +#if defined(TIM4) #define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ #define TIM_TIM4_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ #define TIM_TIM4_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ @@ -151,7 +164,9 @@ typedef struct * @{ */ #define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#if defined(TIM_BDTR_BK2E) #define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +#endif /* TIM_BDTR_BK2E */ /** * @} */ @@ -160,8 +175,10 @@ typedef struct * @{ */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#if defined(COMP1) && defined(COMP2) #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -187,24 +204,33 @@ typedef struct /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ +#if defined(TIM1) #define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ #define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */ #define TIM_TIM1_TI2_GPIO 0x00000000UL /*!< TIM1_TI2 is connected to GPIO */ #define TIM_TIM1_TI3_GPIO 0x00000000UL /*!< TIM1_TI3 is connected to GPIO */ #define TIM_TIM1_TI4_GPIO 0x00000000UL /*!< TIM1_TI4 is connected to GPIO */ +#endif /* TIM1 */ #define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */ #define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */ #define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */ +#endif /* COMP1 && COMP2 */ #define TIM_TIM2_TI3_GPIO 0x00000000UL /*!< TIM2_TI3 is connected to GPIO */ #define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#endif /* COMP1 && COMP2 */ +#if defined(TIM3) #define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ @@ -213,8 +239,9 @@ typedef struct #define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */ #define TIM_TIM3_TI3_GPIO 0x00000000UL /*!< TIM3_TI3 is connected to GPIO */ #define TIM_TIM3_TI4_GPIO 0x00000000UL /*!< TIM3_TI4 is connected to GPIO */ -#if defined(TIM4) +#endif /* TIM3 */ +#if defined(TIM4) #define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ #define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4_TI1 is connected to COMP1 OUT */ #define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP2 OUT */ @@ -418,12 +445,21 @@ typedef struct * @{ */ #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) + +#if defined(TIM_BDTR_BK2E) #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) +#else +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) +#endif /* TIM_BDTR_BK2E */ +#if defined(COMP1) && defined(COMP2) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) +#endif /* COMP1 && COMP2 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) @@ -431,10 +467,14 @@ typedef struct #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) +#if !defined(TIM1) +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xFFFFFFF0U) == 0x00000000U)) +#else #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) +#endif /* !TIM1 */ #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ - (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) + (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) <= TIM_CHANNEL_4)) #if defined(TIM4) && defined(TIM3) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ @@ -527,7 +567,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) -#else +#elif defined(TIM1) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -552,6 +592,31 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) +#else /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM3 */ #if defined(TIM4) && defined(TIM3) @@ -631,7 +696,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) -#else +#elif defined(TIM1) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ @@ -652,6 +717,27 @@ typedef struct ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11))) +#else /* (USB_OTG_HS) || (USB_DRD_FS)*/ +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM3 */ #if defined(TIM4) && defined(TIM3) @@ -710,7 +796,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) -#else +#elif defined(TIM1) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ @@ -725,6 +811,21 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR11) || \ + ((__SELECTION__) == TIM_TS_NONE))) +#else /* (USB_OTG_HS) || (USB_DRD_FS) */ +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) +#endif /* (USB_OTG_HS) || (USB_DRD_FS) */ #endif /* TIM3 */ #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ @@ -878,7 +979,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#if defined(TIM_CCR5_CCR5) HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +#endif /* TIM_CCR5_CCR5 */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); @@ -915,7 +1018,9 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +#if defined(TIM_BDTR_BK2E) void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +#endif /* TIM_BDTR_BK2E */ void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h index 0fb00a91e..8805020de 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h index 5b3a5e69e..55d62d1bc 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_hal_usart.h @@ -550,10 +550,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -575,10 +575,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_adc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_adc.h index a5c71b857..7dcd465ed 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_adc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_adc.h @@ -250,37 +250,37 @@ extern "C" { /* ADC internal channels related definitions */ -#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #else /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#endif /* STM32WBA62xx || STM32WBA63xx || STM32WBA64xx || STM32WBA65xx */ +#endif /* STM32WBA62xx || STM32WBA63xx || STM32WBA64xx || STM32WBA65xx || STM32WBA6Mxx */ #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ -#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA0710UL)) /* Address of parameter TS_CAL1: On this series, +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x0BFA0710UL)) /* Address of parameter TS_CAL1: On this series, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA0742UL)) /* Address of parameter TS_CAL2: On this series, +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x0BFA0742UL)) /* Address of parameter TS_CAL2: On this series, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #else /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series, +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series, +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#endif /* STM32WBA62xx || STM32WBA63xx || STM32WBA64xx || STM32WBA65xx */ +#endif /* STM32WBA62xx || STM32WBA63xx || STM32WBA64xx || STM32WBA65xx || STM32WBA6Mxx */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_comp.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_comp.h index 081cf9da7..be55c3c8f 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_comp.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_comp.h @@ -344,7 +344,7 @@ typedef struct * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON * @retval None */ -__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) +__STATIC_INLINE void LL_COMP_SetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) { /* Note: On this STM32 series, window mode can be set from any instance */ /* of the pair of comparator instances. */ @@ -403,7 +403,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef * * @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 * @retval None */ -__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput) +__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(const COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput) { register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h index aa1db7a06..3a4997eb0 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_cortex.h @@ -946,13 +946,13 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attrib if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0 accordingly */ - MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else { /* Modify Attr field of MPU_MAIR1 accordingly */ - MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } @@ -979,13 +979,13 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Att if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else { /* Modify Attr field of MPU_MAIR1_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } #endif /* __ARM_FEATURE_CMSE */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h index b4d839f8c..f42a30154 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_dma.h @@ -527,8 +527,14 @@ typedef struct /** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port * @{ */ +#if defined(GPDMA1) #define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ #define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_LINK_ALLOCATED_PORT1 LL_DMA_LINK_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -574,8 +580,14 @@ typedef struct /** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port * @{ */ +#if defined(GPDMA1) #define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ #define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_SRC_ALLOCATED_PORT1 LL_DMA_SRC_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -583,8 +595,14 @@ typedef struct /** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port * @{ */ +#if defined(GPDMA1) #define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ #define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_DEST_ALLOCATED_PORT1 LL_DMA_DEST_ALLOCATED_PORT0 /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ @@ -709,9 +727,16 @@ typedef struct /** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction * @{ */ +#if defined(GPDMA1) #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#endif /* GPDMA1 */ +#if defined(LPDMA1) +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Kept for porting purpose */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Kept for porting purpose */ +#endif /* LPDMA1 */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_exti.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_exti.h index 74e659e16..81c7a73a2 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_exti.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_exti.h @@ -126,6 +126,11 @@ typedef struct * @{ */ #define LL_EXTI_CONFIG_PORTA 0U /*!< EXTI PORT A */ +#if !defined (EXTI_EXTICR1_EXTI0) +#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR2_EXTI4_0 /*!< EXTI PORT B */ +#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR2_EXTI4_1 /*!< EXTI PORT C */ +#define LL_EXTI_CONFIG_PORTH (EXTI_EXTICR2_EXTI4_2|EXTI_EXTICR2_EXTI4_1|EXTI_EXTICR2_EXTI4_0) /*!< EXTI PORT H */ +#else /* !defined (EXTI_EXTICR1_EXTI0) */ #define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ #define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ #if defined(GPIOD) @@ -138,6 +143,7 @@ typedef struct #define LL_EXTI_CONFIG_PORTG (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ #endif /* GPIOG */ #define LL_EXTI_CONFIG_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +#endif /* !defined (EXTI_EXTICR1_EXTI0) */ /** * @} */ @@ -1023,7 +1029,11 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) */ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) { +#if defined (EXTI_EXTICR1_EXTI0) MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#else /* defined (EXTI_EXTICR1_EXTI0) */ + MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR2_EXTI4 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#endif /* defined (EXTI_EXTICR1_EXTI0) */ } /** @@ -1069,7 +1079,11 @@ __STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) */ __STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) { +#if defined (EXTI_EXTICR1_EXTI0) return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#else /* defined (EXTI_EXTICR1_EXTI0) */ + return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], (EXTI_EXTICR2_EXTI4 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +#endif /* defined (EXTI_EXTICR1_EXTI0) */ } /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h index d5ec78d20..b37e6fcf3 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_gpio.h @@ -954,7 +954,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) /** * @brief Enable speed optimization for several pin of dedicated port. * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding @@ -1017,7 +1017,7 @@ __STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uin CLEAR_BIT(GPIOx->HSLVR, PinMask); } -#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) */ +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_lptim.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_lptim.h index 723ccd0a3..45334f612 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_lptim.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_lptim.h @@ -69,20 +69,20 @@ static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = { - LPTIM_CCMR1_CC1E_Pos, /* CC1E */ - LPTIM_CCMR1_CC2E_Pos /* CC2E */ + (uint8_t)LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + (uint8_t)LPTIM_CCMR1_CC2E_Pos /* CC2E */ }; static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = { - {2, 7, 9, 13}, - {3, 5, 6, 8}, - {2, 3, 4, 5}, - {2, 2, 3, 3}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2} + {2U, 7U, 9U, 13U}, + {3U, 5U, 6U, 8U}, + {2U, 3u, 4U, 5U}, + {2U, 2U, 3U, 3U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U} }; diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h index 057f9535b..fe91b2e50 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_pwr.h @@ -834,6 +834,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) #endif /* defined(PWR_STOP3_SUPPORT) */ } +#if defined (PWR_CR2_ICRAMPDS) /** * @brief Set the ICACHE SRAM page(s) retention in Stop mode. * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention @@ -862,6 +863,8 @@ __STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void) { return ((~(READ_BIT(PWR->CR2, PWR_CR2_ICRAMPDS))) & PWR_CR2_ICRAMPDS); } +#endif /* PWR_CR2_ICRAMPDS */ + #if defined(PWR_STOP2_SUPPORT) #if defined(USB_OTG_HS) /** @@ -1236,7 +1239,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); } -#elif defined(PWR_STOP3_SUPPORT) +#elif defined(PWR_STOP3_SUPPORT) && defined(PWR_SVMCR_USV) /** * @brief Enable the VDDUSB supply. * @rmtoll VOSR USV LL_PWR_EnableVddUSB @@ -1266,7 +1269,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); } -#endif /* defined(PWR_STOP3_SUPPORT) */ +#endif /* defined(PWR_STOP3_SUPPORT) && defined(PWR_SVMCR_USV) */ #if defined(PWR_SVMCR_IO2SV) /** @@ -1981,7 +1984,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRadioMode(void) * @} */ -#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASREN) /** @defgroup PWR_LL_EF_PTA_STOP2_RETENTION_MANAGEMENT PWR PTA Stop2 Retention Management * @{ */ @@ -2018,7 +2021,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPTAOutputStop2Retention(void) /** * @} */ -#endif /* PWR_STOP2_SUPPORT */ +#endif /* PWR_STOP2_SUPPORT && PWR_S2RETR_PTASREN */ /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management * @{ @@ -2208,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); } -#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) /** * @brief Indicate whether the PTA output signals state retention in Stop 2 mode is active or not. * @rmtoll SVMSR PTASR LL_PWR_IsActiveFlag_PTASR @@ -2218,7 +2221,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PTASR(void) { return ((READ_BIT(PWR->S2RETR, PWR_S2RETR_PTASR) == (PWR_S2RETR_PTASR)) ? 1UL : 0UL); } -#endif /* defined(PWR_STOP2_SUPPORT) */ +#endif /* defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) */ /** * @brief Clear stop flag. @@ -2346,7 +2349,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); } -#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) /** * @brief Clear the PTA output signals state retention in Stop 2 mode active. * @rmtoll SVMSR PTASR LL_PWR_ClearFlag_PTASR @@ -2356,7 +2359,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_PTASR(void) { CLEAR_BIT(PWR->S2RETR, PWR_S2RETR_PTASR); } -#endif /* defined(PWR_STOP2_SUPPORT) */ +#endif /* defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASR) */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h index aa683bdf2..98937ef07 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rcc.h @@ -45,9 +45,9 @@ extern "C" { */ /* Defines used to perform offsets*/ /* Offset used to access to RCC_CCIPR1, RCC_CCIPR2 and RCC_CCIPR3 registers */ -#define RCC_OFFSET_CCIPR1 0U -#define RCC_OFFSET_CCIPR2 0x04U -#define RCC_OFFSET_CCIPR3 0x08U +#define RCC_OFFSET_CCIPR1 0UL +#define RCC_OFFSET_CCIPR2 0x04UL +#define RCC_OFFSET_CCIPR3 0x08UL /* Defines used for security configuration extension */ #define RCC_SECURE_MASK 0x10FBU @@ -272,9 +272,12 @@ typedef struct /** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection * @{ */ -#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */ -#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ -#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) +#define LL_RCC_SYSTICK_CLKSOURCE_HSIDIV4 (RCC_CCIPR1_SYSTICKSEL_1 | RCC_CCIPR1_SYSTICKSEL_0) /*!< HSIDIV4 clock used as SYSTICK clock source */ +#endif /** * @} */ @@ -1535,6 +1538,9 @@ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HSIDIV4 (*) + * + * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) @@ -1641,6 +1647,9 @@ __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HSIDIV4 (*) + * + * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) { @@ -1943,7 +1952,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU))); + MODIFY_REG(*reg, 3UL << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU))); } /** @@ -1974,7 +1983,7 @@ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU))); + MODIFY_REG(*reg, 3UL << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU))); } /** @@ -1995,7 +2004,7 @@ __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU))); + MODIFY_REG(*reg, 3UL << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU))); } diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h index fc4241354..57029c438 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rng.h @@ -677,7 +677,11 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) #if defined(RNG_HTCR_NIST_VALUE) /* For NIST compliance we can fin the recommended value in the application note AN4230 */ #endif /* defined(RNG_HTCR_NIST_VALUE) */ +#if defined(RNG_HTCR0_HTCFG) + WRITE_REG(RNGx->HTCR[0], HTCFG); +#else WRITE_REG(RNGx->HTCR, HTCFG); +#endif /* defined(RNG_HTCR0_HTCFG) */ } /** @@ -688,7 +692,11 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) */ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) { +#if defined(RNG_HTCR0_HTCFG) + return (uint32_t)READ_REG(RNGx->HTCR[0]); +#else return (uint32_t)READ_REG(RNGx->HTCR); +#endif /* defined(RNG_HTCR0_HTCFG) */ } /** diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h index 2826a556c..7ebed7463 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_rtc.h @@ -4282,7 +4282,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U); } +#endif /* TAMP_SR_TAMP4F */ +#ifdef TAMP_SR_TAMP5F /** * @brief Get tamper 5 detection flag. * @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5 @@ -4294,7 +4296,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U); } +#endif /* TAMP_SR_TAMP5F */ +#ifdef TAMP_SR_TAMP6F /** * @brief Get tamper 6 detection flag. * @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6 @@ -4306,7 +4310,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U); } -#endif /* TAMP_SR_TAMP4F */ +#endif /* TAMP_SR_TAMP6F */ /** * @brief Get internal tamper 3 detection flag. @@ -4464,7 +4468,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U); } +#endif /* TAMP_MISR_TAMP4MF */ +#ifdef TAMP_MISR_TAMP5MF /** * @brief Get tamper 5 interrupt masked flag. * @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M @@ -4476,7 +4482,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U); } +#endif /* TAMP_MISR_TAMP5MF */ +#ifdef TAMP_MISR_TAMP6MF /** * @brief Get tamper 6 interrupt masked flag. * @rmtoll TAMP_MISR TAMP6MF LL_RTC_IsActiveFlag_TAMP6M @@ -4488,7 +4496,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U); } -#endif /* TAMP_MISR_TAMP4MF */ +#endif /* TAMP_MISR_TAMP6MF */ /** * @brief Get internal tamper 3 interrupt masked flag. @@ -4646,7 +4654,9 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F); } +#endif /* TAMP_SCR_CTAMP4F */ +#ifdef TAMP_SCR_CTAMP5F /** * @brief Clear tamper 5 detection flag. * @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5 @@ -4658,7 +4668,9 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F); } +#endif /* TAMP_SCR_CTAMP5F */ +#ifdef TAMP_SCR_CTAMP6F /** * @brief Clear tamper 6 detection flag. * @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6 @@ -4670,7 +4682,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F); } -#endif /* TAMP_SCR_CTAMP4F */ +#endif /* TAMP_SCR_CTAMP6F */ /** * @brief Clear internal tamper 3 detection flag. @@ -5363,7 +5375,9 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE); } +#endif /* TAMP_IER_TAMP4IE */ +#ifdef TAMP_IER_TAMP5IE /** * @brief Enable tamper 5 interrupt. * @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5 @@ -5387,7 +5401,9 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE); } +#endif /* TAMP_IER_TAMP5IE */ +#ifdef TAMP_IER_TAMP6IE /** * @brief Enable tamper 6 interrupt. * @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6 @@ -5411,7 +5427,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE); } -#endif /* TAMP_IER_TAMP4IE */ +#endif /* TAMP_IER_TAMP6IE */ /** * @brief Enable internal tamper 3 interrupt. @@ -5677,7 +5693,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U); } +#endif /* TAMP_IER_TAMP4IE */ +#ifdef TAMP_IER_TAMP5IE /** * @brief Check if tamper 5 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP5IE LL_RTC_IsEnabledIT_TAMP5 @@ -5689,7 +5707,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U); } +#endif /* TAMP_IER_TAMP5IE */ +#ifdef TAMP_IER_TAMP6IE /** * @brief Check if tamper 6 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6 @@ -5701,7 +5721,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(const RTC_TypeDef *RTCx) UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U); } -#endif /* TAMP_IER_TAMP4IE */ +#endif /* TAMP_IER_TAMP6IE */ /** * @brief Check if internal tamper 3 interrupt is enabled or not. diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h index 296d4a213..a844b4fa6 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_tim.h @@ -149,7 +149,7 @@ static const uint8_t SHIFT_TAB_OISx[] = */ #define OCREF_CLEAR_SELECT_POS (28U) -#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ +#define OCREF_CLEAR_SELECT_MSK (0x1UL << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ /** * @} */ @@ -172,6 +172,7 @@ static const uint8_t SHIFT_TAB_OISx[] = * @arg @ref LL_TIM_CHANNEL_CH6 * @retval none */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ @@ -182,6 +183,13 @@ static const uint8_t SHIFT_TAB_OISx[] = ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U) +#else +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U : 6U) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E*/ /** @brief Calculate the deadtime sampling period(in ps). * @param __TIMCLK__ timer input clock frequency (in Hz). @@ -515,6 +523,7 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +#if defined(TIM_BDTR_BK2E) uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE @@ -552,6 +561,7 @@ typedef struct @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +#endif /* TIM_BDTR_BK2E */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE @@ -582,12 +592,18 @@ typedef struct #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#if defined(TIM_CCER_CC5E) #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#endif /* TIM_CCER_CC6E */ #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#if defined(TIM_SR_B2IF) #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#endif /* TIM_SR_B2IF */ #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ @@ -610,6 +626,7 @@ typedef struct /** * @} */ +#if defined(TIM_BDTR_BK2E) /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable * @{ @@ -619,6 +636,7 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2E */ /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable * @{ @@ -734,13 +752,23 @@ typedef struct #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#if defined(TIM_CCER_CC2NE) #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#endif /* TIM_CCER_CC2NE */ #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#if defined(TIM_CCER_CC3NE) #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#endif /* TIM_CCER_CC3NE */ #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ -#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#if defined(TIM_CCER_CC4NE) +#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#endif /* TIM_CCER_CC4NE */ +#if defined(TIM_CCER_CC5E) #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +#endif /* TIM_CCER_CC6E */ /** * @} */ @@ -806,6 +834,7 @@ typedef struct * @} */ +#if defined(TIM_CCR5_CCR5) /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 * @{ */ @@ -816,6 +845,7 @@ typedef struct /** * @} */ +#endif /* TIM_CCR5_CCR5 */ /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection * @{ @@ -913,6 +943,7 @@ typedef struct * @} */ +#if defined(TIM_CR2_MMS2) /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 * @{ */ @@ -935,6 +966,7 @@ typedef struct /** * @} */ +#endif /* TIM_CR2_MMS2 */ /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode * @{ @@ -962,17 +994,21 @@ typedef struct /** @defgroup TIM_LL_EC_TS Trigger Selection * @{ */ +#if defined(TIM1) #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ +#endif /* TIM1 */ +#if defined(TIM3) #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ +#endif /* TIM3 */ #if defined(TIM4) #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ #endif /* TIM4 */ #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */ #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */ -#if defined(USB_OTG_HS) +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */ -#endif /* USB_OTG_HS */ +#endif /* USB_OTG_HS || USB_DRD_FS */ #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ @@ -1024,6 +1060,7 @@ typedef struct * @} */ +#if defined(TIM1) /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1 * @{ */ @@ -1039,6 +1076,7 @@ typedef struct /** * @} */ +#endif /* TIM1 */ /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2 * @{ @@ -1049,15 +1087,23 @@ typedef struct #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #endif /* COMP1 && COMP2 */ #define LL_TIM_TIM2_ETRSOURCE_HSI TIM_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */ +#if defined(TIM3) #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ +#endif /* TIM3 */ #if defined(TIM4) #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ #endif /* TIM4 */ #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ +#if defined(TIM2_ETR_ADC4_SUPPORT) +#define LL_TIM_TIM2_ETRSOURCE_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 1 */ +#define LL_TIM_TIM2_ETRSOURCE_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 2 */ +#define LL_TIM_TIM2_ETRSOURCE_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< ADC4 analog watchdog 3 */ +#endif /* TIM2_ETR_ADC4_SUPPORT */ /** * @} */ +#if defined(TIM3) /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3 * @{ */ @@ -1077,8 +1123,9 @@ typedef struct /** * @} */ -#if defined(TIM4) +#endif /* TIM3 */ +#if defined(TIM4) /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4 * @{ */ @@ -1126,6 +1173,7 @@ typedef struct * @} */ +#if defined(TIM_BDTR_BK2P) /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY * @{ */ @@ -1134,7 +1182,9 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2P */ +#if defined(TIM_BDTR_BK2F) /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER * @{ */ @@ -1157,6 +1207,7 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2F */ /** @defgroup TIM_LL_EC_OSSI OSSI * @{ @@ -1180,7 +1231,9 @@ typedef struct * @{ */ #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ +#if defined(TIM_BDTR_BK2E) #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ +#endif /* TIM_BDTR_BK2E */ /** * @} */ @@ -1215,6 +1268,7 @@ typedef struct * @} */ +#if defined(TIM_BDTR_BK2BID) /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE * @{ */ @@ -1223,12 +1277,15 @@ typedef struct /** * @} */ +#endif /* TIM_BDTR_BK2BID */ /** Legacy definitions for compatibility purpose @cond 0 */ #define LL_TIM_ReArmBRK(_PARAM_) +#if defined(TIM_BDTR_BK2E) #define LL_TIM_ReArmBRK2(_PARAM_) +#endif /* TIM_BDTR_BK2E */ /** @endcond */ @@ -1313,6 +1370,7 @@ typedef struct /** * @} */ +#if defined(TIM1) /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap * @{ */ @@ -1324,6 +1382,7 @@ typedef struct /** * @} */ +#endif /* TIM1 */ /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap * @{ @@ -1361,6 +1420,7 @@ typedef struct * @} */ +#if defined(TIM3) /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap * @{ */ @@ -1384,6 +1444,7 @@ typedef struct /** * @} */ +#endif /* TIM3 */ #if defined(TIM4) /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 External Input Ch1 Remap @@ -1409,8 +1470,8 @@ typedef struct /** * @} */ - #endif /* TIM4 */ + /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap * @{ */ @@ -1443,8 +1504,10 @@ typedef struct * @{ */ #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */ +#if defined(COMP1) && defined(COMP2) #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */ #define LL_TIM_OCREF_CLR_INT_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */ +#endif /* COMP1 && COMP2 */ /** * @} */ @@ -2954,6 +3017,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare WRITE_REG(TIMx->CCR4, CompareValue); } +#if defined(TIM_CCR5_CCR5) /** * @brief Set compare value for output channel 5 (TIMx_CCR5). * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not @@ -2969,6 +3033,8 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t Compare MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); } +#endif /* TIM_CCR5_CCR5 */ +#if defined(TIM_CCR6_CCR6) /** * @brief Set compare value for output channel 6 (TIMx_CCR6). * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not @@ -2984,6 +3050,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare WRITE_REG(TIMx->CCR6, CompareValue); } +#endif /* TIM_CCR6_CCR6 */ /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. @@ -3052,6 +3119,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) return (uint32_t)(READ_REG(TIMx->CCR4)); } +#if defined(TIM_CCR5_CCR5) /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not @@ -3066,6 +3134,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } +#endif /* TIM_CCR5_CCR5 */ +#if defined(TIM_CCR6_CCR6) /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not @@ -3080,6 +3150,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) return (uint32_t)(READ_REG(TIMx->CCR6)); } +#endif /* TIM_CCR6_CCR6 */ +#if defined(TIM_CCR5_CCR5) /** * @brief Select on which reference signal the OC5REF is combined to. * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check @@ -3100,6 +3172,7 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); } +#endif /* TIM_CCR5_CCR5 */ /** * @brief Set the pulse on compare pulse width prescaler. * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check @@ -3690,6 +3763,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); } +#if defined(TIM_CR2_MMS2) /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check @@ -3720,6 +3794,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); } +#endif /* TIM_CR2_MMS2 */ /** * @brief Set the synchronization mode of a slave timer. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not @@ -3747,21 +3822,19 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance * @param TriggerInput This parameter can be one of the following values: - * @arg @ref LL_TIM_TS_ITR0 - * @arg @ref LL_TIM_TS_ITR1 - * @arg @ref LL_TIM_TS_ITR2 -#if defined(TIM4) - * @arg @ref LL_TIM_TS_ITR3 -#endif + * @arg @ref LL_TIM_TS_ITR0 (*) + * @arg @ref LL_TIM_TS_ITR1 (*) + * @arg @ref LL_TIM_TS_ITR2 (*) + * @arg @ref LL_TIM_TS_ITR3 (*) * @arg @ref LL_TIM_TS_ITR7 * @arg @ref LL_TIM_TS_ITR8 -#if defined(USB_OTG_HS) - * @arg @ref LL_TIM_TS_ITR11 -#endif + * @arg @ref LL_TIM_TS_ITR11 (*) * @arg @ref LL_TIM_TS_TI1F_ED * @arg @ref LL_TIM_TS_TI1FP1 * @arg @ref LL_TIM_TS_TI2FP2 * @arg @ref LL_TIM_TS_ETRF + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) @@ -3857,11 +3930,11 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @param TIMx Timer instance * @param ETRSource This parameter can be one of the following values: * - * For TIM1, the parameter is one of the following values: + * For TIM1, the parameter is one of the following values: (**) * * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 @@ -3870,31 +3943,29 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * For TIM2, the parameter is one of the following values: * * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI - * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR -#if defined(TIM4) - * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR -#endif + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ADC4_AWD1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ADC4_AWD2 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_ADC4_AWD3 (*) * - * For TIM3, the parameter is one of the following values: + * For TIM3, the parameter is one of the following values: (**) * * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) - * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR -#if defined(TIM4) - * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR -#endif + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*) * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 * -#if defined(TIM4) - * For TIM4, the parameter is one of the following values: + * For TIM4, the parameter is one of the following values: (**) * * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1 @@ -3902,8 +3973,8 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u * @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR * -#endif * (*) Value not defined in all devices. \n + * (**) Timer instance not available on all devices \n * @retval None */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) @@ -4077,6 +4148,7 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } +#if defined(TIM_BDTR_BK2E) /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -4166,6 +4238,7 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } +#endif /* TIM_BDTR_BK2E */ /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -4281,11 +4354,13 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 (*) * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) @@ -4307,11 +4382,13 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 (*) * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) @@ -4333,14 +4410,16 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t * @param TIMx Timer instance * @param BreakInput This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 (*) * @param Source This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 - * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*) + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*) * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BKIN_POLARITY_LOW * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * + * (*) Value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, @@ -4786,7 +4865,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * * Below description summarizes "Timer Instance" and "Remap" param combinations: * - * TIM1: one of the following values: + * TIM1: one of the following values: (**) * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*) * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*) @@ -4802,7 +4881,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output (*) * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output (*) * - * TIM3: one of the following values: + * TIM3: one of the following values: (**) * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*) * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*) @@ -4810,8 +4889,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*) * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*) * -#if defined(TIM4) - * TIM4: one of the following values: + * TIM4: one of the following values: (**) * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO * @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output * @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output @@ -4819,7 +4897,6 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM4_TI2_RMP_COMP1: TIM4 TI2 is connected to COMP1 output * @arg LL_TIM_TIM4_TI2_RMP_COMP2: TIM4 TI2 is connected to COMP2 output * -#endif * TIM16: one of the following values: * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO @@ -4839,7 +4916,7 @@ __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256 * * (*) Value not defined in all devices. \n - + * (**) Timer instance not available on all devices. \n * * @retval None */ @@ -5029,6 +5106,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } +#if defined (TIM_SR_CC5IF) /** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 @@ -5051,6 +5129,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } +#endif /* TIM_SR_CC5IF */ +#if defined (TIM_SR_CC6IF) /** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 @@ -5073,6 +5153,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } +#endif /* TIM_SR_CC6IF */ /** * @brief Clear the commutation interrupt flag (COMIF). * @rmtoll SR COMIF LL_TIM_ClearFlag_COM @@ -5139,6 +5220,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } +#if defined(TIM_SR_B2IF) /** * @brief Clear the break 2 interrupt flag (B2IF). * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 @@ -5161,6 +5243,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } +#endif /* TIM_SR_B2IF */ /** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR @@ -6138,6 +6221,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->EGR, TIM_EGR_BG); } +#if defined(TIM_EGR_B2G) /** * @brief Generate break 2 event. * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 @@ -6149,6 +6233,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->EGR, TIM_EGR_B2G); } +#endif /* TIM_EGR_B2G */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_usb.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_usb.h index 6dde2399d..34385bb1e 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_usb.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_usb.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wbaxx_hal_def.h" -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /** @addtogroup STM32WBAxx_HAL_Driver * @{ */ @@ -56,6 +56,7 @@ typedef enum USB_DRD_MODE = 2 } USB_ModeTypeDef; +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief URB States definition */ @@ -66,7 +67,8 @@ typedef enum URB_NOTREADY, URB_NYET, URB_ERROR, - URB_STALL + URB_STALL, + URB_NAK_WAIT } USB_URBStateTypeDef; /** @@ -85,6 +87,7 @@ typedef enum HC_BBLERR, HC_DATATGLERR } USB_HCStateTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** @@ -122,12 +125,19 @@ typedef struct uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ +#if defined (USB_OTG_HS) uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ +#endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ + uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ +#endif /* defined (USB_DRD_FS) */ } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -139,8 +149,10 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_OTG_HS) uint8_t is_iso_incomplete; /*!< Endpoint isoc condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_OTG_HS) */ uint8_t type; /*!< Endpoint type This parameter can be any value of @ref USB_LL_EP_Type */ @@ -148,6 +160,20 @@ typedef struct uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#if defined (USB_DRD_FS) + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ + uint32_t maxpacket; /*!< Endpoint Max packet size This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -157,6 +183,7 @@ typedef struct uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +#if defined (USB_OTG_HS) uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ @@ -166,31 +193,49 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ uint32_t xfer_size; /*!< requested transfer size */ +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) + uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ +#endif /* defined (USB_DRD_FS) */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ +#if defined (HAL_HCD_MODULE_ENABLED) typedef struct { uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - - uint8_t ch_num; /*!< Host channel number. +#if defined (USB_DRD_FS) + uint8_t phy_ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ep_num; /*!< Endpoint number. +#else + uint8_t ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ +#endif /* defined (USB_DRD_FS) */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ch_dir; /*!< channel direction + This parameter store the physical channel direction IN/OUT/BIDIR */ uint8_t speed; /*!< USB Host Channel speed. This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ +#if defined (USB_OTG_HS) uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ +#endif /* defined (USB_OTG_HS) */ uint8_t hub_port_nbr; /*!< USB HUB port number */ uint8_t hub_addr; /*!< USB HUB address */ @@ -206,9 +251,14 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ +#if defined (USB_OTG_HS) uint32_t XferSize; /*!< OTG Channel transfer size. */ +#endif /* defined (USB_OTG_HS) */ uint32_t xfer_len; /*!< Current transfer length. */ +#if defined (USB_DRD_FS) + uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ +#endif /* defined (USB_DRD_FS) */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ @@ -217,11 +267,28 @@ typedef struct uint8_t toggle_out; /*!< OUT transfer current toggle flag This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - +#if defined (USB_OTG_HS) uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + + uint32_t NakCnt; /*!< Host channel NAK count. */ +#endif /* defined (USB_OTG_HS) */ uint32_t ErrCnt; /*!< Host channel error count. */ - uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + +#if defined (USB_DRD_FS) + uint16_t pmaadress; /*!< PMA Address + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr0; /*!< PMA Address0 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint16_t pmaaddr1; /*!< PMA Address1 + This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ + + uint8_t doublebuffer; /*!< Double buffer enable + This parameter can be 0 or 1 */ +#endif /* defined (USB_DRD_FS) */ USB_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_URBStateTypeDef */ @@ -229,13 +296,37 @@ typedef struct USB_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ +#if defined (USB_OTG_HS) typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) typedef USB_EPTypeDef USB_OTG_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ +#endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; +typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) +typedef USB_EPTypeDef USB_DRD_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) +typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; +typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ +#endif /* defined (USB_DRD_FS) */ /* Exported constants --------------------------------------------------------*/ @@ -471,6 +562,573 @@ typedef USB_HCTypeDef USB_OTG_HCTypeDef; #define EP_ADDR_MSK 0xFU #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +#define USB_CHEP_ERRRX USB_CHEP_ERR_RX +#define USB_EP_ERRRX USB_CHEP_ERR_RX +#define USB_CH_ERRRX USB_CHEP_ERR_RX + +#define USB_CHEP_ERRTX USB_CHEP_ERR_TX +#define USB_EP_ERRTX USB_CHEP_ERR_TX +#define USB_CH_ERRTX USB_CHEP_ERR_TX + +#define USB_CHEP_DTOG_RX USB_CHEP_DTOGRX +#define USB_EP_DTOG_RX USB_CHEP_DTOGRX +#define USB_CH_DTOG_RX USB_CHEP_DTOGRX + +#define USB_CHEP_DTOG_TX USB_CHEP_DTOGTX +#define USB_EP_DTOG_TX USB_CHEP_DTOGTX +#define USB_CH_DTOG_TX USB_CHEP_DTOGTX + +#define USB_CHEP_TX_STTX USB_CHEP_STATTX +#define USB_EP_TX_STTX USB_CHEP_STATTX +#define USB_CH_TX_STTX USB_CHEP_STATTX + +#define USB_CHEP_RX_STRX USB_CHEP_STATRX +#define USB_EP_RX_STRX USB_CHEP_STATRX +#define USB_CH_RX_STRX USB_CHEP_STATRX + +#define USB_CHEP_KIND USB_CHEP_EPKIND +#define USB_CHEP_LSEP USB_CHEP_LS_EP +#define USB_CHEP_ADDR USB_CHEP_EA + +#define USB_ISTR_RESET USB_ISTR_RST_DCON +#define USB_ISTR_DCON USB_ISTR_RST_DCON +#define USB_ISTR_LS_DCONN USB_ISTR_LS_DCON + +#define USB_CNTR_RESETM USB_CNTR_RST_DCONM +#define USB_CNTR_DCON USB_CNTR_RST_DCONM + +#define USB_BCDR_DPPD USB_BCDR_DPPU_DPD +#define USB_BCDR_DPPU USB_BCDR_DPPU_DPD +#define USB_LPMCSR_LMPEN USB_LPMCSR_LPMEN + +#define EP_ADDR_MSK 0x7U + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ + +#define USB_EMBEDDED_PHY 2U + +/*!< USB Speed */ +#define USB_DRD_SPEED_FS 1U +#define USB_DRD_SPEED_LS 2U +#define USB_DRD_SPEED_LSFS 3U + +/*!< Channel Direction */ +#define CH_IN_DIR 1U +#define CH_OUT_DIR 0U + +/*!< Number of used channels in the Application */ +#ifndef USB_DRD_USED_CHANNELS +#define USB_DRD_USED_CHANNELS 8U +#endif /* USB_DRD_USED_CHANNELS */ + +/** + * used for USB_HC_DoubleBuffer API + */ +#define USB_DRD_BULK_DBUFF_ENBALE 1U +#define USB_DRD_BULK_DBUFF_DISABLE 2U +#define USB_DRD_ISOC_DBUFF_ENBALE 3U +#define USB_DRD_ISOC_DBUFF_DISABLE 4U + +/* First available address in PMA */ +#define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) +#define PMA_END_ADDR USB_DRD_PMA_SIZE + +/* Exported macro ------------------------------------------------------------*/ +/** + * @} + */ +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 26) +#define USB_CNTRX_BLSIZE (0x1U << 31) + + +/*Set Channel/Endpoint to the USB Register */ +#define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ + (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) + +/*Get Channel/Endpoint from the USB Register */ +#define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) + + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpChNum, bDir + * @retval None + */ +#define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) + + +/** + * @brief Set the Setup bit in the corresponding channel, when a Setup + transaction is needed. + * @param USBx USB device. + * @param bEpChNum + * @retval None + */ +#define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ + \ + /* Set Setup bit */ \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ + } while(0) + + +/** + * @brief Clears bit ERR_RX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ + _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ + (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ + \ + USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ + } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ + + +/** + * @brief Clears bit ERR_TX in the Channel register + * @param USBx USB peripheral instance register address. + * @param bChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ + _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ + (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ + \ + USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ + } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ + + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_TX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_TX_DTOG2; \ + } \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ + + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_RX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ + { \ + _wRegVal ^= USB_CHEP_RX_DTOG2; \ + } \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ + + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval status + */ +#define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ + ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) + +#define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ + ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) + + +/** + * @brief set EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ + } while(0) /* USB_DRD_SET_CHEP_KIND */ + + +/** + * @brief clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ + + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ + } while(0) /* USB_CLEAR_RX_CHEP_CTR */ + +#define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ + } while(0) /* USB_CLEAR_TX_CHEP_CTR */ + + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_RX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wEPVal; \ + \ + _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ + } while(0) /* USB_DRD_RX_DTOG */ + +#define USB_DRD_TX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wEPVal; \ + \ + _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ + \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ + } while(0) /* USB_TX_DTOG */ + + +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ + \ + if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ + { \ + USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) /* USB_DRD_CLEAR_RX_DTOG */ + +#define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ + do { \ + uint32_t _wRegVal; \ + \ + _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ + \ + if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ + { \ + USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ + } \ + } while(0) /* USB_DRD_CLEAR_TX_DTOG */ + + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ + do { \ + uint32_t _wRegVal; \ + \ + /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ + _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ + \ + /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ + USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ + } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ + + +/* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ +/* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor +* The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) +* TXBD [Reserve |Countx| Address_Tx] +* RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ + +/* Set TX Buffer Descriptor Address Field */ +#define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ + do { \ + /* Reset old Address */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ + \ + /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ + } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ + +/* Set RX Buffer Descriptor Address Field */ +#define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ + do { \ + /* Reset old Address */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ + \ + /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ + } while(0) /* USB_SET_CHEP_RX_ADDRESS */ + + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ + /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ + (wNBlocks) =((uint32_t)(wCount) >> 5U); \ + if (((uint32_t)(wCount) % 32U) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + \ + (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ + } while(0) /* USB_DRD_CALC_BLK32 */ + +#define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ + /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ + (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ + } while(0) /* USB_DRD_CALC_BLK2 */ + +#define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ + do { \ + uint32_t wNBlocks; \ + \ + (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ + \ + if ((wCount) == 0U) \ + { \ + (pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ + + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ + do { \ + /* Reset old TX_Count value */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ + \ + /* Set the wCount in the dedicated EP_TXBuffer */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ + } while(0) + +#define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ + USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) + +#define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ + USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval Counter value + */ +#define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) +#define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) + +#define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT +#define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT + +#define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT +#define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ + USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) + +#define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ + USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) + + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ + do { \ + USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ + USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ + } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ + + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ + +#define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ + (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ + } \ + } \ + } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ + +#define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ + do { \ + USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ + USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ + } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpChNum Endpoint Number. + * @retval None + */ +#define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) +#define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -504,18 +1162,23 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); + HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); @@ -531,13 +1194,17 @@ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, u uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); + +#if defined (HAL_HCD_MODULE_ENABLED) HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); @@ -546,12 +1213,65 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); + +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); + +HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); + +#if defined (HAL_HCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); +HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); +HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); + +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); + +void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -567,11 +1287,10 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); /** * @} */ -#endif /* defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #ifdef __cplusplus } #endif /* __cplusplus */ - #endif /* STM32WBAxx_LL_USB_H */ diff --git a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h index 90867a3ab..173ebd793 100644 --- a/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h +++ b/stm32cube/stm32wbaxx/drivers/include/stm32wbaxx_ll_utils.h @@ -163,7 +163,7 @@ typedef struct #define LL_UTILS_PACKAGETYPE_WLCSP41_SMPS 0x00000009U /*!< WLCSP41 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS 0x0000000AU /*!< UFQFPN48 with internal SMPS package type */ #define LL_UTILS_PACKAGETYPE_UFBGA59 0x0000000BU /*!< UFBGA59 package type */ -#elif defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#elif defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) #define LL_UTILS_PACKAGETYPE_UFQFPN48_USB 0x00000003U /*!< UFQFPN48 with USB package type */ #define LL_UTILS_PACKAGETYPE_WLCSP88_USB 0x00000005U /*!< WLSCP88 with USB package type */ #define LL_UTILS_PACKAGETYPE_UFBGA121_USB 0x00000007U /*!< UFBGA121 with USB package type */ @@ -239,7 +239,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP41_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_SMPS * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA59 -#elif defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#elif defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48_USB * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP88_USB * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA121_USB diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c index 5073cf0fd..c0319d1b2 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal.c @@ -265,6 +265,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); break; +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) + /* HSI_DIV4 selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_HSI_DIV4: + /* Calculate tick value */ + ticknumber = (HSI_VALUE / (4000UL / (uint32_t)uwTickFreq)); + break; +#endif + default: /* Nothing to do */ break; @@ -876,7 +884,7 @@ void HAL_SYSCFG_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32 offset = ((Selection == SYSCFG_IO_CELL) ? 0U : 8U); - MODIFY_REG(SYSCFG->CCCR, (0xFFU << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U)))); + MODIFY_REG(SYSCFG->CCCR, (0xFFUL << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U)))); } MODIFY_REG(SYSCFG->CCCSR, (Selection << 1U), (Code << (POSITION_VAL(Selection) + 1U))); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c index c8654c2d8..454af3d32 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cortex.c @@ -405,6 +405,9 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HSI_DIV4: HSI clock divided by 4 selected as SysTick clock source. (*) + * + * (*) value not defined in all devices. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) @@ -432,6 +435,13 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1); break; +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) + /* Select HSI_DIV4 as Systick clock source */ + case SYSTICK_CLKSOURCE_HSI_DIV4: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (RCC_CCIPR1_SYSTICKSEL_1 | RCC_CCIPR1_SYSTICKSEL_0)); + break; +#endif default: /* Nothing to do */ break; @@ -445,6 +455,9 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HSI_DIV4: HSI clock divided by 4 selected as SysTick clock source. (*) + * + * (*) value not defined in all devices. */ uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) { @@ -469,6 +482,12 @@ uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) systick_source = SYSTICK_CLKSOURCE_LSE; break; +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) + case RCC_SYSTICKCLKSOURCE_HSI_DIV4: + systick_source = SYSTICK_CLKSOURCE_HSI_DIV4; + break; +#endif + default: /* RCC_SYSTICKCLKSOURCE_HCLK_DIV8 */ systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; break; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp.c index 76c12ba59..295443bf0 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp.c @@ -363,6 +363,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -641,12 +642,26 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; #if !defined(SAES) + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #else if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -661,10 +676,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1219,7 +1247,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1391,16 +1423,37 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, } #if !defined(SAES) + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); #else if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1492,10 +1545,26 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { +#if defined(AES_CR_KMOD) + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); +#else + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* AES_CR_KMOD*/ + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1602,7 +1671,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1631,6 +1706,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1705,7 +1781,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1733,6 +1815,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1792,7 +1875,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1902,6 +1991,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1958,7 +2048,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1986,6 +2082,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -2029,26 +2126,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->IER; + uint32_t itflagsr = hcryp->Instance->SR; + uint32_t itflagisr = hcryp->Instance->ISR; + /* Check if Read or write error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + if ((itsource & CRYP_IT_RWEIE) != 0U) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + if ((itflagsr & CRYP_FLAG_WRERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + if ((itflagsr & CRYP_FLAG_RDERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } } /* Check if Key error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + if ((itsource & CRYP_IT_KEIE) != 0U) { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + if ((itflagisr & CRYP_FLAG_KEIF) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); @@ -2057,9 +2158,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + if ((itflagisr & CRYP_FLAG_CCF) != 0U) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) != 0U) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -2505,7 +2606,9 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ { /* key preparation for decryption, operating mode 2*/ +#if defined(AES_CR_KMOD) MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); +#endif /* AES_CR_KMOD*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); /* Set the Key */ @@ -2626,7 +2729,9 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ { /* key preparation for decryption, operating mode 2*/ +#if defined(AES_CR_KMOD) MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); +#endif /* AES_CR_KMOD*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); /* Set the Key */ @@ -2741,7 +2846,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_ISR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -2979,7 +3084,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_ISR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -3267,7 +3372,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t mode; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -3589,7 +3694,7 @@ static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t i; /* Write the input block in the IN FIFO */ @@ -3642,7 +3747,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t i; if (hcryp->State == HAL_CRYP_STATE_BUSY) @@ -3741,7 +3846,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3809,13 +3938,12 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = ((uint32_t)hcryp->Size / 4U); uint32_t npblb; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t index; uint32_t lastwordsize; uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -4585,7 +4713,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ @@ -5346,7 +5474,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; @@ -5490,7 +5618,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr uint32_t index; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0}; /* Temporary CrypOutBuff */ uint32_t count; uint32_t reg; @@ -6190,11 +6318,11 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | - AES_CR_GCMPH_1 | 0x0)) + AES_CR_GCMPH_1 | 0x0UL)) { /* Wait for BUSY flag to be cleared */ @@ -6376,7 +6504,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)) + if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) { /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp_ex.c index 184ae6b09..65cf02730 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_cryp_ex.c @@ -39,7 +39,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -69,6 +69,7 @@ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t T static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyGeneration(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #endif /* defined(SAES) */ +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions * @{ @@ -128,6 +129,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -146,19 +154,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -507,7 +512,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -571,7 +582,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Decryption operating mode(Mode 3)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -877,6 +894,31 @@ static HAL_StatusTypeDef CRYPEx_KeyGeneration(CRYP_HandleTypeDef *hcryp, uint32_ return HAL_OK; } #endif /* defined(SAES)*/ +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_exti.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_exti.c index 7dd51b1fc..7d4a4ecff 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_exti.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_exti.c @@ -136,7 +136,7 @@ * @param pExtiConfig Pointer on EXTI configuration to be set. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, const EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; @@ -208,7 +208,11 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; +#if defined (EXTI_EXTICR1_EXTI0) regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); +#else /* defined (EXTI_EXTICR1_EXTI0) */ + regval &= ~(EXTI_EXTICR2_EXTI4 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); +#endif /* defined (EXTI_EXTICR1_EXTI0) */ regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; } @@ -258,7 +262,7 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { const __IO uint32_t *regaddr; uint32_t regval; @@ -410,7 +414,11 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; +#if defined (EXTI_EXTICR1_EXTI0) regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); +#else /* defined (EXTI_EXTICR1_EXTI0) */ + regval &= ~(EXTI_EXTICR2_EXTI4 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); +#endif /* defined (EXTI_EXTICR1_EXTI0) */ EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; } } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c index b1eabb2e4..a47b7e164 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash.c @@ -703,7 +703,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset. Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t timeout = HAL_GetTick(); uint32_t error; __IO uint32_t *reg_sr; @@ -718,7 +718,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if (Timeout != HAL_MAX_DELAY) { - if (HAL_GetTick() >= timeout) + if ((HAL_GetTick() - timeout) >= Timeout) { return HAL_TIMEOUT; } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c index a4869f467..ccd2e258e 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_flash_ex.c @@ -187,7 +187,7 @@ static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uin * * @retval HAL Status */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status; uint32_t page_index; @@ -525,7 +525,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * * @retval HAL Status */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(const FLASH_BBAttributesTypeDef *pBBAttributes) { HAL_StatusTypeDef status; uint8_t index; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c index 5485b9506..1edb95217 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gpio.c @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) } } -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) /** * @brief Enable speed optimization for several pin of dedicated port. * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding @@ -552,7 +552,7 @@ void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) CLEAR_BIT(GPIOx->HSLVR, GPIO_Pin); } -#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) */ +#endif /* defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) */ /** * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c index bf48c79a2..187fb4613 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_gtzc.c @@ -6,8 +6,9 @@ * This file provides firmware functions to manage the following * functionalities of GTZC peripheral: * + TZSC Initialization and Configuration functions + * + TZSC-MPCWM Initialization and Configuration functions * + MPCBB Initialization and Configuration functions - * + TZSC and MPCBB Lock functions + * + TZSC, TZSC-MPCWM and MPCBB Lock functions * + TZIC Initialization and Configuration functions * ****************************************************************************** @@ -29,7 +30,8 @@ (+) Global TrustZone Controller (GTZC) composed of three sub-blocks: (++) TZSC: TrustZone security controller This sub-block defines the secure/privileged state of master and slave - peripherals. + peripherals. It also controls the secure/privileged state of subregions + for the watermark memory peripheral controller (MPCWM). (++) MPCBB: Block-Based memory protection controller This sub-block defines the secure/privileged state of all blocks (512-byte pages) of the associated SRAM. @@ -63,6 +65,9 @@ (#) Configure or get back securable peripherals attributes using HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes() + (#) Configure or get back MPCWM memories attributes using + HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes() + (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() / HAL_GTZC_TZSC_GetLock() @@ -111,6 +116,7 @@ * @{ */ + /* Definitions for GTZC TZSC & TZIC ALL register values */ /* TZSC1 / TZIC1 instances */ #if defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined(STM32WBA5Mxx) @@ -123,7 +129,7 @@ #define TZSC1_SECCFGR2_ALL (0x018F00EBUL) #define TZSC1_SECCFGR3_ALL (0x01C17858UL) #define TZIC1_IER4_ALL (0xC3C0EF87UL) -#elif defined (STM32WBA62xx) || defined (STM32WBA65xx) +#elif defined (STM32WBA62xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx) #define TZSC1_SECCFGR1_ALL (0x000367C7UL) #define TZSC1_SECCFGR2_ALL (0x038F00EBUL) #define TZSC1_SECCFGR3_ALL (0x01C17C58UL) @@ -470,6 +476,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * @} */ + #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions @@ -623,7 +630,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, MPCBB_ConfigTypeDef *pMPCBB_desc) { - GTZC_MPCBB_TypeDef *mpcbb_ptr; + const GTZC_MPCBB_TypeDef *mpcbb_ptr; uint32_t mem_size; uint32_t size_in_superblocks; uint32_t i; @@ -847,7 +854,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, uint32_t NbBlocks, uint32_t *pMemAttributes) { - GTZC_MPCBB_TypeDef *mpcbb_ptr; + const GTZC_MPCBB_TypeDef *mpcbb_ptr; uint32_t base_address; uint32_t end_address; uint32_t block_start; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c index 802757f48..8ee08b2ae 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hash.c @@ -751,8 +751,10 @@ HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash) /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */ remainingwords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \ & DMA_CBR1_BNDT) / 4U; +#if defined(GPDMA1) remainingwords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \ & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos; +#endif /* GPDMA1 */ if (remainingwords <= nbbytePartialHash) { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hcd.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hcd.c index 897eff1bd..9528b4cbf 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hcd.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_hcd.c @@ -39,6 +39,7 @@ (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_CLK_ENABLE(); (##) Initialize the related GPIO clocks (##) Configure HCD pin-out (##) Configure HCD NVIC interrupt @@ -49,6 +50,9 @@ (#)Enable HCD transmission and reception: (##) HAL_HCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -1227,6 +1231,24 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu return HAL_OK; } + + +/** @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} /** * @} */ @@ -1350,6 +1372,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + hhcd->hc[chnum].NakCnt = 0U; + if (hhcd->hc[chnum].do_ssplit == 1U) { hhcd->hc[chnum].do_csplit = 1U; @@ -1362,6 +1386,14 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + tmpreg = USBx_HC(chnum)->HCCHAR; + + if ((tmpreg & USB_OTG_HCCHAR_CHDIS) != 0U) + { + /* Halt received while channel disable still in progress */ + return; + } + if (hhcd->hc[chnum].state == HC_XFRC) { hhcd->hc[chnum].state = HC_HALTED; @@ -1376,19 +1408,38 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (hhcd->hc[chnum].state == HC_DATATGLERR)) { hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].ErrCnt > 2U) + + if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].do_ssplit == 1U) + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[chnum].do_csplit = 0U; - hhcd->hc[chnum].ep_ss_schedule = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].urb_state = URB_ERROR; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } } else { @@ -1479,11 +1530,24 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; +#if defined (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE) && (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE == 1) + hhcd->hc[chnum].NakCnt++; + + if (hhcd->hc[chnum].NakCnt >= HAL_HCD_CHANNEL_NAK_COUNT) + { + hhcd->hc[chnum].state = HC_IDLE; + hhcd->hc[chnum].urb_state = URB_NAK_WAIT; + hhcd->hc[chnum].NakCnt = 0U; + } + else +#endif /* defined (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE) && (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE == 1) */ + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } } else if (hhcd->hc[chnum].state == HC_BBLERR) @@ -1688,6 +1752,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); @@ -1936,6 +2006,2837 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) */ #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function ----------------------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd); +static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef const *hhcd, uint8_t phy_chnum, uint8_t dir); +static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef const *hhcd, uint8_t ch_num); +static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, uint8_t ep_type); + +#if (USE_USB_DOUBLE_BUFFER == 1U) +static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue); +static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + +static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps); +static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps); +static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== +##### Initialization and de-initialization functions ##### +=============================================================================== +[..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + hhcd->State = HAL_HCD_STATE_BUSY; + + /* Disable the Interrupts */ + (void)__HAL_HCD_DISABLE(hhcd); + + /* Dma not supported, force to zero */ + hhcd->Init.dma_enable = 0U; + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode */ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + hhcd->State = HAL_HCD_STATE_READY; + + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* Init PMA Address */ + (void)HAL_HCD_PMAReset(hhcd); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH High speed mode, + * HCD_DEVICE_SPEED_FULL Full speed mode, + * HCD_DEVICE_SPEED_LOW Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * USBH_EP_CONTROL Control type, + * USBH_EP_ISO Isochronous type, + * USBH_EP_BULK Bulk type, + * USBH_EP_INTERRUPT Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef status; + uint8_t used_channel; + uint8_t ep0_virtual_channel; + + __HAL_LOCK(hhcd); + + if (ch_num > 16U) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; + hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; + hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[0U].pmaaddr1; + + hhcd->phy_chin_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + hhcd->phy_chout_state[0U] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + + /* Check if the logical channel are already allocated */ + used_channel = HAL_HCD_Check_usedChannel(hhcd, ch_num); + + /* Check if the channel is not already opened */ + if (used_channel == 0U) + { + /* Allocate New Physical channel */ + hhcd->hc[ch_num & 0xFU].phy_ch_num = HAL_HCD_Get_FreePhyChannel(hhcd, ch_num, epnum, ep_type); + + /* No free Channel available, return error */ + if (hhcd->hc[ch_num & 0xFU].phy_ch_num == HCD_FREE_CH_NOT_FOUND) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + } + /* Channel already opened */ + else + { + /* Get Physical Channel number */ + hhcd->hc[ch_num & 0xFU].phy_ch_num = (used_channel & 0xF0U) >> 4U; + } + + if ((epnum & 0x80U) != 0U) + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR; + } + else + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; + } + + hhcd->hc[ch_num & 0xFU].dev_addr = dev_address; + hhcd->hc[ch_num & 0xFU].max_packet = mps; + hhcd->hc[ch_num & 0xFU].ep_type = ep_type; + hhcd->hc[ch_num & 0xFU].ep_num = epnum & 0x7FU; + hhcd->hc[ch_num & 0xFU].speed = speed; + + /* Check if the channel is not already opened */ + if (used_channel == 0U) + { + if (((ep_type == EP_TYPE_ISOC) && (hhcd->Init.iso_singlebuffer_enable == 0U)) || + ((ep_type == EP_TYPE_BULK) && (hhcd->Init.bulk_doublebuffer_enable == 1U))) + { + /* PMA Dynamic Allocation */ + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_DBL_BUF, mps); + + if (status == HAL_ERROR) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + + /* Clear Channel DTOG_TX */ + HCD_CLEAR_TX_DTOG(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num); + + /* Clear Channel DTOG RX */ + HCD_CLEAR_RX_DTOG(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num); + + } + else + { + if (hhcd->hc[ch_num & 0xFU].ep_num != 0U) + { + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, mps); + + if (status == HAL_ERROR) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + } + else + { + if (ch_num == 0U) + { + ep0_virtual_channel = (uint8_t)(hhcd->ep0_PmaAllocState & 0xFU); + + if ((ep0_virtual_channel != 0U) && (((hhcd->ep0_PmaAllocState & 0xF0U) >> 4) == CH_IN_DIR)) + { + if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_OUT_DIR) + { + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + } + else + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + } + else + { + /* This is a dual EP0 PMA allocation */ + hhcd->ep0_PmaAllocState |= (0x1U << 12); + + /* PMA Dynamic Allocation for EP0 OUT direction */ + hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + + /* PMA Dynamic Allocation for EP0 IN direction */ + hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR; + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + } + } + else + { + if (((hhcd->ep0_PmaAllocState & 0xF00U) >> 8) == 1U) + { + ep0_virtual_channel = (uint8_t)(hhcd->ep0_PmaAllocState & 0xFU); + + if (((hhcd->ep0_PmaAllocState & 0xF0U) >> 4) == CH_IN_DIR) + { + hhcd->hc[ch_num & 0xFU].pmaaddr1 = hhcd->hc[ep0_virtual_channel & 0xFU].pmaaddr1; + } + else + { + hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[ep0_virtual_channel & 0xFU].pmaaddr0; + } + } + else + { + status = HAL_HCD_PMAlloc(hhcd, ch_num, HCD_SNG_BUF, 64U); + + if (status == HAL_ERROR) + { + __HAL_UNLOCK(hhcd); + return HAL_ERROR; + } + } + } + } + } + } + + if ((epnum & 0x80U) != 0U) + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_IN_DIR; + + if (hhcd->hc[ch_num & 0xFU].ep_num == 0U) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[ch_num & 0xFU].pmaaddr1; + } + } + else + { + hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; + + if (hhcd->hc[ch_num & 0xFU].ep_num == 0U) + { + hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[ch_num & 0xFU].pmaaddr0; + } + } + + /* Init the USB Channel CHEPRx */ + status = USB_HC_Init(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num, + epnum, dev_address, speed, ep_type, mps); + + /* check single buffer for isochronous channel */ + if (ep_type == EP_TYPE_ISOC) + { + if (hhcd->Init.iso_singlebuffer_enable == 1U) + { + (void)USB_HC_DoubleBuffer(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num, + USB_DRD_ISOC_DBUFF_DISABLE); + } + } + + /* Bulk double buffer check */ + if (ep_type == EP_TYPE_BULK) + { + if (hhcd->Init.bulk_doublebuffer_enable == 1U) + { + (void)USB_HC_DoubleBuffer(hhcd->Instance, hhcd->hc[ch_num & 0xFU].phy_ch_num, + USB_DRD_BULK_DBUFF_ENBALE); + } + } + + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief HAL_HCD_HC_Close Pipe + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + /* Stop the channel */ + (void) HAL_HCD_HC_Halt(hhcd, ch_num); + + HAL_Delay(3U); + + if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_IN_DIR) + { + /* Free Allocated Channel */ + hhcd->phy_chin_state[hhcd->hc[ch_num & 0xFU].phy_ch_num] = 0U; + } + else + { + /* Free Allocated Channel */ + hhcd->phy_chout_state[hhcd->hc[ch_num & 0xFU].phy_ch_num] = 0U; + } + + /* Reset PMA Channel_Allocation */ + (void)HAL_HCD_PMADeAlloc(hhcd, ch_num); + + return HAL_OK; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + if (hhcd->hc[ch_num & 0xFU].ch_dir == CH_IN_DIR) + { + (void)USB_HC_IN_Halt(hhcd->Instance, (uint8_t) hhcd->hc[ch_num & 0xFU].phy_ch_num); + } + else + { + (void)USB_HC_OUT_Halt(hhcd->Instance, (uint8_t) hhcd->hc[ch_num & 0xFU].phy_ch_num); + } + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + uint8_t idx; + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* Reset PMA Address */ + (void)HAL_HCD_PMAReset(hhcd); + + for (idx = 0U; idx < hhcd->Init.Host_channels; idx++) + { + hhcd->phy_chin_state[idx] = 0U; + hhcd->phy_chout_state[idx] = 0U; + } + + /* reset Ep0 Pma allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC. */ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +__weak void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_SuspendCallback could be implemented in the user file + */ + +} + +__weak void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim +=============================================================================== +##### IO operation functions ##### +=============================================================================== +[..] This subsection provides a set of functions allowing to manage the USB Host Data +Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * USBH_EP_CONTROL : Control type/ + * USBH_EP_ISO : Isochronous type/ + * USBH_EP_BULK : Bulk type/ + * USBH_EP_INTERRUPT : Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping) +{ + UNUSED(do_ping); + + if (token == 0U) + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_SETUP; + } + else + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /* send data */ + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num & 0xFU].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num & 0xFU].toggle_in == 0U) + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num & 0xFU].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num & 0xFU].toggle_in == 0U) + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num & 0xFU].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num & 0xFU].xfer_buff = pbuff; + hhcd->hc[ch_num & 0xFU].xfer_len = length; + hhcd->hc[ch_num & 0xFU].xfer_len_db = length; + hhcd->hc[ch_num & 0xFU].urb_state = URB_IDLE; + hhcd->hc[ch_num & 0xFU].xfer_count = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); +} +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + uint8_t phy_chnum; + uint8_t ch_dir; + uint32_t wIstr = USB_ReadInterrupts(hhcd->Instance); + + /* Port Change Detected (Connection/Disconnection) */ + if ((wIstr & USB_ISTR_DCON) == USB_ISTR_DCON) + { + /* Clear Flag */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_DCON); + + /* Call Port IRQHandler */ + HCD_Port_IRQHandler(hhcd); + + return; + } + + /* Correct Transaction Detected -------*/ + if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) + { + /* Get Physical channel */ + phy_chnum = (uint8_t)__HAL_HCD_GET_CHNUM(hhcd); + + /* Get channel direction */ + ch_dir = (uint8_t)__HAL_HCD_GET_CHDIR(hhcd); + + if (ch_dir == CH_OUT_DIR) + { + /* Call Channel_OUT_IRQ() */ + HCD_HC_OUT_IRQHandler(hhcd, phy_chnum); + } + else + { + /* Call Channel_IN_IRQ() */ + HCD_HC_IN_IRQHandler(hhcd, phy_chnum); + } + + return; + } + + /* Wakeup Flag Detected */ + if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) + { + if (hhcd->HostState == HCD_HCD_STATE_SUSPEND) + { + /* Set The L2Resume bit */ + hhcd->Instance->CNTR |= USB_CNTR_L2RES; + + /* Clear the wake-up flag */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_WKUP); + + /* Update the USB Software state machine */ + HAL_HCD_ResumeCallback(hhcd); + hhcd->HostState = HCD_HCD_STATE_RESUME; + } + else + { + /* Clear the wake-up flag */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_WKUP); + } + + return; + } + + /* Global Error Flag Detected */ + if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_ERR); + + return; + } + + /* PMA Overrun detected */ + if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_PMAOVR); + + return; + } + + /* Suspend Detected */ + if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) + { + /* Set HAL State to Suspend */ + hhcd->HostState = HCD_HCD_STATE_SUSPEND; + + /* Force low-power mode in the macrocell */ + hhcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_SUSP); + + /* Call suspend Callback */ + HAL_HCD_SuspendCallback(hhcd); + + return; + } + + /* Start Of Frame Detected */ + if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_ISTR_SOF); + + /* when first SOF is detected after USB_RESET is asserted */ + if (hhcd->HostState == HCD_HCD_STATE_RESETED) + { + /* HAL State */ + hhcd->HostState = HCD_HCD_STATE_RUN; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + + return; + } +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, + uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID DRD HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim +=============================================================================== +##### Peripheral Control functions ##### +=============================================================================== +[..] +This subsection provides a set of functions allowing to control the HCD data +transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __IO uint32_t count = HCD_PDWN_EXIT_CNT; + + __HAL_LOCK(hhcd); + + /* Remove PowerDown */ + hhcd->Instance->CNTR &= ~USB_CNTR_PDWN; + + /* Few cycles to ensure exit from powerdown */ + while (count > 0U) + { + count--; + } + + /* Clear Reset */ + hhcd->Instance->CNTR &= ~USB_CNTR_USBRST; + + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + /*Stop the Host IP: setting powerdown */ + (void)USB_StopHost(hhcd->Instance); + + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); + + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); + + /* reset Ep0 Pma allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + __HAL_UNLOCK(hhcd); + return HAL_OK; +} + +/** + * @brief Put the Device in suspend mode + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd) +{ + __IO uint32_t count = 0U; + + /* Set Suspend Mode */ + hhcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + /* wait for Suspend Ready */ + while ((hhcd->Instance->CNTR & USB_CNTR_SUSPRDY) == 0U) + { + if (++count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Resume host port + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd) +{ + /* Set Resume bit */ + hhcd->Instance->CNTR |= USB_CNTR_L2RES; + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + + /* Reset the USB Port by inserting an SE0 on the bus */ + (void)USB_ResetPort(hhcd->Instance); + + if (hhcd->HostState == HCD_HCD_STATE_CONNECTED) + { + hhcd->HostState = HCD_HCD_STATE_RESETED; + } + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Resme the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd) +{ + /* Set Resume bit */ + hhcd->Instance->CNTR |= USB_CNTR_L2RES; + HAL_Delay(30U); + + /* Clear Resume bit */ + hhcd->Instance->CNTR &= ~USB_CNTR_L2RES; + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim +=============================================================================== +##### Peripheral State functions ##### +=============================================================================== +[..] +This subsection permits to get in run-time the status of the peripheral +and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval speed : Device speed after Host enumeration + * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @brief Set host channel Hub Information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr) +{ + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + + return HAL_OK; +} + + +/** + * @brief Clear host channel hub information. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + + return HAL_OK; +} + +/** + * @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} + +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Handle Host Channel OUT Double Buffer Bulk requests. + * @param hhcd HCD handle + * @param ch_num Channel number This parameter can be a value from 1 to 15 + * @param phy_chnum Physical Channel number [0..7] + * @param regvalue contain Snapshot of the EPCHn register when ISR is detected + * @retval none + */ +static void HCD_HC_OUT_BulkDb(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t phy_chnum, uint32_t regvalue) +{ + uint16_t data_xfr; + uint16_t len; + + /* Send Buffer0 */ + if ((regvalue & USB_CH_DTOG_TX) != 0U) + { + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); + + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) + { + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) + { + /* manage multiple Xfer */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + + /* check if we need to free user buffer */ + if ((regvalue & USB_CH_DTOG_RX) != 0U) + { + /* Toggle SwBuff */ + HCD_CLEAR_TX_DTOG(hhcd->Instance, phy_chnum); + HCD_CLEAR_RX_DTOG(hhcd->Instance, phy_chnum); + HCD_TX_DTOG(hhcd->Instance, phy_chnum); + } + + /* hhcd->hc[ch_num&0xFU].xfer_len_db==0 ==> when all data are written in the PMA to yet transferred */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > 0U) /* Still data to fill in the buffer */ + { + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + + /* calculate len of new buffer to fill */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > hhcd->hc[ch_num & 0xFU].max_packet) + { + len = (uint16_t)hhcd->hc[ch_num & 0xFU].max_packet; + hhcd->hc[ch_num & 0xFU].xfer_len_db -= len; + } + else + { + len = (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_len_db; + hhcd->hc[ch_num & 0xFU].xfer_len_db = 0U; /* end of fill buffer */ + } + + /* Write remaining data to Buffer0 */ + HCD_SET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum, 1U, (uint16_t)len); + USB_WritePMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr0, (uint16_t)len); + } + /* start a new transfer */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_VALID); + } + else + { + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + /* Close the Channel */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + } + } + else + { + /* Send Buffer1 */ + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->RXBD & 0x03FF0000U) >> 16U); + + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) /* updated */ + { + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) + { + /* manage multiple Xfer */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + + /* check if we need to free user buffer */ + if ((regvalue & USB_CH_DTOG_RX) == 0U) + { + /* Toggle SwBuff */ + HCD_CLEAR_TX_DTOG(hhcd->Instance, phy_chnum); + HCD_CLEAR_RX_DTOG(hhcd->Instance, phy_chnum); + HCD_RX_DTOG(hhcd->Instance, phy_chnum); + } + + /* hhcd->hc[ch_num&0xFU].xfer_len_db==0 ==> when all data are written in the PMA to yet transferred */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > 0U) /* Still data to fill in the buffer */ + { + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + + /* calculate len of new buffer to fill */ + if (hhcd->hc[ch_num & 0xFU].xfer_len_db > hhcd->hc[ch_num & 0xFU].max_packet) + { + len = hhcd->hc[ch_num & 0xFU].max_packet; + hhcd->hc[ch_num & 0xFU].xfer_len_db -= len; + } + else + { + len = (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_len_db; + hhcd->hc[ch_num & 0xFU].xfer_len_db = 0U; /* end of fill buffer */ + } + + /* Write remaining data to Buffer0 */ + HCD_SET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum, 1U, (uint16_t)len); + + USB_WritePMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr1, (uint16_t)len); + } + + /* start a new transfer */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_VALID); + } + else + { + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + + /* Close the channel */ + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + } + } +} + + +/** + * @brief Handle Host Channel IN Double Buffer Bulk requests. + * @param hhcd HCD handle + * @param ch_num Channel number: This parameter can be a value from 1 to 15 + * @param phy_chnum Physical Channel number [0..7] + * @param regvalue contain Snapshot of the EPCHn register when ISR is detected + * @retval none + */ +static void HCD_HC_IN_BulkDb(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, uint8_t phy_chnum, uint32_t regvalue) +{ + uint16_t received_bytes; + + /* Read from Buffer 0 */ + if ((regvalue & USB_CH_DTOG_RX) != 0U) + { + received_bytes = (uint16_t)HCD_GET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes) + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes; + } + + /* Check if we Need to free the other buffer for the IP */ + if ((hhcd->hc[ch_num & 0xFU].xfer_len != 0U) && ((regvalue & USB_CH_DTOG_TX) != 0U)) + { + /* Toggle SwBuff to Allow the IP to submit a new IN */ + HCD_FREE_USER_BUFFER(hhcd->Instance, phy_chnum, 0U); + } + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr0, (uint16_t)received_bytes); + } + else + { + /* Read from Buffer 1 */ + received_bytes = (uint16_t) HCD_GET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes) + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes; + } + + /* Check if we Need to free the other buffer for the IP */ + if ((hhcd->hc[ch_num & 0xFU].xfer_len != 0U) && ((regvalue & USB_CH_DTOG_TX) == 0U)) + { + /* Toggle SwBuff */ + HCD_FREE_USER_BUFFER(hhcd->Instance, phy_chnum, 0U); + } + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr1, (uint16_t)received_bytes); + } + + /* update the global number of all received bytes */ + hhcd->hc[ch_num & 0xFU].xfer_count += received_bytes; + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_ACK; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + + if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || + ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + + /* disable channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_buff += received_bytes; + + /* Reactivate the Channel Submit an other URB since the Transfer is not yet completed */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_STRX); + } +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + +/** + * @brief Handle Host Channel IN Isochronous Transaction + * @param hhcd HCD handle + * @param ch_num Channel number: This parameter can be a value from 1 to 15 + * @param phy_chnum Physical Channel number [0..7] + * @param regvalue contain Snapshot of the EPCHn register when ISR is detected + * @retval none + */ +static void inline HCD_HC_IN_ISO(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t phy_chnum, uint32_t regvalue) +{ + /* Check if Double buffer isochronous */ + if ((regvalue & USB_CH_KIND) != 0U) + { + /* Get Data IN Packet */ + hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_RX_CNT(hhcd->Instance, phy_chnum); + if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U) + { + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaadress, + (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count); + + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* double buffer isochronous */ + { + /* Read from Buffer0 */ + if ((regvalue & USB_CH_DTOG_RX) != 0U) + { + /* Get number of Received byte in buffer0 */ + hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_DBUF0_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U) + { + /* Read from Buffer0 */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr0, + (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count); + + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } + else + { + /* Get number of Received byte in buffer1 */ + hhcd->hc[ch_num & 0xFU].xfer_count = HCD_GET_CH_DBUF1_CNT(hhcd->Instance, phy_chnum); + + if (hhcd->hc[ch_num & 0xFU].xfer_count != 0U) + { + /* Read from Buffer1 */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaaddr1, + (uint16_t)hhcd->hc[ch_num & 0xFU].xfer_count); + + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + + /* Clear VTRX */ + HCD_CLEAR_RX_CH_CTR(hhcd->Instance, phy_chnum); +} + +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number + * This parameter can be a value from 1 to 8 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + uint16_t received_bytes; + uint8_t phy_chnum = chnum; + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 1U); + + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control and status */ + uint32_t ch_reg = HCD_GET_CHANNEL(hhcd->Instance, phy_chnum); + + /* Manage Correct Transaction */ + if ((ch_reg & USB_CH_ERRRX) == 0U) + { + /* Isochronous Channel */ + if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) + { + HCD_HC_IN_ISO(hhcd, ch_num, phy_chnum, ch_reg); + } + else + { + /* manage ACK response single buffer */ + if (((ch_reg) & USB_CH_RX_STRX) == USB_CH_RX_ACK_SBUF) + { + /* Get Control Data OUT Packet */ + received_bytes = (uint16_t)HCD_GET_CH_RX_CNT(hhcd->Instance, phy_chnum); + + /* Read the byte from PMA to user Buffer(System Memory) */ + USB_ReadPMA(hhcd->Instance, hhcd->hc[ch_num & 0xFU].xfer_buff, + hhcd->hc[ch_num & 0xFU].pmaadress, (uint16_t)received_bytes); + + /* update the global number of all received bytes */ + hhcd->hc[ch_num & 0xFU].xfer_count += received_bytes; + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_ACK; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + + if (hhcd->hc[ch_num & 0xFU].xfer_len <= received_bytes) + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len -= received_bytes; + } + + if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || + ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_buff += received_bytes; + + /* Reactivate the Channel to Submit another URB since the Transfer is not yet completed */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_STRX); + } + + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U; + } + } + /* Manage NACK Response */ + else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) + && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + hhcd->hc[ch_num & 0xFU].state = HC_NAK; + + if (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR) + { + /* Close the channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } + } + /* Manage STALL Response */ + else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) + { + (void)HAL_HCD_HC_Halt(hhcd, ch_num); + hhcd->hc[ch_num & 0xFU].state = HC_STALL; + hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; + + /* Close the channel */ + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer Management in case of Bulk Transaction */ + else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_ACK_DBUF) + && ((ch_reg & USB_CH_KIND) != 0U)) + { + /* Bulk IN Double Buffer ISR */ + HCD_HC_IN_BulkDb(hhcd, ch_num, phy_chnum, ch_reg); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + else + { + /*....*/ + /* not defined state: STRX=11 in single buffer no iso is not defined */ + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + /*Clear VTRX */ + HCD_CLEAR_RX_CH_CTR(hhcd->Instance, phy_chnum); + } + } + else /* Error detected during last transaction */ + { + /* Set URB Error State */ + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt++; + hhcd->hc[ch_num & 0xFU].state = HC_XACTERR; + + /* Clear VTTRX & ERR_RX */ + HCD_CLEAR_RX_CH_ERR(hhcd->Instance, phy_chnum); + + /* Check Error number */ + if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U) + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR; + HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); + + /* Clear pending err_tx */ + HCD_CLEAR_RX_CH_ERR(hhcd->Instance, phy_chnum); + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number + * This parameter can be a value from 1 to 8 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + __IO uint32_t WregCh; + uint16_t data_xfr; + uint8_t phy_chnum = chnum; + + /* Get Virtual Channel number */ + uint8_t ch_num = HAL_HCD_GetLogical_Channel(hhcd, phy_chnum, 0U); + + /* Take a Flag snapshot from the CHEP register, due to STRX bits are used for both control &status */ + uint32_t ch_reg = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); + + /*------ Manage Correct Transaction ------*/ + if ((ch_reg & USB_CH_ERRTX) == 0U) + { + /* Handle Isochronous channel */ + if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) + { + /* Correct transaction */ + if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) + { + /* Double buffer isochronous out */ + if ((ch_reg & USB_CH_KIND) != 0U) + { + HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* Double buffer isochronous out */ + { + /* Odd Transaction */ + if ((ch_reg & USB_CH_DTOG_TX) != 0U) + { + HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); + } + /* Even Transaction */ + else + { + HCD_SET_CH_RX_CNT(hhcd->Instance, phy_chnum, 0U); + } + + USB_DRD_SET_CHEP_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Transfer complete state */ + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + + /*Clear Correct Transfer */ + HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); + + /*TX COMPLETE*/ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else /* Manage all Non Isochronous Transaction */ + { + /* Check ACK response */ + if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_SBUF) + { + data_xfr = (uint16_t)(((USB_DRD_PMA_BUFF + phy_chnum)->TXBD & 0x03FF0000U) >> 16U); + + if (hhcd->hc[ch_num & 0xFU].xfer_len >= data_xfr) + { + hhcd->hc[ch_num & 0xFU].xfer_len -= data_xfr; + } + else + { + hhcd->hc[ch_num & 0xFU].xfer_len = 0U; + } + + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + } + + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ + if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) + { + /* Manage multiple Xfer */ + hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + + /* Start a new transfer */ + (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); + } + else + { + /* Transfer complete */ + hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + } + } + /* Check NACK Response */ + else if (((ch_reg & USB_CHEP_NAK) == USB_CHEP_NAK) || + ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_NAK)) + { + /* Update Channel status */ + hhcd->hc[ch_num & 0xFU].state = HC_NAK; + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + hhcd->hc[ch_num & 0xFU].ErrCnt = 0U; + + /* Get Channel register value */ + WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); + + /* Clear NAK status */ + WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; + + /* Update channel register Value */ + HCD_SET_CHANNEL(hhcd->Instance, phy_chnum, WregCh); + + if (hhcd->hc[ch_num & 0xFU].doublebuffer == 0U) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + /* Check STALL Response */ + else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_STALL) + { + (void) HAL_HCD_HC_Halt(hhcd, (uint8_t)ch_num); + hhcd->hc[ch_num & 0xFU].state = HC_STALL; + hhcd->hc[ch_num & 0xFU].urb_state = URB_STALL; + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Check double buffer ACK in case of bulk transaction */ + else if ((ch_reg & USB_CH_TX_STTX) == USB_CH_TX_ACK_DBUF) + { + /* Double buffer management Bulk Out */ + (void) HCD_HC_OUT_BulkDb(hhcd, ch_num, (uint8_t)phy_chnum, ch_reg); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + else + { + /*...*/ + } + + if ((ch_reg & USB_CH_TX_STTX) != USB_CH_TX_NAK) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + + HCD_CLEAR_TX_CH_CTR(hhcd->Instance, phy_chnum); + } /* End no isochronous */ + } + /*------ Manage Transaction Error------*/ + else + { + hhcd->hc[ch_num & 0xFU].ErrCnt++; + if (hhcd->hc[ch_num & 0xFU].ErrCnt > 3U) + { + HCD_SET_CH_TX_STATUS(hhcd->Instance, phy_chnum, USB_CH_TX_DIS); + hhcd->hc[ch_num & 0xFU].urb_state = URB_ERROR; + } + else + { + hhcd->hc[ch_num & 0xFU].urb_state = URB_NOTREADY; + } + + hhcd->hc[ch_num & 0xFU].state = HC_XACTERR; + + /* Clear ERR_TX */ + HCD_CLEAR_TX_CH_ERR(hhcd->Instance, phy_chnum); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num & 0xFU].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + uint32_t FnrReg = hhcd->Instance->FNR; + uint32_t IstrReg = hhcd->Instance->ISTR; + + /* SE0 detected USB Disconnected state */ + if ((FnrReg & (USB_FNR_RXDP | USB_FNR_RXDM)) == 0U) + { + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* Clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); + + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); + + /* Reset Ep0 Pma allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + /* Disconnection Callback */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + return; + } + + if ((hhcd->HostState == HCD_HCD_STATE_DISCONNECTED) != 0U) + { + /* J-state or K-state detected & LastState=Disconnected */ + if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) + { + hhcd->HostState = HCD_HCD_STATE_CONNECTED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + else + { + /* J-state or K-state detected & lastState=Connected: a Missed disconnection is detected */ + if (((FnrReg & USB_FNR_RXDP) != 0U) || ((IstrReg & USB_ISTR_LS_DCONN) != 0U)) + { + /* Host Port State */ + hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; + + /* clear all allocated virtual channel */ + HAL_HCD_ClearPhyChannel(hhcd); + + /* Reset the PMA current pointer */ + (void)HAL_HCD_PMAReset(hhcd); + + /* reset Ep0 PMA allocation state */ + hhcd->ep0_PmaAllocState = 0U; + + /* Disconnection Callback */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } +} + + +/** + * @brief Check if the ch_num are already reserved to a physical channel + * @param hhcd HCD handle + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +static uint8_t HAL_HCD_Check_usedChannel(HCD_HandleTypeDef const *hhcd, uint8_t ch_num) +{ + uint8_t idx; + + /* Check if the logical channel are already opened */ + for (idx = 0U; idx < hhcd->Init.Host_channels; idx++) + { + if ((((hhcd->phy_chin_state[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) && + (hhcd->phy_chin_state[idx] != 0U)) + { + return (1U | (idx << 4U)); + } + + if ((((hhcd->phy_chout_state[idx] & 0xF0U) >> 4U) == ((uint16_t)ch_num + 1U)) && + (hhcd->phy_chout_state[idx] != 0U)) + { + return (1U | (idx << 4U)); + } + } + + return 0U; +} + + +/** + * @brief Get a Logical Channel number from physical Channel + * @param hhcd HCD handle + * @param phy_chnum + * This parameter can be a value from 1 to 15 + * @param dir Channel direction + * -0 OUT_Channel + * -1 IN_Channel + * @retval HAL status + */ +static uint8_t HAL_HCD_GetLogical_Channel(HCD_HandleTypeDef const *hhcd, + uint8_t phy_chnum, uint8_t dir) +{ + /* Out Channel Direction */ + if (dir == 0U) + { + if (((hhcd->phy_chout_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) != 0U) + { + return ((uint8_t)((hhcd->phy_chout_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) - 1U); + } + else + { + /* Channel not registered Error */ + return HCD_LOGICAL_CH_NOT_OPENED; + } + } + /* IN Channel Direction */ + else + { + if (((hhcd->phy_chin_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) != 0U) + { + return ((uint8_t)((hhcd->phy_chin_state[phy_chnum & 0x7U] & 0x00F0U) >> 4U) - 1U); + } + else + { + /* Channel not registered Error */ + return HCD_LOGICAL_CH_NOT_OPENED; + } + } +} + + +/** + * @brief Get a free physical Channel number according to the direction + * @param hhcd HCD handle + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * EP_TYPE_CTRL Control type, + * EP_TYPE_ISOC Isochronous type, + * EP_TYPE_BULK Bulk type, + * EP_TYPE_INTR Interrupt type + * @retval if physical channel is available return Phy_channel number + else return HCD_FREE_CH_NOT_FOUND + */ +static uint8_t HAL_HCD_Get_FreePhyChannel(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t ep_type) +{ + uint8_t idx; + + if ((epnum & 0x7FU) == 0U) + { + idx = 0U; + + if (ch_num == 0U) + { + if (hhcd->phy_chin_state[idx] == 0U) + { + /* chin_state to store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + + if (hhcd->phy_chout_state[idx] == 0U) + { + /* chout_state will store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + } + else + { + if ((epnum & 0x80U) != 0U) + { + if (((hhcd->phy_chin_state[idx] & 0xF0U) >> 4U) != ((uint16_t)ch_num + 1U)) + { + /* chin_state to store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + } + else + { + if (((hhcd->phy_chout_state[idx] & 0xF0U) >> 4U) != ((uint16_t)ch_num + 1U)) + { + /* chout_state will store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + } + } + } + + return idx; + } + + if ((epnum & 0x80U) != 0U) + { + /* Find a new available physical in channel */ + for (idx = 1U; idx < hhcd->Init.Host_channels; idx++) + { + /* Check if the same epnum is allocated then allocate the same physical channel OUT for IN Logical Channel */ + if ((hhcd->phy_chin_state[idx] == 0U) && + ((((hhcd->phy_chout_state[idx] & 0x000FU) == ((uint16_t)ep_type + 1U)) && + (((hhcd->phy_chout_state[idx] & 0x0F00U) == ((uint16_t)epnum & 0x0FU)))) || + (hhcd->phy_chout_state[idx] == 0U))) + { + /* chin_state to store the ep_type to be used for the same channel in OUT direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chin_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + return idx; + } + } + } + else + { + /* Find a new available physical out channel */ + for (idx = 1U; idx < hhcd->Init.Host_channels; idx++) + { + /* Check if the same epnum is allocated then allocate the same physical channel IN for OUT Logical Channel */ + if ((hhcd->phy_chout_state[idx] == 0U) && + ((((hhcd->phy_chin_state[idx] & 0x0FU) == ((uint16_t)ep_type + 1U)) && + ((hhcd->phy_chin_state[idx] & 0x0F00U) == ((uint16_t)epnum & 0x0FU))) || + (hhcd->phy_chin_state[idx] == 0U))) + { + /* chout_state will store the ep_type to be used for the same channel in IN direction + * adding + 1 to ep_type avoid starting with a 0 value. ep_type take by default (0/1/2/3) */ + hhcd->phy_chout_state[idx] = (((uint16_t)ch_num + 1U) << 4U) | + ((uint16_t)ep_type + 1U) | + (((uint16_t)epnum & 0x0FU) << 8U); + + return idx; + } + } + } + + /* in case of Error */ + return HCD_FREE_CH_NOT_FOUND; +} + +/** + * @brief Free All Channel allocation + * @param hhcd HCD handle + * @retval HAL status + */ +static void HAL_HCD_ClearPhyChannel(HCD_HandleTypeDef *hhcd) +{ + uint8_t idx; + + for (idx = 0U; idx < hhcd->Init.Host_channels; idx++) + { + /*Reset channel allocation value */ + hhcd->phy_chout_state[idx] = 0U; + hhcd->phy_chin_state[idx] = 0U; + } +} + +/*---------------------- PMA Allocation Section --------------------- */ +/* + __col31________________col0__ Column-- > + lin0 | entry31.|....... | entry0 | Line + |---------|---------|--------| | + line1| entry63.|....... | entry32| | + |---------|---------|--------| \|/ + | entry127|....... | entry64| + |---------|---------|--------| + | entry256|...... |entry128| + ---------------------------- + an allocation space of 64byte need 8 Free contiguous Entry in the Matrix + - a Free Entry is a bit with 0 Value/ a busy entry is a bit with 1 value. */ + +/** + * @brief Fetch in the PMA_LockupTable free space of number of mps byte + * @param hhcd Host instance + * @param mps Channel Max Packet Size + * @retval PMA_Address of the first free block containing mps byte + 0xFFFF in case of no space available + */ +static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) +{ + uint32_t Entry; + uint32_t FreeBlocks = 0U; + uint8_t FirstFreeBlock_col = 0U; + uint8_t FirstFreeBlock_line = 0U; + uint8_t ColIndex; + uint16_t NbrReqBlocks; + uint16_t mps_t = mps; + + /* since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64 + allocation in PMA is done in 32Bytes each entry */ + if ((mps_t > 64U) && ((mps_t % 32U) != 0U)) + { + /* Align the mps to 32byte block to match the allocation in PMA, + check Definition of allocation buffer memory in usb user spec */ + mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U); + } + + /* calculate the number of block(8byte) to allocate */ + NbrReqBlocks = mps_t / 8U; + + /* check if we need remaining Block */ + if ((mps_t % 8U) != 0U) + { + NbrReqBlocks++; + } + + /* Look For NbrReqBlocks * Empty Block */ + for (uint8_t i = 0U; ((i < PMA_BLOCKS) && (FreeBlocks != NbrReqBlocks)); i++) + { + Entry = hhcd->PMALookupTable[i]; + + /* when parse is in progress, check the first col to look for a contiguous block */ + if ((FreeBlocks != 0U) && ((Entry & (uint32_t)1U) != 0U)) + { + FreeBlocks = 0U; + } + uint8_t j = 0U; + while ((j <= 31U) && (FreeBlocks != NbrReqBlocks)) + { + /* check if block j is free */ + if ((Entry & ((uint32_t)1U << j)) == 0U) + { + if (FreeBlocks == 0U) + { + FirstFreeBlock_col = j; + FirstFreeBlock_line = i; + FreeBlocks++; + } + j++; + + /* Parse Column PMALockTable */ + while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) + { + FreeBlocks++; + j++; + } + + /* Free contiguous Blocks not found */ + if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) || + ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U))) + { + FreeBlocks = 0U; + } + } + j++; + } /* end for j */ + } /* end for i */ + + /* Free block found */ + if (FreeBlocks >= NbrReqBlocks) + { + ColIndex = FirstFreeBlock_col; + + for (uint8_t i = FirstFreeBlock_line; ((i < PMA_BLOCKS) && (FreeBlocks > 0U)); i++) + { + for (uint8_t j = ColIndex; j <= 31U; j++) + { + hhcd->PMALookupTable[i] |= ((uint32_t)1U << j); + if (--FreeBlocks == 0U) + { + break; + } + } + ColIndex = 0U; + } + + return (uint16_t)((FirstFreeBlock_line * (uint16_t)256U) + (FirstFreeBlock_col * (uint16_t)8U)); + } + else + { + return 0xFFFFU; + } +} + +/** + * @brief Allocate PMA buffer for Channel + * This API will fetch a free space + * @param hhcd Host instance + * @param ch_num Channel number + * @param ch_kind endpoint Kind + * USB_SNG_BUF Single Buffer used + * USB_DBL_BUF Double Buffer used + * @param mps Channel Max Packet Size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint16_t ch_kind, uint16_t mps) +{ + uint16_t pma_addr0; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint16_t pma_addr1; /* used for double buffer mode if enabled */ +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Host Channel */ + HCD_HCTypeDef *hc = &(hhcd->hc[ch_num]); + + /* Get a FreePMA Address */ + pma_addr0 = HAL_HCD_GetFreePMA(hhcd, mps); + + /* If there is no free space to allocate */ + if (pma_addr0 == 0xFFFFU) + { + return HAL_ERROR; + } + else + { + /* Here we check if the endpoint is single or double Buffer */ + if (ch_kind == HCD_SNG_BUF) + { + /* Single Buffer */ + hc->doublebuffer = 0U; + + if (hc->ep_num == 0U) + { + hhcd->ep0_PmaAllocState &= 0xFFF0U; + hhcd->ep0_PmaAllocState |= ch_num; + hhcd->ep0_PmaAllocState |= (1U << 8); + } + + /* Configure the PMA */ + if (hc->ch_dir == CH_IN_DIR) + { + hc->pmaaddr1 = pma_addr0; + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->RXBD = hc->pmaaddr1; + + if (hc->ep_num == 0U) + { + hhcd->ep0_PmaAllocState |= (CH_IN_DIR << 4); + } + } + else + { + hc->pmaaddr0 = pma_addr0; + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->TXBD = hc->pmaaddr0; + } + + /* Set the PmaAddress */ + hc->pmaadress = pma_addr0; + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + hc->doublebuffer = 1U; + + /* Get a FreePMA Address for buffer 2 */ + pma_addr1 = HAL_HCD_GetFreePMA(hhcd, mps); + + if (pma_addr1 == 0xFFFFU) + { + /* Free the first buffer */ + (void)HAL_HCD_PMAFree(hhcd, pma_addr0, mps); + return HAL_ERROR; + } + else + { + /* Configure the PMA */ + hc->pmaaddr0 = (uint16_t)(pma_addr0); + hc->pmaaddr1 = (uint16_t)(pma_addr1); + + /* Set Buffer0 pma address */ + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->TXBD = pma_addr0; + + /* Set Buffer1 pma address */ + (USB_DRD_PMA_BUFF + hc->phy_ch_num)->RXBD = pma_addr1; + + /* Used for Bulk DB MPS < 64bytes */ + if (hc->ch_dir == CH_IN_DIR) + { + hc->pmaadress = hc->pmaaddr1; + } + else + { + hc->pmaadress = hc->pmaaddr0; + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + } + + return HAL_OK; +} + +/** + * @brief PMA De-Allocation for Channel Free the reserved block in the PMA-LookupTable + * @param hhcd Host instance + * @param ch_num Channel number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status; + +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint8_t Err = 0U; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Host Channel */ + HCD_HCTypeDef *hc = &(hhcd->hc[ch_num]); + + /* Single Buffer */ + if (hc->doublebuffer == 0U) + { + status = HAL_HCD_PMAFree(hhcd, hc->pmaadress, hc->max_packet); + } + else /* Double buffer */ + { +#if (USE_USB_DOUBLE_BUFFER == 1U) + status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr0, hc->max_packet); + if (status != HAL_OK) + { + Err++; + } + + status = HAL_HCD_PMAFree(hhcd, hc->pmaaddr1, hc->max_packet); + if (status != HAL_OK) + { + Err++; + } + + if (Err != 0U) + { + return HAL_ERROR; + } +#else + status = HAL_ERROR; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + } + + return status; +} + + +/** + * @brief PMA Reset + * @param hhcd Host instance + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd) +{ + /* Reset All PMA Entry */ + for (uint8_t i = 0U; i < PMA_BLOCKS; i++) + { + hhcd->PMALookupTable[i] = 0U; + } + + /* Allocate a Space for buffer descriptor table depending on the Host channel number */ + for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++) + { + hhcd->PMALookupTable[0] |= ((uint32_t)1U << i); + } + + return HAL_OK; +} + +/** + * @brief PMA Free + * @param hhcd Host instance + * @param pma_base PMA base offset stored in hhcd->hc.pmaaddr + * @param mps Max Packet Size + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_base, uint16_t mps) +{ + uint32_t block_nbr; + uint8_t ColIndex; + uint8_t LineIndex; + uint16_t mps_t = mps; + + /* since PMA buffer descriptor RXBD allocate address according to BLSIZE, BLSIZE=1==> mps>64 + allocation in PMA is done in 32Bytes each entry */ + if ((mps_t > 64U) && ((mps_t % 32U) != 0U)) + { + /* Align the mps to 32byte block to match the allocation in PMA, + check Definition of allocation buffer memory in usb user spec */ + mps_t = (uint16_t)(((mps_t / 32U) + 1U) * 32U); + } + + /* Calculate the number of needed block to Free */ + if ((mps_t / 8U) != 0U) + { + block_nbr = ((uint32_t)mps_t / 8U); + + if ((mps_t % 8U) != 0U) + { + block_nbr++; + } + } + else + { + block_nbr = 1U; + } + + /* Decode Col/Line of PMA_Base position in the PMA_LookupTable */ + if (pma_base > 256U) + { + LineIndex = (uint8_t)(pma_base / 256U); + ColIndex = (uint8_t)((pma_base - ((uint32_t)LineIndex * 256U)) / 8U); + } + else + { + LineIndex = 0U; + ColIndex = (uint8_t)(pma_base / 8U); + } + + /* Reset the corresponding bit in the lookupTable */ + for (uint8_t i = LineIndex; ((i < PMA_BLOCKS) && (block_nbr > 0U)); i++) + { + for (uint8_t j = ColIndex; j <= 31U; j++) + { + /* Check if the block is not already reserved or it was already closed */ + if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U) + { + return HAL_ERROR; + } + /* Free the reserved block by resetting the corresponding bit */ + hhcd->PMALookupTable[i] &= ~(1U << j); + + if (--block_nbr == 0U) + { + break; + } + } + ColIndex = 0U; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_DRD_FS) */ #endif /* HAL_HCD_MODULE_ENABLED */ /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c index 4c9b7a5df..b304a6174 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_i2c.c @@ -406,7 +406,11 @@ */ #if defined(HAL_DMA_MODULE_ENABLED) /* Macro to get remaining data to transfer on DMA side */ +#if defined(GPDMA1) #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#else /* GPDMA1 */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +#endif /* GPDMA1 */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd.c index 94b8aabce..2e169f908 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd.c @@ -37,6 +37,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) @@ -50,6 +51,9 @@ (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -68,7 +72,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -92,6 +96,14 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); #endif /* defined (USB_OTG_HS) */ + +#if defined (USB_DRD_FS) +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +#if (USE_USB_DOUBLE_BUFFER == 1U) +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (USB_DRD_FS) */ /** * @} */ @@ -191,7 +203,9 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Init ep structure */ hpcd->IN_ep[i].is_in = 1U; hpcd->IN_ep[i].num = i; +#if defined (USB_OTG_HS) hpcd->IN_ep[i].tx_fifo_num = i; +#endif /* defined (USB_OTG_HS) */ /* Control until ep is activated */ hpcd->IN_ep[i].type = EP_TYPE_CTRL; hpcd->IN_ep[i].maxpacket = 0U; @@ -1014,7 +1028,10 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); +#if defined (USB_OTG_HS) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); +#endif /* defined (USB_OTG_HS) */ + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1398,8 +1415,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) { - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + /* disable the EP */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); } } } @@ -1433,7 +1451,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1481,6 +1499,151 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +/** + * @brief This function handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); + + if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + (void)PCD_EP_ISR_Handler(hpcd); + + return; + } + + if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + (void)HAL_PCD_SetAddress(hpcd, 0U); + + return; + } + + if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); + + return; + } + + if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); + + return; + } + + if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) + { + hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPRDY); + hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPEN); + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); + + return; + } + + if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) + { + /* Force low-power mode in the macrocell */ + hpcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + + hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + /* Handle LPM Interrupt */ + if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); + if (hpcd->LPM_State == LPM_L0) + { + /* Force suspend and low-power mode before going to L1 state*/ + hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY; + hpcd->Instance->CNTR |= USB_CNTR_SUSPEN; + + hpcd->LPM_State = LPM_L1; + hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + return; + } + + if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + return; + } + + if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) + { + /* clear ESOF flag in ISTR */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); + + return; + } +} +#endif /* defined (USB_DRD_FS) */ /** * @brief Data OUT stage callback. @@ -1727,7 +1890,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1742,14 +1905,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; +#if defined (USB_OTG_HS) if (ep->is_in != 0U) { /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } +#endif /* defined (USB_OTG_HS) */ /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) @@ -1814,12 +1979,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->is_in = 0U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_HS) if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else + (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_HS) */ return HAL_OK; } @@ -1851,16 +2020,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; +#if defined (USB_DRD_FS) + ep->xfer_fill_db = 1U; + ep->xfer_len_db = len; +#endif /* defined (USB_DRD_FS) */ ep->xfer_count = 0U; ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; +#if defined (USB_OTG_HS) if (hpcd->Init.dma_enable == 1U) { ep->dma_addr = (uint32_t)pBuf; } (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); +#else + (void)USB_EPStartXfer(hpcd->Instance, ep); +#endif /* defined (USB_OTG_HS) */ return HAL_OK; } @@ -1898,10 +2075,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) (void)USB_EPSetStall(hpcd->Instance, ep); +#if defined (USB_OTG_HS) if ((ep_addr & EP_ADDR_MSK) == 0U) { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } +#endif /* defined (USB_OTG_HS) */ __HAL_UNLOCK(hpcd); @@ -2062,6 +2241,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; @@ -2292,13 +2472,567 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint } #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +/** + * @brief This function handles PCD Endpoint interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) +{ + PCD_EPTypeDef *ep; + uint16_t count; + uint16_t wIstr; + uint16_t wEPVal; + uint16_t TxPctSize; + uint8_t epindex; + +#if (USE_USB_DOUBLE_BUFFER != 1U) + count = 0U; +#endif /* USE_USB_DOUBLE_BUFFER */ + + /* stay in loop while pending interrupts */ + while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) + { + wIstr = (uint16_t)hpcd->Instance->ISTR; + + /* extract highest priority endpoint number */ + epindex = (uint8_t)(wIstr & USB_ISTR_IDN); + + if (epindex == 0U) + { + /* Decode and service control endpoint interrupt */ + + /* DIR bit = origin of the interrupt */ + if ((wIstr & USB_ISTR_DIR) == 0U) + { + /* DIR = 0 */ + + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); + ep = &hpcd->IN_ep[0]; + + ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + ep->xfer_buff += ep->xfer_count; + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, 0U); +#else + HAL_PCD_DataInStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) + { + hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); + hpcd->USB_Address = 0U; + } + } + else + { + /* DIR = 1 */ + + /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ + ep = &hpcd->OUT_ep[0]; + wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); + + if ((wEPVal & USB_EP_SETUP) != 0U) + { + /* Get SETUP Packet */ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, + ep->pmaadress, (uint16_t)ep->xfer_count); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Process SETUP Packet*/ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else if ((wEPVal & USB_EP_VTRX) != 0U) + { + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + /* Get Control Data OUT Packet */ + ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_count == 0U) + { + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else + { + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ + + ep->xfer_buff += ep->xfer_count; + + /* Process Control Data OUT Packet */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, 0U); +#else + HAL_PCD_DataOutStageCallback(hpcd, 0U); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + } + } + } + else + { + /* Decode and service non control endpoints interrupt */ + /* process related endpoint register */ + wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, epindex); + + if ((wEPVal & USB_EP_VTRX) != 0U) + { + /* clear int flag */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); + ep = &hpcd->OUT_ep[epindex]; + + /* OUT Single Buffering */ + if (ep->doublebuffer == 0U) + { + count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else + { + /* manage double buffer bulk out */ + if (ep->type == EP_TYPE_BULK) + { + count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); + } + else /* manage double buffer iso out */ + { + /* free EP OUT Buffer */ + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) + { + /* read from endpoint BUF0Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /* read from endpoint BUF1Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* multi-packet on the NON control OUT endpoint */ + ep->xfer_count += count; + + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) + { + /* RX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataOutStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + ep->xfer_buff += count; + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + } + + if ((wEPVal & USB_EP_VTTX) != 0U) + { + ep = &hpcd->IN_ep[epindex]; + + /* clear int flag */ + PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); + + if (ep->type == EP_TYPE_ISOC) + { + ep->xfer_len = 0U; + +#if (USE_USB_DOUBLE_BUFFER == 1U) + if (ep->doublebuffer != 0U) + { + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + } + else + { + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Manage Single Buffer Transaction */ + if ((wEPVal & USB_EP_KIND) == 0U) + { + /* Multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Transfer is not yet Done */ + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ + else + { + (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + } + } + } + } + + return HAL_OK; +} + + +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Manage double buffer bulk out transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint16_t count; + + /* Manage Buffer0 OUT */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + /* Get count of received Data on buffer0 */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* Set NAK to OUT endpoint since double buffer is enabled */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /* Check if Buffer1 is in blocked state which requires to toggle */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + /* Manage Buffer 1 DTOG_RX=0 */ + else + { + /* Get count of received data */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* Set NAK on the current endpoint */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /* Need to FreeUser Buffer */ + if ((wEPVal & USB_EP_DTOG_TX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + + return count; +} + + +/** + * @brief Manage double buffer bulk IN transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint32_t len; + uint16_t TxPctSize; + + /* Data Buffer0 ACK received */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + return HAL_OK; + } + else /* Transfer is not yet Done */ + { + /* Need to Free USB Buffer */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxPctSize; + ep->xfer_fill_db = 0U; + } + else + { + ep->xfer_fill_db = 0U; + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Write remaining Data to Buffer */ + /* Set the Double buffer counter for pma buffer0 */ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); + } + } + } + else /* Data Buffer1 ACK received */ + { + /* multi-packet on the NON control IN endpoint */ + TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= TxPctSize) + { + ep->xfer_len -= TxPctSize; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + return HAL_OK; + } + else /* Transfer is not yet Done */ + { + /* Need to Free USB Buffer */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxPctSize; + ep->xfer_count += TxPctSize; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxPctSize; + ep->xfer_fill_db = 0U; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + ep->xfer_fill_db = 0; + } + + /* Set the Double buffer counter for pma buffer1 */ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy the user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); + } + } + } + + /* Enable endpoint IN */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + + return HAL_OK; +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (USB_DRD_FS) */ /** * @} */ -#endif /* defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd_ex.c index 7894b187d..9a42d8916 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pcd_ex.c @@ -34,7 +34,7 @@ #ifdef HAL_PCD_MODULE_ENABLED -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -269,6 +269,213 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) } #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +/** + * @brief Configure PMA for EP + * @param hpcd Device instance + * @param ep_addr endpoint address + * @param ep_kind endpoint Kind + * USB_SNG_BUF: Single Buffer used + * USB_DBL_BUF: Double Buffer used + * @param pmaadress: EP address in The PMA: In case of single buffer endpoint + * this parameter is 16-bit value providing the address + * in PMA allocated to endpoint. + * In case of double buffer endpoint this parameter + * is a 32-bit value providing the endpoint buffer 0 address + * in the LSB part of 32-bit value and endpoint buffer 1 address + * in the MSB part of 32-bit value. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress) +{ + PCD_EPTypeDef *ep; + + /* Initialize ep structure */ + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + } + + /* Here we check if the endpoint is single or double Buffer*/ + if (ep_kind == PCD_SNG_BUF) + { + /* Single Buffer */ + ep->doublebuffer = 0U; + + /* Configure the PMA */ + ep->pmaadress = (uint16_t)pmaadress; + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else /* USB_DBL_BUF */ + { + /* Double Buffer Endpoint */ + ep->doublebuffer = 1U; + + /* Configure the PMA */ + ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); + ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + return HAL_OK; +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + hpcd->battery_charging_active = 1U; + + USBx->BCDR &= ~(USB_BCDR_PDEN); + USBx->BCDR &= ~(USB_BCDR_SDEN); + + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + hpcd->battery_charging_active = 0U; + + /* Disable BCD feature */ + USBx->BCDR &= ~(USB_BCDR_BCDEN); + + return HAL_OK; +} + +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + uint32_t tickstart = HAL_GetTick(); + + /* Wait for Min DCD Timeout */ + HAL_Delay(350U); + + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + USBx->BCDR |= (USB_BCDR_PDEN); + HAL_Delay(50U); + + /* If Charger detect ? */ + if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) + { + /* Start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + USBx->BCDR &= ~(USB_BCDR_PDEN); + HAL_Delay(50U); + USBx->BCDR |= (USB_BCDR_SDEN); + HAL_Delay(50U); + + /* If CDP ? */ + if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) + { + /* Dedicated Downstream Port DCP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Charging Downstream Port CDP */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else /* NO */ + { + /* Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + /* Battery Charging capability discovery finished Start Enumeration */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + + USB_DRD_TypeDef *USBx = hpcd->Instance; + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + + USBx->LPMCSR |= USB_LPMCSR_LMPEN; + USBx->LPMCSR |= USB_LPMCSR_LPMACK; + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_DRD_TypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + + USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN); + USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK); + + return HAL_OK; +} +#endif /* defined (USB_DRD_FS) */ /** * @brief Send LPM message to user layer callback. @@ -311,7 +518,7 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ -#endif /* defined (USB_OTG_HS) */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c index b5e4f32c8..70a11dab2 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_pwr_ex.c @@ -139,7 +139,7 @@ #define PWR_PORTC_AVAILABLE_PINS (0x0E0F0U) #define PWR_PORTD_AVAILABLE_PINS (0x003C0U) #define PWR_PORTH_AVAILABLE_PINS (0x00008U) -#elif defined(STM32WBA62xx) || defined(STM32WBA65xx) +#elif defined(STM32WBA62xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) #define PWR_PORTA_AVAILABLE_PINS (0x0FFFFU) #define PWR_PORTB_AVAILABLE_PINS (0x0FFFFU) #define PWR_PORTC_AVAILABLE_PINS (0x0E1FBU) @@ -1268,7 +1268,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, ui return ret; } -#if defined(PWR_STOP2_SUPPORT) +#if defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASREN) /** * @brief Enable the PTA output signals retention in Stop 2 mode. * @retval None. @@ -1305,7 +1305,7 @@ void HAL_PWREx_ClearPTAOutputStop2RetentionState(void) { CLEAR_BIT(PWR->S2RETR, PWR_S2RETR_PTASR); } -#endif /* defined(PWR_STOP2_SUPPORT) */ +#endif /* defined(PWR_STOP2_SUPPORT) && defined(PWR_S2RETR_PTASREN) */ /** * @} */ diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_ramcfg.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_ramcfg.c index e7f201adc..dcdc0c637 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_ramcfg.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_ramcfg.c @@ -662,14 +662,17 @@ uint32_t HAL_RAMCFG_GetWaitState(const RAMCFG_HandleTypeDef *hramcfg) * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that * contains the configuration information for the * specified RAMCFG instance. - * @param StartPage : Select the start page number (from 0 to 63) + * @param StartPage : Select the start page number (from 0 to 63 or + * from 0 to 31 according devices) * @param NbPage : Number of pages to be protected. * @retval HAL status. */ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage) { uint32_t page_mask_0 = 0U; +#if defined(RAMCFG_WPR2_P32WP) uint32_t page_mask_1 = 0U; +#endif /* defined(RAMCFG_WPR2_P32WP) */ /* Check the parameters */ assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance)); @@ -688,15 +691,19 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg { page_mask_0 |= (1UL << (StartPage + count)); } +#if defined(RAMCFG_WPR2_P32WP) else { page_mask_1 |= (1UL << ((StartPage + count) - 32U)); } +#endif /* defined(RAMCFG_WPR2_P32WP) */ } /* Apply mask to protect pages */ WRITE_REG(hramcfg->Instance->WPR1, page_mask_0); +#if defined(RAMCFG_WPR2_P32WP) WRITE_REG(hramcfg->Instance->WPR2, page_mask_1); +#endif /* defined(RAMCFG_WPR2_P32WP) */ } else { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c index a34f1193c..4ad558065 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rcc_ex.c @@ -986,7 +986,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else { -#if defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) +#if !defined (STM32WBA50xx) && !defined (STM32WBA52xx) && !defined (STM32WBA54xx) && !defined (STM32WBA55xx) && !defined (STM32WBA5Mxx) if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { frequency = HSI_VALUE/4U; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c index e3dc2106b..d7087e9fa 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng.c @@ -207,7 +207,11 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #endif /* RNG_CR_NIST_VALUE */ #if defined(RNG_HTCR_NIST_VALUE) /* Recommended value for NIST compliance, refer to application note AN4230 */ +#if defined(RNG_HTCR0_HTCFG) + WRITE_REG(hrng->Instance->HTCR[0], RNG_HTCR_NIST_VALUE); +#else WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* defined(RNG_HTCR0_HTCFG) */ #endif /* RNG_HTCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ @@ -651,6 +655,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng_ex.c index a45b5ca48..10d66b7a4 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rng_ex.c @@ -127,7 +127,11 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT (uint32_t)(RNG_CR_CONDRST | cr_value)); /* RNG health test control in accordance with NIST */ +#if defined(RNG_HTCR0_HTCFG) + WRITE_REG(hrng->Instance->HTCR[0], pConf->HealthTest); +#else WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); +#endif /* defined(RNG_HTCR0_HTCFG) */ /* Writing bit CONDRST=0*/ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -202,7 +206,11 @@ HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV); pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); +#if defined(RNG_HTCR0_HTCFG) + pConf->HealthTest = (hrng->Instance->HTCR[0]); +#else pConf->HealthTest = (hrng->Instance->HTCR); +#endif /* defined(RNG_HTCR0_HTCFG) */ /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; @@ -306,6 +314,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rtc_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rtc_ex.c index 951f2e1eb..ac0a49a7a 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rtc_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_rtc_ex.c @@ -179,9 +179,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#ifdef TAMP_CR1_TAMP4E +#ifdef TAMP_CR1_TAMP5E #define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E | TAMP_CR1_TAMP4E | \ TAMP_CR1_TAMP5E | TAMP_CR1_TAMP6E) +#elif defined(TAMP_CR1_TAMP4E) +#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E | TAMP_CR1_TAMP4E) #else #define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) #endif /* TAMP_CR1_TAMP4E */ @@ -2164,7 +2166,9 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_Tamper4EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } +#endif /* RTC_TAMPER_4 */ +#ifdef RTC_TAMPER_5 /* Check Tamper5 status */ if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5) { @@ -2176,7 +2180,9 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_Tamper5EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } +#endif /* RTC_TAMPER_5 */ +#ifdef RTC_TAMPER_6 /* Check Tamper6 status */ if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6) { @@ -2188,7 +2194,7 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_Tamper6EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* RTC_TAMPER_4 */ +#endif /* RTC_TAMPER_6 */ /* Check Internal Tamper3 status */ if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai_ex.c index e20951b45..160c3f917 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_sai_ex.c @@ -40,7 +40,7 @@ /** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines * @{ */ -#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_MASK 0x77UL #define SAI_PDM_DELAY_OFFSET 8U #define SAI_PDM_RIGHT_DELAY_OFFSET 4U /** diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c index cd990cb4e..0419c56bc 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim.c @@ -153,7 +153,7 @@ (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) BreakCallback : TIM Break Callback. - (+) Break2Callback : TIM Break2 Callback. + (+) Break2Callback : TIM Break2 Callback (when supported). (+) EncoderIndexCallback : TIM Encoder Index Callback. (+) DirectionChangeCallback : TIM Direction Change Callback (+) IndexErrorCallback : TIM Index Error Callback. @@ -220,8 +220,12 @@ all interrupt callbacks are set to the corresponding weak functions: static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +#if defined(TIM_CCER_CC5E) static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +#endif /* TIM_CCER_CC6E */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -799,8 +803,9 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -855,8 +860,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1468,8 +1474,9 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1524,8 +1531,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -3998,6 +4006,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } +#if defined(TIM_BDTR_BK2E) /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) { @@ -4011,6 +4020,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } +#endif /* TIM_BDTR_BK2E */ /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { @@ -4125,8 +4135,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, @@ -4185,6 +4196,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break; } +#if defined(TIM_CCER_CC5E) case TIM_CHANNEL_5: { /* Check the parameters */ @@ -4194,7 +4206,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC5_SetConfig(htim->Instance, sConfig); break; } +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) case TIM_CHANNEL_6: { /* Check the parameters */ @@ -4204,6 +4218,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC6_SetConfig(htim->Instance, sConfig); break; } +#endif /* TIM_CCER_CC6E */ default: status = HAL_ERROR; @@ -4325,8 +4340,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, @@ -4414,6 +4430,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break; } +#if defined(TIM_CCER_CC5E) case TIM_CHANNEL_5: { /* Check the parameters */ @@ -4430,7 +4447,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, htim->Instance->CCMR3 |= sConfig->OCFastMode; break; } +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) case TIM_CHANNEL_6: { /* Check the parameters */ @@ -4447,6 +4466,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; break; } +#endif /* TIM_CCER_CC6E */ default: status = HAL_ERROR; @@ -5554,8 +5574,9 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 + * @arg TIM_CHANNEL_5: TIM Channel 5 (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, @@ -5592,6 +5613,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, break; } +#if defined(COMP1) && defined(COMP2) case TIM_CLEARINPUTSOURCE_COMP1: case TIM_CLEARINPUTSOURCE_COMP2: { @@ -5605,6 +5627,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); break; } +#endif /* COMP1 && COMP2 */ case TIM_CLEARINPUTSOURCE_ETR: { @@ -5702,6 +5725,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } break; } +#if defined(TIM_CCER_CC5E) case TIM_CHANNEL_5: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) @@ -5716,6 +5740,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } break; } +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) case TIM_CHANNEL_6: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) @@ -5730,6 +5756,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } break; } +#endif /* TIM_CCER_CC6E */ default: break; } @@ -5868,17 +5895,21 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_C break; } +#if defined(TIM1) case TIM_CLOCKSOURCE_ITR0: case TIM_CLOCKSOURCE_ITR1: +#endif /* TIM1 */ +#if defined(TIM3) case TIM_CLOCKSOURCE_ITR2: +#endif /* TIM3 */ #if defined(TIM4) case TIM_CLOCKSOURCE_ITR3: #endif /* TIM4 */ case TIM_CLOCKSOURCE_ITR7: case TIM_CLOCKSOURCE_ITR8: -#if defined(USB_OTG_HS) +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) case TIM_CLOCKSOURCE_ITR11: -#endif /* USB_OTG_HS */ +#endif /* USB_OTG_HS || USB_DRD_FS */ { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); @@ -6329,7 +6360,9 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +#if defined(TIM_BDTR_BK2E) * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +#endif * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID @@ -6458,10 +6491,12 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call case HAL_TIM_BREAK_CB_ID : htim->BreakCallback = pCallback; break; +#if defined(TIM_BDTR_BK2E) case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = pCallback; break; +#endif /* TIM_BDTR_BK2E */ case HAL_TIM_ENCODER_INDEX_CB_ID : htim->EncoderIndexCallback = pCallback; @@ -6593,7 +6628,9 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +#if defined(TIM_BDTR_BK2E) * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +#endif * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID @@ -6742,11 +6779,13 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca /* Legacy weak Break Callback */ htim->BreakCallback = HAL_TIMEx_BreakCallback; break; +#if defined(TIM_BDTR_BK2E) case HAL_TIM_BREAK2_CB_ID : /* Legacy weak Break2 Callback */ htim->Break2Callback = HAL_TIMEx_Break2Callback; break; +#endif /* TIM_BDTR_BK2E */ case HAL_TIM_ENCODER_INDEX_CB_ID : /* Legacy weak Encoder Index Callback */ @@ -7295,8 +7334,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -7309,16 +7346,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** @@ -7361,12 +7397,13 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 1N: Reset the CC1NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC1NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7433,18 +7470,22 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); +#if defined(TIM_CCER_CC2NE) if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 2N: Reset the CC2NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC2NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; } +#endif /* TIM_CCER_CC2NE */ +#if defined(TIM_CR2_OIS2) if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ @@ -7459,6 +7500,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); } +#endif /* TIM_CR2_OIS2 */ /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -7508,18 +7550,22 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); +#if defined(TIM_CCER_CC3NE) if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 3N: Reset the CC3NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC3NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; } +#endif /* TIM_CCER_CC3NE */ +#if defined(TIM_CR2_OIS3) if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ @@ -7534,6 +7580,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); } +#endif /* TIM_CR2_OIS3 */ /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -7584,18 +7631,22 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); +#if defined(TIM_CCER_CC4NE) if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 4N: Reset the CC4NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC4NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC4NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 12U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC4NE; } +#endif /* TIM_CCER_CC4NE */ +#if defined(TIM_CR2_OIS4) if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ @@ -7612,6 +7663,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 6U); } +#endif /* TIM_CR2_OIS4 */ /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; @@ -7626,6 +7678,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co TIMx->CCER = tmpccer; } +#if defined(TIM_CCER_CC5E) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral @@ -7679,7 +7732,9 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral @@ -7734,6 +7789,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } +#endif /* TIM_CCER_CC6E */ /** * @brief Slave Timer configuration function @@ -7838,17 +7894,21 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, break; } +#if defined(TIM1) case TIM_TS_ITR0: case TIM_TS_ITR1: +#endif /* TIM1 */ +#if defined(TIM3) case TIM_TS_ITR2: +#endif /* TIM3 */ #if defined(TIM4) case TIM_TS_ITR3: #endif /* TIM4 */ case TIM_TS_ITR7: case TIM_TS_ITR8: -#if defined(USB_OTG_HS) +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) case TIM_TS_ITR11: -#endif /* USB_OTG_HS */ +#endif /* USB_OTG_HS || USB_DRD_FS */ { /* Check the parameter */ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); @@ -7889,9 +7949,18 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7935,9 +8004,18 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7979,9 +8057,20 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; +#if defined(TIM_CCER_CC2NE) + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } +#endif /* TIM_CCER_CC2NE */ + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -8018,9 +8107,20 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; +#if defined(TIM_CCER_CC2NE) + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } +#endif /* TIM_CCER_CC2NE */ + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -8062,9 +8162,20 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 3: Reset the CC3E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; +#if defined(TIM_CCER_CC3NE) + /* Disable the Channel 3N: Reset the CC3NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + TIMx->CCER &= ~TIM_CCER_CC3NE; + } +#endif /* TIM_CCER_CC3NE */ + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -8110,9 +8221,20 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 4: Reset the CC4E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; +#if defined(TIM_CCER_CC4NE) + /* Disable the Channel 4N: Reset the CC4NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) + { + TIMx->CCER &= ~TIM_CCER_CC4NE; + } +#endif /* TIM_CCER_CC4NE */ + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -8137,21 +8259,20 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIMx to select the TIM peripheral * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 -#if defined(TIM4) - * @arg TIM_TS_ITR3: Internal Trigger 3 -#endif + * @arg TIM_TS_ITR0: Internal Trigger 0 (*) + * @arg TIM_TS_ITR1: Internal Trigger 1 (*) + * @arg TIM_TS_ITR2: Internal Trigger 2 (*) + * @arg TIM_TS_ITR3: Internal Trigger 3 (*) * @arg TIM_TS_ITR7: Internal Trigger 7 * @arg TIM_TS_ITR8: Internal Trigger 8 -#if defined(USB_OTG_HS) - * @arg TIM_TS_ITR11: Internal Trigger 11 -#endif + * @arg TIM_TS_ITR11: Internal Trigger 11 (*) * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input + * + * (*) Value not defined in all devices. + * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) @@ -8206,12 +8327,13 @@ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None @@ -8256,7 +8378,9 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim) htim->CommutationCallback = HAL_TIMEx_CommutCallback; htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; htim->BreakCallback = HAL_TIMEx_BreakCallback; +#if defined(TIM_BDTR_BK2E) htim->Break2Callback = HAL_TIMEx_Break2Callback; +#endif /* TIM_BDTR_BK2E */ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c index 7c40759ef..eaa861628 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_tim_ex.c @@ -243,7 +243,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_H TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +#endif /* TIM_CCER_CC2NE */ /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -285,7 +287,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); +#endif /* TIM_CCER_CC2NE */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -337,7 +341,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); +#if defined(TIM_CCER_CC2NE) HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); +#endif /* TIM_CCER_CC2NE */ /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); @@ -345,8 +351,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +#if defined(TIM_CCER_CC2NE) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +#else + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) +#endif /* TIM_CCER_CC2NE */ { return HAL_ERROR; } @@ -355,7 +365,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +#endif /* TIM_CCER_CC2NE */ /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, @@ -402,7 +414,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +#endif /* TIM_CCER_CC2NE */ /* Return function status */ return HAL_OK; @@ -419,7 +433,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); +#if defined(TIM_CCER_CC2NE) HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); +#endif /* TIM_CCER_CC2NE */ /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); @@ -427,8 +443,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +#if defined(TIM_CCER_CC2NE) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +#else + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) +#endif /* TIM_CCER_CC2NE */ { return HAL_ERROR; } @@ -437,7 +457,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +#endif /* TIM_CCER_CC2NE */ /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -490,7 +512,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +#endif /* TIM_CCER_CC2NE */ /* Return function status */ return HAL_OK; @@ -637,9 +661,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -689,9 +714,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -722,9 +748,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -744,6 +771,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -779,6 +807,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Enable the TIM Output Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -817,9 +849,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -830,6 +863,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -864,6 +898,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Disable the TIM Output Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -898,9 +936,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status @@ -935,6 +974,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan return HAL_ERROR; } +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -1025,6 +1065,24 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -1060,9 +1118,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1072,6 +1131,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -1110,6 +1170,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -1159,9 +1224,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1210,9 +1276,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1243,9 +1310,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1265,6 +1333,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -1299,6 +1368,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -1337,9 +1410,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1350,6 +1424,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -1384,6 +1459,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -1418,9 +1497,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status @@ -1455,6 +1535,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha return HAL_ERROR; } +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -1545,6 +1626,24 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -1580,9 +1679,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1592,6 +1692,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +#if defined(TIM_CCER_CC2NE) switch (Channel) { case TIM_CHANNEL_1: @@ -1630,6 +1731,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan status = HAL_ERROR; break; } +#else /* (only CH1N available) */ + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +#endif /* TIM_CCER_CC2NE */ if (status == HAL_OK) { @@ -1681,7 +1787,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1690,7 +1797,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); +#if defined(TIM_CCER_CC2NE) HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); +#endif /* TIM_CCER_CC2NE */ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1698,8 +1807,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +#if defined(TIM_CCER_CC2NE) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +#else + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) +#endif /* TIM_CCER_CC2NE */ { return HAL_ERROR; } @@ -1708,7 +1821,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +#endif /* TIM_CCER_CC2NE */ /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); @@ -1730,7 +1845,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1754,7 +1870,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +#endif /* TIM_CCER_CC2NE */ /* Return function status */ return HAL_OK; @@ -1769,7 +1887,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1778,7 +1897,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); +#if defined(TIM_CCER_CC2NE) HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); +#endif /* TIM_CCER_CC2NE */ /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1786,8 +1907,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +#if defined(TIM_CCER_CC2NE) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +#else + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) +#endif /* TIM_CCER_CC2NE */ { return HAL_ERROR; } @@ -1796,7 +1921,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +#endif /* TIM_CCER_CC2NE */ /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -1824,7 +1951,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -1854,7 +1982,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +#if defined(TIM_CCER_CC2NE) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +#endif /* TIM_CCER_CC2NE */ /* Return function status */ return HAL_OK; @@ -1899,19 +2029,17 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected -#if defined(TIM4) - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_ITR7: Internal trigger 7 selected - * @arg TIM_TS_ITR8: Internal trigger 8 selected - * @arg TIM_TS_ITR11: Internal trigger 11 selected -#else + * @arg TIM_TS_ITR0: Internal trigger 0 selected (*) + * @arg TIM_TS_ITR1: Internal trigger 1 selected (*) + * @arg TIM_TS_ITR2: Internal trigger 2 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 3 selected (*) * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected -#endif + * @arg TIM_TS_ITR11: Internal trigger 11 selected (*) * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer @@ -1932,10 +2060,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) -#else +#elif defined(TIM1) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8)) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) + if ((InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR11)) +#else + if ((InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8)) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM4 */ { /* Select the Input trigger */ @@ -1971,19 +2106,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected -#if defined(TIM4) - * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR0: Internal trigger 0 selected (*) + * @arg TIM_TS_ITR1: Internal trigger 1 selected (*) + * @arg TIM_TS_ITR2: Internal trigger 2 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 3 selected (*) * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected - * @arg TIM_TS_ITR11: Internal trigger 11 selected -#else - * @arg TIM_TS_ITR7: Internal trigger 7 selected - * @arg TIM_TS_ITR8: Internal trigger 8 selected -#endif + * @arg TIM_TS_ITR11: Internal trigger 11 selected (*) * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer @@ -2004,10 +2137,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) -#else +#elif defined(TIM1) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8)) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) + if ((InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR11)) +#else + if ((InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8)) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM4 */ { /* Select the Input trigger */ @@ -2044,19 +2184,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected -#if defined(TIM4) - * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR0: Internal trigger 0 selected (*) + * @arg TIM_TS_ITR1: Internal trigger 1 selected (*) + * @arg TIM_TS_ITR2: Internal trigger 2 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 3 selected (*) * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected - * @arg TIM_TS_ITR11: Internal trigger 11 selected -#else - * @arg TIM_TS_ITR7: Internal trigger 7 selected - * @arg TIM_TS_ITR8: Internal trigger 8 selected -#endif + * @arg TIM_TS_ITR11: Internal trigger 11 selected (*) * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer @@ -2077,10 +2215,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) -#else +#elif defined(TIM1) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8)) +#else +#if defined(USB_OTG_HS) || defined(USB_DRD_FS) + if ((InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR11)) +#else + if ((InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8)) +#endif /* (USB_OTG_HS) || (USB_DRD_FS)*/ #endif /* TIM4 */ { /* Select the Input trigger */ @@ -2143,6 +2288,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; +#if defined(TIM_CR2_MMS2) /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) { @@ -2154,6 +2300,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; } +#endif /* TIM_CR2_MMS2 */ /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; @@ -2228,6 +2375,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); +#if defined(TIM_BDTR_BK2E) if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ @@ -2242,6 +2390,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } +#endif /* TIM_BDTR_BK2E */ /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; @@ -2292,6 +2441,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM_AF1_BKINP_Pos; break; } +#if defined(COMP1) && defined(COMP2) case TIM_BREAKINPUTSOURCE_COMP1: { bkin_enable_mask = TIM_AF1_BKCMP1E; @@ -2308,6 +2458,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, bkin_polarity_bitpos = TIM_AF1_BKCMP2P_Pos; break; } +#endif /* COMP1 && COMP2 */ default: { @@ -2338,6 +2489,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, htim->Instance->AF1 = tmporx; break; } +#if defined(TIM_BDTR_BK2E) case TIM_BREAKINPUT_BRK2: { /* Get the TIMx_AF2 register value */ @@ -2355,6 +2507,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, htim->Instance->AF2 = tmporx; break; } +#endif /* TIM_BDTR_BK2E */ default: status = HAL_ERROR; break; @@ -2369,7 +2522,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. - * For TIM1, the parameter can take one of the following values: + * For TIM1, the parameter can take one of the following values: (**) * @arg TIM_TIM1_ETR_GPIO TIM1_ETR is not connected to I/O * @arg TIM_TIM1_ETR_COMP1 TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2 TIM1_ETR is connected to COMP2 output @@ -2380,35 +2533,35 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * * For TIM2, the parameter can take one of the following values: * @arg TIM_TIM2_ETR_GPIO TIM2_ETR is not connected to I/O - * @arg TIM_TIM2_ETR_COMP1 TIM2_ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2 TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_COMP1 TIM2_ETR is connected to COMP1 output (*) + * @arg TIM_TIM2_ETR_COMP2 TIM2_ETR is connected to COMP2 output (*) * @arg TIM_TIM2_ETR_HSI TIM2_ETR is connected to HSI - * @arg TIM_TIM2_ETR_TIM3_ETR TIM2_ETR is connected to TIM3 ETR -#if defined(TIM4) - * @arg TIM_TIM2_ETR_TIM4_ETR TIM2_ETR is connected to TIM4 ETR -#endif + * @arg TIM_TIM2_ETR_TIM3_ETR TIM2_ETR is connected to TIM3 ETR (*) + * @arg TIM_TIM2_ETR_TIM4_ETR TIM2_ETR is connected to TIM4 ETR (*) * @arg TIM_TIM2_ETR_LSE TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_ADC4_AWD1 TIM2_ETR is connected to ADC4 AWD1 (*) + * @arg TIM_TIM2_ETR_ADC4_AWD2 TIM2_ETR is connected to ADC4 AWD2 (*) + * @arg TIM_TIM2_ETR_ADC4_AWD3 TIM2_ETR is connected to ADC4 AWD3 (*) * - * For TIM3, the parameter can take one of the following values: + * For TIM3, the parameter can take one of the following values: (**) * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is not connected to I/O * @arg TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output * @arg TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output * @arg TIM_TIM3_ETR_HSI TIM3_ETR is connected to HSI * @arg TIM_TIM3_ETR_TIM2_ETR TIM3_ETR is connected to TIM2 ETR -#if defined(TIM4) - * @arg TIM_TIM3_ETR_TIM4_ETR TIM3_ETR is connected to TIM4 ETR -#endif + * @arg TIM_TIM3_ETR_TIM4_ETR TIM3_ETR is connected to TIM4 ETR (*) * @arg TIM_TIM3_ETR_ADC4_AWD2 TIM3_ETR is connected to ADC4 AWD2 * @arg TIM_TIM3_ETR_ADC4_AWD3 TIM3_ETR is connected to ADC4 AWD3 -#if defined(TIM4) * - * For TIM4, the parameter can take one of the following values: + * For TIM4, the parameter can take one of the following values: (**) * @arg TIM_TIM4_ETR_GPIO TIM4_ETR is not connected to I/O * @arg TIM_TIM4_ETR_COMP1 TIM4_ETR is connected to COMP1 output * @arg TIM_TIM4_ETR_COMP2 TIM4_ETR is connected to COMP2 output * @arg TIM_TIM4_ETR_HSI TIM4_ETR is connected to HSI * @arg TIM_TIM4_ETR_TIM3_ETR TIM4_ETR is connected to TIM3 ETR -#endif + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. \n * * @retval HAL status */ @@ -2436,23 +2589,23 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_CHANNEL_2: TI2 input channel * @arg TIM_CHANNEL_4: TI4 input channel * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: - * For TIM1, the parameter is one of the following values: + * For TIM1, the parameter is one of the following values: (**) * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output * * For TIM2, the parameter is one of the following values: * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO - * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output - * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output + * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output (*) * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO - * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output - * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output + * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output (*) * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*) + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*) * - * For TIM3, the parameter is one of the following values: + * For TIM3, the parameter is one of the following values: (**) * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output @@ -2460,8 +2613,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP1 output * -#if defined(TIM4) - * For TIM4, the parameter is one of the following values: + * For TIM4, the parameter is one of the following values: (**) * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output @@ -2469,7 +2621,6 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP1 output * -#endif * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO @@ -2485,6 +2636,9 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32 + * + * (*) Value not defined in all devices. + * (**) Timer instance not available on all devices. \n * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) @@ -2528,6 +2682,7 @@ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISel return status; } +#if defined(TIM_CCR5_CCR5) /** * @brief Group channel 5 and channel 1, 2 or 3 * @param htim TIM handle. @@ -2563,6 +2718,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan return HAL_OK; } +#endif /* TIM_CCR5_CCR5 */ /** * @brief Disarm the designated break input (when it operates in bidirectional mode). @@ -2600,6 +2756,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } +#if defined(TIM_BDTR_BK2DSRM) case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2612,6 +2769,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } +#endif /* TIM_BDTR_BK2DSRM */ default: status = HAL_ERROR; break; @@ -2665,6 +2823,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3 break; } +#if defined(TIM_BDTR_BK2DSRM) case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -2687,6 +2846,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint3 } break; } +#endif /* TIM_BDTR_BK2DSRM */ default: status = HAL_ERROR; break; @@ -3094,6 +3254,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) */ } +#if defined(TIM_BDTR_BK2E) /** * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle @@ -3108,6 +3269,7 @@ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) the HAL_TIMEx_Break2Callback could be implemented in the user file */ } +#endif /* TIM_BDTR_BK2E */ /** * @brief Encoder index callback in non-blocking mode @@ -3203,10 +3365,11 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) @@ -3285,6 +3448,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } +#if defined(TIM_CCER_CC2NE) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; @@ -3297,6 +3461,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } +#endif /* TIM_CCER_CC2NE */ else { /* nothing to do */ @@ -3325,6 +3490,7 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } +#if defined(TIM_CCER_CC2NE) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; @@ -3340,6 +3506,7 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } +#endif /* TIM_CCER_CC2NE */ else { /* nothing to do */ @@ -3359,10 +3526,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected (*) + * @arg TIM_CHANNEL_3: TIM Channel 3 selected (*) + * @arg TIM_CHANNEL_4: TIM Channel 4 selected (*) + * (*) Value not defined for all devices * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_timebase_tim_template.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_timebase_tim_template.c index 2060c01c3..76fbb71d7 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_timebase_tim_template.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_timebase_tim_template.c @@ -116,6 +116,10 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) Status = HAL_TIM_Base_Init(&TimHandle); if (Status == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif + /* Start the TIM time Base generation in interrupt mode */ Status = HAL_TIM_Base_Start_IT(&TimHandle); if (Status == HAL_OK) @@ -132,9 +136,6 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) } } } -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) - HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); -#endif HAL_NVIC_EnableIRQ(TIM16_IRQn); diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c index e46f2954e..baed117d7 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart.c @@ -1014,75 +1014,76 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c index 49d92c7e2..af7385cd5 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -253,12 +253,11 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -323,19 +322,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -343,13 +342,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -923,17 +922,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c index 7a00eb73a..f03715619 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_rcc.c @@ -41,7 +41,7 @@ /** @addtogroup RCC_LL_Private_Macros * @{ */ -#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) +#if defined(STM32WBA62xx) || defined(STM32WBA63xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) || defined (STM32WBA6Mxx) #if defined(USART2) #define IS_LL_RCC_USART2_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) #else diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c index 71cff9338..04981dae7 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_tim.c @@ -159,6 +159,7 @@ #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) +#if defined(TIM_BDTR_BK2E) #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) @@ -185,6 +186,7 @@ #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) +#endif /* TIM_BDTR_BK2E */ #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) @@ -201,8 +203,12 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +#if defined(TIM_CCER_CC5E) static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +#endif /* TIM_CCER_CC6E */ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); @@ -234,16 +240,18 @@ ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); - if (TIMx == TIM1) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); - } - else if (TIMx == TIM2) + if (TIMx == TIM2) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } +#if defined(TIM1) + else if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } +#endif /* TIM1 */ #if defined(TIM3) else if (TIMx == TIM3) { @@ -402,12 +410,16 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_ case LL_TIM_CHANNEL_CH4: result = OC4Config(TIMx, TIM_OC_InitStruct); break; +#if defined(TIM_CCER_CC5E) case LL_TIM_CHANNEL_CH5: result = OC5Config(TIMx, TIM_OC_InitStruct); break; +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) case LL_TIM_CHANNEL_CH6: result = OC6Config(TIMx, TIM_OC_InitStruct); break; +#endif /* TIM_CCER_CC6E */ default: break; } @@ -682,10 +694,12 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; +#if defined(TIM_BDTR_BK2E) TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; +#endif /* TIM_BDTR_BK2E */ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; } @@ -734,6 +748,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); +#if defined(TIM_BDTR_BK2E) if (IS_TIM_BKIN2_INSTANCE(TIMx)) { @@ -748,6 +763,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); } +#endif /* TIM_BDTR_BK2E */ /* Set TIMx_BDTR */ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); @@ -889,6 +905,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); +#if defined(TIM_CR2_OIS2) if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); @@ -908,6 +925,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); } +#endif /* TIM_CR2_OIS2 */ /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); @@ -968,6 +986,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); +#if defined(TIM_CR2_OIS3) if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); @@ -987,6 +1006,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); } +#endif /* TIM_CR2_OIS3 */ /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); @@ -1047,6 +1067,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); +#if defined(TIM_CR2_OIS4) if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); @@ -1066,6 +1087,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); } +#endif /* TIM_CR2_OIS4 */ /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); @@ -1082,6 +1104,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM return SUCCESS; } +#if defined(TIM_CCER_CC5E) /** * @brief Configure the TIMx output channel 5. * @param TIMx Timer Instance @@ -1142,7 +1165,9 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM return SUCCESS; } +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) /** * @brief Configure the TIMx output channel 6. * @param TIMx Timer Instance @@ -1202,6 +1227,7 @@ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM return SUCCESS; } +#endif /* TIM_CCER_CC6E */ /** * @brief Configure the TIMx input channel 1. diff --git a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_usb.c b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_usb.c index f2ebc5f60..47a92d9f9 100644 --- a/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_usb.c +++ b/stm32cube/stm32wbaxx/drivers/src/stm32wbaxx_ll_usb.c @@ -33,6 +33,9 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** @@ -46,7 +49,7 @@ */ #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB_OTG_HS) +#if defined (USB_OTG_HS) || defined (USB_DRD_FS) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -545,6 +548,7 @@ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) return speed; } +#if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint * @param USBx Selected device @@ -754,17 +758,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -889,11 +893,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t dma_enable = (USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) >> 0x5U; + uint32_t RegVal; /* IN endpoint */ if (ep->is_in == 1U) @@ -908,37 +914,145 @@ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy { count++; - if (count > 10000U) + if (count > 0xF0000U) { ret = HAL_ERROR; break; } - } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); } } else /* OUT endpoint */ { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + } + if (dma_enable == 0U) + { do { count++; - if (count > 10000U) + if (count > 0xF0000U) { ret = HAL_ERROR; break; } - } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } while (((USBx->GINTSTS & USB_OTG_GINTSTS_RXFLVL) & USB_OTG_GINTSTS_RXFLVL) != USB_OTG_GINTSTS_RXFLVL); + + /* POP the RX status register to generate the NAK Effective interrupt */ + RegVal = USBx->GRXSTSP; + UNUSED(RegVal); } + + /* Wait for Global NAK effective to be set */ + count = 0U; + + do + { + count++; + + if (count > 0xF0000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) + & USB_OTG_GINTSTS_BOUTNAKEFF) != USB_OTG_GINTSTS_BOUTNAKEFF); + + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + /* Wait for EP disable to take effect */ + count = 0U; + + do + { + count++; + + if (count > 0xF0000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_EPDISD) + & USB_OTG_DOEPINT_EPDISD) != USB_OTG_DOEPINT_EPDISD); + + /* Clear OUT EP disable interrupt */ + USBx_OUTEP(ep->num)->DOEPINT |= USB_OTG_DOEPINT_EPDISD; + + /* Clear Global OUT NAK */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; } return ret; } +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated @@ -1020,67 +1134,6 @@ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t return ((void *)pDest); } -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - /** * @brief USB_StopDevice : Stop the usb device mode * @param USBx Selected device @@ -1291,8 +1344,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { @@ -1374,8 +1427,15 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + count = 10U; + + /* few cycles before setting core reset */ + while (count > 0U) + { + count--; + } + /* Core Soft Reset */ - count = 0U; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do @@ -1571,13 +1631,13 @@ HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state } /** - * @brief Return Host Core speed + * @brief Return Host Port speed * @param USBx Selected device - * @retval speed : Host speed + * @retval speed : Host port device speed * This parameter can be one of these values: - * @arg HCD_SPEED_HIGH: High speed mode - * @arg HCD_SPEED_FULL: Full speed mode - * @arg HCD_SPEED_LOW: Low speed mode + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode */ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) { @@ -1600,6 +1660,7 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel * @param USBx Selected device @@ -2100,6 +2161,34 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) return HAL_OK; } +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param ch_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir) +{ + UNUSED(ch_dir); + + __IO uint32_t tmpreg; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + + if ((tmpreg & USB_OTG_HCCHAR_CHDIS) == 0U) + { + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + + return HAL_OK; +} +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + /** * @brief Initiate Do Ping protocol * @param USBx Selected device @@ -2225,14 +2314,1451 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) } #endif /* defined (USB_OTG_HS) */ +#if defined (USB_DRD_FS) +static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); +#if defined (HAL_HCD_MODULE_ENABLED) +#if (USE_USB_DOUBLE_BUFFER == 1U) +static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t ch_reg, + uint32_t *len); + +static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t len); +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + /** - * @} + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status */ +static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx) +{ + /* Disable Host Mode */ + USBx->CNTR &= ~USB_CNTR_HOST; + + /* Force Reset IP */ + USBx->CNTR |= USB_CNTR_USBRST; + + return HAL_OK; +} /** - * @} + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status */ -#endif /* defined (USB_OTG_HS) */ +HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + UNUSED(cfg); + + if (USBx == NULL) + { + return HAL_ERROR; + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + return ret; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx) +{ + uint32_t winterruptmask; + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + + /* Set interrupt mask */ + USBx->CNTR = winterruptmask; + + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx) +{ + uint32_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM | USB_CNTR_L1REQM; + + /* Clear interrupt mask */ + USBx->CNTR &= ~winterruptmask; + + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of the these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode) +{ + if (mode == USB_DEVICE_MODE) + { + USBx->CNTR &= ~USB_CNTR_HOST; + } + else if (mode == USB_HOST_MODE) + { + USBx->CNTR |= USB_CNTR_HOST; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(cfg); + + /* Force Reset */ + USBx->CNTR = USB_CNTR_USBRST; + + /* Release Reset */ + USBx->CNTR &= ~USB_CNTR_USBRST; + + /* Set the Device Mode */ + ret = USB_SetCurrentMode(USBx, USB_DEVICE_MODE); + + /* Clear pending interrupts */ + USBx->ISTR = 0U; + + return ret; +} + +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + + +#if defined (HAL_PCD_MODULE_ENABLED) +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t wEpRegVal; + + wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; + + /* initialize Endpoint */ + switch (ep->type) + { + case EP_TYPE_CTRL: + wEpRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wEpRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wEpRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wEpRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; + break; + } + + PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_VTRX | USB_EP_VTTX)); + + PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); + + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + } + else + { + /* Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); + + /* Set the endpoint Receive buffer counter */ + PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + if (ep->num == 0U) + { + /* Configure VALID status for EP0 */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + else + { + /* Configure NAK status for OUT Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); + } + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer */ + else + { + if (ep->type == EP_TYPE_BULK) + { + /* Set bulk endpoint as double buffered */ + PCD_SET_BULK_EP_DBUF(USBx, ep->num); + } + else + { + /* Set the ISOC endpoint in double buffer mode */ + PCD_CLEAR_EP_KIND(USBx, ep->num); + } + + /* Set buffer address for double buffered mode */ + PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); + + if (ep->is_in == 0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT */ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + return ret; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + if (ep->doublebuffer == 0U) + { + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Configure DISABLE status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure DISABLE status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + /* Double Buffer */ + else + { + if (ep->is_in == 0U) + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + /* Reset value of the data toggle bits for the endpoint out*/ + PCD_TX_DTOG(USBx, ep->num); + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + else + { + /* Clear the data toggle bits for the endpoint IN/OUT*/ + PCD_CLEAR_RX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_RX_DTOG(USBx, ep->num); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + uint32_t len; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint16_t pmabuffer; + uint16_t wEPVal; +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Multi packet transfer */ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + } + else + { + len = ep->xfer_len; + } + + /* configure and validate Tx endpoint */ + if (ep->doublebuffer == 0U) + { + USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else + { + /* double buffer bulk management */ + if (ep->type == EP_TYPE_BULK) + { + if (ep->xfer_len_db > ep->maxpacket) + { + /* enable double buffer */ + PCD_SET_BULK_EP_DBUF(USBx, ep->num); + + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the two first buffer in the Buffer0 & Buffer1 */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + /* auto Switch to single buffer mode when transfer xfer_len_db; + + /* disable double buffer mode for Bulk endpoint */ + PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); + + /* Set Tx count with nbre of byte to be transmitted */ + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + else /* Manage isochronous double buffer IN mode */ + { + /* Each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the data buffer */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); + } + else /* OUT endpoint */ + { + if (ep->doublebuffer == 0U) + { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + + /* Multi packet transfer */ + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len -= ep->maxpacket; + } + else + { + ep->xfer_len = 0U; + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else + { + /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ + /* Set the Double buffer counter */ + if (ep->type == EP_TYPE_BULK) + { + /* Coming from ISR */ + if (ep->xfer_count != 0U) + { + /* Update last value to check if there is blocking state */ + wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); + + /* Blocking State */ + if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || + (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) + { + PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); + } + } + } + /* iso out double */ + else if (ep->type == EP_TYPE_ISOC) + { + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; + } + else + { + return HAL_ERROR; + } + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPSetStall set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + if (ep->is_in != 0U) + { + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); + } + else + { + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + if (ep->is_in != 0U) + { + PCD_CLEAR_TX_DTOG(USBx, ep->num); + + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) +{ + /* IN endpoint */ + if (ep->is_in == 1U) + { + if (ep->doublebuffer == 0U) + { + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); + } + else + { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); + } + } + } + else /* OUT endpoint */ + { + if (ep->doublebuffer == 0U) + { + if (ep->type != EP_TYPE_ISOC) + { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); + } + else + { + /* Configure RX Endpoint to disabled state */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); + } + } + } + + return HAL_OK; +} +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +/** + * @brief USB_StopDevice Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx) +{ + /* disable all interrupts and force USB reset */ + USBx->CNTR = USB_CNTR_USBRST; + + /* clear interrupt status register */ + USBx->ISTR = 0U; + + /* switch-off device */ + USBx->CNTR = (USB_CNTR_USBRST | USB_CNTR_PDWN); + + return HAL_OK; +} + +/** + * @brief USB_SetDevAddress Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address) +{ + if (address == 0U) + { + /* set device address and enable function */ + USBx->DADDR = USB_DADDR_EF; + } + + return HAL_OK; +} + +/** + * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx) +{ + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + USBx->BCDR |= USB_BCDR_DPPU; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx) +{ + /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ + USBx->BCDR &= ~(USB_BCDR_DPPU); + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->ISTR; + return tmpreg; +} + +/** + * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx) +{ + USBx->CNTR |= USB_CNTR_L2RES; + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx) +{ + USBx->CNTR &= ~USB_CNTR_L2RES; + + return HAL_OK; +} + +/** + * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + UNUSED(USBx); + uint32_t WrVal; + uint32_t count; + __IO uint32_t *pdwVal; + uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U; + /* Due to the PMA access 32bit only so the last non word data should be processed alone */ + uint16_t remaining_bytes = wNBytes % 4U; + uint8_t *pBuf = pbUsrBuf; + + /* Check if there is a remaining byte */ + if (remaining_bytes != 0U) + { + NbWords--; + } + + /* Get the PMA Buffer pointer */ + pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr); + + /* Write the Calculated Word into the PMA related Buffer */ + for (count = NbWords; count != 0U; count--) + { + *pdwVal = __UNALIGNED_UINT32_READ(pBuf); + pdwVal++; + /* Increment pBuf 4 Time as Word Increment */ + pBuf++; + pBuf++; + pBuf++; + pBuf++; + } + + /* When Number of data is not word aligned, write the remaining Byte */ + if (remaining_bytes != 0U) + { + WrVal = 0U; + + do + { + WrVal |= (uint32_t)(*(uint8_t *)pBuf) << (8U * count); + count++; + pBuf++; + remaining_bytes--; + } while (remaining_bytes != 0U); + + *pdwVal = WrVal; + } +} + +/** + * @brief Copy data from packet memory area (PMA) to user memory buffer + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + UNUSED(USBx); + uint32_t count; + uint32_t RdVal; + __IO uint32_t *pdwVal; + uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U; + /*Due to the PMA access 32bit only so the last non word data should be processed alone */ + uint16_t remaining_bytes = wNBytes % 4U; + uint8_t *pBuf = pbUsrBuf; + + /* Get the PMA Buffer pointer */ + pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr); + + /* if nbre of byte is not word aligned decrement the nbre of word*/ + if (remaining_bytes != 0U) + { + NbWords--; + } + + /*Read the Calculated Word From the PMA related Buffer*/ + for (count = NbWords; count != 0U; count--) + { + __UNALIGNED_UINT32_WRITE(pBuf, *pdwVal); + + pdwVal++; + pBuf++; + pBuf++; + pBuf++; + pBuf++; + } + + /*When Number of data is not word aligned, read the remaining byte*/ + if (remaining_bytes != 0U) + { + RdVal = *(__IO uint32_t *)pdwVal; + + do + { + *(uint8_t *)pBuf = (uint8_t)(RdVal >> (8U * (uint8_t)(count))); + count++; + pBuf++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } +} + + +/*------------------------------------------------------------------------*/ +/* HOST API */ +/*------------------------------------------------------------------------*/ + +/** + * @brief USB_HostInit Initializes the USB DRD controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) +{ + UNUSED(cfg); + + /* Clear All Pending Interrupt */ + USBx->ISTR = 0U; + + /* Disable all interrupts */ + USBx->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | + USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | + USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); + + /* Clear All Pending Interrupt */ + USBx->ISTR = 0U; + + /* Set the PullDown on the PHY */ + USBx->BCDR |= USB_BCDR_DPPD; + + /* Enable Global interrupt */ + USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | + USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | + USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); + + return HAL_OK; +} + + +/** + * @brief USB_DRD_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx) +{ + /* Force USB Reset */ + USBx->CNTR |= USB_CNTR_USBRST; + HAL_Delay(100); + /* Release USB Reset */ + USBx->CNTR &= ~USB_CNTR_USBRST; + HAL_Delay(30); + + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed Host speed + * This parameter can be one of these values + * @arg USB_DRD_SPEED_FS Full speed mode + * @arg USB_DRD_SPEED_LS Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) +{ + if ((USBx->ISTR & USB_ISTR_LS_DCONN) != 0U) + { + return USB_DRD_SPEED_LS; + } + else + { + return USB_DRD_SPEED_FS; + } +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) +{ + return USBx->FNR & 0x7FFU; +} + +#if defined (HAL_HCD_MODULE_ENABLED) +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param phy_ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_DRD_SPEED_FULL Full speed mode + * @arg USB_DRD_SPEED_LOW Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL Control type + * @arg EP_TYPE_ISOC Isochronous type + * @arg EP_TYPE_BULK Bulk type + * @arg EP_TYPE_INTR Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t wChRegVal; + uint32_t HostCoreSpeed; + + UNUSED(mps); + + wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; + + /* Initialize host Channel */ + switch (ep_type) + { + case EP_TYPE_CTRL: + wChRegVal |= USB_EP_CONTROL; + break; + + case EP_TYPE_BULK: + wChRegVal |= USB_EP_BULK; + break; + + case EP_TYPE_INTR: + wChRegVal |= USB_EP_INTERRUPT; + break; + + case EP_TYPE_ISOC: + wChRegVal |= USB_EP_ISOCHRONOUS; + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Clear device address, Endpoint number and Low Speed Endpoint fields */ + wChRegVal &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFU << 27)); + + /* Set device address and Endpoint number associated to the channel */ + wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | + ((uint32_t)epnum & 0x0FU)); + + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* Set the device speed in case using HUB FS with device LS */ + if ((speed == USB_DRD_SPEED_LS) && (HostCoreSpeed == USB_DRD_SPEED_FS)) + { + wChRegVal |= USB_CHEP_LSEP; + } + + /* Update the channel register value */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); + + return ret; +} + +/** + * @brief Set the channel Kind (Single/double buffer mode) + * @param USBx Selected device + * @param phy_ch_num Selected device + * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, + uint8_t phy_ch_num, uint8_t db_state) +{ + uint32_t tmp; + + if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) + { + tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; + } + else + { + tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; + } + + /* Set the device speed in case using HUB FS with device LS */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); + + return HAL_OK; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) +{ + uint32_t len; + uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; +#if (USE_USB_DOUBLE_BUFFER == 1U) + uint32_t ch_reg = USB_DRD_GET_CHEP(USBx, phy_ch_num); +#endif /* USE_USB_DOUBLE_BUFFER */ + + if (hc->ch_dir == CH_IN_DIR) /* In Channel */ + { + /* Multi packet transfer */ + if (hc->xfer_len > hc->max_packet) + { + len = hc->max_packet; + } + else + { + len = hc->xfer_len; + } + + if (hc->doublebuffer == 0U) + { + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_RX_DTOG(USBx, phy_ch_num); + } + } + + /* Set RX buffer count */ + USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else if (hc->ep_type == EP_TYPE_BULK) + { + /* Double buffer activated */ + if ((hc->xfer_len > hc->max_packet)) + { + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); + + /* Set the Double buffer counter */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); + } + else /* Switch to single buffer mode */ + { + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); + + /* Set RX buffer count */ + USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); + } + } + else /* Isochronous */ + { + /* Set the Double buffer counter */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); + } +#endif /* USE_USB_DOUBLE_BUFFER */ + + /* Enable host channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); + } + else /* Out Channel */ + { + /* Multi packet transfer */ + if (hc->xfer_len > hc->max_packet) + { + len = hc->max_packet; + } + else + { + len = hc->xfer_len; + } + + /* Configure and validate Tx endpoint */ + if (hc->doublebuffer == 0U) + { + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len); + USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len); + + /* SET PID SETUP */ + if ((hc->data_pid) == HC_PID_SETUP) + { + USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); + } + + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_TX_DTOG(USBx, phy_ch_num); + } + } + } +#if (USE_USB_DOUBLE_BUFFER == 1U) + else if (hc->ep_type == EP_TYPE_BULK) + { + (void)USB_HC_BULK_DB_StartXfer(USBx, hc, ch_reg, &len); + } + else + { + (void)USB_HC_ISO_DB_StartXfer(USBx, hc, len); + } +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + /* Enable host channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, hc->phy_ch_num, USB_CH_TX_VALID); + } + + return HAL_OK; +} + +#if (USE_USB_DOUBLE_BUFFER == 1U) +/** + * @brief Start Transfer of Channel isochronous out double buffer + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param len Transfer Length + * @retval HAL state + */ +static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t len) +{ + uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; + + /* check the DTOG_TX to determine in which buffer we should write */ + if ((USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_DTOG_TX) != 0U) + { + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)len); + } + else + { + /* DTOGTX=0 */ + /* Set the Double buffer counter for pmabuffer0 */ + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)len); + } + + return HAL_OK; +} + +/** + * @brief Start Transfer of Channel bulk out double buffer + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param ch_reg snapshot of the CHEPR register + * @param len Transfer Length + * @retval HAL state + */ +static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, + USB_DRD_HCTypeDef *hc, + uint32_t ch_reg, + uint32_t *len) +{ + uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; + + /* -Double Buffer Mangement- */ + if (hc->xfer_len_db > hc->max_packet) + { + /* enable double buffer mode */ + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); + *len = hc->max_packet; + hc->xfer_len_db -= *len; + + /* Prepare two buffer before enabling host */ + if ((ch_reg & USB_CH_DTOG_TX) == 0U) + { + /* Write Buffer0 */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); + } + else + { + /* Write Buffer1 */ + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len); + } + + hc->xfer_buff += *len; + + /* Multi packet transfer */ + if (hc->xfer_len_db > hc->max_packet) + { + hc->xfer_len_db -= *len; + } + else + { + *len = hc->xfer_len_db; + hc->xfer_len_db = 0U; + } + + if ((ch_reg & USB_CH_DTOG_TX) == 0U) + { + /* Write Buffer1 */ + USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len); + } + else + { + /* Write Buffer0 */ + USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); + } + } + else + { + /* Disable bulk double buffer mode */ + (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); + USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); + USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)*len); + } + + return HAL_OK; +} +#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ + + +/** + * @brief Halt a host channel in + * @param USBx Selected device + * @param hc_num Host Channel number + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +{ + /* Set disable to Channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS); + + return HAL_OK; +} + + +/** + * @brief Halt a host channel out + * @param USBx Selected device + * @param hc_num Host Channel number + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +{ + /* Set disable to Channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS); + + return HAL_OK; +} + +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param ch_num Host Channel number + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch, uint8_t ch_dir) +{ + if (ch_dir == CH_IN_DIR) + { + /* Enable TX host Channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_VALID); + } + else + { + /* Enable RX host Channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_VALID); + } + + return HAL_OK; +} +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) +{ + USBx->ISTR &= ~(USB_ISTR_DIR | USB_ISTR_L1REQ | + USB_ISTR_ESOF | USB_ISTR_SOF | + USB_ISTR_RESET | USB_ISTR_DCON | + USB_ISTR_SUSP | USB_ISTR_WKUP | + USB_ISTR_ERR | USB_ISTR_PMAOVR | + USB_ISTR_CTR); + + /* Set PowerDown */ + USBx->CNTR |= USB_CNTR_PDWN; + + /* Force a Reset */ + USBx->CNTR |= USB_CNTR_USBRST; + + return HAL_OK; +} +#endif /* defined (USB_DRD_FS) */ +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ /** diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba52xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba52xx.h index ade3f2dbe..b69d27591 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba52xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba52xx.h @@ -160,12 +160,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20008000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2000FFFF /* end address of SAU region 3 */ /* // Region is @@ -207,17 +207,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20018000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2001FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba54xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba54xx.h index 30b3a85f9..4ec526960 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba54xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba54xx.h @@ -160,12 +160,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20008000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2000FFFF /* end address of SAU region 3 */ /* // Region is @@ -207,17 +207,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20018000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2001FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba55xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba55xx.h index 07ac11b16..bccfaa29e 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba55xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba55xx.h @@ -160,12 +160,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20008000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2000FFFF /* end address of SAU region 3 */ /* // Region is @@ -207,17 +207,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20018000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2001FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba5mxx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba5mxx.h index 8c9eae96e..928ea47fa 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba5mxx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba5mxx.h @@ -160,12 +160,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20008000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2000FFFF /* end address of SAU region 3 */ /* // Region is @@ -207,17 +207,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20018000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2001FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba62xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba62xx.h index 381638e3d..afae4bbc8 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba62xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba62xx.h @@ -151,12 +151,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20040000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20038000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2007FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2006FFFF /* end address of SAU region 3 */ /* // Region is @@ -198,17 +198,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20078000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2007FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba63xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba63xx.h index adb3d94ea..bbc28583f 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba63xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba63xx.h @@ -151,12 +151,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20040000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20038000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2007FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2006FFFF /* end address of SAU region 3 */ /* // Region is @@ -198,17 +198,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20078000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2007FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba64xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba64xx.h index f4d144040..0d86f1b37 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba64xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba64xx.h @@ -151,12 +151,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20040000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20038000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2007FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2006FFFF /* end address of SAU region 3 */ /* // Region is @@ -198,17 +198,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20078000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2007FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba65xx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba65xx.h index ccd342487..be12e5308 100644 --- a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba65xx.h +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba65xx.h @@ -151,12 +151,12 @@ /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START3 0x20040000 /* start address of SAU region 3 */ +#define SAU_INIT_START3 0x20038000 /* start address of SAU region 3 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END3 0x2007FFFF /* end address of SAU region 3 */ +#define SAU_INIT_END3 0x2006FFFF /* end address of SAU region 3 */ /* // Region is @@ -198,17 +198,17 @@ // Initialize SAU Region 5 // Setup SAU Region 5 memory attributes */ -#define SAU_INIT_REGION5 0 +#define SAU_INIT_REGION5 1 /* // Start Address <0-0xFFFFFFE0> */ -#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ +#define SAU_INIT_START5 0x20078000 /* start address of SAU region 5 */ /* // End Address <0x1F-0xFFFFFFFF> */ -#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ +#define SAU_INIT_END5 0x2007FFFF /* end address of SAU region 5 */ /* // Region is diff --git a/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba6mxx.h b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba6mxx.h new file mode 100644 index 000000000..09a90b1ff --- /dev/null +++ b/stm32cube/stm32wbaxx/soc/Templates/partition_stm32wba6mxx.h @@ -0,0 +1,594 @@ +/** + ****************************************************************************** + * @file partition_stm32wba6mxx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA6Mxx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef PARTITION_STM32WBA6MXX_H +#define PARTITION_STM32WBA6MXX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x08100000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x081FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF90000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BFB7FFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C0FE000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C0FFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20038000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2006FFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x40000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x4FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x20078000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x2007FFFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// RADIO_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_S_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_S_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_AUDIOSYNC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI19_RADIO_IO_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI20_RADIO_IO_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + +} + +#endif /* PARTITION_STM32WBA6MXX_H */ diff --git a/stm32cube/stm32wbaxx/soc/partition_stm32wbaxx.h b/stm32cube/stm32wbaxx/soc/partition_stm32wbaxx.h index ae3aae6d3..f984ac000 100644 --- a/stm32cube/stm32wbaxx/soc/partition_stm32wbaxx.h +++ b/stm32cube/stm32wbaxx/soc/partition_stm32wbaxx.h @@ -58,6 +58,8 @@ #include "partition_stm32wba64xx.h" #elif defined(STM32WBA65xx) #include "partition_stm32wba65xx.h" +#elif defined(STM32WBA6Mxx) + #include "partition_stm32wba6mxx.h" #else #error "Please select first the target STM32WBAxx device used in your application (in stm32wbaxx.h file)" #endif diff --git a/stm32cube/stm32wbaxx/soc/stm32wba50xx.h b/stm32cube/stm32wbaxx/soc/stm32wba50xx.h index 736533e35..901e674ea 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wba50xx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wba50xx.h @@ -334,7 +334,7 @@ typedef struct uint32_t RESERVED7[3]; /*!< Reserved7, Address offset: 0x4C-0x54 */ __IO uint32_t WRPAR; /*!< FLASH WRP area A address register, Address offset: 0x58 */ __IO uint32_t WRPBR; /*!< FLASH WRP area B address register, Address offset: 0x5C */ - uint32_t RESERVED8[4]; /*!< Reserved3, Address offset: 0x60-0x6C */ + uint32_t RESERVED8[4]; /*!< Reserved8, Address offset: 0x60-0x6C */ __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ @@ -700,9 +700,9 @@ typedef struct __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensation Cell Control&Status register,Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensation Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensation Cell Code register, Address offset: 0x24 */ uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ } SYSCFG_TypeDef; @@ -1162,147 +1162,147 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Pos (11UL) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ -#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Pos (12UL) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ /******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Pos (11UL) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ -#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Pos (12UL) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR1 register *****************/ -#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Pos (0UL) #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Pos (1UL) #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Pos (2UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR1_SCANDIR_Pos (4U) +#define ADC_CFGR1_SCANDIR_Pos (4UL) #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ -#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Pos (5UL) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ -#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Pos (6UL) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Pos (14UL) #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ -#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Pos (21UL) #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -1312,18 +1312,18 @@ typedef struct #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Pos (0UL) #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Pos (2UL) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -1331,89 +1331,89 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Pos (9UL) #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Pos (29UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ /******************** Bit definition for ADC_SMPR register ******************/ -#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Pos (0UL) #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ -#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Pos (4UL) #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Pos (8UL) #define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ -#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Pos (8UL) #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Pos (9UL) #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Pos (10UL) #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Pos (11UL) #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Pos (12UL) #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Pos (13UL) #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Pos (14UL) #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Pos (15UL) #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Pos (16UL) #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Pos (17UL) #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Pos (18UL) #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Pos (19UL) #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Pos (20UL) #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Pos (21UL) #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Pos (22UL) #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Pos (23UL) #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Pos (24UL) #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Pos (25UL) #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ /******************** Bit definition for ADC_AWD1TR register *******************/ -#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Pos (0UL) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ @@ -1429,7 +1429,7 @@ typedef struct #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ -#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Pos (16UL) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ @@ -1446,7 +1446,7 @@ typedef struct #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWDTR2 register *******************/ -#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Pos (0UL) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ @@ -1462,7 +1462,7 @@ typedef struct #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ -#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Pos (16UL) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ @@ -1479,69 +1479,69 @@ typedef struct #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_CHSELR register ****************/ -#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Pos (0UL) #define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Pos (17UL) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Pos (16UL) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Pos (15UL) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Pos (14UL) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Pos (13UL) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Pos (12UL) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Pos (11UL) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Pos (10UL) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Pos (9UL) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Pos (8UL) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Pos (7UL) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Pos (6UL) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Pos (5UL) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Pos (4UL) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Pos (3UL) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Pos (2UL) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Pos (1UL) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Pos (0UL) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Pos (0UL) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Pos (28UL) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ @@ -1549,7 +1549,7 @@ typedef struct #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ -#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Pos (24UL) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ @@ -1557,7 +1557,7 @@ typedef struct #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ -#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Pos (20UL) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ @@ -1565,7 +1565,7 @@ typedef struct #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ -#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Pos (16UL) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ @@ -1573,7 +1573,7 @@ typedef struct #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ -#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Pos (12UL) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ @@ -1581,7 +1581,7 @@ typedef struct #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Pos (8UL) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ @@ -1589,7 +1589,7 @@ typedef struct #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Pos (4UL) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ @@ -1597,7 +1597,7 @@ typedef struct #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Pos (0UL) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ @@ -1606,7 +1606,7 @@ typedef struct #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ /******************** Bit definition for ADC_AWD3TR register *******************/ -#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Pos (0UL) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ @@ -1622,7 +1622,7 @@ typedef struct #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ -#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Pos (16UL) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ @@ -1639,20 +1639,20 @@ typedef struct #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Pos (0UL) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ /******************** Bit definition for ADC_PWRR register ******************/ -#define ADC_PWRR_AUTOFF_Pos (0U) +#define ADC_PWRR_AUTOFF_Pos (0UL) #define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ #define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ -#define ADC_PWRR_DPD_Pos (1U) +#define ADC_PWRR_DPD_Pos (1UL) #define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ #define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ /******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -1675,7 +1675,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -1698,7 +1698,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ /******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Pos (0UL) #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -1711,7 +1711,7 @@ typedef struct /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -1719,10 +1719,10 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Pos (23UL) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ @@ -1733,40 +1733,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ @@ -1777,222 +1777,222 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for AES_CR register *********************/ -#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Pos (0UL) #define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ -#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Pos (1UL) #define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ #define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ #define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ -#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Pos (3UL) #define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ #define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ #define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ -#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Pos (5UL) #define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ #define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ #define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ #define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ -#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Pos (11UL) #define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ -#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Pos (12UL) #define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ -#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Pos (13UL) #define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ #define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ #define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ #define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ -#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Pos (18UL) #define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ #define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ -#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Pos (20UL) #define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ #define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ #define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ #define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ #define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ -#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Pos (24UL) #define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ #define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ #define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ #define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ -#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Pos (31UL) #define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ #define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ /******************* Bit definition for AES_SR register *********************/ -#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Pos (0UL) #define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ -#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Pos (1UL) #define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ -#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Pos (2UL) #define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ -#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Pos (3UL) #define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ #define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ -#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Pos (7UL) #define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ #define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ /******************* Bit definition for AES_DINR register *******************/ -#define AES_DINR_Pos (0U) +#define AES_DINR_Pos (0UL) #define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ /******************* Bit definition for AES_DOUTR register ******************/ -#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Pos (0UL) #define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ /******************* Bit definition for AES_KEYR0 register ******************/ -#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Pos (0UL) #define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ /******************* Bit definition for AES_KEYR1 register ******************/ -#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Pos (0UL) #define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ /******************* Bit definition for AES_KEYR2 register ******************/ -#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Pos (0UL) #define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ /******************* Bit definition for AES_KEYR3 register ******************/ -#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Pos (0UL) #define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ /******************* Bit definition for AES_KEYR4 register ******************/ -#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Pos (0UL) #define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ /******************* Bit definition for AES_KEYR5 register ******************/ -#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Pos (0UL) #define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ /******************* Bit definition for AES_KEYR6 register ******************/ -#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Pos (0UL) #define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ /******************* Bit definition for AES_KEYR7 register ******************/ -#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Pos (0UL) #define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ #define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ /******************* Bit definition for AES_IVR0 register ******************/ -#define AES_IVR0_Pos (0U) +#define AES_IVR0_Pos (0UL) #define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ /******************* Bit definition for AES_IVR1 register ******************/ -#define AES_IVR1_Pos (0U) +#define AES_IVR1_Pos (0UL) #define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ /******************* Bit definition for AES_IVR2 register ******************/ -#define AES_IVR2_Pos (0U) +#define AES_IVR2_Pos (0UL) #define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ /******************* Bit definition for AES_IVR3 register ******************/ -#define AES_IVR3_Pos (0U) +#define AES_IVR3_Pos (0UL) #define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ /******************* Bit definition for AES_SUSP0R register ******************/ -#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Pos (0UL) #define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ /******************* Bit definition for AES_SUSP1R register ******************/ -#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Pos (0UL) #define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ /******************* Bit definition for AES_SUSP2R register ******************/ -#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Pos (0UL) #define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ /******************* Bit definition for AES_SUSP3R register ******************/ -#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Pos (0UL) #define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ /******************* Bit definition for AES_SUSP4R register ******************/ -#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Pos (0UL) #define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ /******************* Bit definition for AES_SUSP5R register ******************/ -#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Pos (0UL) #define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ /******************* Bit definition for AES_SUSP6R register ******************/ -#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Pos (0UL) #define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ /******************* Bit definition for AES_SUSP7R register ******************/ -#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Pos (0UL) #define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ #define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ /******************* Bit definition for AES_IER register ******************/ -#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Pos (0UL) #define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ #define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ -#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Pos (1UL) #define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ #define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ -#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Pos (2UL) #define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ #define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ -#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Pos (3UL) #define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ #define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ /******************* Bit definition for AES_ISR register ******************/ -#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Pos (0UL) #define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ #define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ -#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Pos (1UL) #define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ #define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ -#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Pos (2UL) #define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ #define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ -#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Pos (3UL) #define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ #define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ /******************* Bit definition for AES_ICR register ******************/ -#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Pos (0UL) #define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ #define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ -#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Pos (1UL) #define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ #define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ -#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Pos (2UL) #define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ #define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ -#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Pos (3UL) #define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ #define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ @@ -2002,92 +2002,92 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for DBGMCU_IDCODE register *************/ -#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk -#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /******************** Bit definition for DBGMCU_SCR register *****************/ -#define DBGMCU_SCR_DBG_STOP_Pos (1U) +#define DBGMCU_SCR_DBG_STOP_Pos (1UL) #define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk -#define DBGMCU_SCR_DBG_STANDBY_Pos (2U) +#define DBGMCU_SCR_DBG_STANDBY_Pos (2UL) #define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ #define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk -#define DBGMCU_SCR_DBG_LPMS_Pos (16U) +#define DBGMCU_SCR_DBG_LPMS_Pos (16UL) #define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ #define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk #define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) #define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) #define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) -#define DBGMCU_SCR_DBG_STOPF_Pos (19U) +#define DBGMCU_SCR_DBG_STOPF_Pos (19UL) #define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ #define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk -#define DBGMCU_SCR_DBG_SBF_Pos (20U) +#define DBGMCU_SCR_DBG_SBF_Pos (20UL) #define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ #define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk -#define DBGMCU_SCR_DBG_CS_Pos (24U) +#define DBGMCU_SCR_DBG_CS_Pos (24UL) #define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ #define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk -#define DBGMCU_SCR_DBG_CDS_Pos (25U) +#define DBGMCU_SCR_DBG_CDS_Pos (25UL) #define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ #define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk /******************** Bit definition for DBGMCU_APB1LFZR register ***********/ -#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0UL) #define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) #define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk -#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11UL) #define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) #define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk -#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12UL) #define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) #define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZR register ***********/ -#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11UL) #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) #define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk -#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17UL) #define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) #define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk /******************** Bit definition for DBGMCU_APB7FZR register ***********/ -#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10U) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10UL) #define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) #define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk -#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17UL) #define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) #define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk -#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30UL) #define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) #define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk /******************** Bit definition for DBGMCU_AHB1FZR register ***********/ -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk -#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7UL) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk @@ -2099,274 +2099,274 @@ typedef struct /******************************************************************************/ /******************* Bit definition for DMA_MISR register ****************/ -#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Pos (0UL) #define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ #define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ -#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Pos (1UL) #define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ #define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ -#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Pos (2UL) #define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ #define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ -#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Pos (3UL) #define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ #define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ -#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Pos (4UL) #define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ #define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ -#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Pos (5UL) #define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ #define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ -#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Pos (6UL) #define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ #define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ -#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Pos (7UL) #define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ #define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ /******************* Bit definition for DMA_SMISR register ****************/ -#define DMA_SMISR_MIS0_Pos (0U) +#define DMA_SMISR_MIS0_Pos (0UL) #define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ #define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ -#define DMA_SMISR_MIS1_Pos (1U) +#define DMA_SMISR_MIS1_Pos (1UL) #define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ #define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ -#define DMA_SMISR_MIS2_Pos (2U) +#define DMA_SMISR_MIS2_Pos (2UL) #define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ #define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ -#define DMA_SMISR_MIS3_Pos (3U) +#define DMA_SMISR_MIS3_Pos (3UL) #define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ #define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ -#define DMA_SMISR_MIS4_Pos (4U) +#define DMA_SMISR_MIS4_Pos (4UL) #define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ #define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ -#define DMA_SMISR_MIS5_Pos (5U) +#define DMA_SMISR_MIS5_Pos (5UL) #define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ #define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ -#define DMA_SMISR_MIS6_Pos (6U) +#define DMA_SMISR_MIS6_Pos (6UL) #define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ #define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ -#define DMA_SMISR_MIS7_Pos (7U) +#define DMA_SMISR_MIS7_Pos (7UL) #define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ #define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ /******************* Bit definition for DMA_CLBAR register ****************/ -#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Pos (16UL) #define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ /******************* Bit definition for DMA_CFCR register *******************/ -#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Pos (8UL) #define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ #define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ -#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Pos (9UL) #define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ #define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ -#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Pos (10UL) #define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ #define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ -#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Pos (11UL) #define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ #define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ -#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Pos (12UL) #define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ #define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ -#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Pos (13UL) #define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ #define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ -#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Pos (14UL) #define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ #define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ /******************* Bit definition for DMA_CSR register *******************/ -#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Pos (0UL) #define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ #define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ -#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Pos (8UL) #define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ #define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ -#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Pos (9UL) #define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ #define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ -#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Pos (10UL) #define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ #define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ -#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Pos (11UL) #define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ #define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ -#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Pos (12UL) #define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ #define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ -#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Pos (13UL) #define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ #define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ -#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Pos (14UL) #define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ #define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ -#define DMA_CSR_FIFOL_Pos (16U) +#define DMA_CSR_FIFOL_Pos (16UL) #define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ #define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ /******************* Bit definition for DMA_CCR register ********************/ -#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Pos (0UL) #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ -#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Pos (1UL) #define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ #define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ -#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Pos (2UL) #define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ #define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ -#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Pos (8UL) #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ -#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Pos (9UL) #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ -#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Pos (10UL) #define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ #define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ -#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Pos (11UL) #define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ #define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ -#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Pos (12UL) #define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ #define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ -#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Pos (13UL) #define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ #define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ -#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Pos (14UL) #define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ #define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ -#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Pos (16UL) #define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ #define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ -#define DMA_CCR_LAP_Pos (17U) +#define DMA_CCR_LAP_Pos (17UL) #define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ -#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Pos (22UL) #define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ #define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ #define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ #define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ /******************* Bit definition for DMA_CTR1 register *******************/ -#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Pos (0UL) #define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ #define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ #define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ #define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ -#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Pos (3UL) #define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ #define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ -#define DMA_CTR1_SBL_1_Pos (4U) +#define DMA_CTR1_SBL_1_Pos (4UL) #define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ #define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ -#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Pos (11UL) #define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ #define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ #define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ #define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ -#define DMA_CTR1_SBX_Pos (13U) +#define DMA_CTR1_SBX_Pos (13UL) #define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ #define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ -#define DMA_CTR1_SAP_Pos (14U) +#define DMA_CTR1_SAP_Pos (14UL) #define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ #define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ -#define DMA_CTR1_SSEC_Pos (15U) +#define DMA_CTR1_SSEC_Pos (15UL) #define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ #define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ -#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Pos (16UL) #define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ #define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ #define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ #define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ -#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Pos (19UL) #define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ #define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ -#define DMA_CTR1_DBL_1_Pos (20U) +#define DMA_CTR1_DBL_1_Pos (20UL) #define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ #define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ -#define DMA_CTR1_DBX_Pos (26U) +#define DMA_CTR1_DBX_Pos (26UL) #define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ #define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ -#define DMA_CTR1_DHX_Pos (27U) +#define DMA_CTR1_DHX_Pos (27UL) #define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ #define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ -#define DMA_CTR1_DAP_Pos (30U) +#define DMA_CTR1_DAP_Pos (30UL) #define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ #define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ -#define DMA_CTR1_DSEC_Pos (31U) +#define DMA_CTR1_DSEC_Pos (31UL) #define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ #define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ /****************** Bit definition for DMA_CTR2 register *******************/ -#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Pos (0UL) #define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ #define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ -#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Pos (9UL) #define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ #define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ -#define DMA_CTR2_DREQ_Pos (10U) +#define DMA_CTR2_DREQ_Pos (10UL) #define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ #define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ -#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Pos (11UL) #define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ #define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ -#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Pos (14UL) #define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ #define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ #define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ #define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ -#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Pos (16UL) #define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ #define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ -#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Pos (24UL) #define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ #define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ #define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ #define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ -#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Pos (30UL) #define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ #define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ #define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ #define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ /****************** Bit definition for DMA_CBR1 register *******************/ -#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Pos (0UL) #define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ #define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ /****************** Bit definition for DMA_CSAR register ********************/ -#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Pos (0UL) #define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ /****************** Bit definition for DMA_CDAR register *******************/ -#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Pos (0UL) #define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ /****************** Bit definition for DMA_CLLR register *******************/ -#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Pos (2UL) #define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ #define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ -#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Pos (16UL) #define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ #define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ -#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Pos (27UL) #define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ #define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ -#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Pos (28UL) #define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ #define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ -#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Pos (29UL) #define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ #define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ -#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Pos (30UL) #define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ #define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ -#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Pos (31UL) #define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ #define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ @@ -2376,242 +2376,242 @@ typedef struct /* */ /******************************************************************************/ /****************** Bit definition for EXTI_RTSR1 register ******************/ -#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Pos (0UL) #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ -#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Pos (1UL) #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ -#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Pos (2UL) #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ -#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Pos (3UL) #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ -#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Pos (4UL) #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ -#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Pos (5UL) #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ -#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Pos (6UL) #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ -#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Pos (7UL) #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ -#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Pos (8UL) #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ -#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Pos (9UL) #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ -#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Pos (12UL) #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ -#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Pos (13UL) #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ -#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Pos (14UL) #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ -#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Pos (15UL) #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ -#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Pos (18UL) #define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ /****************** Bit definition for EXTI_FTSR1 register ******************/ -#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Pos (0UL) #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ -#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Pos (1UL) #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ -#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Pos (2UL) #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ -#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Pos (3UL) #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ -#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Pos (4UL) #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ -#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Pos (5UL) #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ -#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Pos (6UL) #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ -#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Pos (7UL) #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ -#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Pos (8UL) #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ -#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Pos (9UL) #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ -#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Pos (12UL) #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ -#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Pos (13UL) #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ -#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Pos (14UL) #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ -#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Pos (15UL) #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ -#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Pos (18UL) #define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ /****************** Bit definition for EXTI_SWIER1 register *****************/ -#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Pos (0UL) #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Pos (1UL) #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Pos (2UL) #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Pos (3UL) #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Pos (4UL) #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Pos (5UL) #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Pos (6UL) #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Pos (7UL) #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Pos (8UL) #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Pos (9UL) #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Pos (12UL) #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Pos (13UL) #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Pos (14UL) #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Pos (15UL) #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Pos (18UL) #define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ /******************* Bit definition for EXTI_RPR1 register ******************/ -#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Pos (0UL) #define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ #define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ -#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Pos (1UL) #define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ #define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ -#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Pos (2UL) #define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ #define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ -#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Pos (3UL) #define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ #define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ -#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Pos (4UL) #define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ #define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ -#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Pos (5UL) #define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ #define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ -#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Pos (6UL) #define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ #define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ -#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Pos (7UL) #define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ #define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ -#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Pos (8UL) #define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ #define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ -#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Pos (9UL) #define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ #define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ -#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Pos (12UL) #define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ #define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ -#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Pos (13UL) #define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ #define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ -#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Pos (14UL) #define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ #define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ -#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Pos (15UL) #define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ #define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ -#define EXTI_RPR1_RPIF18_Pos (18U) +#define EXTI_RPR1_RPIF18_Pos (18UL) #define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ #define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ /******************* Bit definition for EXTI_FPR1 register ******************/ -#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Pos (0UL) #define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ #define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ -#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Pos (1UL) #define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ #define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ -#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Pos (2UL) #define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ #define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ -#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Pos (3UL) #define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ #define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ -#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Pos (4UL) #define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ #define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ -#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Pos (5UL) #define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ #define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ -#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Pos (6UL) #define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ #define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ -#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Pos (7UL) #define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ #define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ -#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Pos (8UL) #define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ #define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ -#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Pos (9UL) #define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ #define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ -#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Pos (12UL) #define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ #define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ -#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Pos (13UL) #define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ #define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ -#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Pos (14UL) #define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ #define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ -#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Pos (15UL) #define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ #define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ -#define EXTI_FPR1_FPIF18_Pos (18U) +#define EXTI_FPR1_FPIF18_Pos (18UL) #define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ #define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ /***************** Bit definition for EXTI_EXTICR1 register **************/ -#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Pos (0UL) #define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ #define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ #define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ @@ -2622,7 +2622,7 @@ typedef struct #define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ #define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ #define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ -#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Pos (8UL) #define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ #define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ #define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ @@ -2633,7 +2633,7 @@ typedef struct #define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ #define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ #define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ -#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Pos (16UL) #define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ #define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ #define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ @@ -2644,7 +2644,7 @@ typedef struct #define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ #define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ #define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ -#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Pos (24UL) #define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ #define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ #define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ @@ -2657,7 +2657,7 @@ typedef struct #define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ /***************** Bit definition for EXTI_EXTICR2 register **************/ -#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Pos (0UL) #define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ #define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ #define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ @@ -2668,7 +2668,7 @@ typedef struct #define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ #define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ #define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ -#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Pos (8UL) #define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ #define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ #define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ @@ -2679,7 +2679,7 @@ typedef struct #define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ #define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ #define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ -#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Pos (16UL) #define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ #define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ #define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ @@ -2690,7 +2690,7 @@ typedef struct #define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ #define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ #define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ -#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Pos (24UL) #define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ #define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ #define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ @@ -2703,7 +2703,7 @@ typedef struct #define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ /***************** Bit definition for EXTI_EXTICR3 register **************/ -#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Pos (0UL) #define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ #define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ #define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ @@ -2714,7 +2714,7 @@ typedef struct #define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ #define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ #define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ -#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Pos (8UL) #define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ #define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ #define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ @@ -2727,7 +2727,7 @@ typedef struct #define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ /***************** Bit definition for EXTI_EXTICR4 register **************/ -#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Pos (0UL) #define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ #define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ #define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ @@ -2738,7 +2738,7 @@ typedef struct #define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ #define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ #define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ -#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Pos (8UL) #define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ #define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ #define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ @@ -2749,7 +2749,7 @@ typedef struct #define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ #define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ #define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ -#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Pos (16UL) #define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ #define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ #define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ @@ -2760,7 +2760,7 @@ typedef struct #define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ #define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ #define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ -#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Pos (24UL) #define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ #define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ #define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ @@ -2773,96 +2773,96 @@ typedef struct #define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ /******************* Bit definition for EXTI_IMR1 register ******************/ -#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Pos (0UL) #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Pos (1UL) #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Pos (2UL) #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Pos (3UL) #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Pos (4UL) #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Pos (5UL) #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Pos (6UL) #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Pos (7UL) #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Pos (8UL) #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Pos (9UL) #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Pos (12UL) #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Pos (13UL) #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Pos (14UL) #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Pos (15UL) #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Pos (18UL) #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ /******************* Bit definition for EXTI_EMR1 register ******************/ -#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Pos (0UL) #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ -#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Pos (1UL) #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ -#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Pos (2UL) #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ -#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Pos (3UL) #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ -#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Pos (4UL) #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ -#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Pos (5UL) #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ -#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Pos (6UL) #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ -#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Pos (7UL) #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ -#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Pos (8UL) #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ -#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Pos (9UL) #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ -#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Pos (12UL) #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ -#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Pos (13UL) #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ -#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Pos (14UL) #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ -#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Pos (15UL) #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ -#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Pos (18UL) #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ @@ -2875,148 +2875,148 @@ typedef struct #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ /******************* Bits definition for FLASH_ACR register *****************/ -#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Pos (0UL) #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ #define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ -#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Pos (8UL) #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ -#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Pos (11UL) #define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ #define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ -#define FLASH_ACR_PDREQ_Pos (12U) +#define FLASH_ACR_PDREQ_Pos (12UL) #define FLASH_ACR_PDREQ_Msk (0x1UL << FLASH_ACR_PDREQ_Pos) /*!< 0x00001000 */ #define FLASH_ACR_PDREQ FLASH_ACR_PDREQ_Msk /*!< Flash power-down mode request */ -#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Pos (14UL) #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ /****************** Bits definition for FLASH_NSKEYR register *****************/ -#define FLASH_NSKEYR_NSKEY_Pos (0U) +#define FLASH_NSKEYR_NSKEY_Pos (0UL) #define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ /****************** Bits definition for FLASH_OPTKEYR register *****************/ -#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Pos (0UL) #define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ /****************** Bits definition for FLASH_PDKEYR register *****************/ -#define FLASH_PDKEYR_PDKEY_Pos (0U) +#define FLASH_PDKEYR_PDKEY_Pos (0UL) #define FLASH_PDKEYR_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_PDKEYR_PDKEY FLASH_PDKEYR_PDKEY_Msk /*!< Flash power-down key */ /****************** Bits definition for FLASH_NSSR register *****************/ -#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Pos (0UL) #define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ #define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ -#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Pos (1UL) #define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ #define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ -#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Pos (3UL) #define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ #define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ -#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Pos (4UL) #define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ #define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ -#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Pos (5UL) #define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ #define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ -#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Pos (6UL) #define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ #define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ -#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Pos (7UL) #define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ #define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ -#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Pos (13UL) #define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ #define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ -#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Pos (16UL) #define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ #define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ -#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Pos (17UL) #define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ #define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ -#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) #define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ #define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ -#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) #define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ #define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ -#define FLASH_NSSR_PD_Pos (20U) +#define FLASH_NSSR_PD_Pos (20UL) #define FLASH_NSSR_PD_Msk (0x1UL << FLASH_NSSR_PD_Pos) /*!< 0x00100000 */ #define FLASH_NSSR_PD FLASH_NSSR_PD_Msk /*!< Flash in power-down mode */ /****************** Bits definition for FLASH_NSCR1 register *****************/ -#define FLASH_NSCR1_PG_Pos (0U) +#define FLASH_NSCR1_PG_Pos (0UL) #define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ #define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ -#define FLASH_NSCR1_PER_Pos (1U) +#define FLASH_NSCR1_PER_Pos (1UL) #define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ #define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ -#define FLASH_NSCR1_MER_Pos (2U) +#define FLASH_NSCR1_MER_Pos (2UL) #define FLASH_NSCR1_MER_Msk (0x1UL << FLASH_NSCR1_MER_Pos) /*!< 0x00000004 */ #define FLASH_NSCR1_MER FLASH_NSCR1_MER_Msk /*!< Non-secure Mass Erase */ -#define FLASH_NSCR1_PNB_Pos (3U) +#define FLASH_NSCR1_PNB_Pos (3UL) #define FLASH_NSCR1_PNB_Msk (0x3FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000001F8 */ #define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ -#define FLASH_NSCR1_BWR_Pos (14U) +#define FLASH_NSCR1_BWR_Pos (14UL) #define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ #define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ -#define FLASH_NSCR1_STRT_Pos (16U) +#define FLASH_NSCR1_STRT_Pos (16UL) #define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ #define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ -#define FLASH_NSCR1_OPTSTRT_Pos (17U) +#define FLASH_NSCR1_OPTSTRT_Pos (17UL) #define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ #define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ -#define FLASH_NSCR1_EOPIE_Pos (24U) +#define FLASH_NSCR1_EOPIE_Pos (24UL) #define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ -#define FLASH_NSCR1_ERRIE_Pos (25U) +#define FLASH_NSCR1_ERRIE_Pos (25UL) #define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ #define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ -#define FLASH_NSCR1_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27UL) #define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ #define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ -#define FLASH_NSCR1_OPTLOCK_Pos (30U) +#define FLASH_NSCR1_OPTLOCK_Pos (30UL) #define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ #define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ -#define FLASH_NSCR1_LOCK_Pos (31U) +#define FLASH_NSCR1_LOCK_Pos (31UL) #define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ /******************* Bits definition for FLASH_ECCR register ***************/ -#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) #define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */ #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ -#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ -#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Pos (24UL) #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ -#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Pos (30UL) #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ -#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Pos (31UL) #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ /******************* Bits definition for FLASH_OPSR register ***************/ -#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Pos (0UL) #define FLASH_OPSR_ADDR_OP_Msk (0x7FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0007FFFF */ #define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ -#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Pos (22UL) #define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ #define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ -#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Pos (29UL) #define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ #define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ #define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ @@ -3024,106 +3024,106 @@ typedef struct #define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ /******************* Bits definition for FLASH_NSCR2 register ***************/ -#define FLASH_NSCR2_PS_Pos (0U) +#define FLASH_NSCR2_PS_Pos (0UL) #define FLASH_NSCR2_PS_Msk (0x1UL << FLASH_NSCR2_PS_Pos) /*!< 0x00000001 */ #define FLASH_NSCR2_PS FLASH_NSCR2_PS_Msk /*!< Program suspend request */ -#define FLASH_NSCR2_ES_Pos (1U) +#define FLASH_NSCR2_ES_Pos (1UL) #define FLASH_NSCR2_ES_Msk (0x1UL << FLASH_NSCR2_ES_Pos) /*!< 0x00000002 */ #define FLASH_NSCR2_ES FLASH_NSCR2_ES_Msk /*!< Erase suspend request */ /******************* Bits definition for FLASH_OPTR register ***************/ -#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Pos (0UL) #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ -#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Pos (8UL) #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ #define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ #define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ #define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ -#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Pos (12UL) #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ -#define FLASH_OPTR_SRAM1_RST_Pos (15U) +#define FLASH_OPTR_SRAM1_RST_Pos (15UL) #define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ #define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ -#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Pos (16UL) #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ -#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ -#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ -#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Pos (19UL) #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ -#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Pos (24UL) #define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ -#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) #define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ -#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ -#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Pos (27UL) #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ /**************** Bits definition for FLASH_NSBOOTADD0R register ************/ -#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) #define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ #define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ /**************** Bits definition for FLASH_NSBOOTADD1R register ************/ -#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) #define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ #define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ /****************** Bits definition for FLASH_WRPAR register ***************/ -#define FLASH_WRPAR_WRPA_PSTRT_Pos (0U) +#define FLASH_WRPAR_WRPA_PSTRT_Pos (0UL) #define FLASH_WRPAR_WRPA_PSTRT_Msk (0x3FUL << FLASH_WRPAR_WRPA_PSTRT_Pos) /*!< 0x0000003F */ #define FLASH_WRPAR_WRPA_PSTRT FLASH_WRPAR_WRPA_PSTRT_Msk /*!< WPR first area A start page */ -#define FLASH_WRPAR_WRPA_PEND_Pos (16U) +#define FLASH_WRPAR_WRPA_PEND_Pos (16UL) #define FLASH_WRPAR_WRPA_PEND_Msk (0x3FUL << FLASH_WRPAR_WRPA_PEND_Pos) /*!< 0x003F0000 */ #define FLASH_WRPAR_WRPA_PEND FLASH_WRPAR_WRPA_PEND_Msk /*!< WPR first area A end page */ -#define FLASH_WRPAR_UNLOCK_Pos (31U) +#define FLASH_WRPAR_UNLOCK_Pos (31UL) #define FLASH_WRPAR_UNLOCK_Msk (0x1UL << FLASH_WRPAR_UNLOCK_Pos) /*!< 0x80000000 */ #define FLASH_WRPAR_UNLOCK FLASH_WRPAR_UNLOCK_Msk /*!< WPR first area A unlock */ /****************** Bits definition for FLASH_WRPBR register ***************/ -#define FLASH_WRPBR_WRPB_PSTRT_Pos (0U) +#define FLASH_WRPBR_WRPB_PSTRT_Pos (0UL) #define FLASH_WRPBR_WRPB_PSTRT_Msk (0x3FUL << FLASH_WRPBR_WRPB_PSTRT_Pos) /*!< 0x0000003F */ #define FLASH_WRPBR_WRPB_PSTRT FLASH_WRPBR_WRPB_PSTRT_Msk /*!< WPR second area B start page */ -#define FLASH_WRPBR_WRPB_PEND_Pos (16U) +#define FLASH_WRPBR_WRPB_PEND_Pos (16UL) #define FLASH_WRPBR_WRPB_PEND_Msk (0x3FUL << FLASH_WRPBR_WRPB_PEND_Pos) /*!< 0x003F0000 */ #define FLASH_WRPBR_WRPB_PEND FLASH_WRPBR_WRPB_PEND_Msk /*!< WPR second area B end page */ -#define FLASH_WRPBR_UNLOCK_Pos (31U) +#define FLASH_WRPBR_UNLOCK_Pos (31UL) #define FLASH_WRPBR_UNLOCK_Msk (0x1UL << FLASH_WRPBR_UNLOCK_Pos) /*!< 0x80000000 */ #define FLASH_WRPBR_UNLOCK FLASH_WRPBR_UNLOCK_Msk /*!< WPR first area B unlock */ /****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ -#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0UL) #define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ /****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ -#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0UL) #define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ /****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ -#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0UL) #define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ /****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ -#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0UL) #define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ #define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ @@ -3133,603 +3133,603 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Pos (0UL) #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ -#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Pos (2UL) #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ -#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Pos (4UL) #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ -#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Pos (6UL) #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ -#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Pos (8UL) #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ -#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Pos (10UL) #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ -#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Pos (12UL) #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ -#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Pos (14UL) #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ -#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Pos (16UL) #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ -#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Pos (18UL) #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ -#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Pos (20UL) #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ -#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Pos (22UL) #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ -#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Pos (24UL) #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ -#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Pos (26UL) #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ -#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Pos (28UL) #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ -#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Pos (30UL) #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_OTYPER register ****************/ -#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Pos (0UL) #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk -#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Pos (1UL) #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk -#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Pos (2UL) #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk -#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Pos (3UL) #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk -#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Pos (4UL) #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk -#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Pos (5UL) #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk -#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Pos (6UL) #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk -#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Pos (7UL) #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk -#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Pos (8UL) #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk -#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Pos (9UL) #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk -#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Pos (10UL) #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk -#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Pos (11UL) #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk -#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Pos (12UL) #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk -#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Pos (13UL) #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk -#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Pos (14UL) #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk -#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Pos (15UL) #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /****************** Bits definition for GPIO_OSPEEDR register ***************/ -#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Pos (0UL) #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Pos (2UL) #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Pos (4UL) #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Pos (6UL) #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Pos (8UL) #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Pos (10UL) #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Pos (12UL) #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Pos (14UL) #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Pos (16UL) #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Pos (18UL) #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Pos (20UL) #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Pos (22UL) #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Pos (24UL) #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Pos (26UL) #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Pos (28UL) #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Pos (30UL) #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_PUPDR register *****************/ -#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Pos (0UL) #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ -#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Pos (2UL) #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ -#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Pos (4UL) #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ -#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Pos (6UL) #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ -#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Pos (8UL) #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ -#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Pos (10UL) #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ -#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Pos (12UL) #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ -#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Pos (14UL) #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ -#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Pos (16UL) #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ -#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Pos (18UL) #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ -#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Pos (20UL) #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ -#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Pos (22UL) #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ -#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Pos (24UL) #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ -#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Pos (26UL) #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ -#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Pos (28UL) #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ -#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Pos (30UL) #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_IDR register *******************/ -#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Pos (0UL) #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk -#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Pos (1UL) #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk -#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Pos (2UL) #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk -#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Pos (3UL) #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk -#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Pos (4UL) #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk -#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Pos (5UL) #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk -#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Pos (6UL) #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk -#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Pos (7UL) #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk -#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Pos (8UL) #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk -#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Pos (9UL) #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk -#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Pos (10UL) #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk -#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Pos (11UL) #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk -#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Pos (12UL) #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk -#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Pos (13UL) #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk -#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Pos (14UL) #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk -#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Pos (15UL) #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /****************** Bits definition for GPIO_ODR register *******************/ -#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Pos (0UL) #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk -#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Pos (1UL) #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk -#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Pos (2UL) #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk -#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Pos (3UL) #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk -#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Pos (4UL) #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk -#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Pos (5UL) #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk -#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Pos (6UL) #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk -#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Pos (7UL) #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk -#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Pos (8UL) #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk -#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Pos (9UL) #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk -#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Pos (10UL) #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk -#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Pos (11UL) #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk -#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Pos (12UL) #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk -#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Pos (13UL) #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk -#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Pos (14UL) #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk -#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Pos (15UL) #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /****************** Bits definition for GPIO_BSRR register ******************/ -#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Pos (0UL) #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk -#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Pos (1UL) #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk -#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Pos (2UL) #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk -#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Pos (3UL) #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk -#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Pos (4UL) #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk -#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Pos (5UL) #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk -#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Pos (6UL) #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk -#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Pos (7UL) #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk -#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Pos (8UL) #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk -#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Pos (9UL) #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk -#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Pos (10UL) #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk -#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Pos (11UL) #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk -#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Pos (12UL) #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk -#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Pos (13UL) #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk -#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Pos (14UL) #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk -#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Pos (15UL) #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk -#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Pos (16UL) #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk -#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Pos (17UL) #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk -#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Pos (18UL) #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk -#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Pos (19UL) #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk -#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Pos (20UL) #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk -#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Pos (21UL) #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk -#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Pos (22UL) #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk -#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Pos (23UL) #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk -#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Pos (24UL) #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk -#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Pos (25UL) #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk -#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Pos (26UL) #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk -#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Pos (27UL) #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk -#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Pos (28UL) #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk -#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Pos (29UL) #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk -#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Pos (30UL) #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk -#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Pos (31UL) #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /****************** Bit definition for GPIO_LCKR register *********************/ -#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Pos (0UL) #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk -#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Pos (1UL) #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk -#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Pos (2UL) #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk -#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Pos (3UL) #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk -#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Pos (4UL) #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk -#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Pos (5UL) #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk -#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Pos (6UL) #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk -#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Pos (7UL) #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk -#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Pos (8UL) #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk -#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Pos (9UL) #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk -#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Pos (10UL) #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk -#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Pos (11UL) #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk -#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Pos (12UL) #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk -#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Pos (13UL) #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk -#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Pos (14UL) #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk -#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Pos (15UL) #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk -#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Pos (16UL) #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ -#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Pos (0UL) #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ -#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Pos (4UL) #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ -#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Pos (8UL) #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ -#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Pos (12UL) #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ -#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Pos (16UL) #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ -#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Pos (20UL) #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ -#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Pos (24UL) #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ -#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Pos (28UL) #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ @@ -3738,56 +3738,56 @@ typedef struct #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ /****************** Bit definition for GPIO_AFRH register *********************/ -#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Pos (0UL) #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ -#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Pos (4UL) #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ -#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Pos (8UL) #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ -#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Pos (12UL) #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ -#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Pos (16UL) #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ -#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Pos (20UL) #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ -#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Pos (24UL) #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ -#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Pos (28UL) #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ @@ -3796,52 +3796,52 @@ typedef struct #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_BRR register ******************/ -#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Pos (0UL) #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk -#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Pos (1UL) #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk -#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Pos (2UL) #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk -#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Pos (3UL) #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk -#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Pos (4UL) #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk -#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Pos (5UL) #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk -#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Pos (6UL) #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk -#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Pos (7UL) #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk -#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Pos (8UL) #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk -#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Pos (9UL) #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk -#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Pos (10UL) #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk -#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Pos (11UL) #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk -#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Pos (12UL) #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk -#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Pos (13UL) #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk -#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Pos (14UL) #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk -#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Pos (15UL) #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk @@ -3852,44 +3852,44 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for HASH_CR register ********************/ -#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Pos (2UL) #define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ #define HASH_CR_INIT HASH_CR_INIT_Msk -#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Pos (3UL) #define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ #define HASH_CR_DMAE HASH_CR_DMAE_Msk -#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Pos (4UL) #define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk #define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ #define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ -#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Pos (6UL) #define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ #define HASH_CR_MODE HASH_CR_MODE_Msk -#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Pos (8UL) #define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ #define HASH_CR_NBW HASH_CR_NBW_Msk #define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ #define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ #define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ #define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ -#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Pos (12UL) #define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ #define HASH_CR_DINNE HASH_CR_DINNE_Msk -#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Pos (13UL) #define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk -#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Pos (16UL) #define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ #define HASH_CR_LKEY HASH_CR_LKEY_Msk -#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Pos (17UL) #define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ #define HASH_CR_ALGO HASH_CR_ALGO_Msk #define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ #define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ /****************** Bits definition for HASH_STR register *******************/ -#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Pos (0UL) #define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ #define HASH_STR_NBLW HASH_STR_NBLW_Msk #define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ @@ -3897,42 +3897,42 @@ typedef struct #define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ #define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ #define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ -#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Pos (8UL) #define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ #define HASH_STR_DCAL HASH_STR_DCAL_Msk /****************** Bits definition for HASH_IMR register *******************/ -#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Pos (0UL) #define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk -#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Pos (1UL) #define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk /****************** Bits definition for HASH_SR register ********************/ -#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Pos (0UL) #define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ #define HASH_SR_DINIS HASH_SR_DINIS_Msk -#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Pos (1UL) #define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ #define HASH_SR_DCIS HASH_SR_DCIS_Msk -#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Pos (2UL) #define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ #define HASH_SR_DMAS HASH_SR_DMAS_Msk -#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Pos (3UL) #define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ #define HASH_SR_BUSY HASH_SR_BUSY_Msk -#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Pos (16UL) #define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ #define HASH_SR_NBWE HASH_SR_NBWE_Msk #define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ #define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ #define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ #define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ -#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Pos (15UL) #define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ #define HASH_SR_DINNE HASH_SR_DINNE_Msk -#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Pos (9UL) #define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ #define HASH_SR_NBWP HASH_SR_NBWP_Msk #define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ @@ -3947,239 +3947,239 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for HSEM_R register ********************/ -#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Pos (0UL) #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -7076,85 +7107,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -7163,77 +7194,77 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -7244,44 +7275,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_SPE_Pos (0U) +#define SPI_CR1_SPE_Pos (0UL) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11059,85 +11090,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11146,97 +11177,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -11247,44 +11278,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for SPI_CR1 register ********************/ -#define SPI_CR1_SPE_Pos (0U) +#define SPI_CR1_SPE_Pos (0UL) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11453,85 +11453,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11540,97 +11540,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -11641,61 +11641,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11471,85 +11471,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11558,97 +11558,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -11659,61 +11659,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11471,85 +11471,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -11558,97 +11558,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -11659,61 +11659,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -13266,85 +13269,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -13353,97 +13356,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -13454,61 +13457,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -12456,85 +12459,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -12543,97 +12546,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -12644,61 +12647,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -12882,85 +12885,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -12969,97 +12972,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -13070,61 +13073,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -13284,85 +13287,85 @@ typedef struct #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ @@ -13371,97 +13374,97 @@ typedef struct #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ #define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -13472,61 +13475,61 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Pos (0UL) #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the STM32WBAxx System On Chip ------ */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x02C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x30-0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED2[22];/*!< Reserved, Address offset: 0x48-0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED3[7]; /*!< Reserved, Address offset: 0xA8-0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xC4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Analog comparators (COMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA secure and privilege lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< RESERVED1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR1; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR1; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + __IO uint32_t NSCR2; /*!< FLASH non-secure control register, Address offset: 0x38 */ + __IO uint32_t SECCR2; /*!< FLASH secure control register, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH bank 1 secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH bank 1 secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP bank 1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP bank 1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH bank 2 secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH bank 2 secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP bank 2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP bank 2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH bank 1 secure block-based bank register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH bank 1 secure block-based bank register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH bank 1 secure block-based bank register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH bank 1 secure block-based bank register 4, Address offset: 0x8C */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x90-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH bank 2 secure block-based bank register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH bank 2 secure block-based bank register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH bank 2 secure block-based bank register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH bank 2 secure block-based bank register 4, Address offset: 0xAC */ + uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0xB0-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH bank 1 privilege block-based bank register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH bank 1 privilege block-based bank register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH bank 1 privilege block-based bank register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH bank 1 privilege block-based bank register 4, Address offset: 0xDC */ + uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xE0-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH bank 2 privilege block-based bank register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH bank 2 privilege block-based bank register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH bank 2 privilege block-based bank register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH bank 2 privilege block-based bank register 4, Address offset: 0xFC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCK; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[28]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x16C */ + uint32_t RESERVED3[36]; /*!< Reserved3, Address offset: 0x170-0x1FC */ + __IO uint32_t PRIVCFGR[28]; /*!< MPCBBx privilege configuration registers,Address offset: 0x200-0x26C */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED0[52]; /*!< Reserved, Address offset: 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 100h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 104h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 108h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: 10Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 110h-17Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 180h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 184h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 188h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 18Ch */ + uint32_t Reserved4[28]; /*!< Reserved Address offset: 190h-1FCh */ + __IO uint32_t SECCFGR; /*!< HSEM security configuration register, Address offset: 200h */ + uint32_t Reserved5[3]; /*!< Reserved Address offset: 204h-20Ch */ + __IO uint32_t PRIVCFGR; /*!< HSEM privilege configuration register, Address offset: 210h */ + uint32_t Reserved6[7]; /*!< Reserved Address offset: 214h-22Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register, Address offset: 230h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register, Address offset: 234h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 10h-7Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 80h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 84h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 88h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 8Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief PTACONV + */ +typedef struct +{ + __IO uint32_t ACTCR; /*!< PTACONV active control register, Address offset: 0x00 */ + __IO uint32_t PRICR; /*!< PTACONV priority control register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< PTACONV control register, Address offset: 0x08 */ +} PTACONV_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t IORETENRA; /*!< PWR Port A IO retention in Standby register, Address offset: 0x50 */ + __IO uint32_t IORETRA; /*!< PWR Port A IO retention status in Standby register, Address offset: 0x54 */ + __IO uint32_t IORETENRB; /*!< PWR Port B IO retention in Standby register, Address offset: 0x58 */ + __IO uint32_t IORETRB; /*!< PWR Port B IO retention status in Standby register, Address offset: 0x5C */ + __IO uint32_t IORETENRC; /*!< PWR Port C IO retention in Standby register, Address offset: 0x60 */ + __IO uint32_t IORETRC; /*!< PWR Port C IO retention status in Standby register, Address offset: 0x64 */ + __IO uint32_t IORETENRD; /*!< PWR Port D IO retention in Standby register, Address offset: 0x68 */ + __IO uint32_t IORETRD; /*!< PWR Port D IO retention status in Standby register, Address offset: 0x6C */ + __IO uint32_t IORETENRE; /*!< PWR Port E IO retention in Standby register, Address offset: 0x70 */ + __IO uint32_t IORETRE; /*!< PWR Port E IO retention status in Standby register, Address offset: 0x74 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x78 -- 0x7C */ + __IO uint32_t IORETENRG; /*!< PWR Port G IO retention in Standby register, Address offset: 0x80 */ + __IO uint32_t IORETRG; /*!< PWR Port G IO retention status in Standby register, Address offset: 0x84 */ + __IO uint32_t IORETENRH; /*!< PWR Port H IO retention in Standby register, Address offset: 0x88 */ + __IO uint32_t IORETRH; /*!< PWR Port H IO retention status in Standby register, Address offset: 0x8C */ + uint32_t RESERVED4[28]; /*!< Reserved, Address offset: 0x90 -- 0xFC */ + __IO uint32_t RADIOSCR; /*!< PWR 2.4 GHZ radio status and control register, Address offset: 0x100 */ + __IO uint32_t S2RETR; /*!< PWR Stop 2 peripheral IOs retention register, Address offset: 0x104 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved 0x004 -- 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved 0x014 -- 0x018 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x024 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x028 */ + uint32_t RESERVED2[2]; /*!< Reserved 0x02C -- 0x030 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x034 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved 0x03C -- 0x04C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x060 */ + __IO uint32_t AHB2RSTR; /*!< AHB2 Peripherals Reset Register Address offset: 0x064 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x068 */ + __IO uint32_t AHB4RSTR; /*!< AHB4 Peripherals Reset Register Address offset: 0x06C */ + __IO uint32_t AHB5RSTR; /*!< AHB5 Peripherals Reset Register Address offset: 0x070 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset High Register Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB7RSTR; /*!< APB7 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x088 */ + __IO uint32_t AHB2ENR; /*!< AHB2 Peripherals Clock Enable Register Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x090 */ + __IO uint32_t AHB4ENR; /*!< AHB4 Peripherals Clock Enable Register Address offset: 0x094 */ + __IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Low Register Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB7ENR; /*!< APB7 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Low Power Enable Register Address offset: 0x0B0 */ + __IO uint32_t AHB2SMENR; /*!< AHB2 Peripherals Clock Low Power Enable Register Address offset: 0x0B4 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0B8 */ + __IO uint32_t AHB4SMENR; /*!< AHB4 Peripherals Clock Low Power Enable Register Address offset: 0x0BC */ + __IO uint32_t AHB5SMENR; /*!< AHB5 Peripherals Clock Low Power Enable Register Address offset: 0x0C0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Low Power Enable Low Register Address offset: 0x0C4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Low Power Enable High Register Address offset: 0x0C8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Low Power Enable Register Address offset: 0x0CC */ + __IO uint32_t APB7SMENR; /*!< APB7 Peripherals Clock Low Power Enable Register Address offset: 0x0D0 */ + uint32_t RESERVED10[3]; /*!< Reserved 0x0D4 -- 0x0DC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0x0E0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0x0E4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0x0E8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0EC */ + __IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address offset: 0x0F0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0x0F4 */ + __IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address offset: 0x0F8 */ + uint32_t RESERVED12[5]; /*!< Reserved 0x0FC -- 0x010C */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ + uint32_t RESERVED13[42]; /*!< Reserved 0x118 -- 0x1BC */ + __IO uint32_t ASCR; /*!< RCC privilege configuration register Address offset: 0x1C0 */ + __IO uint32_t ASIER; /*!< RCC privilege configuration register Address offset: 0x1C4 */ + __IO uint32_t ASSR; /*!< RCC privilege configuration register Address offset: 0x1C8 */ + __IO uint32_t ASCNTR; /*!< RCC privilege configuration register Address offset: 0x1CC */ + __IO uint32_t ASARR; /*!< RCC privilege configuration register Address offset: 0x1D0 */ + __IO uint32_t ASCAR; /*!< RCC privilege configuration register Address offset: 0x1D4 */ + __IO uint32_t ASCOR; /*!< RCC privilege configuration register Address offset: 0x1D8 */ + uint32_t RESERVED14[9]; /*!< Reserved 0x1DC -- 0x1FC */ + __IO uint32_t CFGR4; /*!< RCC clock configuration register 4 Address offset: 0x200 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x204 */ + __IO uint32_t RADIOENR; /*!< RCC RADIO peripheral clock enable register Address offset: 0x208 */ + uint32_t RESERVED16; /*!< Reserved Address offset: 0x20C */ + __IO uint32_t ECSCR1; /*!< RCC external clock sources calibration register 1 Address offset: 0x210 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_BACKUP_NB RTC_BKP_NB + +#define RTC_TAMP_NB 6U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensation Cell Control&Status register,Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensation Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensation Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30-0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG HS PHY control register, Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG HS PHY tune register 2, Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x68-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief TSC + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC Control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC Interrupt Enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC Interrupt Control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC Interrupt Status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /*! USB_OTG core ID 040h */ + uint32_t Reserved44[4]; /*!< Reserved 044h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved60[40]; /*!< Reserved 060h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/*@}*/ /* end of group STM32WBA6Mxx_Peripherals */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_peripheralAddr + * @{ + */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF90000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20070000UL /*!< SRAM2 non-secure base address */ +#define SRAM6_BASE_NS 0x48028000UL /*!< 2.4 GHz RADIO TXRX SRAM non-secure base address */ +#define SEQSRAM_BASE_NS 0x48021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define DBGMCU_BASE 0xE0044000UL /*!< Debug MCU registers base address */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x200000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x200000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/* Internal SRAMs size */ +#define SRAM1_SIZE 0x00070000UL /*!< SRAM1 = 448 Kbytes */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2 = 64 Kbytes */ +#define SRAM6_SIZE 0x00004000UL /*!< 2.4 GHz RADIO TXRX SRAM 16 Kbytes */ +#define SEQSRAM_SIZE 0x00000200UL /*!< SRAM Sequence / retention 512 bytes */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00010000UL) +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ + +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00010500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB7PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS APB1PERIPH_BASE_NS +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x14000UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS AHB2PERIPH_BASE_NS +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define HSEM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA1C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB7 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB7PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB7PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB7PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB7PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB7PERIPH_BASE_NS + 0x4400UL) +#define COMP12_BASE_NS (APB7PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB7PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB7PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB7PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB4 Non secure peripherals */ +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB4PERIPH_BASE_NS + 0x1308UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB5 Non secure peripherals */ +#define RADIO_BASE_NS AHB5PERIPH_BASE_NS +#define PTACONV_BASE_NS (AHB5PERIPH_BASE_NS + 0x18000UL) + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30070000UL /*!< SRAM2 secure base address */ +#define SRAM6_BASE_S 0x58028000UL /*!< 2.4 GHz RADIO TXRX SRAM secure base address */ +#define SEQSRAM_BASE_S 0x58021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB7PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S APB1PERIPH_BASE_S +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x14000UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0140UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S AHB2PERIPH_BASE_S +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define HSEM_BASE_S (AHB2PERIPH_BASE_S + 0xA1C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB7 Secure peripherals */ +#define SYSCFG_BASE_S (APB7PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB7PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB7PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB7PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB7PERIPH_BASE_S + 0x4400UL) +#define COMP12_BASE_S (APB7PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB7PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB7PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB7PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB4 Secure peripherals */ +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB4PERIPH_BASE_S + 0x1308UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x2000UL) + +/*!< AHB5 Secure peripherals */ +#define RADIO_BASE_S AHB5PERIPH_BASE_S +#define PTACONV_BASE_S (AHB5PERIPH_BASE_S + 0x18000UL) +#endif + +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (SYSTEM_FLASH_BASE_NS + 0x00007E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (SYSTEM_FLASH_BASE_NS + 0x00007E6BUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param VectorTableAddr pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32WBAxx_Peripheral_peripheralAddr */ +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_declaration + * @{ + */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HSEM_NS ((HSEM_TypeDef *) HSEM_BASE_NS) +#define HSEM_COMMON_NS ((HSEM_Common_TypeDef *) (HSEM_BASE_NS + 0x100U)) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PTACONV_NS ((PTACONV_TypeDef *) PTACONV_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S) +#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HSEM_S ((HSEM_TypeDef *) HSEM_BASE_S) +#define HSEM_COMMON_S ((HSEM_Common_TypeDef *) (HSEM_BASE_S + 0x100U)) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PTACONV_S ((PTACONV_TypeDef *) PTACONV_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define SEQSRAM_BASE SEQSRAM_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S +#define GTZC_TZIC GTZC_TZIC_S +#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S +#define GTZC_TZSC GTZC_TZSC_S +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define HSEM HSEM_S +#define HSEM_BASE HSEM_BASE_S +#define HSEM_COMMON HSEM_COMMON_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PTACONV_BASE PTACONV_BASE_S +#define PTACONV PTACONV_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RADIO_BASE RADIO_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define SEQSRAM_BASE SEQSRAM_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS +#define GTZC_TZSC GTZC_TZSC_NS +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define HSEM HSEM_NS +#define HSEM_BASE HSEM_BASE_NS +#define HSEM_COMMON HSEM_COMMON_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PTACONV_BASE PTACONV_BASE_NS +#define PTACONV PTACONV_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RADIO_BASE RADIO_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif + + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0UL) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1UL) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_SCANDIR_Pos (4UL) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_ALIGN_Pos (5UL) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6UL) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14UL) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0UL) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2UL) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9UL) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0UL) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4UL) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8UL) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8UL) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9UL) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10UL) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11UL) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12UL) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13UL) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14UL) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15UL) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16UL) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17UL) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18UL) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19UL) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20UL) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21UL) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22UL) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23UL) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24UL) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25UL) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0UL) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_PWRR register ******************/ +#define ADC_PWRR_AUTOFF_Pos (0UL) +#define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ +#define ADC_PWRR_DPD_Pos (1UL) +#define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0UL) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23UL) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ + +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ + +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ + +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0UL) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1UL) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3UL) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5UL) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11UL) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12UL) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13UL) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18UL) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19UL) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20UL) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24UL) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26UL) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28UL) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31UL) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0UL) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1UL) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2UL) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3UL) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7UL) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0UL) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0UL) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0UL) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0UL) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0UL) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0UL) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0UL) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0UL) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0UL) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0UL) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0UL) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0UL) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0UL) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0UL) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0UL) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0UL) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0UL) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0UL) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0UL) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0UL) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0UL) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0UL) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0UL) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1UL) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2UL) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3UL) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0UL) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1UL) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2UL) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3UL) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0UL) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1UL) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2UL) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3UL) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0UL) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16UL) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_SCR register *****************/ +#define DBGMCU_SCR_DBG_STOP_Pos (1UL) +#define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk +#define DBGMCU_SCR_DBG_STANDBY_Pos (2UL) +#define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk +#define DBGMCU_SCR_TRACE_IOEN_Pos (4UL) +#define DBGMCU_SCR_TRACE_IOEN_Msk (0x1UL << DBGMCU_SCR_TRACE_IOEN_Pos) /*!< 0x00000010 */ +#define DBGMCU_SCR_TRACE_IOEN DBGMCU_SCR_TRACE_IOEN_Msk /*!< Trace port pins enable */ +#define DBGMCU_SCR_TRACE_EN_Pos (5UL) +#define DBGMCU_SCR_TRACE_EN_Msk (0x1UL << DBGMCU_SCR_TRACE_EN_Pos) /*!< 0x00000020 */ +#define DBGMCU_SCR_TRACE_EN DBGMCU_SCR_TRACE_EN_Msk /*!< Trace port enable */ +#define DBGMCU_SCR_TRACE_MODE_Pos (6UL) +#define DBGMCU_SCR_TRACE_MODE_Msk (0x3UL << DBGMCU_SCR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_SCR_TRACE_MODE DBGMCU_SCR_TRACE_MODE_Msk /*!< Trace pin assignment */ +#define DBGMCU_SCR_TRACE_MODE_0 (0x1UL << DBGMCU_SCR_TRACE_MODE_Pos) +#define DBGMCU_SCR_TRACE_MODE_1 (0x2UL << DBGMCU_SCR_TRACE_MODE_Pos) +#define DBGMCU_SCR_DBG_LPMS_Pos (16UL) +#define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ +#define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk +#define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_STOPF_Pos (19UL) +#define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ +#define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk +#define DBGMCU_SCR_DBG_SBF_Pos (20UL) +#define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ +#define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk +#define DBGMCU_SCR_DBG_CS_Pos (24UL) +#define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ +#define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk +#define DBGMCU_SCR_DBG_CDS_Pos (25UL) +#define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ +#define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk + +/******************** Bit definition for DBGMCU_APB1LFZR register ***********/ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0UL) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1UL) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos (2UL) +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM4_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM4_STOP DBGMCU_APB1LFZR_DBG_TIM4_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11UL) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12UL) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21UL) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos (22UL) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_I2C2_STOP DBGMCU_APB1LFZR_DBG_I2C2_STOP_Msk + +/******************** Bit definition for DBGMCU_APB1HFZR register ***********/ +#define DBGMCU_APB1HFZR_DBG_I2C4_STOP_Pos (1UL) +#define DBGMCU_APB1HFZR_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1HFZR_DBG_I2C4_STOP_Pos) +#define DBGMCU_APB1HFZR_DBG_I2C4_STOP DBGMCU_APB1HFZR_DBG_I2C4_STOP_Msk +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos (5UL) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk + +/******************** Bit definition for DBGMCU_APB2FZR register ***********/ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11UL) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17UL) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18UL) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk + +/******************** Bit definition for DBGMCU_APB7FZR register ***********/ +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10UL) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17UL) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30UL) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk + +/******************** Bit definition for DBGMCU_AHB1FZR register ***********/ +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7UL) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_SECCFGR register ****************/ +#define DMA_SECCFGR_SEC0_Pos (0UL) +#define DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk /*!< Secure State of Channel 0 */ +#define DMA_SECCFGR_SEC1_Pos (1UL) +#define DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk /*!< Secure State of Channel 1 */ +#define DMA_SECCFGR_SEC2_Pos (2UL) +#define DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk /*!< Secure State of Channel 2 */ +#define DMA_SECCFGR_SEC3_Pos (3UL) +#define DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk /*!< Secure State of Channel 3 */ +#define DMA_SECCFGR_SEC4_Pos (4UL) +#define DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk /*!< Secure State of Channel 4 */ +#define DMA_SECCFGR_SEC5_Pos (5UL) +#define DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk /*!< Secure State of Channel 5 */ +#define DMA_SECCFGR_SEC6_Pos (6UL) +#define DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk /*!< Secure State of Channel 6 */ +#define DMA_SECCFGR_SEC7_Pos (7UL) +#define DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk /*!< Secure State of Channel 7 */ + +/******************* Bit definition for DMA_PRIVCFGR register ****************/ +#define DMA_PRIVCFGR_PRIV0_Pos (0UL) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1UL) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2UL) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3UL) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4UL) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5UL) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6UL) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7UL) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of Channel 7 */ + +/******************* Bit definition for DMA_RCFGLOCKR register ****************/ +#define DMA_RCFGLOCKR_LOCK0_Pos (0UL) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Privileged and Secure State Lock of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1UL) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Privileged and Secure State Lock of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2UL) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Privileged and Secure State Lock of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3UL) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Privileged and Secure State Lock of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4UL) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Privileged and Secure State Lock of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5UL) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Privileged and Secure State Lock of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6UL) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Privileged and Secure State Lock of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7UL) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Privileged and Secure State Lock of Channel 7 */ + +/******************* Bit definition for DMA_MISR register ****************/ +#define DMA_MISR_MIS0_Pos (0UL) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ +#define DMA_MISR_MIS1_Pos (1UL) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ +#define DMA_MISR_MIS2_Pos (2UL) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ +#define DMA_MISR_MIS3_Pos (3UL) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ +#define DMA_MISR_MIS4_Pos (4UL) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ +#define DMA_MISR_MIS5_Pos (5UL) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ +#define DMA_MISR_MIS6_Pos (6UL) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ +#define DMA_MISR_MIS7_Pos (7UL) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ + +/******************* Bit definition for DMA_SMISR register ****************/ +#define DMA_SMISR_MIS0_Pos (0UL) +#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ +#define DMA_SMISR_MIS1_Pos (1UL) +#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ +#define DMA_SMISR_MIS2_Pos (2UL) +#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ +#define DMA_SMISR_MIS3_Pos (3UL) +#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ +#define DMA_SMISR_MIS4_Pos (4UL) +#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ +#define DMA_SMISR_MIS5_Pos (5UL) +#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ +#define DMA_SMISR_MIS6_Pos (6UL) +#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ +#define DMA_SMISR_MIS7_Pos (7UL) +#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ + +/******************* Bit definition for DMA_CLBAR register ****************/ +#define DMA_CLBAR_LBA_Pos (16UL) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ + +/******************* Bit definition for DMA_CFCR register *******************/ +#define DMA_CFCR_TCF_Pos (8UL) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ +#define DMA_CFCR_HTF_Pos (9UL) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ +#define DMA_CFCR_DTEF_Pos (10UL) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ +#define DMA_CFCR_ULEF_Pos (11UL) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ +#define DMA_CFCR_USEF_Pos (12UL) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ +#define DMA_CFCR_SUSPF_Pos (13UL) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ +#define DMA_CFCR_TOF_Pos (14UL) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ + +/******************* Bit definition for DMA_CSR register *******************/ +#define DMA_CSR_IDLEF_Pos (0UL) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8UL) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9UL) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10UL) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11UL) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ +#define DMA_CSR_USEF_Pos (12UL) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13UL) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_TOF_Pos (14UL) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ +#define DMA_CSR_FIFOL_Pos (16UL) +#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ +#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0UL) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1UL) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2UL) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8UL) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (9UL) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10UL) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCR_ULEIE_Pos (11UL) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12UL) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13UL) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ +#define DMA_CCR_TOIE_Pos (14UL) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_CCR_LSM_Pos (16UL) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_LAP_Pos (17UL) +#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ +#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ +#define DMA_CCR_PRIO_Pos (22UL) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for DMA_CTR1 register *******************/ +#define DMA_CTR1_SDW_LOG2_Pos (0UL) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3UL) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_SBL_1_Pos (4UL) +#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ +#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ +#define DMA_CTR1_PAM_Pos (11UL) +#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ +#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SBX_Pos (13UL) +#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ +#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ +#define DMA_CTR1_SAP_Pos (14UL) +#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ +#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ +#define DMA_CTR1_SSEC_Pos (15UL) +#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ +#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ +#define DMA_CTR1_DDW_LOG2_Pos (16UL) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19UL) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ +#define DMA_CTR1_DBL_1_Pos (20UL) +#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ +#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ +#define DMA_CTR1_DBX_Pos (26UL) +#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ +#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ +#define DMA_CTR1_DHX_Pos (27UL) +#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ +#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ +#define DMA_CTR1_DAP_Pos (30UL) +#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ +#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ +#define DMA_CTR1_DSEC_Pos (31UL) +#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ +#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ + +/****************** Bit definition for DMA_CTR2 register *******************/ +#define DMA_CTR2_REQSEL_Pos (0UL) +#define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ +#define DMA_CTR2_SWREQ_Pos (9UL) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_DREQ_Pos (10UL) +#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ +#define DMA_CTR2_BREQ_Pos (11UL) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_TRIGM_Pos (14UL) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16UL) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24UL) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30UL) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/****************** Bit definition for DMA_CBR1 register *******************/ +#define DMA_CBR1_BNDT_Pos (0UL) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ + +/****************** Bit definition for DMA_CSAR register ********************/ +#define DMA_CSAR_SA_Pos (0UL) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/****************** Bit definition for DMA_CDAR register *******************/ +#define DMA_CDAR_DA_Pos (0UL) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/****************** Bit definition for DMA_CLLR register *******************/ +#define DMA_CLLR_LA_Pos (2UL) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16UL) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ +#define DMA_CLLR_UDA_Pos (27UL) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ +#define DMA_CLLR_USA_Pos (28UL) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ +#define DMA_CLLR_UB1_Pos (29UL) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ +#define DMA_CLLR_UT2_Pos (30UL) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ +#define DMA_CLLR_UT1_Pos (31UL) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0UL) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1UL) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2UL) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3UL) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4UL) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5UL) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6UL) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7UL) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8UL) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9UL) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10UL) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11UL) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12UL) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13UL) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14UL) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15UL) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT16_Pos (16UL) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */ +#define EXTI_RTSR1_RT17_Pos (17UL) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */ +#define EXTI_RTSR1_RT18_Pos (18UL) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0UL) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1UL) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2UL) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3UL) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4UL) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5UL) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6UL) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7UL) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8UL) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9UL) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10UL) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11UL) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12UL) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13UL) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14UL) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15UL) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT16_Pos (16UL) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */ +#define EXTI_FTSR1_FT17_Pos (17UL) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */ +#define EXTI_FTSR1_FT18_Pos (18UL) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0UL) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1UL) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2UL) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3UL) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4UL) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5UL) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6UL) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7UL) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8UL) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9UL) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10UL) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11UL) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12UL) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13UL) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14UL) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15UL) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16UL) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17UL) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18UL) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0UL) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1UL) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2UL) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3UL) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4UL) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5UL) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6UL) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7UL) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8UL) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9UL) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10UL) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11UL) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12UL) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13UL) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14UL) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15UL) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF16_Pos (16UL) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */ +#define EXTI_RPR1_RPIF17_Pos (17UL) +#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */ +#define EXTI_RPR1_RPIF18_Pos (18UL) +#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0UL) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1UL) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2UL) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3UL) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4UL) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5UL) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6UL) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7UL) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8UL) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9UL) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10UL) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11UL) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12UL) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13UL) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14UL) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15UL) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF16_Pos (16UL) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ +#define EXTI_FPR1_FPIF17_Pos (17UL) +#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */ +#define EXTI_FPR1_FPIF18_Pos (18UL) +#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0UL) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1UL) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2UL) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3UL) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4UL) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5UL) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6UL) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7UL) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8UL) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9UL) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10UL) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11UL) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12UL) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13UL) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14UL) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15UL) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16UL) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17UL) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18UL) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0UL) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1UL) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2UL) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3UL) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4UL) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5UL) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6UL) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7UL) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8UL) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9UL) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10UL) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11UL) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12UL) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13UL) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14UL) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15UL) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16UL) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17UL) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18UL) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0UL) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR1_EXTI1_Pos (8UL) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR1_EXTI2_Pos (16UL) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24UL) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0UL) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR2_EXTI5_Pos (8UL) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR2_EXTI6_Pos (16UL) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24UL) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0UL) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR3_EXTI9_Pos (8UL) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR3_EXTI10_Pos (16UL) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI10_4 (0x10UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR3_EXTI10_5 (0x20UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR3_EXTI10_6 (0x40UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR3_EXTI10_7 (0x80UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24UL) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR3_EXTI11_4 (0x10UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR3_EXTI11_5 (0x20UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR3_EXTI11_6 (0x40UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR3_EXTI11_7 (0x80UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0UL) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR4_EXTI13_Pos (8UL) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR4_EXTI14_Pos (16UL) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24UL) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for EXTI_LOCKR register ******************/ +#define EXTI_LOCKR_LOCK_Pos (0UL) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Security and privilege configuration lock */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0UL) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1UL) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2UL) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3UL) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4UL) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5UL) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6UL) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7UL) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8UL) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9UL) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10UL) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11UL) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12UL) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13UL) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14UL) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15UL) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16UL) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17UL) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18UL) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0UL) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1UL) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2UL) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3UL) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4UL) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5UL) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6UL) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7UL) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8UL) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9UL) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10UL) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11UL) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12UL) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13UL) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14UL) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15UL) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16UL) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17UL) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18UL) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define FLASH_DBANK_SUPPORT /*!< Flash feature available only on specific devices: dualbank */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Flash bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Flash bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSKEYR register *****************/ +#define FLASH_NSKEYR_NSKEY_Pos (0UL) +#define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ + +/****************** Bits definition for FLASH_SECKEYR register *****************/ +#define FLASH_SECKEYR_SECKEY_Pos (0UL) +#define FLASH_SECKEYR_SECKEY_Msk (0xFFFFFFFFUL << FLASH_SECKEYR_SECKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_SECKEYR_SECKEY FLASH_SECKEYR_SECKEY_Msk /*!< Flash memory secure key */ + +/****************** Bits definition for FLASH_OPTKEYR register *****************/ +#define FLASH_OPTKEYR_OPTKEY_Pos (0UL) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ + +/****************** Bits definition for FLASH_PDKEY1R register *****************/ +#define FLASH_PDKEY1R_PDKEY_Pos (0UL) +#define FLASH_PDKEY1R_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEY1R_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEY1R_PDKEY FLASH_PDKEY1R_PDKEY_Msk /*!< Flash bank 1 power-down key */ + +/****************** Bits definition for FLASH_PDKEY2R register *****************/ +#define FLASH_PDKEY2R_PDKEY_Pos (0UL) +#define FLASH_PDKEY2R_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEY2R_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEY2R_PDKEY FLASH_PDKEY2R_PDKEY_Msk /*!< Flash bank 2 power-down key */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Flash bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Flash bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR1 register *****************/ +#define FLASH_NSCR1_PG_Pos (0UL) +#define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR1_PER_Pos (1UL) +#define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR1_MER1_Pos (2UL) +#define FLASH_NSCR1_MER1_Msk (0x1UL << FLASH_NSCR1_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR1_MER1 FLASH_NSCR1_MER1_Msk /*!< Non-secure Flash Bank 1 Erase */ +#define FLASH_NSCR1_PNB_Pos (3UL) +#define FLASH_NSCR1_PNB_Msk (0x7FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR1_BKER_Pos (11UL) +#define FLASH_NSCR1_BKER_Msk (0x1UL << FLASH_NSCR1_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR1_BKER FLASH_NSCR1_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR1_BWR_Pos (14UL) +#define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR1_MER2_Pos (15UL) +#define FLASH_NSCR1_MER2_Msk (0x1UL << FLASH_NSCR1_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR1_MER2 FLASH_NSCR1_MER2_Msk /*!< Non-secure Flash Bank 2 Erase */ +#define FLASH_NSCR1_STRT_Pos (16UL) +#define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR1_OPTSTRT_Pos (17UL) +#define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR1_EOPIE_Pos (24UL) +#define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR1_ERRIE_Pos (25UL) +#define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR1_OPTLOCK_Pos (30UL) +#define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR1_LOCK_Pos (31UL) +#define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR1 register ****************/ +#define FLASH_SECCR1_PG_Pos (0UL) +#define FLASH_SECCR1_PG_Msk (0x1UL << FLASH_SECCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR1_PG FLASH_SECCR1_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR1_PER_Pos (1UL) +#define FLASH_SECCR1_PER_Msk (0x1UL << FLASH_SECCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR1_PER FLASH_SECCR1_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR1_MER1_Pos (2UL) +#define FLASH_SECCR1_MER1_Msk (0x1UL << FLASH_SECCR1_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR1_MER1 FLASH_SECCR1_MER1_Msk /*!< Secure Flash Bank 1 Erase */ +#define FLASH_SECCR1_PNB_Pos (3UL) +#define FLASH_SECCR1_PNB_Msk (0x7FUL << FLASH_SECCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR1_PNB FLASH_SECCR1_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR1_BKER_Pos (11UL) +#define FLASH_SECCR1_BKER_Msk (0x1UL << FLASH_SECCR1_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR1_BKER FLASH_SECCR1_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR1_BWR_Pos (14UL) +#define FLASH_SECCR1_BWR_Msk (0x1UL << FLASH_SECCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR1_BWR FLASH_SECCR1_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR1_MER2_Pos (15UL) +#define FLASH_SECCR1_MER2_Msk (0x1UL << FLASH_SECCR1_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR1_MER2 FLASH_SECCR1_MER2_Msk /*!< Secure Flash Bank 2 Erase */ +#define FLASH_SECCR1_STRT_Pos (16UL) +#define FLASH_SECCR1_STRT_Msk (0x1UL << FLASH_SECCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR1_STRT FLASH_SECCR1_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR1_EOPIE_Pos (24UL) +#define FLASH_SECCR1_EOPIE_Msk (0x1UL << FLASH_SECCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR1_EOPIE FLASH_SECCR1_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR1_ERRIE_Pos (25UL) +#define FLASH_SECCR1_ERRIE_Msk (0x1UL << FLASH_SECCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR1_ERRIE FLASH_SECCR1_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR1_INV_Pos (29UL) +#define FLASH_SECCR1_INV_Msk (0x1UL << FLASH_SECCR1_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR1_INV FLASH_SECCR1_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR1_LOCK_Pos (31UL) +#define FLASH_SECCR1_LOCK_Msk (0x1UL << FLASH_SECCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR1_LOCK FLASH_SECCR1_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< Bank ECC fail */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Operation in bank interrupted */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x02000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ + +/******************* Bits definition for FLASH_NSCR2 register ***************/ +#define FLASH_NSCR2_PS1_Pos (0UL) +#define FLASH_NSCR2_PS1_Msk (0x1UL << FLASH_NSCR2_PS1_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR2_PS1 FLASH_NSCR2_PS1_Msk /*!< Bank 1 non-secure program suspend request */ +#define FLASH_NSCR2_ES1_Pos (1UL) +#define FLASH_NSCR2_ES1_Msk (0x1UL << FLASH_NSCR2_ES1_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR2_ES1 FLASH_NSCR2_ES1_Msk /*!< Bank 1 non-secure erase suspend request */ +#define FLASH_NSCR2_PS2_Pos (16UL) +#define FLASH_NSCR2_PS2_Msk (0x1UL << FLASH_NSCR2_PS2_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR2_PS2 FLASH_NSCR2_PS2_Msk /*!< Bank 2 non-secure program suspend request */ +#define FLASH_NSCR2_ES2_Pos (17UL) +#define FLASH_NSCR2_ES2_Msk (0x1UL << FLASH_NSCR2_ES2_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR2_ES2 FLASH_NSCR2_ES2_Msk /*!< Bank 2 non-secure erase suspend request */ + +/******************* Bits definition for FLASH_SECCR2 register ***************/ +#define FLASH_SECCR2_PS1_Pos (0UL) +#define FLASH_SECCR2_PS1_Msk (0x1UL << FLASH_SECCR2_PS1_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR2_PS1 FLASH_SECCR2_PS1_Msk /*!< Bank 1 secure program suspend request */ +#define FLASH_SECCR2_ES1_Pos (1UL) +#define FLASH_SECCR2_ES1_Msk (0x1UL << FLASH_SECCR2_ES1_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR2_ES1 FLASH_SECCR2_ES1_Msk /*!< Bank 1 secure erase suspend request */ +#define FLASH_SECCR2_PS2_Pos (16UL) +#define FLASH_SECCR2_PS2_Msk (0x1UL << FLASH_SECCR2_PS2_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR2_PS2 FLASH_SECCR2_PS2_Msk /*!< Bank 2 secure program suspend request */ +#define FLASH_SECCR2_ES2_Pos (17UL) +#define FLASH_SECCR2_ES2_Msk (0x1UL << FLASH_SECCR2_ES2_Pos) /*!< 0x00020000 */ +#define FLASH_SECCR2_ES2 FLASH_SECCR2_ES2_Msk /*!< Bank 2 secure erase suspend request */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_SRAM1_RST_Pos (15UL) +#define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap bank */ +#define FLASH_OPTR_DUAL_BANK_Pos (21UL) +#define FLASH_OPTR_DUAL_BANK_Msk (0x1UL << FLASH_OPTR_DUAL_BANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUAL_BANK FLASH_OPTR_DUAL_BANK_Msk /*!< Dual bank */ +#define FLASH_OPTR_SRAM2_PE_Pos (24UL) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High-speed IO at low Vdd voltage configuration */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High-speed IO at low Vddio2 voltage configuration */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Bank 1 start page of secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< Bank 1 end page of secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< Bank 1 end page of secure hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Bank 1 secure hide protection area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< WPR bank 1 area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< WPR bank 1 area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< WPR bank 1 area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< WPR bank 1 area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< WPR bank 1 area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< WPR bank 1 area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Bank 2 start page of secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< Bank 2 end page of secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< Bank 2 end page of secure hide protection area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Bank 2 secure hide protection area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< WPR bank 2 area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< WPR bank 2 area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< WPR bank 2 area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< WPR bank 2 area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< WPR bank 2 area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< WPR bank 2 area B unlock */ + +/****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0UL) +#define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0UL) +#define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0UL) +#define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0UL) +#define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ + +/******************* Bit definition for FLASH_SECBB1R1 register ******************/ +#define FLASH_SECBB1R1_SECBB0_Pos (0UL) +#define FLASH_SECBB1R1_SECBB0_Msk (0x1UL << FLASH_SECBB1R1_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB1R1_SECBB0 FLASH_SECBB1R1_SECBB0_Msk /*!< Page 0 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB1_Pos (1UL) +#define FLASH_SECBB1R1_SECBB1_Msk (0x1UL << FLASH_SECBB1R1_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB1R1_SECBB1 FLASH_SECBB1R1_SECBB1_Msk /*!< Page 1 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB2_Pos (2UL) +#define FLASH_SECBB1R1_SECBB2_Msk (0x1UL << FLASH_SECBB1R1_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB1R1_SECBB2 FLASH_SECBB1R1_SECBB2_Msk /*!< Page 2 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB3_Pos (3UL) +#define FLASH_SECBB1R1_SECBB3_Msk (0x1UL << FLASH_SECBB1R1_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB1R1_SECBB3 FLASH_SECBB1R1_SECBB3_Msk /*!< Page 3 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB4_Pos (4UL) +#define FLASH_SECBB1R1_SECBB4_Msk (0x1UL << FLASH_SECBB1R1_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB1R1_SECBB4 FLASH_SECBB1R1_SECBB4_Msk /*!< Page 4 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB5_Pos (5UL) +#define FLASH_SECBB1R1_SECBB5_Msk (0x1UL << FLASH_SECBB1R1_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB1R1_SECBB5 FLASH_SECBB1R1_SECBB5_Msk /*!< Page 5 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB6_Pos (6UL) +#define FLASH_SECBB1R1_SECBB6_Msk (0x1UL << FLASH_SECBB1R1_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB1R1_SECBB6 FLASH_SECBB1R1_SECBB6_Msk /*!< Page 6 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB7_Pos (7UL) +#define FLASH_SECBB1R1_SECBB7_Msk (0x1UL << FLASH_SECBB1R1_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB1R1_SECBB7 FLASH_SECBB1R1_SECBB7_Msk /*!< Page 7 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB8_Pos (8UL) +#define FLASH_SECBB1R1_SECBB8_Msk (0x1UL << FLASH_SECBB1R1_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB1R1_SECBB8 FLASH_SECBB1R1_SECBB8_Msk /*!< Page 8 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB9_Pos (9UL) +#define FLASH_SECBB1R1_SECBB9_Msk (0x1UL << FLASH_SECBB1R1_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB1R1_SECBB9 FLASH_SECBB1R1_SECBB9_Msk /*!< Page 9 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB10_Pos (10UL) +#define FLASH_SECBB1R1_SECBB10_Msk (0x1UL << FLASH_SECBB1R1_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB1R1_SECBB10 FLASH_SECBB1R1_SECBB10_Msk /*!< Page 10 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB11_Pos (11UL) +#define FLASH_SECBB1R1_SECBB11_Msk (0x1UL << FLASH_SECBB1R1_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB1R1_SECBB11 FLASH_SECBB1R1_SECBB11_Msk /*!< Page 11 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB12_Pos (12UL) +#define FLASH_SECBB1R1_SECBB12_Msk (0x1UL << FLASH_SECBB1R1_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB1R1_SECBB12 FLASH_SECBB1R1_SECBB12_Msk /*!< Page 12 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB13_Pos (13UL) +#define FLASH_SECBB1R1_SECBB13_Msk (0x1UL << FLASH_SECBB1R1_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB1R1_SECBB13 FLASH_SECBB1R1_SECBB13_Msk /*!< Page 13 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB14_Pos (14UL) +#define FLASH_SECBB1R1_SECBB14_Msk (0x1UL << FLASH_SECBB1R1_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB1R1_SECBB14 FLASH_SECBB1R1_SECBB14_Msk /*!< Page 14 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB15_Pos (15UL) +#define FLASH_SECBB1R1_SECBB15_Msk (0x1UL << FLASH_SECBB1R1_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB1R1_SECBB15 FLASH_SECBB1R1_SECBB15_Msk /*!< Page 15 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB16_Pos (16UL) +#define FLASH_SECBB1R1_SECBB16_Msk (0x1UL << FLASH_SECBB1R1_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB1R1_SECBB16 FLASH_SECBB1R1_SECBB16_Msk /*!< Page 16 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB17_Pos (17UL) +#define FLASH_SECBB1R1_SECBB17_Msk (0x1UL << FLASH_SECBB1R1_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB1R1_SECBB17 FLASH_SECBB1R1_SECBB17_Msk /*!< Page 17 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB18_Pos (18UL) +#define FLASH_SECBB1R1_SECBB18_Msk (0x1UL << FLASH_SECBB1R1_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB1R1_SECBB18 FLASH_SECBB1R1_SECBB18_Msk /*!< Page 18 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB19_Pos (19UL) +#define FLASH_SECBB1R1_SECBB19_Msk (0x1UL << FLASH_SECBB1R1_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB1R1_SECBB19 FLASH_SECBB1R1_SECBB19_Msk /*!< Page 19 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB20_Pos (20UL) +#define FLASH_SECBB1R1_SECBB20_Msk (0x1UL << FLASH_SECBB1R1_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB1R1_SECBB20 FLASH_SECBB1R1_SECBB20_Msk /*!< Page 20 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB21_Pos (21UL) +#define FLASH_SECBB1R1_SECBB21_Msk (0x1UL << FLASH_SECBB1R1_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB1R1_SECBB21 FLASH_SECBB1R1_SECBB21_Msk /*!< Page 21 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB22_Pos (22UL) +#define FLASH_SECBB1R1_SECBB22_Msk (0x1UL << FLASH_SECBB1R1_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB1R1_SECBB22 FLASH_SECBB1R1_SECBB22_Msk /*!< Page 22 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB23_Pos (23UL) +#define FLASH_SECBB1R1_SECBB23_Msk (0x1UL << FLASH_SECBB1R1_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB1R1_SECBB23 FLASH_SECBB1R1_SECBB23_Msk /*!< Page 23 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB24_Pos (24UL) +#define FLASH_SECBB1R1_SECBB24_Msk (0x1UL << FLASH_SECBB1R1_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB1R1_SECBB24 FLASH_SECBB1R1_SECBB24_Msk /*!< Page 24 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB25_Pos (25UL) +#define FLASH_SECBB1R1_SECBB25_Msk (0x1UL << FLASH_SECBB1R1_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB1R1_SECBB25 FLASH_SECBB1R1_SECBB25_Msk /*!< Page 25 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB26_Pos (26UL) +#define FLASH_SECBB1R1_SECBB26_Msk (0x1UL << FLASH_SECBB1R1_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB1R1_SECBB26 FLASH_SECBB1R1_SECBB26_Msk /*!< Page 26 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB27_Pos (27UL) +#define FLASH_SECBB1R1_SECBB27_Msk (0x1UL << FLASH_SECBB1R1_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB1R1_SECBB27 FLASH_SECBB1R1_SECBB27_Msk /*!< Page 27 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB28_Pos (28UL) +#define FLASH_SECBB1R1_SECBB28_Msk (0x1UL << FLASH_SECBB1R1_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB1R1_SECBB28 FLASH_SECBB1R1_SECBB28_Msk /*!< Page 28 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB29_Pos (29UL) +#define FLASH_SECBB1R1_SECBB29_Msk (0x1UL << FLASH_SECBB1R1_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB1R1_SECBB29 FLASH_SECBB1R1_SECBB29_Msk /*!< Page 29 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB30_Pos (30UL) +#define FLASH_SECBB1R1_SECBB30_Msk (0x1UL << FLASH_SECBB1R1_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB1R1_SECBB30 FLASH_SECBB1R1_SECBB30_Msk /*!< Page 30 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R1_SECBB31_Pos (31UL) +#define FLASH_SECBB1R1_SECBB31_Msk (0x1UL << FLASH_SECBB1R1_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB1R1_SECBB31 FLASH_SECBB1R1_SECBB31_Msk /*!< Page 31 in Flash bank 1 block-based secure */ + +/******************* Bit definition for FLASH_SECBB1R2 register ******************/ +#define FLASH_SECBB1R2_SECBB0_Pos (0UL) +#define FLASH_SECBB1R2_SECBB0_Msk (0x1UL << FLASH_SECBB1R2_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB1R2_SECBB0 FLASH_SECBB1R2_SECBB0_Msk /*!< Page 32 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB1_Pos (1UL) +#define FLASH_SECBB1R2_SECBB1_Msk (0x1UL << FLASH_SECBB1R2_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB1R2_SECBB1 FLASH_SECBB1R2_SECBB1_Msk /*!< Page 33 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB2_Pos (2UL) +#define FLASH_SECBB1R2_SECBB2_Msk (0x1UL << FLASH_SECBB1R2_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB1R2_SECBB2 FLASH_SECBB1R2_SECBB2_Msk /*!< Page 34 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB3_Pos (3UL) +#define FLASH_SECBB1R2_SECBB3_Msk (0x1UL << FLASH_SECBB1R2_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB1R2_SECBB3 FLASH_SECBB1R2_SECBB3_Msk /*!< Page 35 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB4_Pos (4UL) +#define FLASH_SECBB1R2_SECBB4_Msk (0x1UL << FLASH_SECBB1R2_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB1R2_SECBB4 FLASH_SECBB1R2_SECBB4_Msk /*!< Page 36 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB5_Pos (5UL) +#define FLASH_SECBB1R2_SECBB5_Msk (0x1UL << FLASH_SECBB1R2_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB1R2_SECBB5 FLASH_SECBB1R2_SECBB5_Msk /*!< Page 37 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB6_Pos (6UL) +#define FLASH_SECBB1R2_SECBB6_Msk (0x1UL << FLASH_SECBB1R2_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB1R2_SECBB6 FLASH_SECBB1R2_SECBB6_Msk /*!< Page 38 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB7_Pos (7UL) +#define FLASH_SECBB1R2_SECBB7_Msk (0x1UL << FLASH_SECBB1R2_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB1R2_SECBB7 FLASH_SECBB1R2_SECBB7_Msk /*!< Page 39 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB8_Pos (8UL) +#define FLASH_SECBB1R2_SECBB8_Msk (0x1UL << FLASH_SECBB1R2_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB1R2_SECBB8 FLASH_SECBB1R2_SECBB8_Msk /*!< Page 40 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB9_Pos (9UL) +#define FLASH_SECBB1R2_SECBB9_Msk (0x1UL << FLASH_SECBB1R2_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB1R2_SECBB9 FLASH_SECBB1R2_SECBB9_Msk /*!< Page 41 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB10_Pos (10UL) +#define FLASH_SECBB1R2_SECBB10_Msk (0x1UL << FLASH_SECBB1R2_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB1R2_SECBB10 FLASH_SECBB1R2_SECBB10_Msk /*!< Page 42 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB11_Pos (11UL) +#define FLASH_SECBB1R2_SECBB11_Msk (0x1UL << FLASH_SECBB1R2_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB1R2_SECBB11 FLASH_SECBB1R2_SECBB11_Msk /*!< Page 43 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB12_Pos (12UL) +#define FLASH_SECBB1R2_SECBB12_Msk (0x1UL << FLASH_SECBB1R2_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB1R2_SECBB12 FLASH_SECBB1R2_SECBB12_Msk /*!< Page 44 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB13_Pos (13UL) +#define FLASH_SECBB1R2_SECBB13_Msk (0x1UL << FLASH_SECBB1R2_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB1R2_SECBB13 FLASH_SECBB1R2_SECBB13_Msk /*!< Page 45 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB14_Pos (14UL) +#define FLASH_SECBB1R2_SECBB14_Msk (0x1UL << FLASH_SECBB1R2_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB1R2_SECBB14 FLASH_SECBB1R2_SECBB14_Msk /*!< Page 46 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB15_Pos (15UL) +#define FLASH_SECBB1R2_SECBB15_Msk (0x1UL << FLASH_SECBB1R2_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB1R2_SECBB15 FLASH_SECBB1R2_SECBB15_Msk /*!< Page 47 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB16_Pos (16UL) +#define FLASH_SECBB1R2_SECBB16_Msk (0x1UL << FLASH_SECBB1R2_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB1R2_SECBB16 FLASH_SECBB1R2_SECBB16_Msk /*!< Page 48 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB17_Pos (17UL) +#define FLASH_SECBB1R2_SECBB17_Msk (0x1UL << FLASH_SECBB1R2_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB1R2_SECBB17 FLASH_SECBB1R2_SECBB17_Msk /*!< Page 49 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB18_Pos (18UL) +#define FLASH_SECBB1R2_SECBB18_Msk (0x1UL << FLASH_SECBB1R2_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB1R2_SECBB18 FLASH_SECBB1R2_SECBB18_Msk /*!< Page 50 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB19_Pos (19UL) +#define FLASH_SECBB1R2_SECBB19_Msk (0x1UL << FLASH_SECBB1R2_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB1R2_SECBB19 FLASH_SECBB1R2_SECBB19_Msk /*!< Page 51 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB20_Pos (20UL) +#define FLASH_SECBB1R2_SECBB20_Msk (0x1UL << FLASH_SECBB1R2_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB1R2_SECBB20 FLASH_SECBB1R2_SECBB20_Msk /*!< Page 52 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB21_Pos (21UL) +#define FLASH_SECBB1R2_SECBB21_Msk (0x1UL << FLASH_SECBB1R2_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB1R2_SECBB21 FLASH_SECBB1R2_SECBB21_Msk /*!< Page 53 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB22_Pos (22UL) +#define FLASH_SECBB1R2_SECBB22_Msk (0x1UL << FLASH_SECBB1R2_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB1R2_SECBB22 FLASH_SECBB1R2_SECBB22_Msk /*!< Page 54 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB23_Pos (23UL) +#define FLASH_SECBB1R2_SECBB23_Msk (0x1UL << FLASH_SECBB1R2_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB1R2_SECBB23 FLASH_SECBB1R2_SECBB23_Msk /*!< Page 55 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB24_Pos (24UL) +#define FLASH_SECBB1R2_SECBB24_Msk (0x1UL << FLASH_SECBB1R2_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB1R2_SECBB24 FLASH_SECBB1R2_SECBB24_Msk /*!< Page 56 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB25_Pos (25UL) +#define FLASH_SECBB1R2_SECBB25_Msk (0x1UL << FLASH_SECBB1R2_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB1R2_SECBB25 FLASH_SECBB1R2_SECBB25_Msk /*!< Page 57 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB26_Pos (26UL) +#define FLASH_SECBB1R2_SECBB26_Msk (0x1UL << FLASH_SECBB1R2_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB1R2_SECBB26 FLASH_SECBB1R2_SECBB26_Msk /*!< Page 58 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB27_Pos (27UL) +#define FLASH_SECBB1R2_SECBB27_Msk (0x1UL << FLASH_SECBB1R2_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB1R2_SECBB27 FLASH_SECBB1R2_SECBB27_Msk /*!< Page 59 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB28_Pos (28UL) +#define FLASH_SECBB1R2_SECBB28_Msk (0x1UL << FLASH_SECBB1R2_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB1R2_SECBB28 FLASH_SECBB1R2_SECBB28_Msk /*!< Page 60 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB29_Pos (29UL) +#define FLASH_SECBB1R2_SECBB29_Msk (0x1UL << FLASH_SECBB1R2_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB1R2_SECBB29 FLASH_SECBB1R2_SECBB29_Msk /*!< Page 61 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB30_Pos (30UL) +#define FLASH_SECBB1R2_SECBB30_Msk (0x1UL << FLASH_SECBB1R2_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB1R2_SECBB30 FLASH_SECBB1R2_SECBB30_Msk /*!< Page 62 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R2_SECBB31_Pos (31UL) +#define FLASH_SECBB1R2_SECBB31_Msk (0x1UL << FLASH_SECBB1R2_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB1R2_SECBB31 FLASH_SECBB1R2_SECBB31_Msk /*!< Page 63 in Flash bank 1 block-based secure */ + +/******************* Bit definition for FLASH_SECBB1R3 register ******************/ +#define FLASH_SECBB1R3_SECBB0_Pos (0UL) +#define FLASH_SECBB1R3_SECBB0_Msk (0x1UL << FLASH_SECBB1R3_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB1R3_SECBB0 FLASH_SECBB1R3_SECBB0_Msk /*!< Page 64 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB1_Pos (1UL) +#define FLASH_SECBB1R3_SECBB1_Msk (0x1UL << FLASH_SECBB1R3_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB1R3_SECBB1 FLASH_SECBB1R3_SECBB1_Msk /*!< Page 65 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB2_Pos (2UL) +#define FLASH_SECBB1R3_SECBB2_Msk (0x1UL << FLASH_SECBB1R3_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB1R3_SECBB2 FLASH_SECBB1R3_SECBB2_Msk /*!< Page 66 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB3_Pos (3UL) +#define FLASH_SECBB1R3_SECBB3_Msk (0x1UL << FLASH_SECBB1R3_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB1R3_SECBB3 FLASH_SECBB1R3_SECBB3_Msk /*!< Page 67 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB4_Pos (4UL) +#define FLASH_SECBB1R3_SECBB4_Msk (0x1UL << FLASH_SECBB1R3_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB1R3_SECBB4 FLASH_SECBB1R3_SECBB4_Msk /*!< Page 68 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB5_Pos (5UL) +#define FLASH_SECBB1R3_SECBB5_Msk (0x1UL << FLASH_SECBB1R3_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB1R3_SECBB5 FLASH_SECBB1R3_SECBB5_Msk /*!< Page 69 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB6_Pos (6UL) +#define FLASH_SECBB1R3_SECBB6_Msk (0x1UL << FLASH_SECBB1R3_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB1R3_SECBB6 FLASH_SECBB1R3_SECBB6_Msk /*!< Page 70 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB7_Pos (7UL) +#define FLASH_SECBB1R3_SECBB7_Msk (0x1UL << FLASH_SECBB1R3_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB1R3_SECBB7 FLASH_SECBB1R3_SECBB7_Msk /*!< Page 71 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB8_Pos (8UL) +#define FLASH_SECBB1R3_SECBB8_Msk (0x1UL << FLASH_SECBB1R3_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB1R3_SECBB8 FLASH_SECBB1R3_SECBB8_Msk /*!< Page 72 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB9_Pos (9UL) +#define FLASH_SECBB1R3_SECBB9_Msk (0x1UL << FLASH_SECBB1R3_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB1R3_SECBB9 FLASH_SECBB1R3_SECBB9_Msk /*!< Page 73 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB10_Pos (10UL) +#define FLASH_SECBB1R3_SECBB10_Msk (0x1UL << FLASH_SECBB1R3_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB1R3_SECBB10 FLASH_SECBB1R3_SECBB10_Msk /*!< Page 74 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB11_Pos (11UL) +#define FLASH_SECBB1R3_SECBB11_Msk (0x1UL << FLASH_SECBB1R3_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB1R3_SECBB11 FLASH_SECBB1R3_SECBB11_Msk /*!< Page 75 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB12_Pos (12UL) +#define FLASH_SECBB1R3_SECBB12_Msk (0x1UL << FLASH_SECBB1R3_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB1R3_SECBB12 FLASH_SECBB1R3_SECBB12_Msk /*!< Page 76 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB13_Pos (13UL) +#define FLASH_SECBB1R3_SECBB13_Msk (0x1UL << FLASH_SECBB1R3_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB1R3_SECBB13 FLASH_SECBB1R3_SECBB13_Msk /*!< Page 77 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB14_Pos (14UL) +#define FLASH_SECBB1R3_SECBB14_Msk (0x1UL << FLASH_SECBB1R3_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB1R3_SECBB14 FLASH_SECBB1R3_SECBB14_Msk /*!< Page 78 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB15_Pos (15UL) +#define FLASH_SECBB1R3_SECBB15_Msk (0x1UL << FLASH_SECBB1R3_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB1R3_SECBB15 FLASH_SECBB1R3_SECBB15_Msk /*!< Page 79 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB16_Pos (16UL) +#define FLASH_SECBB1R3_SECBB16_Msk (0x1UL << FLASH_SECBB1R3_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB1R3_SECBB16 FLASH_SECBB1R3_SECBB16_Msk /*!< Page 80 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB17_Pos (17UL) +#define FLASH_SECBB1R3_SECBB17_Msk (0x1UL << FLASH_SECBB1R3_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB1R3_SECBB17 FLASH_SECBB1R3_SECBB17_Msk /*!< Page 81 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB18_Pos (18UL) +#define FLASH_SECBB1R3_SECBB18_Msk (0x1UL << FLASH_SECBB1R3_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB1R3_SECBB18 FLASH_SECBB1R3_SECBB18_Msk /*!< Page 82 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB19_Pos (19UL) +#define FLASH_SECBB1R3_SECBB19_Msk (0x1UL << FLASH_SECBB1R3_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB1R3_SECBB19 FLASH_SECBB1R3_SECBB19_Msk /*!< Page 83 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB20_Pos (20UL) +#define FLASH_SECBB1R3_SECBB20_Msk (0x1UL << FLASH_SECBB1R3_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB1R3_SECBB20 FLASH_SECBB1R3_SECBB20_Msk /*!< Page 84 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB21_Pos (21UL) +#define FLASH_SECBB1R3_SECBB21_Msk (0x1UL << FLASH_SECBB1R3_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB1R3_SECBB21 FLASH_SECBB1R3_SECBB21_Msk /*!< Page 85 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB22_Pos (22UL) +#define FLASH_SECBB1R3_SECBB22_Msk (0x1UL << FLASH_SECBB1R3_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB1R3_SECBB22 FLASH_SECBB1R3_SECBB22_Msk /*!< Page 86 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB23_Pos (23UL) +#define FLASH_SECBB1R3_SECBB23_Msk (0x1UL << FLASH_SECBB1R3_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB1R3_SECBB23 FLASH_SECBB1R3_SECBB23_Msk /*!< Page 87 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB24_Pos (24UL) +#define FLASH_SECBB1R3_SECBB24_Msk (0x1UL << FLASH_SECBB1R3_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB1R3_SECBB24 FLASH_SECBB1R3_SECBB24_Msk /*!< Page 88 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB25_Pos (25UL) +#define FLASH_SECBB1R3_SECBB25_Msk (0x1UL << FLASH_SECBB1R3_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB1R3_SECBB25 FLASH_SECBB1R3_SECBB25_Msk /*!< Page 89 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB26_Pos (26UL) +#define FLASH_SECBB1R3_SECBB26_Msk (0x1UL << FLASH_SECBB1R3_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB1R3_SECBB26 FLASH_SECBB1R3_SECBB26_Msk /*!< Page 90 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB27_Pos (27UL) +#define FLASH_SECBB1R3_SECBB27_Msk (0x1UL << FLASH_SECBB1R3_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB1R3_SECBB27 FLASH_SECBB1R3_SECBB27_Msk /*!< Page 91 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB28_Pos (28UL) +#define FLASH_SECBB1R3_SECBB28_Msk (0x1UL << FLASH_SECBB1R3_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB1R3_SECBB28 FLASH_SECBB1R3_SECBB28_Msk /*!< Page 92 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB29_Pos (29UL) +#define FLASH_SECBB1R3_SECBB29_Msk (0x1UL << FLASH_SECBB1R3_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB1R3_SECBB29 FLASH_SECBB1R3_SECBB29_Msk /*!< Page 93 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB30_Pos (30UL) +#define FLASH_SECBB1R3_SECBB30_Msk (0x1UL << FLASH_SECBB1R3_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB1R3_SECBB30 FLASH_SECBB1R3_SECBB30_Msk /*!< Page 94 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R3_SECBB31_Pos (31UL) +#define FLASH_SECBB1R3_SECBB31_Msk (0x1UL << FLASH_SECBB1R3_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB1R3_SECBB31 FLASH_SECBB1R3_SECBB31_Msk /*!< Page 95 in Flash bank 1 block-based secure */ + +/******************* Bit definition for FLASH_SECBB1R4 register ******************/ +#define FLASH_SECBB1R4_SECBB0_Pos (0UL) +#define FLASH_SECBB1R4_SECBB0_Msk (0x1UL << FLASH_SECBB1R4_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB1R4_SECBB0 FLASH_SECBB1R4_SECBB0_Msk /*!< Page 96 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB1_Pos (1UL) +#define FLASH_SECBB1R4_SECBB1_Msk (0x1UL << FLASH_SECBB1R4_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB1R4_SECBB1 FLASH_SECBB1R4_SECBB1_Msk /*!< Page 97 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB2_Pos (2UL) +#define FLASH_SECBB1R4_SECBB2_Msk (0x1UL << FLASH_SECBB1R4_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB1R4_SECBB2 FLASH_SECBB1R4_SECBB2_Msk /*!< Page 98 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB3_Pos (3UL) +#define FLASH_SECBB1R4_SECBB3_Msk (0x1UL << FLASH_SECBB1R4_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB1R4_SECBB3 FLASH_SECBB1R4_SECBB3_Msk /*!< Page 99 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB4_Pos (4UL) +#define FLASH_SECBB1R4_SECBB4_Msk (0x1UL << FLASH_SECBB1R4_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB1R4_SECBB4 FLASH_SECBB1R4_SECBB4_Msk /*!< Page 100 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB5_Pos (5UL) +#define FLASH_SECBB1R4_SECBB5_Msk (0x1UL << FLASH_SECBB1R4_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB1R4_SECBB5 FLASH_SECBB1R4_SECBB5_Msk /*!< Page 101 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB6_Pos (6UL) +#define FLASH_SECBB1R4_SECBB6_Msk (0x1UL << FLASH_SECBB1R4_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB1R4_SECBB6 FLASH_SECBB1R4_SECBB6_Msk /*!< Page 102 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB7_Pos (7UL) +#define FLASH_SECBB1R4_SECBB7_Msk (0x1UL << FLASH_SECBB1R4_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB1R4_SECBB7 FLASH_SECBB1R4_SECBB7_Msk /*!< Page 103 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB8_Pos (8UL) +#define FLASH_SECBB1R4_SECBB8_Msk (0x1UL << FLASH_SECBB1R4_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB1R4_SECBB8 FLASH_SECBB1R4_SECBB8_Msk /*!< Page 104 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB9_Pos (9UL) +#define FLASH_SECBB1R4_SECBB9_Msk (0x1UL << FLASH_SECBB1R4_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB1R4_SECBB9 FLASH_SECBB1R4_SECBB9_Msk /*!< Page 105 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB10_Pos (10UL) +#define FLASH_SECBB1R4_SECBB10_Msk (0x1UL << FLASH_SECBB1R4_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB1R4_SECBB10 FLASH_SECBB1R4_SECBB10_Msk /*!< Page 106 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB11_Pos (11UL) +#define FLASH_SECBB1R4_SECBB11_Msk (0x1UL << FLASH_SECBB1R4_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB1R4_SECBB11 FLASH_SECBB1R4_SECBB11_Msk /*!< Page 107 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB12_Pos (12UL) +#define FLASH_SECBB1R4_SECBB12_Msk (0x1UL << FLASH_SECBB1R4_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB1R4_SECBB12 FLASH_SECBB1R4_SECBB12_Msk /*!< Page 108 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB13_Pos (13UL) +#define FLASH_SECBB1R4_SECBB13_Msk (0x1UL << FLASH_SECBB1R4_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB1R4_SECBB13 FLASH_SECBB1R4_SECBB13_Msk /*!< Page 109 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB14_Pos (14UL) +#define FLASH_SECBB1R4_SECBB14_Msk (0x1UL << FLASH_SECBB1R4_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB1R4_SECBB14 FLASH_SECBB1R4_SECBB14_Msk /*!< Page 110 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB15_Pos (15UL) +#define FLASH_SECBB1R4_SECBB15_Msk (0x1UL << FLASH_SECBB1R4_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB1R4_SECBB15 FLASH_SECBB1R4_SECBB15_Msk /*!< Page 111 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB16_Pos (16UL) +#define FLASH_SECBB1R4_SECBB16_Msk (0x1UL << FLASH_SECBB1R4_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB1R4_SECBB16 FLASH_SECBB1R4_SECBB16_Msk /*!< Page 112 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB17_Pos (17UL) +#define FLASH_SECBB1R4_SECBB17_Msk (0x1UL << FLASH_SECBB1R4_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB1R4_SECBB17 FLASH_SECBB1R4_SECBB17_Msk /*!< Page 113 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB18_Pos (18UL) +#define FLASH_SECBB1R4_SECBB18_Msk (0x1UL << FLASH_SECBB1R4_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB1R4_SECBB18 FLASH_SECBB1R4_SECBB18_Msk /*!< Page 114 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB19_Pos (19UL) +#define FLASH_SECBB1R4_SECBB19_Msk (0x1UL << FLASH_SECBB1R4_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB1R4_SECBB19 FLASH_SECBB1R4_SECBB19_Msk /*!< Page 115 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB20_Pos (20UL) +#define FLASH_SECBB1R4_SECBB20_Msk (0x1UL << FLASH_SECBB1R4_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB1R4_SECBB20 FLASH_SECBB1R4_SECBB20_Msk /*!< Page 116 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB21_Pos (21UL) +#define FLASH_SECBB1R4_SECBB21_Msk (0x1UL << FLASH_SECBB1R4_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB1R4_SECBB21 FLASH_SECBB1R4_SECBB21_Msk /*!< Page 117 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB22_Pos (22UL) +#define FLASH_SECBB1R4_SECBB22_Msk (0x1UL << FLASH_SECBB1R4_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB1R4_SECBB22 FLASH_SECBB1R4_SECBB22_Msk /*!< Page 118 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB23_Pos (23UL) +#define FLASH_SECBB1R4_SECBB23_Msk (0x1UL << FLASH_SECBB1R4_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB1R4_SECBB23 FLASH_SECBB1R4_SECBB23_Msk /*!< Page 119 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB24_Pos (24UL) +#define FLASH_SECBB1R4_SECBB24_Msk (0x1UL << FLASH_SECBB1R4_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB1R4_SECBB24 FLASH_SECBB1R4_SECBB24_Msk /*!< Page 120 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB25_Pos (25UL) +#define FLASH_SECBB1R4_SECBB25_Msk (0x1UL << FLASH_SECBB1R4_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB1R4_SECBB25 FLASH_SECBB1R4_SECBB25_Msk /*!< Page 121 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB26_Pos (26UL) +#define FLASH_SECBB1R4_SECBB26_Msk (0x1UL << FLASH_SECBB1R4_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB1R4_SECBB26 FLASH_SECBB1R4_SECBB26_Msk /*!< Page 122 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB27_Pos (27UL) +#define FLASH_SECBB1R4_SECBB27_Msk (0x1UL << FLASH_SECBB1R4_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB1R4_SECBB27 FLASH_SECBB1R4_SECBB27_Msk /*!< Page 123 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB28_Pos (28UL) +#define FLASH_SECBB1R4_SECBB28_Msk (0x1UL << FLASH_SECBB1R4_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB1R4_SECBB28 FLASH_SECBB1R4_SECBB28_Msk /*!< Page 124 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB29_Pos (29UL) +#define FLASH_SECBB1R4_SECBB29_Msk (0x1UL << FLASH_SECBB1R4_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB1R4_SECBB29 FLASH_SECBB1R4_SECBB29_Msk /*!< Page 125 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB30_Pos (30UL) +#define FLASH_SECBB1R4_SECBB30_Msk (0x1UL << FLASH_SECBB1R4_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB1R4_SECBB30 FLASH_SECBB1R4_SECBB30_Msk /*!< Page 126 in Flash bank 1 block-based secure */ +#define FLASH_SECBB1R4_SECBB31_Pos (31UL) +#define FLASH_SECBB1R4_SECBB31_Msk (0x1UL << FLASH_SECBB1R4_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB1R4_SECBB31 FLASH_SECBB1R4_SECBB31_Msk /*!< Page 127 in Flash bank 1 block-based secure */ + +/******************* Bit definition for FLASH_SECBB2R1 register ******************/ +#define FLASH_SECBB2R1_SECBB0_Pos (0UL) +#define FLASH_SECBB2R1_SECBB0_Msk (0x1UL << FLASH_SECBB2R1_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB2R1_SECBB0 FLASH_SECBB2R1_SECBB0_Msk /*!< Page 0 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB1_Pos (1UL) +#define FLASH_SECBB2R1_SECBB1_Msk (0x1UL << FLASH_SECBB2R1_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB2R1_SECBB1 FLASH_SECBB2R1_SECBB1_Msk /*!< Page 1 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB2_Pos (2UL) +#define FLASH_SECBB2R1_SECBB2_Msk (0x1UL << FLASH_SECBB2R1_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB2R1_SECBB2 FLASH_SECBB2R1_SECBB2_Msk /*!< Page 2 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB3_Pos (3UL) +#define FLASH_SECBB2R1_SECBB3_Msk (0x1UL << FLASH_SECBB2R1_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB2R1_SECBB3 FLASH_SECBB2R1_SECBB3_Msk /*!< Page 3 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB4_Pos (4UL) +#define FLASH_SECBB2R1_SECBB4_Msk (0x1UL << FLASH_SECBB2R1_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB2R1_SECBB4 FLASH_SECBB2R1_SECBB4_Msk /*!< Page 4 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB5_Pos (5UL) +#define FLASH_SECBB2R1_SECBB5_Msk (0x1UL << FLASH_SECBB2R1_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB2R1_SECBB5 FLASH_SECBB2R1_SECBB5_Msk /*!< Page 5 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB6_Pos (6UL) +#define FLASH_SECBB2R1_SECBB6_Msk (0x1UL << FLASH_SECBB2R1_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB2R1_SECBB6 FLASH_SECBB2R1_SECBB6_Msk /*!< Page 6 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB7_Pos (7UL) +#define FLASH_SECBB2R1_SECBB7_Msk (0x1UL << FLASH_SECBB2R1_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB2R1_SECBB7 FLASH_SECBB2R1_SECBB7_Msk /*!< Page 7 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB8_Pos (8UL) +#define FLASH_SECBB2R1_SECBB8_Msk (0x1UL << FLASH_SECBB2R1_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB2R1_SECBB8 FLASH_SECBB2R1_SECBB8_Msk /*!< Page 8 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB9_Pos (9UL) +#define FLASH_SECBB2R1_SECBB9_Msk (0x1UL << FLASH_SECBB2R1_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB2R1_SECBB9 FLASH_SECBB2R1_SECBB9_Msk /*!< Page 9 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB10_Pos (10UL) +#define FLASH_SECBB2R1_SECBB10_Msk (0x1UL << FLASH_SECBB2R1_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB2R1_SECBB10 FLASH_SECBB2R1_SECBB10_Msk /*!< Page 10 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB11_Pos (11UL) +#define FLASH_SECBB2R1_SECBB11_Msk (0x1UL << FLASH_SECBB2R1_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB2R1_SECBB11 FLASH_SECBB2R1_SECBB11_Msk /*!< Page 11 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB12_Pos (12UL) +#define FLASH_SECBB2R1_SECBB12_Msk (0x1UL << FLASH_SECBB2R1_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB2R1_SECBB12 FLASH_SECBB2R1_SECBB12_Msk /*!< Page 12 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB13_Pos (13UL) +#define FLASH_SECBB2R1_SECBB13_Msk (0x1UL << FLASH_SECBB2R1_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB2R1_SECBB13 FLASH_SECBB2R1_SECBB13_Msk /*!< Page 13 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB14_Pos (14UL) +#define FLASH_SECBB2R1_SECBB14_Msk (0x1UL << FLASH_SECBB2R1_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB2R1_SECBB14 FLASH_SECBB2R1_SECBB14_Msk /*!< Page 14 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB15_Pos (15UL) +#define FLASH_SECBB2R1_SECBB15_Msk (0x1UL << FLASH_SECBB2R1_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB2R1_SECBB15 FLASH_SECBB2R1_SECBB15_Msk /*!< Page 15 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB16_Pos (16UL) +#define FLASH_SECBB2R1_SECBB16_Msk (0x1UL << FLASH_SECBB2R1_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB2R1_SECBB16 FLASH_SECBB2R1_SECBB16_Msk /*!< Page 16 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB17_Pos (17UL) +#define FLASH_SECBB2R1_SECBB17_Msk (0x1UL << FLASH_SECBB2R1_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB2R1_SECBB17 FLASH_SECBB2R1_SECBB17_Msk /*!< Page 17 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB18_Pos (18UL) +#define FLASH_SECBB2R1_SECBB18_Msk (0x1UL << FLASH_SECBB2R1_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB2R1_SECBB18 FLASH_SECBB2R1_SECBB18_Msk /*!< Page 18 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB19_Pos (19UL) +#define FLASH_SECBB2R1_SECBB19_Msk (0x1UL << FLASH_SECBB2R1_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB2R1_SECBB19 FLASH_SECBB2R1_SECBB19_Msk /*!< Page 19 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB20_Pos (20UL) +#define FLASH_SECBB2R1_SECBB20_Msk (0x1UL << FLASH_SECBB2R1_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB2R1_SECBB20 FLASH_SECBB2R1_SECBB20_Msk /*!< Page 20 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB21_Pos (21UL) +#define FLASH_SECBB2R1_SECBB21_Msk (0x1UL << FLASH_SECBB2R1_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB2R1_SECBB21 FLASH_SECBB2R1_SECBB21_Msk /*!< Page 21 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB22_Pos (22UL) +#define FLASH_SECBB2R1_SECBB22_Msk (0x1UL << FLASH_SECBB2R1_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB2R1_SECBB22 FLASH_SECBB2R1_SECBB22_Msk /*!< Page 22 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB23_Pos (23UL) +#define FLASH_SECBB2R1_SECBB23_Msk (0x1UL << FLASH_SECBB2R1_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB2R1_SECBB23 FLASH_SECBB2R1_SECBB23_Msk /*!< Page 23 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB24_Pos (24UL) +#define FLASH_SECBB2R1_SECBB24_Msk (0x1UL << FLASH_SECBB2R1_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB2R1_SECBB24 FLASH_SECBB2R1_SECBB24_Msk /*!< Page 24 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB25_Pos (25UL) +#define FLASH_SECBB2R1_SECBB25_Msk (0x1UL << FLASH_SECBB2R1_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB2R1_SECBB25 FLASH_SECBB2R1_SECBB25_Msk /*!< Page 25 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB26_Pos (26UL) +#define FLASH_SECBB2R1_SECBB26_Msk (0x1UL << FLASH_SECBB2R1_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB2R1_SECBB26 FLASH_SECBB2R1_SECBB26_Msk /*!< Page 26 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB27_Pos (27UL) +#define FLASH_SECBB2R1_SECBB27_Msk (0x1UL << FLASH_SECBB2R1_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB2R1_SECBB27 FLASH_SECBB2R1_SECBB27_Msk /*!< Page 27 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB28_Pos (28UL) +#define FLASH_SECBB2R1_SECBB28_Msk (0x1UL << FLASH_SECBB2R1_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB2R1_SECBB28 FLASH_SECBB2R1_SECBB28_Msk /*!< Page 28 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB29_Pos (29UL) +#define FLASH_SECBB2R1_SECBB29_Msk (0x1UL << FLASH_SECBB2R1_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB2R1_SECBB29 FLASH_SECBB2R1_SECBB29_Msk /*!< Page 29 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB30_Pos (30UL) +#define FLASH_SECBB2R1_SECBB30_Msk (0x1UL << FLASH_SECBB2R1_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB2R1_SECBB30 FLASH_SECBB2R1_SECBB30_Msk /*!< Page 30 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R1_SECBB31_Pos (31UL) +#define FLASH_SECBB2R1_SECBB31_Msk (0x1UL << FLASH_SECBB2R1_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB2R1_SECBB31 FLASH_SECBB2R1_SECBB31_Msk /*!< Page 31 in Flash bank 2 block-based secure */ + +/******************* Bit definition for FLASH_SECBB2R2 register ******************/ +#define FLASH_SECBB2R2_SECBB0_Pos (0UL) +#define FLASH_SECBB2R2_SECBB0_Msk (0x1UL << FLASH_SECBB2R2_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB2R2_SECBB0 FLASH_SECBB2R2_SECBB0_Msk /*!< Page 32 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB1_Pos (1UL) +#define FLASH_SECBB2R2_SECBB1_Msk (0x1UL << FLASH_SECBB2R2_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB2R2_SECBB1 FLASH_SECBB2R2_SECBB1_Msk /*!< Page 33 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB2_Pos (2UL) +#define FLASH_SECBB2R2_SECBB2_Msk (0x1UL << FLASH_SECBB2R2_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB2R2_SECBB2 FLASH_SECBB2R2_SECBB2_Msk /*!< Page 34 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB3_Pos (3UL) +#define FLASH_SECBB2R2_SECBB3_Msk (0x1UL << FLASH_SECBB2R2_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB2R2_SECBB3 FLASH_SECBB2R2_SECBB3_Msk /*!< Page 35 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB4_Pos (4UL) +#define FLASH_SECBB2R2_SECBB4_Msk (0x1UL << FLASH_SECBB2R2_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB2R2_SECBB4 FLASH_SECBB2R2_SECBB4_Msk /*!< Page 36 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB5_Pos (5UL) +#define FLASH_SECBB2R2_SECBB5_Msk (0x1UL << FLASH_SECBB2R2_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB2R2_SECBB5 FLASH_SECBB2R2_SECBB5_Msk /*!< Page 37 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB6_Pos (6UL) +#define FLASH_SECBB2R2_SECBB6_Msk (0x1UL << FLASH_SECBB2R2_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB2R2_SECBB6 FLASH_SECBB2R2_SECBB6_Msk /*!< Page 38 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB7_Pos (7UL) +#define FLASH_SECBB2R2_SECBB7_Msk (0x1UL << FLASH_SECBB2R2_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB2R2_SECBB7 FLASH_SECBB2R2_SECBB7_Msk /*!< Page 39 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB8_Pos (8UL) +#define FLASH_SECBB2R2_SECBB8_Msk (0x1UL << FLASH_SECBB2R2_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB2R2_SECBB8 FLASH_SECBB2R2_SECBB8_Msk /*!< Page 40 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB9_Pos (9UL) +#define FLASH_SECBB2R2_SECBB9_Msk (0x1UL << FLASH_SECBB2R2_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB2R2_SECBB9 FLASH_SECBB2R2_SECBB9_Msk /*!< Page 41 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB10_Pos (10UL) +#define FLASH_SECBB2R2_SECBB10_Msk (0x1UL << FLASH_SECBB2R2_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB2R2_SECBB10 FLASH_SECBB2R2_SECBB10_Msk /*!< Page 42 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB11_Pos (11UL) +#define FLASH_SECBB2R2_SECBB11_Msk (0x1UL << FLASH_SECBB2R2_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB2R2_SECBB11 FLASH_SECBB2R2_SECBB11_Msk /*!< Page 43 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB12_Pos (12UL) +#define FLASH_SECBB2R2_SECBB12_Msk (0x1UL << FLASH_SECBB2R2_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB2R2_SECBB12 FLASH_SECBB2R2_SECBB12_Msk /*!< Page 44 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB13_Pos (13UL) +#define FLASH_SECBB2R2_SECBB13_Msk (0x1UL << FLASH_SECBB2R2_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB2R2_SECBB13 FLASH_SECBB2R2_SECBB13_Msk /*!< Page 45 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB14_Pos (14UL) +#define FLASH_SECBB2R2_SECBB14_Msk (0x1UL << FLASH_SECBB2R2_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB2R2_SECBB14 FLASH_SECBB2R2_SECBB14_Msk /*!< Page 46 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB15_Pos (15UL) +#define FLASH_SECBB2R2_SECBB15_Msk (0x1UL << FLASH_SECBB2R2_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB2R2_SECBB15 FLASH_SECBB2R2_SECBB15_Msk /*!< Page 47 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB16_Pos (16UL) +#define FLASH_SECBB2R2_SECBB16_Msk (0x1UL << FLASH_SECBB2R2_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB2R2_SECBB16 FLASH_SECBB2R2_SECBB16_Msk /*!< Page 48 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB17_Pos (17UL) +#define FLASH_SECBB2R2_SECBB17_Msk (0x1UL << FLASH_SECBB2R2_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB2R2_SECBB17 FLASH_SECBB2R2_SECBB17_Msk /*!< Page 49 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB18_Pos (18UL) +#define FLASH_SECBB2R2_SECBB18_Msk (0x1UL << FLASH_SECBB2R2_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB2R2_SECBB18 FLASH_SECBB2R2_SECBB18_Msk /*!< Page 50 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB19_Pos (19UL) +#define FLASH_SECBB2R2_SECBB19_Msk (0x1UL << FLASH_SECBB2R2_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB2R2_SECBB19 FLASH_SECBB2R2_SECBB19_Msk /*!< Page 51 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB20_Pos (20UL) +#define FLASH_SECBB2R2_SECBB20_Msk (0x1UL << FLASH_SECBB2R2_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB2R2_SECBB20 FLASH_SECBB2R2_SECBB20_Msk /*!< Page 52 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB21_Pos (21UL) +#define FLASH_SECBB2R2_SECBB21_Msk (0x1UL << FLASH_SECBB2R2_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB2R2_SECBB21 FLASH_SECBB2R2_SECBB21_Msk /*!< Page 53 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB22_Pos (22UL) +#define FLASH_SECBB2R2_SECBB22_Msk (0x1UL << FLASH_SECBB2R2_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB2R2_SECBB22 FLASH_SECBB2R2_SECBB22_Msk /*!< Page 54 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB23_Pos (23UL) +#define FLASH_SECBB2R2_SECBB23_Msk (0x1UL << FLASH_SECBB2R2_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB2R2_SECBB23 FLASH_SECBB2R2_SECBB23_Msk /*!< Page 55 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB24_Pos (24UL) +#define FLASH_SECBB2R2_SECBB24_Msk (0x1UL << FLASH_SECBB2R2_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB2R2_SECBB24 FLASH_SECBB2R2_SECBB24_Msk /*!< Page 56 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB25_Pos (25UL) +#define FLASH_SECBB2R2_SECBB25_Msk (0x1UL << FLASH_SECBB2R2_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB2R2_SECBB25 FLASH_SECBB2R2_SECBB25_Msk /*!< Page 57 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB26_Pos (26UL) +#define FLASH_SECBB2R2_SECBB26_Msk (0x1UL << FLASH_SECBB2R2_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB2R2_SECBB26 FLASH_SECBB2R2_SECBB26_Msk /*!< Page 58 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB27_Pos (27UL) +#define FLASH_SECBB2R2_SECBB27_Msk (0x1UL << FLASH_SECBB2R2_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB2R2_SECBB27 FLASH_SECBB2R2_SECBB27_Msk /*!< Page 59 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB28_Pos (28UL) +#define FLASH_SECBB2R2_SECBB28_Msk (0x1UL << FLASH_SECBB2R2_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB2R2_SECBB28 FLASH_SECBB2R2_SECBB28_Msk /*!< Page 60 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB29_Pos (29UL) +#define FLASH_SECBB2R2_SECBB29_Msk (0x1UL << FLASH_SECBB2R2_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB2R2_SECBB29 FLASH_SECBB2R2_SECBB29_Msk /*!< Page 61 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB30_Pos (30UL) +#define FLASH_SECBB2R2_SECBB30_Msk (0x1UL << FLASH_SECBB2R2_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB2R2_SECBB30 FLASH_SECBB2R2_SECBB30_Msk /*!< Page 62 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R2_SECBB31_Pos (31UL) +#define FLASH_SECBB2R2_SECBB31_Msk (0x1UL << FLASH_SECBB2R2_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB2R2_SECBB31 FLASH_SECBB2R2_SECBB31_Msk /*!< Page 63 in Flash bank 2 block-based secure */ + +/******************* Bit definition for FLASH_SECBB2R3 register ******************/ +#define FLASH_SECBB2R3_SECBB0_Pos (0UL) +#define FLASH_SECBB2R3_SECBB0_Msk (0x1UL << FLASH_SECBB2R3_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB2R3_SECBB0 FLASH_SECBB2R3_SECBB0_Msk /*!< Page 64 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB1_Pos (1UL) +#define FLASH_SECBB2R3_SECBB1_Msk (0x1UL << FLASH_SECBB2R3_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB2R3_SECBB1 FLASH_SECBB2R3_SECBB1_Msk /*!< Page 65 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB2_Pos (2UL) +#define FLASH_SECBB2R3_SECBB2_Msk (0x1UL << FLASH_SECBB2R3_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB2R3_SECBB2 FLASH_SECBB2R3_SECBB2_Msk /*!< Page 66 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB3_Pos (3UL) +#define FLASH_SECBB2R3_SECBB3_Msk (0x1UL << FLASH_SECBB2R3_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB2R3_SECBB3 FLASH_SECBB2R3_SECBB3_Msk /*!< Page 67 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB4_Pos (4UL) +#define FLASH_SECBB2R3_SECBB4_Msk (0x1UL << FLASH_SECBB2R3_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB2R3_SECBB4 FLASH_SECBB2R3_SECBB4_Msk /*!< Page 68 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB5_Pos (5UL) +#define FLASH_SECBB2R3_SECBB5_Msk (0x1UL << FLASH_SECBB2R3_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB2R3_SECBB5 FLASH_SECBB2R3_SECBB5_Msk /*!< Page 69 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB6_Pos (6UL) +#define FLASH_SECBB2R3_SECBB6_Msk (0x1UL << FLASH_SECBB2R3_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB2R3_SECBB6 FLASH_SECBB2R3_SECBB6_Msk /*!< Page 70 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB7_Pos (7UL) +#define FLASH_SECBB2R3_SECBB7_Msk (0x1UL << FLASH_SECBB2R3_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB2R3_SECBB7 FLASH_SECBB2R3_SECBB7_Msk /*!< Page 71 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB8_Pos (8UL) +#define FLASH_SECBB2R3_SECBB8_Msk (0x1UL << FLASH_SECBB2R3_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB2R3_SECBB8 FLASH_SECBB2R3_SECBB8_Msk /*!< Page 72 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB9_Pos (9UL) +#define FLASH_SECBB2R3_SECBB9_Msk (0x1UL << FLASH_SECBB2R3_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB2R3_SECBB9 FLASH_SECBB2R3_SECBB9_Msk /*!< Page 73 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB10_Pos (10UL) +#define FLASH_SECBB2R3_SECBB10_Msk (0x1UL << FLASH_SECBB2R3_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB2R3_SECBB10 FLASH_SECBB2R3_SECBB10_Msk /*!< Page 74 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB11_Pos (11UL) +#define FLASH_SECBB2R3_SECBB11_Msk (0x1UL << FLASH_SECBB2R3_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB2R3_SECBB11 FLASH_SECBB2R3_SECBB11_Msk /*!< Page 75 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB12_Pos (12UL) +#define FLASH_SECBB2R3_SECBB12_Msk (0x1UL << FLASH_SECBB2R3_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB2R3_SECBB12 FLASH_SECBB2R3_SECBB12_Msk /*!< Page 76 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB13_Pos (13UL) +#define FLASH_SECBB2R3_SECBB13_Msk (0x1UL << FLASH_SECBB2R3_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB2R3_SECBB13 FLASH_SECBB2R3_SECBB13_Msk /*!< Page 77 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB14_Pos (14UL) +#define FLASH_SECBB2R3_SECBB14_Msk (0x1UL << FLASH_SECBB2R3_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB2R3_SECBB14 FLASH_SECBB2R3_SECBB14_Msk /*!< Page 78 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB15_Pos (15UL) +#define FLASH_SECBB2R3_SECBB15_Msk (0x1UL << FLASH_SECBB2R3_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB2R3_SECBB15 FLASH_SECBB2R3_SECBB15_Msk /*!< Page 79 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB16_Pos (16UL) +#define FLASH_SECBB2R3_SECBB16_Msk (0x1UL << FLASH_SECBB2R3_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB2R3_SECBB16 FLASH_SECBB2R3_SECBB16_Msk /*!< Page 80 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB17_Pos (17UL) +#define FLASH_SECBB2R3_SECBB17_Msk (0x1UL << FLASH_SECBB2R3_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB2R3_SECBB17 FLASH_SECBB2R3_SECBB17_Msk /*!< Page 81 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB18_Pos (18UL) +#define FLASH_SECBB2R3_SECBB18_Msk (0x1UL << FLASH_SECBB2R3_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB2R3_SECBB18 FLASH_SECBB2R3_SECBB18_Msk /*!< Page 82 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB19_Pos (19UL) +#define FLASH_SECBB2R3_SECBB19_Msk (0x1UL << FLASH_SECBB2R3_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB2R3_SECBB19 FLASH_SECBB2R3_SECBB19_Msk /*!< Page 83 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB20_Pos (20UL) +#define FLASH_SECBB2R3_SECBB20_Msk (0x1UL << FLASH_SECBB2R3_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB2R3_SECBB20 FLASH_SECBB2R3_SECBB20_Msk /*!< Page 84 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB21_Pos (21UL) +#define FLASH_SECBB2R3_SECBB21_Msk (0x1UL << FLASH_SECBB2R3_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB2R3_SECBB21 FLASH_SECBB2R3_SECBB21_Msk /*!< Page 85 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB22_Pos (22UL) +#define FLASH_SECBB2R3_SECBB22_Msk (0x1UL << FLASH_SECBB2R3_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB2R3_SECBB22 FLASH_SECBB2R3_SECBB22_Msk /*!< Page 86 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB23_Pos (23UL) +#define FLASH_SECBB2R3_SECBB23_Msk (0x1UL << FLASH_SECBB2R3_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB2R3_SECBB23 FLASH_SECBB2R3_SECBB23_Msk /*!< Page 87 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB24_Pos (24UL) +#define FLASH_SECBB2R3_SECBB24_Msk (0x1UL << FLASH_SECBB2R3_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB2R3_SECBB24 FLASH_SECBB2R3_SECBB24_Msk /*!< Page 88 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB25_Pos (25UL) +#define FLASH_SECBB2R3_SECBB25_Msk (0x1UL << FLASH_SECBB2R3_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB2R3_SECBB25 FLASH_SECBB2R3_SECBB25_Msk /*!< Page 89 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB26_Pos (26UL) +#define FLASH_SECBB2R3_SECBB26_Msk (0x1UL << FLASH_SECBB2R3_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB2R3_SECBB26 FLASH_SECBB2R3_SECBB26_Msk /*!< Page 90 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB27_Pos (27UL) +#define FLASH_SECBB2R3_SECBB27_Msk (0x1UL << FLASH_SECBB2R3_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB2R3_SECBB27 FLASH_SECBB2R3_SECBB27_Msk /*!< Page 91 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB28_Pos (28UL) +#define FLASH_SECBB2R3_SECBB28_Msk (0x1UL << FLASH_SECBB2R3_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB2R3_SECBB28 FLASH_SECBB2R3_SECBB28_Msk /*!< Page 92 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB29_Pos (29UL) +#define FLASH_SECBB2R3_SECBB29_Msk (0x1UL << FLASH_SECBB2R3_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB2R3_SECBB29 FLASH_SECBB2R3_SECBB29_Msk /*!< Page 93 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB30_Pos (30UL) +#define FLASH_SECBB2R3_SECBB30_Msk (0x1UL << FLASH_SECBB2R3_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB2R3_SECBB30 FLASH_SECBB2R3_SECBB30_Msk /*!< Page 94 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R3_SECBB31_Pos (31UL) +#define FLASH_SECBB2R3_SECBB31_Msk (0x1UL << FLASH_SECBB2R3_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB2R3_SECBB31 FLASH_SECBB2R3_SECBB31_Msk /*!< Page 95 in Flash bank 2 block-based secure */ + +/******************* Bit definition for FLASH_SECBB2R4 register ******************/ +#define FLASH_SECBB2R4_SECBB0_Pos (0UL) +#define FLASH_SECBB2R4_SECBB0_Msk (0x1UL << FLASH_SECBB2R4_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBB2R4_SECBB0 FLASH_SECBB2R4_SECBB0_Msk /*!< Page 96 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB1_Pos (1UL) +#define FLASH_SECBB2R4_SECBB1_Msk (0x1UL << FLASH_SECBB2R4_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBB2R4_SECBB1 FLASH_SECBB2R4_SECBB1_Msk /*!< Page 97 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB2_Pos (2UL) +#define FLASH_SECBB2R4_SECBB2_Msk (0x1UL << FLASH_SECBB2R4_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBB2R4_SECBB2 FLASH_SECBB2R4_SECBB2_Msk /*!< Page 98 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB3_Pos (3UL) +#define FLASH_SECBB2R4_SECBB3_Msk (0x1UL << FLASH_SECBB2R4_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBB2R4_SECBB3 FLASH_SECBB2R4_SECBB3_Msk /*!< Page 99 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB4_Pos (4UL) +#define FLASH_SECBB2R4_SECBB4_Msk (0x1UL << FLASH_SECBB2R4_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBB2R4_SECBB4 FLASH_SECBB2R4_SECBB4_Msk /*!< Page 100 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB5_Pos (5UL) +#define FLASH_SECBB2R4_SECBB5_Msk (0x1UL << FLASH_SECBB2R4_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBB2R4_SECBB5 FLASH_SECBB2R4_SECBB5_Msk /*!< Page 101 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB6_Pos (6UL) +#define FLASH_SECBB2R4_SECBB6_Msk (0x1UL << FLASH_SECBB2R4_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBB2R4_SECBB6 FLASH_SECBB2R4_SECBB6_Msk /*!< Page 102 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB7_Pos (7UL) +#define FLASH_SECBB2R4_SECBB7_Msk (0x1UL << FLASH_SECBB2R4_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBB2R4_SECBB7 FLASH_SECBB2R4_SECBB7_Msk /*!< Page 103 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB8_Pos (8UL) +#define FLASH_SECBB2R4_SECBB8_Msk (0x1UL << FLASH_SECBB2R4_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBB2R4_SECBB8 FLASH_SECBB2R4_SECBB8_Msk /*!< Page 104 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB9_Pos (9UL) +#define FLASH_SECBB2R4_SECBB9_Msk (0x1UL << FLASH_SECBB2R4_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBB2R4_SECBB9 FLASH_SECBB2R4_SECBB9_Msk /*!< Page 105 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB10_Pos (10UL) +#define FLASH_SECBB2R4_SECBB10_Msk (0x1UL << FLASH_SECBB2R4_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBB2R4_SECBB10 FLASH_SECBB2R4_SECBB10_Msk /*!< Page 106 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB11_Pos (11UL) +#define FLASH_SECBB2R4_SECBB11_Msk (0x1UL << FLASH_SECBB2R4_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBB2R4_SECBB11 FLASH_SECBB2R4_SECBB11_Msk /*!< Page 107 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB12_Pos (12UL) +#define FLASH_SECBB2R4_SECBB12_Msk (0x1UL << FLASH_SECBB2R4_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBB2R4_SECBB12 FLASH_SECBB2R4_SECBB12_Msk /*!< Page 108 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB13_Pos (13UL) +#define FLASH_SECBB2R4_SECBB13_Msk (0x1UL << FLASH_SECBB2R4_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBB2R4_SECBB13 FLASH_SECBB2R4_SECBB13_Msk /*!< Page 109 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB14_Pos (14UL) +#define FLASH_SECBB2R4_SECBB14_Msk (0x1UL << FLASH_SECBB2R4_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBB2R4_SECBB14 FLASH_SECBB2R4_SECBB14_Msk /*!< Page 110 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB15_Pos (15UL) +#define FLASH_SECBB2R4_SECBB15_Msk (0x1UL << FLASH_SECBB2R4_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBB2R4_SECBB15 FLASH_SECBB2R4_SECBB15_Msk /*!< Page 111 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB16_Pos (16UL) +#define FLASH_SECBB2R4_SECBB16_Msk (0x1UL << FLASH_SECBB2R4_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBB2R4_SECBB16 FLASH_SECBB2R4_SECBB16_Msk /*!< Page 112 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB17_Pos (17UL) +#define FLASH_SECBB2R4_SECBB17_Msk (0x1UL << FLASH_SECBB2R4_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBB2R4_SECBB17 FLASH_SECBB2R4_SECBB17_Msk /*!< Page 113 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB18_Pos (18UL) +#define FLASH_SECBB2R4_SECBB18_Msk (0x1UL << FLASH_SECBB2R4_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBB2R4_SECBB18 FLASH_SECBB2R4_SECBB18_Msk /*!< Page 114 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB19_Pos (19UL) +#define FLASH_SECBB2R4_SECBB19_Msk (0x1UL << FLASH_SECBB2R4_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBB2R4_SECBB19 FLASH_SECBB2R4_SECBB19_Msk /*!< Page 115 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB20_Pos (20UL) +#define FLASH_SECBB2R4_SECBB20_Msk (0x1UL << FLASH_SECBB2R4_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBB2R4_SECBB20 FLASH_SECBB2R4_SECBB20_Msk /*!< Page 116 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB21_Pos (21UL) +#define FLASH_SECBB2R4_SECBB21_Msk (0x1UL << FLASH_SECBB2R4_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBB2R4_SECBB21 FLASH_SECBB2R4_SECBB21_Msk /*!< Page 117 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB22_Pos (22UL) +#define FLASH_SECBB2R4_SECBB22_Msk (0x1UL << FLASH_SECBB2R4_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBB2R4_SECBB22 FLASH_SECBB2R4_SECBB22_Msk /*!< Page 118 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB23_Pos (23UL) +#define FLASH_SECBB2R4_SECBB23_Msk (0x1UL << FLASH_SECBB2R4_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBB2R4_SECBB23 FLASH_SECBB2R4_SECBB23_Msk /*!< Page 119 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB24_Pos (24UL) +#define FLASH_SECBB2R4_SECBB24_Msk (0x1UL << FLASH_SECBB2R4_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBB2R4_SECBB24 FLASH_SECBB2R4_SECBB24_Msk /*!< Page 120 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB25_Pos (25UL) +#define FLASH_SECBB2R4_SECBB25_Msk (0x1UL << FLASH_SECBB2R4_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBB2R4_SECBB25 FLASH_SECBB2R4_SECBB25_Msk /*!< Page 121 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB26_Pos (26UL) +#define FLASH_SECBB2R4_SECBB26_Msk (0x1UL << FLASH_SECBB2R4_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBB2R4_SECBB26 FLASH_SECBB2R4_SECBB26_Msk /*!< Page 122 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB27_Pos (27UL) +#define FLASH_SECBB2R4_SECBB27_Msk (0x1UL << FLASH_SECBB2R4_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBB2R4_SECBB27 FLASH_SECBB2R4_SECBB27_Msk /*!< Page 123 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB28_Pos (28UL) +#define FLASH_SECBB2R4_SECBB28_Msk (0x1UL << FLASH_SECBB2R4_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBB2R4_SECBB28 FLASH_SECBB2R4_SECBB28_Msk /*!< Page 124 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB29_Pos (29UL) +#define FLASH_SECBB2R4_SECBB29_Msk (0x1UL << FLASH_SECBB2R4_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBB2R4_SECBB29 FLASH_SECBB2R4_SECBB29_Msk /*!< Page 125 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB30_Pos (30UL) +#define FLASH_SECBB2R4_SECBB30_Msk (0x1UL << FLASH_SECBB2R4_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBB2R4_SECBB30 FLASH_SECBB2R4_SECBB30_Msk /*!< Page 126 in Flash bank 2 block-based secure */ +#define FLASH_SECBB2R4_SECBB31_Pos (31UL) +#define FLASH_SECBB2R4_SECBB31_Msk (0x1UL << FLASH_SECBB2R4_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBB2R4_SECBB31 FLASH_SECBB2R4_SECBB31_Msk /*!< Page 127 in Flash bank 2 block-based secure */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< Bank 1 secure HDP area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< Bank 2 secure HDP area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************* Bit definition for FLASH_PRIVBB1R1 register ******************/ +#define FLASH_PRIVBB1R1_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB1R1_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB1R1_PRIVBB0 FLASH_PRIVBB1R1_PRIVBB0_Msk /*!< Page 0 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB1R1_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB1R1_PRIVBB1 FLASH_PRIVBB1R1_PRIVBB1_Msk /*!< Page 1 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB1R1_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB1R1_PRIVBB2 FLASH_PRIVBB1R1_PRIVBB2_Msk /*!< Page 2 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB1R1_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB1R1_PRIVBB3 FLASH_PRIVBB1R1_PRIVBB3_Msk /*!< Page 3 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB1R1_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB1R1_PRIVBB4 FLASH_PRIVBB1R1_PRIVBB4_Msk /*!< Page 4 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB1R1_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB1R1_PRIVBB5 FLASH_PRIVBB1R1_PRIVBB5_Msk /*!< Page 5 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB1R1_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB1R1_PRIVBB6 FLASH_PRIVBB1R1_PRIVBB6_Msk /*!< Page 6 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB1R1_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB1R1_PRIVBB7 FLASH_PRIVBB1R1_PRIVBB7_Msk /*!< Page 7 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB1R1_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB1R1_PRIVBB8 FLASH_PRIVBB1R1_PRIVBB8_Msk /*!< Page 8 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB1R1_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB1R1_PRIVBB9 FLASH_PRIVBB1R1_PRIVBB9_Msk /*!< Page 9 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB1R1_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB1R1_PRIVBB10 FLASH_PRIVBB1R1_PRIVBB10_Msk /*!< Page 10 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB1R1_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB1R1_PRIVBB11 FLASH_PRIVBB1R1_PRIVBB11_Msk /*!< Page 11 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB1R1_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB1R1_PRIVBB12 FLASH_PRIVBB1R1_PRIVBB12_Msk /*!< Page 12 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB1R1_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB1R1_PRIVBB13 FLASH_PRIVBB1R1_PRIVBB13_Msk /*!< Page 13 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB1R1_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB1R1_PRIVBB14 FLASH_PRIVBB1R1_PRIVBB14_Msk /*!< Page 14 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB1R1_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB1R1_PRIVBB15 FLASH_PRIVBB1R1_PRIVBB15_Msk /*!< Page 15 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB1R1_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB1R1_PRIVBB16 FLASH_PRIVBB1R1_PRIVBB16_Msk /*!< Page 16 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB1R1_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB1R1_PRIVBB17 FLASH_PRIVBB1R1_PRIVBB17_Msk /*!< Page 17 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB1R1_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB1R1_PRIVBB18 FLASH_PRIVBB1R1_PRIVBB18_Msk /*!< Page 18 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB1R1_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB1R1_PRIVBB19 FLASH_PRIVBB1R1_PRIVBB19_Msk /*!< Page 19 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB1R1_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB1R1_PRIVBB20 FLASH_PRIVBB1R1_PRIVBB20_Msk /*!< Page 20 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB1R1_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB1R1_PRIVBB21 FLASH_PRIVBB1R1_PRIVBB21_Msk /*!< Page 21 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB1R1_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB1R1_PRIVBB22 FLASH_PRIVBB1R1_PRIVBB22_Msk /*!< Page 22 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB1R1_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB1R1_PRIVBB23 FLASH_PRIVBB1R1_PRIVBB23_Msk /*!< Page 23 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB1R1_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB1R1_PRIVBB24 FLASH_PRIVBB1R1_PRIVBB24_Msk /*!< Page 24 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB1R1_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB1R1_PRIVBB25 FLASH_PRIVBB1R1_PRIVBB25_Msk /*!< Page 25 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB1R1_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB1R1_PRIVBB26 FLASH_PRIVBB1R1_PRIVBB26_Msk /*!< Page 26 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB1R1_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB1R1_PRIVBB27 FLASH_PRIVBB1R1_PRIVBB27_Msk /*!< Page 27 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB1R1_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB1R1_PRIVBB28 FLASH_PRIVBB1R1_PRIVBB28_Msk /*!< Page 28 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB1R1_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB1R1_PRIVBB29 FLASH_PRIVBB1R1_PRIVBB29_Msk /*!< Page 29 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB1R1_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB1R1_PRIVBB30 FLASH_PRIVBB1R1_PRIVBB30_Msk /*!< Page 30 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R1_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB1R1_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB1R1_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB1R1_PRIVBB31 FLASH_PRIVBB1R1_PRIVBB31_Msk /*!< Page 31 in Flash bank 1 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB1R2 register ******************/ +#define FLASH_PRIVBB1R2_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB1R2_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB1R2_PRIVBB0 FLASH_PRIVBB1R2_PRIVBB0_Msk /*!< Page 32 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB1R2_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB1R2_PRIVBB1 FLASH_PRIVBB1R2_PRIVBB1_Msk /*!< Page 33 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB1R2_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB1R2_PRIVBB2 FLASH_PRIVBB1R2_PRIVBB2_Msk /*!< Page 34 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB1R2_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB1R2_PRIVBB3 FLASH_PRIVBB1R2_PRIVBB3_Msk /*!< Page 35 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB1R2_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB1R2_PRIVBB4 FLASH_PRIVBB1R2_PRIVBB4_Msk /*!< Page 36 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB1R2_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB1R2_PRIVBB5 FLASH_PRIVBB1R2_PRIVBB5_Msk /*!< Page 37 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB1R2_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB1R2_PRIVBB6 FLASH_PRIVBB1R2_PRIVBB6_Msk /*!< Page 38 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB1R2_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB1R2_PRIVBB7 FLASH_PRIVBB1R2_PRIVBB7_Msk /*!< Page 39 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB1R2_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB1R2_PRIVBB8 FLASH_PRIVBB1R2_PRIVBB8_Msk /*!< Page 40 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB1R2_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB1R2_PRIVBB9 FLASH_PRIVBB1R2_PRIVBB9_Msk /*!< Page 41 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB1R2_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB1R2_PRIVBB10 FLASH_PRIVBB1R2_PRIVBB10_Msk /*!< Page 42 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB1R2_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB1R2_PRIVBB11 FLASH_PRIVBB1R2_PRIVBB11_Msk /*!< Page 43 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB1R2_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB1R2_PRIVBB12 FLASH_PRIVBB1R2_PRIVBB12_Msk /*!< Page 44 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB1R2_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB1R2_PRIVBB13 FLASH_PRIVBB1R2_PRIVBB13_Msk /*!< Page 45 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB1R2_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB1R2_PRIVBB14 FLASH_PRIVBB1R2_PRIVBB14_Msk /*!< Page 46 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB1R2_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB1R2_PRIVBB15 FLASH_PRIVBB1R2_PRIVBB15_Msk /*!< Page 47 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB1R2_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB1R2_PRIVBB16 FLASH_PRIVBB1R2_PRIVBB16_Msk /*!< Page 48 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB1R2_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB1R2_PRIVBB17 FLASH_PRIVBB1R2_PRIVBB17_Msk /*!< Page 49 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB1R2_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB1R2_PRIVBB18 FLASH_PRIVBB1R2_PRIVBB18_Msk /*!< Page 50 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB1R2_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB1R2_PRIVBB19 FLASH_PRIVBB1R2_PRIVBB19_Msk /*!< Page 51 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB1R2_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB1R2_PRIVBB20 FLASH_PRIVBB1R2_PRIVBB20_Msk /*!< Page 52 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB1R2_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB1R2_PRIVBB21 FLASH_PRIVBB1R2_PRIVBB21_Msk /*!< Page 53 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB1R2_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB1R2_PRIVBB22 FLASH_PRIVBB1R2_PRIVBB22_Msk /*!< Page 54 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB1R2_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB1R2_PRIVBB23 FLASH_PRIVBB1R2_PRIVBB23_Msk /*!< Page 55 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB1R2_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB1R2_PRIVBB24 FLASH_PRIVBB1R2_PRIVBB24_Msk /*!< Page 56 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB1R2_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB1R2_PRIVBB25 FLASH_PRIVBB1R2_PRIVBB25_Msk /*!< Page 57 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB1R2_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB1R2_PRIVBB26 FLASH_PRIVBB1R2_PRIVBB26_Msk /*!< Page 58 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB1R2_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB1R2_PRIVBB27 FLASH_PRIVBB1R2_PRIVBB27_Msk /*!< Page 59 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB1R2_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB1R2_PRIVBB28 FLASH_PRIVBB1R2_PRIVBB28_Msk /*!< Page 60 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB1R2_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB1R2_PRIVBB29 FLASH_PRIVBB1R2_PRIVBB29_Msk /*!< Page 61 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB1R2_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB1R2_PRIVBB30 FLASH_PRIVBB1R2_PRIVBB30_Msk /*!< Page 62 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R2_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB1R2_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB1R2_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB1R2_PRIVBB31 FLASH_PRIVBB1R2_PRIVBB31_Msk /*!< Page 63 in Flash bank 1 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB1R3 register ******************/ +#define FLASH_PRIVBB1R3_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB1R3_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB1R3_PRIVBB0 FLASH_PRIVBB1R3_PRIVBB0_Msk /*!< Page 64 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB1R3_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB1R3_PRIVBB1 FLASH_PRIVBB1R3_PRIVBB1_Msk /*!< Page 65 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB1R3_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB1R3_PRIVBB2 FLASH_PRIVBB1R3_PRIVBB2_Msk /*!< Page 66 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB1R3_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB1R3_PRIVBB3 FLASH_PRIVBB1R3_PRIVBB3_Msk /*!< Page 67 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB1R3_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB1R3_PRIVBB4 FLASH_PRIVBB1R3_PRIVBB4_Msk /*!< Page 68 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB1R3_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB1R3_PRIVBB5 FLASH_PRIVBB1R3_PRIVBB5_Msk /*!< Page 69 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB1R3_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB1R3_PRIVBB6 FLASH_PRIVBB1R3_PRIVBB6_Msk /*!< Page 70 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB1R3_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB1R3_PRIVBB7 FLASH_PRIVBB1R3_PRIVBB7_Msk /*!< Page 71 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB1R3_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB1R3_PRIVBB8 FLASH_PRIVBB1R3_PRIVBB8_Msk /*!< Page 72 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB1R3_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB1R3_PRIVBB9 FLASH_PRIVBB1R3_PRIVBB9_Msk /*!< Page 73 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB1R3_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB1R3_PRIVBB10 FLASH_PRIVBB1R3_PRIVBB10_Msk /*!< Page 74 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB1R3_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB1R3_PRIVBB11 FLASH_PRIVBB1R3_PRIVBB11_Msk /*!< Page 75 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB1R3_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB1R3_PRIVBB12 FLASH_PRIVBB1R3_PRIVBB12_Msk /*!< Page 76 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB1R3_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB1R3_PRIVBB13 FLASH_PRIVBB1R3_PRIVBB13_Msk /*!< Page 77 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB1R3_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB1R3_PRIVBB14 FLASH_PRIVBB1R3_PRIVBB14_Msk /*!< Page 78 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB1R3_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB1R3_PRIVBB15 FLASH_PRIVBB1R3_PRIVBB15_Msk /*!< Page 79 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB1R3_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB1R3_PRIVBB16 FLASH_PRIVBB1R3_PRIVBB16_Msk /*!< Page 80 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB1R3_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB1R3_PRIVBB17 FLASH_PRIVBB1R3_PRIVBB17_Msk /*!< Page 81 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB1R3_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB1R3_PRIVBB18 FLASH_PRIVBB1R3_PRIVBB18_Msk /*!< Page 82 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB1R3_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB1R3_PRIVBB19 FLASH_PRIVBB1R3_PRIVBB19_Msk /*!< Page 83 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB1R3_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB1R3_PRIVBB20 FLASH_PRIVBB1R3_PRIVBB20_Msk /*!< Page 84 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB1R3_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB1R3_PRIVBB21 FLASH_PRIVBB1R3_PRIVBB21_Msk /*!< Page 85 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB1R3_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB1R3_PRIVBB22 FLASH_PRIVBB1R3_PRIVBB22_Msk /*!< Page 86 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB1R3_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB1R3_PRIVBB23 FLASH_PRIVBB1R3_PRIVBB23_Msk /*!< Page 87 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB1R3_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB1R3_PRIVBB24 FLASH_PRIVBB1R3_PRIVBB24_Msk /*!< Page 88 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB1R3_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB1R3_PRIVBB25 FLASH_PRIVBB1R3_PRIVBB25_Msk /*!< Page 89 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB1R3_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB1R3_PRIVBB26 FLASH_PRIVBB1R3_PRIVBB26_Msk /*!< Page 90 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB1R3_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB1R3_PRIVBB27 FLASH_PRIVBB1R3_PRIVBB27_Msk /*!< Page 91 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB1R3_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB1R3_PRIVBB28 FLASH_PRIVBB1R3_PRIVBB28_Msk /*!< Page 92 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB1R3_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB1R3_PRIVBB29 FLASH_PRIVBB1R3_PRIVBB29_Msk /*!< Page 93 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB1R3_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB1R3_PRIVBB30 FLASH_PRIVBB1R3_PRIVBB30_Msk /*!< Page 94 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R3_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB1R3_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB1R3_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB1R3_PRIVBB31 FLASH_PRIVBB1R3_PRIVBB31_Msk /*!< Page 95 in Flash bank 1 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB1R4 register ******************/ +#define FLASH_PRIVBB1R4_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB1R4_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB1R4_PRIVBB0 FLASH_PRIVBB1R4_PRIVBB0_Msk /*!< Page 96 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB1R4_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB1R4_PRIVBB1 FLASH_PRIVBB1R4_PRIVBB1_Msk /*!< Page 97 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB1R4_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB1R4_PRIVBB2 FLASH_PRIVBB1R4_PRIVBB2_Msk /*!< Page 98 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB1R4_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB1R4_PRIVBB3 FLASH_PRIVBB1R4_PRIVBB3_Msk /*!< Page 99 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB1R4_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB1R4_PRIVBB4 FLASH_PRIVBB1R4_PRIVBB4_Msk /*!< Page 100 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB1R4_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB1R4_PRIVBB5 FLASH_PRIVBB1R4_PRIVBB5_Msk /*!< Page 101 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB1R4_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB1R4_PRIVBB6 FLASH_PRIVBB1R4_PRIVBB6_Msk /*!< Page 102 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB1R4_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB1R4_PRIVBB7 FLASH_PRIVBB1R4_PRIVBB7_Msk /*!< Page 103 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB1R4_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB1R4_PRIVBB8 FLASH_PRIVBB1R4_PRIVBB8_Msk /*!< Page 104 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB1R4_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB1R4_PRIVBB9 FLASH_PRIVBB1R4_PRIVBB9_Msk /*!< Page 105 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB1R4_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB1R4_PRIVBB10 FLASH_PRIVBB1R4_PRIVBB10_Msk /*!< Page 106 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB1R4_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB1R4_PRIVBB11 FLASH_PRIVBB1R4_PRIVBB11_Msk /*!< Page 107 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB1R4_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB1R4_PRIVBB12 FLASH_PRIVBB1R4_PRIVBB12_Msk /*!< Page 108 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB1R4_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB1R4_PRIVBB13 FLASH_PRIVBB1R4_PRIVBB13_Msk /*!< Page 109 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB1R4_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB1R4_PRIVBB14 FLASH_PRIVBB1R4_PRIVBB14_Msk /*!< Page 110 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB1R4_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB1R4_PRIVBB15 FLASH_PRIVBB1R4_PRIVBB15_Msk /*!< Page 111 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB1R4_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB1R4_PRIVBB16 FLASH_PRIVBB1R4_PRIVBB16_Msk /*!< Page 112 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB1R4_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB1R4_PRIVBB17 FLASH_PRIVBB1R4_PRIVBB17_Msk /*!< Page 113 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB1R4_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB1R4_PRIVBB18 FLASH_PRIVBB1R4_PRIVBB18_Msk /*!< Page 114 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB1R4_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB1R4_PRIVBB19 FLASH_PRIVBB1R4_PRIVBB19_Msk /*!< Page 115 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB1R4_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB1R4_PRIVBB20 FLASH_PRIVBB1R4_PRIVBB20_Msk /*!< Page 116 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB1R4_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB1R4_PRIVBB21 FLASH_PRIVBB1R4_PRIVBB21_Msk /*!< Page 117 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB1R4_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB1R4_PRIVBB22 FLASH_PRIVBB1R4_PRIVBB22_Msk /*!< Page 118 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB1R4_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB1R4_PRIVBB23 FLASH_PRIVBB1R4_PRIVBB23_Msk /*!< Page 119 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB1R4_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB1R4_PRIVBB24 FLASH_PRIVBB1R4_PRIVBB24_Msk /*!< Page 120 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB1R4_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB1R4_PRIVBB25 FLASH_PRIVBB1R4_PRIVBB25_Msk /*!< Page 121 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB1R4_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB1R4_PRIVBB26 FLASH_PRIVBB1R4_PRIVBB26_Msk /*!< Page 122 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB1R4_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB1R4_PRIVBB27 FLASH_PRIVBB1R4_PRIVBB27_Msk /*!< Page 123 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB1R4_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB1R4_PRIVBB28 FLASH_PRIVBB1R4_PRIVBB28_Msk /*!< Page 124 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB1R4_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB1R4_PRIVBB29 FLASH_PRIVBB1R4_PRIVBB29_Msk /*!< Page 125 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB1R4_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB1R4_PRIVBB30 FLASH_PRIVBB1R4_PRIVBB30_Msk /*!< Page 126 in Flash bank 1 only accessible by privileged access */ +#define FLASH_PRIVBB1R4_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB1R4_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB1R4_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB1R4_PRIVBB31 FLASH_PRIVBB1R4_PRIVBB31_Msk /*!< Page 127 in Flash bank 1 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB2R1 register ******************/ +#define FLASH_PRIVBB2R1_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB2R1_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB2R1_PRIVBB0 FLASH_PRIVBB2R1_PRIVBB0_Msk /*!< Page 0 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB2R1_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB2R1_PRIVBB1 FLASH_PRIVBB2R1_PRIVBB1_Msk /*!< Page 1 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB2R1_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB2R1_PRIVBB2 FLASH_PRIVBB2R1_PRIVBB2_Msk /*!< Page 2 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB2R1_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB2R1_PRIVBB3 FLASH_PRIVBB2R1_PRIVBB3_Msk /*!< Page 3 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB2R1_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB2R1_PRIVBB4 FLASH_PRIVBB2R1_PRIVBB4_Msk /*!< Page 4 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB2R1_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB2R1_PRIVBB5 FLASH_PRIVBB2R1_PRIVBB5_Msk /*!< Page 5 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB2R1_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB2R1_PRIVBB6 FLASH_PRIVBB2R1_PRIVBB6_Msk /*!< Page 6 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB2R1_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB2R1_PRIVBB7 FLASH_PRIVBB2R1_PRIVBB7_Msk /*!< Page 7 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB2R1_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB2R1_PRIVBB8 FLASH_PRIVBB2R1_PRIVBB8_Msk /*!< Page 8 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB2R1_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB2R1_PRIVBB9 FLASH_PRIVBB2R1_PRIVBB9_Msk /*!< Page 9 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB2R1_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB2R1_PRIVBB10 FLASH_PRIVBB2R1_PRIVBB10_Msk /*!< Page 10 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB2R1_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB2R1_PRIVBB11 FLASH_PRIVBB2R1_PRIVBB11_Msk /*!< Page 11 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB2R1_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB2R1_PRIVBB12 FLASH_PRIVBB2R1_PRIVBB12_Msk /*!< Page 12 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB2R1_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB2R1_PRIVBB13 FLASH_PRIVBB2R1_PRIVBB13_Msk /*!< Page 13 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB2R1_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB2R1_PRIVBB14 FLASH_PRIVBB2R1_PRIVBB14_Msk /*!< Page 14 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB2R1_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB2R1_PRIVBB15 FLASH_PRIVBB2R1_PRIVBB15_Msk /*!< Page 15 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB2R1_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB2R1_PRIVBB16 FLASH_PRIVBB2R1_PRIVBB16_Msk /*!< Page 16 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB2R1_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB2R1_PRIVBB17 FLASH_PRIVBB2R1_PRIVBB17_Msk /*!< Page 17 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB2R1_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB2R1_PRIVBB18 FLASH_PRIVBB2R1_PRIVBB18_Msk /*!< Page 18 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB2R1_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB2R1_PRIVBB19 FLASH_PRIVBB2R1_PRIVBB19_Msk /*!< Page 19 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB2R1_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB2R1_PRIVBB20 FLASH_PRIVBB2R1_PRIVBB20_Msk /*!< Page 20 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB2R1_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB2R1_PRIVBB21 FLASH_PRIVBB2R1_PRIVBB21_Msk /*!< Page 21 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB2R1_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB2R1_PRIVBB22 FLASH_PRIVBB2R1_PRIVBB22_Msk /*!< Page 22 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB2R1_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB2R1_PRIVBB23 FLASH_PRIVBB2R1_PRIVBB23_Msk /*!< Page 23 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB2R1_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB2R1_PRIVBB24 FLASH_PRIVBB2R1_PRIVBB24_Msk /*!< Page 24 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB2R1_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB2R1_PRIVBB25 FLASH_PRIVBB2R1_PRIVBB25_Msk /*!< Page 25 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB2R1_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB2R1_PRIVBB26 FLASH_PRIVBB2R1_PRIVBB26_Msk /*!< Page 26 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB2R1_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB2R1_PRIVBB27 FLASH_PRIVBB2R1_PRIVBB27_Msk /*!< Page 27 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB2R1_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB2R1_PRIVBB28 FLASH_PRIVBB2R1_PRIVBB28_Msk /*!< Page 28 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB2R1_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB2R1_PRIVBB29 FLASH_PRIVBB2R1_PRIVBB29_Msk /*!< Page 29 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB2R1_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB2R1_PRIVBB30 FLASH_PRIVBB2R1_PRIVBB30_Msk /*!< Page 30 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R1_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB2R1_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB2R1_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB2R1_PRIVBB31 FLASH_PRIVBB2R1_PRIVBB31_Msk /*!< Page 31 in Flash bank 2 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB2R2 register ******************/ +#define FLASH_PRIVBB2R2_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB2R2_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB2R2_PRIVBB0 FLASH_PRIVBB2R2_PRIVBB0_Msk /*!< Page 32 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB2R2_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB2R2_PRIVBB1 FLASH_PRIVBB2R2_PRIVBB1_Msk /*!< Page 33 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB2R2_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB2R2_PRIVBB2 FLASH_PRIVBB2R2_PRIVBB2_Msk /*!< Page 34 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB2R2_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB2R2_PRIVBB3 FLASH_PRIVBB2R2_PRIVBB3_Msk /*!< Page 35 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB2R2_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB2R2_PRIVBB4 FLASH_PRIVBB2R2_PRIVBB4_Msk /*!< Page 36 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB2R2_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB2R2_PRIVBB5 FLASH_PRIVBB2R2_PRIVBB5_Msk /*!< Page 37 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB2R2_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB2R2_PRIVBB6 FLASH_PRIVBB2R2_PRIVBB6_Msk /*!< Page 38 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB2R2_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB2R2_PRIVBB7 FLASH_PRIVBB2R2_PRIVBB7_Msk /*!< Page 39 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB2R2_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB2R2_PRIVBB8 FLASH_PRIVBB2R2_PRIVBB8_Msk /*!< Page 40 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB2R2_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB2R2_PRIVBB9 FLASH_PRIVBB2R2_PRIVBB9_Msk /*!< Page 41 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB2R2_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB2R2_PRIVBB10 FLASH_PRIVBB2R2_PRIVBB10_Msk /*!< Page 42 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB2R2_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB2R2_PRIVBB11 FLASH_PRIVBB2R2_PRIVBB11_Msk /*!< Page 43 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB2R2_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB2R2_PRIVBB12 FLASH_PRIVBB2R2_PRIVBB12_Msk /*!< Page 44 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB2R2_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB2R2_PRIVBB13 FLASH_PRIVBB2R2_PRIVBB13_Msk /*!< Page 45 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB2R2_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB2R2_PRIVBB14 FLASH_PRIVBB2R2_PRIVBB14_Msk /*!< Page 46 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB2R2_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB2R2_PRIVBB15 FLASH_PRIVBB2R2_PRIVBB15_Msk /*!< Page 47 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB2R2_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB2R2_PRIVBB16 FLASH_PRIVBB2R2_PRIVBB16_Msk /*!< Page 48 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB2R2_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB2R2_PRIVBB17 FLASH_PRIVBB2R2_PRIVBB17_Msk /*!< Page 49 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB2R2_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB2R2_PRIVBB18 FLASH_PRIVBB2R2_PRIVBB18_Msk /*!< Page 50 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB2R2_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB2R2_PRIVBB19 FLASH_PRIVBB2R2_PRIVBB19_Msk /*!< Page 51 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB2R2_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB2R2_PRIVBB20 FLASH_PRIVBB2R2_PRIVBB20_Msk /*!< Page 52 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB2R2_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB2R2_PRIVBB21 FLASH_PRIVBB2R2_PRIVBB21_Msk /*!< Page 53 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB2R2_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB2R2_PRIVBB22 FLASH_PRIVBB2R2_PRIVBB22_Msk /*!< Page 54 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB2R2_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB2R2_PRIVBB23 FLASH_PRIVBB2R2_PRIVBB23_Msk /*!< Page 55 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB2R2_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB2R2_PRIVBB24 FLASH_PRIVBB2R2_PRIVBB24_Msk /*!< Page 56 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB2R2_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB2R2_PRIVBB25 FLASH_PRIVBB2R2_PRIVBB25_Msk /*!< Page 57 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB2R2_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB2R2_PRIVBB26 FLASH_PRIVBB2R2_PRIVBB26_Msk /*!< Page 58 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB2R2_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB2R2_PRIVBB27 FLASH_PRIVBB2R2_PRIVBB27_Msk /*!< Page 59 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB2R2_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB2R2_PRIVBB28 FLASH_PRIVBB2R2_PRIVBB28_Msk /*!< Page 60 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB2R2_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB2R2_PRIVBB29 FLASH_PRIVBB2R2_PRIVBB29_Msk /*!< Page 61 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB2R2_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB2R2_PRIVBB30 FLASH_PRIVBB2R2_PRIVBB30_Msk /*!< Page 62 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R2_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB2R2_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB2R2_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB2R2_PRIVBB31 FLASH_PRIVBB2R2_PRIVBB31_Msk /*!< Page 63 in Flash bank 2 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB2R3 register ******************/ +#define FLASH_PRIVBB2R3_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB2R3_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB2R3_PRIVBB0 FLASH_PRIVBB2R3_PRIVBB0_Msk /*!< Page 64 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB2R3_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB2R3_PRIVBB1 FLASH_PRIVBB2R3_PRIVBB1_Msk /*!< Page 65 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB2R3_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB2R3_PRIVBB2 FLASH_PRIVBB2R3_PRIVBB2_Msk /*!< Page 66 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB2R3_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB2R3_PRIVBB3 FLASH_PRIVBB2R3_PRIVBB3_Msk /*!< Page 67 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB2R3_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB2R3_PRIVBB4 FLASH_PRIVBB2R3_PRIVBB4_Msk /*!< Page 68 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB2R3_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB2R3_PRIVBB5 FLASH_PRIVBB2R3_PRIVBB5_Msk /*!< Page 69 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB2R3_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB2R3_PRIVBB6 FLASH_PRIVBB2R3_PRIVBB6_Msk /*!< Page 70 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB2R3_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB2R3_PRIVBB7 FLASH_PRIVBB2R3_PRIVBB7_Msk /*!< Page 71 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB2R3_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB2R3_PRIVBB8 FLASH_PRIVBB2R3_PRIVBB8_Msk /*!< Page 72 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB2R3_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB2R3_PRIVBB9 FLASH_PRIVBB2R3_PRIVBB9_Msk /*!< Page 73 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB2R3_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB2R3_PRIVBB10 FLASH_PRIVBB2R3_PRIVBB10_Msk /*!< Page 74 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB2R3_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB2R3_PRIVBB11 FLASH_PRIVBB2R3_PRIVBB11_Msk /*!< Page 75 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB2R3_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB2R3_PRIVBB12 FLASH_PRIVBB2R3_PRIVBB12_Msk /*!< Page 76 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB2R3_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB2R3_PRIVBB13 FLASH_PRIVBB2R3_PRIVBB13_Msk /*!< Page 77 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB2R3_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB2R3_PRIVBB14 FLASH_PRIVBB2R3_PRIVBB14_Msk /*!< Page 78 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB2R3_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB2R3_PRIVBB15 FLASH_PRIVBB2R3_PRIVBB15_Msk /*!< Page 79 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB2R3_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB2R3_PRIVBB16 FLASH_PRIVBB2R3_PRIVBB16_Msk /*!< Page 80 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB2R3_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB2R3_PRIVBB17 FLASH_PRIVBB2R3_PRIVBB17_Msk /*!< Page 81 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB2R3_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB2R3_PRIVBB18 FLASH_PRIVBB2R3_PRIVBB18_Msk /*!< Page 82 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB2R3_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB2R3_PRIVBB19 FLASH_PRIVBB2R3_PRIVBB19_Msk /*!< Page 83 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB2R3_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB2R3_PRIVBB20 FLASH_PRIVBB2R3_PRIVBB20_Msk /*!< Page 84 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB2R3_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB2R3_PRIVBB21 FLASH_PRIVBB2R3_PRIVBB21_Msk /*!< Page 85 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB2R3_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB2R3_PRIVBB22 FLASH_PRIVBB2R3_PRIVBB22_Msk /*!< Page 86 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB2R3_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB2R3_PRIVBB23 FLASH_PRIVBB2R3_PRIVBB23_Msk /*!< Page 87 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB2R3_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB2R3_PRIVBB24 FLASH_PRIVBB2R3_PRIVBB24_Msk /*!< Page 88 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB2R3_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB2R3_PRIVBB25 FLASH_PRIVBB2R3_PRIVBB25_Msk /*!< Page 89 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB2R3_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB2R3_PRIVBB26 FLASH_PRIVBB2R3_PRIVBB26_Msk /*!< Page 90 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB2R3_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB2R3_PRIVBB27 FLASH_PRIVBB2R3_PRIVBB27_Msk /*!< Page 91 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB2R3_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB2R3_PRIVBB28 FLASH_PRIVBB2R3_PRIVBB28_Msk /*!< Page 92 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB2R3_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB2R3_PRIVBB29 FLASH_PRIVBB2R3_PRIVBB29_Msk /*!< Page 93 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB2R3_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB2R3_PRIVBB30 FLASH_PRIVBB2R3_PRIVBB30_Msk /*!< Page 94 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R3_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB2R3_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB2R3_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB2R3_PRIVBB31 FLASH_PRIVBB2R3_PRIVBB31_Msk /*!< Page 95 in Flash bank 2 only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBB2R4 register ******************/ +#define FLASH_PRIVBB2R4_PRIVBB0_Pos (0UL) +#define FLASH_PRIVBB2R4_PRIVBB0_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBB2R4_PRIVBB0 FLASH_PRIVBB2R4_PRIVBB0_Msk /*!< Page 96 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB1_Pos (1UL) +#define FLASH_PRIVBB2R4_PRIVBB1_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBB2R4_PRIVBB1 FLASH_PRIVBB2R4_PRIVBB1_Msk /*!< Page 97 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB2_Pos (2UL) +#define FLASH_PRIVBB2R4_PRIVBB2_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBB2R4_PRIVBB2 FLASH_PRIVBB2R4_PRIVBB2_Msk /*!< Page 98 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB3_Pos (3UL) +#define FLASH_PRIVBB2R4_PRIVBB3_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBB2R4_PRIVBB3 FLASH_PRIVBB2R4_PRIVBB3_Msk /*!< Page 99 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB4_Pos (4UL) +#define FLASH_PRIVBB2R4_PRIVBB4_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBB2R4_PRIVBB4 FLASH_PRIVBB2R4_PRIVBB4_Msk /*!< Page 100 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB5_Pos (5UL) +#define FLASH_PRIVBB2R4_PRIVBB5_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBB2R4_PRIVBB5 FLASH_PRIVBB2R4_PRIVBB5_Msk /*!< Page 101 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB6_Pos (6UL) +#define FLASH_PRIVBB2R4_PRIVBB6_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBB2R4_PRIVBB6 FLASH_PRIVBB2R4_PRIVBB6_Msk /*!< Page 102 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB7_Pos (7UL) +#define FLASH_PRIVBB2R4_PRIVBB7_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBB2R4_PRIVBB7 FLASH_PRIVBB2R4_PRIVBB7_Msk /*!< Page 103 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB8_Pos (8UL) +#define FLASH_PRIVBB2R4_PRIVBB8_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBB2R4_PRIVBB8 FLASH_PRIVBB2R4_PRIVBB8_Msk /*!< Page 104 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB9_Pos (9UL) +#define FLASH_PRIVBB2R4_PRIVBB9_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBB2R4_PRIVBB9 FLASH_PRIVBB2R4_PRIVBB9_Msk /*!< Page 105 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB10_Pos (10UL) +#define FLASH_PRIVBB2R4_PRIVBB10_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBB2R4_PRIVBB10 FLASH_PRIVBB2R4_PRIVBB10_Msk /*!< Page 106 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB11_Pos (11UL) +#define FLASH_PRIVBB2R4_PRIVBB11_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBB2R4_PRIVBB11 FLASH_PRIVBB2R4_PRIVBB11_Msk /*!< Page 107 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB12_Pos (12UL) +#define FLASH_PRIVBB2R4_PRIVBB12_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBB2R4_PRIVBB12 FLASH_PRIVBB2R4_PRIVBB12_Msk /*!< Page 108 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB13_Pos (13UL) +#define FLASH_PRIVBB2R4_PRIVBB13_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBB2R4_PRIVBB13 FLASH_PRIVBB2R4_PRIVBB13_Msk /*!< Page 109 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB14_Pos (14UL) +#define FLASH_PRIVBB2R4_PRIVBB14_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBB2R4_PRIVBB14 FLASH_PRIVBB2R4_PRIVBB14_Msk /*!< Page 110 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB15_Pos (15UL) +#define FLASH_PRIVBB2R4_PRIVBB15_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBB2R4_PRIVBB15 FLASH_PRIVBB2R4_PRIVBB15_Msk /*!< Page 111 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB16_Pos (16UL) +#define FLASH_PRIVBB2R4_PRIVBB16_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBB2R4_PRIVBB16 FLASH_PRIVBB2R4_PRIVBB16_Msk /*!< Page 112 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB17_Pos (17UL) +#define FLASH_PRIVBB2R4_PRIVBB17_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBB2R4_PRIVBB17 FLASH_PRIVBB2R4_PRIVBB17_Msk /*!< Page 113 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB18_Pos (18UL) +#define FLASH_PRIVBB2R4_PRIVBB18_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBB2R4_PRIVBB18 FLASH_PRIVBB2R4_PRIVBB18_Msk /*!< Page 114 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB19_Pos (19UL) +#define FLASH_PRIVBB2R4_PRIVBB19_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBB2R4_PRIVBB19 FLASH_PRIVBB2R4_PRIVBB19_Msk /*!< Page 115 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB20_Pos (20UL) +#define FLASH_PRIVBB2R4_PRIVBB20_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBB2R4_PRIVBB20 FLASH_PRIVBB2R4_PRIVBB20_Msk /*!< Page 116 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB21_Pos (21UL) +#define FLASH_PRIVBB2R4_PRIVBB21_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBB2R4_PRIVBB21 FLASH_PRIVBB2R4_PRIVBB21_Msk /*!< Page 117 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB22_Pos (22UL) +#define FLASH_PRIVBB2R4_PRIVBB22_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBB2R4_PRIVBB22 FLASH_PRIVBB2R4_PRIVBB22_Msk /*!< Page 118 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB23_Pos (23UL) +#define FLASH_PRIVBB2R4_PRIVBB23_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBB2R4_PRIVBB23 FLASH_PRIVBB2R4_PRIVBB23_Msk /*!< Page 119 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB24_Pos (24UL) +#define FLASH_PRIVBB2R4_PRIVBB24_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBB2R4_PRIVBB24 FLASH_PRIVBB2R4_PRIVBB24_Msk /*!< Page 120 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB25_Pos (25UL) +#define FLASH_PRIVBB2R4_PRIVBB25_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBB2R4_PRIVBB25 FLASH_PRIVBB2R4_PRIVBB25_Msk /*!< Page 121 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB26_Pos (26UL) +#define FLASH_PRIVBB2R4_PRIVBB26_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBB2R4_PRIVBB26 FLASH_PRIVBB2R4_PRIVBB26_Msk /*!< Page 122 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB27_Pos (27UL) +#define FLASH_PRIVBB2R4_PRIVBB27_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBB2R4_PRIVBB27 FLASH_PRIVBB2R4_PRIVBB27_Msk /*!< Page 123 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB28_Pos (28UL) +#define FLASH_PRIVBB2R4_PRIVBB28_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBB2R4_PRIVBB28 FLASH_PRIVBB2R4_PRIVBB28_Msk /*!< Page 124 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB29_Pos (29UL) +#define FLASH_PRIVBB2R4_PRIVBB29_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBB2R4_PRIVBB29 FLASH_PRIVBB2R4_PRIVBB29_Msk /*!< Page 125 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB30_Pos (30UL) +#define FLASH_PRIVBB2R4_PRIVBB30_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBB2R4_PRIVBB30 FLASH_PRIVBB2R4_PRIVBB30_Msk /*!< Page 126 in Flash bank 2 only accessible by privileged access */ +#define FLASH_PRIVBB2R4_PRIVBB31_Pos (31UL) +#define FLASH_PRIVBB2R4_PRIVBB31_Msk (0x1UL << FLASH_PRIVBB2R4_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBB2R4_PRIVBB31 FLASH_PRIVBB2R4_PRIVBB31_Msk /*!< Page 127 in Flash bank 2 only accessible by privileged access */ + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0UL) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2UL) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4UL) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6UL) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8UL) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10UL) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12UL) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14UL) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16UL) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18UL) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20UL) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22UL) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24UL) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26UL) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28UL) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30UL) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0UL) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1UL) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2UL) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3UL) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4UL) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5UL) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6UL) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7UL) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8UL) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9UL) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10UL) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11UL) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12UL) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13UL) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14UL) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15UL) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0UL) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2UL) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4UL) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6UL) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8UL) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10UL) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12UL) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14UL) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16UL) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18UL) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20UL) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22UL) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24UL) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26UL) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28UL) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30UL) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0UL) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2UL) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4UL) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6UL) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8UL) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10UL) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12UL) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14UL) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16UL) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18UL) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20UL) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22UL) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24UL) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26UL) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28UL) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30UL) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0UL) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1UL) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2UL) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3UL) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4UL) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5UL) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6UL) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7UL) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8UL) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9UL) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10UL) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11UL) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12UL) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13UL) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14UL) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15UL) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0UL) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1UL) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2UL) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3UL) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4UL) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5UL) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6UL) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7UL) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8UL) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9UL) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10UL) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11UL) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12UL) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13UL) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14UL) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15UL) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0UL) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1UL) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2UL) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3UL) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4UL) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5UL) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6UL) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7UL) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8UL) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9UL) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10UL) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11UL) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12UL) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13UL) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14UL) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15UL) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16UL) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17UL) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18UL) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19UL) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20UL) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21UL) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22UL) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23UL) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24UL) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25UL) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26UL) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27UL) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28UL) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29UL) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30UL) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31UL) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0UL) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1UL) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2UL) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3UL) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4UL) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5UL) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6UL) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7UL) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8UL) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9UL) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10UL) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11UL) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12UL) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13UL) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14UL) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15UL) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16UL) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0UL) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4UL) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8UL) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12UL) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16UL) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20UL) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24UL) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28UL) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0UL) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4UL) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8UL) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12UL) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16UL) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20UL) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24UL) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28UL) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0UL) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1UL) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2UL) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3UL) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4UL) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5UL) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6UL) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7UL) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8UL) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9UL) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10UL) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11UL) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12UL) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13UL) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14UL) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15UL) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0UL) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1UL) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2UL) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3UL) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4UL) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5UL) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6UL) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7UL) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8UL) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9UL) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10UL) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11UL) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12UL) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13UL) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14UL) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15UL) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0UL) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1UL) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2UL) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3UL) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4UL) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5UL) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6UL) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7UL) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8UL) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9UL) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10UL) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11UL) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12UL) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13UL) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14UL) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15UL) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0UL) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ +#define GTZC_TZSC_CR_LCK GTZC_TZSC_CR_LCK_Msk /*!< GTZC Secure and privilege configurations lock */ + +/******* Bits definition for GTZC_TZSC_SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for GTZC_TZIC_IERx/_SRx/_IFCRx registers ********/ + +/******************* Bits definition for GTZC_TZSC_SECCFGR1 register ***************/ +#define GTZC_CFGR1_TIM2_Pos GTZC_TZSC_SECCFGR1_TIM2SEC_Pos +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos GTZC_TZSC_SECCFGR1_TIM3SEC_Pos +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos GTZC_TZSC_SECCFGR1_TIM4SEC_Pos +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_WWDG_Pos GTZC_TZSC_SECCFGR1_WWDGSEC_Pos +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos GTZC_TZSC_SECCFGR1_IWDGSEC_Pos +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos GTZC_TZSC_SECCFGR1_SPI2SEC_Pos +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_USART2_Pos GTZC_TZSC_SECCFGR1_USART2SEC_Pos +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos GTZC_TZSC_SECCFGR1_USART3SEC_Pos +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_I2C1_Pos GTZC_TZSC_SECCFGR1_I2C1SEC_Pos +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos GTZC_TZSC_SECCFGR1_I2C2SEC_Pos +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I2C4_Pos GTZC_TZSC_SECCFGR1_I2C4SEC_Pos +#define GTZC_CFGR1_I2C4_Msk (0x01UL << GTZC_CFGR1_I2C4_Pos) +#define GTZC_CFGR1_LPTIM2_Pos GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_CFGR2_TIM1_Pos GTZC_TZSC_SECCFGR2_TIM1SEC_Pos +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_USART1_Pos GTZC_TZSC_SECCFGR2_USART1SEC_Pos +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM16_Pos GTZC_TZSC_SECCFGR2_TIM16SEC_Pos +#define GTZC_CFGR2_TIM16_Msk (0x01UL << GTZC_CFGR2_TIM16_Pos) +#define GTZC_CFGR2_TIM17_Pos GTZC_TZSC_SECCFGR2_TIM17SEC_Pos +#define GTZC_CFGR2_TIM17_Msk (0x01UL << GTZC_CFGR2_TIM17_Pos) +#define GTZC_CFGR2_SAI1_Pos GTZC_TZSC_SECCFGR2_SAI1SEC_Pos +#define GTZC_CFGR2_SAI1_Msk (0x01UL << GTZC_CFGR2_SAI1_Pos) +#define GTZC_CFGR2_SPI3_Pos GTZC_TZSC_SECCFGR2_SPI3SEC_Pos +#define GTZC_CFGR2_SPI3_Msk (0x01UL << GTZC_CFGR2_SPI3_Pos) +#define GTZC_CFGR2_LPUART1_Pos GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos GTZC_TZSC_SECCFGR2_I2C3SEC_Pos +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) +#define GTZC_CFGR2_COMP_Pos GTZC_TZSC_SECCFGR2_COMPSEC_Pos +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_ADC4_Pos GTZC_TZSC_SECCFGR2_ADC4SEC_Pos +#define GTZC_CFGR2_ADC4_Msk (0x01UL << GTZC_CFGR2_ADC4_Pos) +#define GTZC_CFGR2_VREFBUF_Pos GTZC_TZSC_SECCFGR2_VREFBUFSEC_Pos +#define GTZC_CFGR2_VREFBUF_Msk (0x01UL << GTZC_CFGR2_VREFBUFSEC_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_CFGR3_CRC_Pos GTZC_TZSC_SECCFGR3_CRCSEC_Pos +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_TSC_Pos GTZC_TZSC_SECCFGR3_TSCSEC_Pos +#define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_OTG_Pos GTZC_TZSC_SECCFGR3_OTGSEC_Pos +#define GTZC_CFGR3_OTG_Msk (0x01UL << GTZC_CFGR3_OTG_Pos) +#define GTZC_CFGR3_AES_Pos GTZC_TZSC_SECCFGR3_AESSEC_Pos +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos GTZC_TZSC_SECCFGR3_HASHSEC_Pos +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos GTZC_TZSC_SECCFGR3_RNGSEC_Pos +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos GTZC_TZSC_SECCFGR3_SAESSEC_Pos +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_HSEM_Pos GTZC_TZIC_IER3_HSEMIE_Pos +#define GTZC_CFGR3_HSEM_Msk (0x01UL << GTZC_CFGR3_HSEM_Pos) +#define GTZC_CFGR3_PKA_Pos GTZC_TZSC_SECCFGR3_PKASEC_Pos +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_RAMCFG_Pos GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) +#define GTZC_CFGR3_RADIO_Pos GTZC_TZSC_SECCFGR3_RADIOSEC_Pos +#define GTZC_CFGR3_RADIO_Msk (0x01UL << GTZC_CFGR3_RADIO_Pos) +#define GTZC_CFGR3_PTACONV_Pos GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos +#define GTZC_CFGR3_PTACONV_Msk (0x01UL << GTZC_CFGR3_PTACONV_Pos) + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_CFGR4_GPDMA1_Pos GTZC_TZIC_IER4_GPDMA1IE_Pos +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_FLASH_Pos GTZC_TZIC_IER4_FLASHIE_Pos +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos GTZC_TZIC_IER4_FLASH_REGIE_Pos +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_CFGR4_TZSC_Pos GTZC_TZIC_IER4_TZSCIE_Pos +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos GTZC_TZIC_IER4_TZICIE_Pos +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_SYSCFG_Pos GTZC_TZIC_IER4_SYSCFGIE_Pos +#define GTZC_CFGR4_SYSCFG_Msk (0x01UL << GTZC_CFGR4_SYSCFG_Pos) +#define GTZC_CFGR4_RTC_Pos GTZC_TZIC_IER4_RTCIE_Pos +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos GTZC_TZIC_IER4_TAMPIE_Pos +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos GTZC_TZIC_IER4_PWRIE_Pos +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos GTZC_TZIC_IER4_RCCIE_Pos +#define GTZC_CFGR4_RCC_sk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos GTZC_TZIC_IER4_EXTIIE_Pos +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_SRAM1_Pos GTZC_TZIC_IER4_SRAM1IE_Pos +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos GTZC_TZIC_IER4_SRAM2IE_Pos +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos GTZC_TZIC_IER4_MPCBB2IE_Pos +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM6_Pos GTZC_TZIC_IER4_SRAM6IE_Pos +#define GTZC_CFGR4_SRAM6_Msk (0x01UL << GTZC_CFGR4_SRAM6_Pos) +#define GTZC_CFGR4_MPCBB6_REG_Pos GTZC_TZIC_IER4_MPCBB6IE_Pos +#define GTZC_CFGR4_MPCBB6_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos) + +/*************** Bits definition for register x=1 (GTZC_TZSC_SECCFGR1) *************/ +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Pos (0UL) +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM2SEC GTZC_TZSC_SECCFGR1_TIM2SEC_Msk /*!< secure access mode for TIM2 */ +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Pos (1UL) +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM3SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM3SEC GTZC_TZSC_SECCFGR1_TIM3SEC_Msk /*!< secure access mode for TIM3 */ +#define GTZC_TZSC_SECCFGR1_TIM4SEC_Pos (2UL) +#define GTZC_TZSC_SECCFGR1_TIM4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM4SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM4SEC GTZC_TZSC_SECCFGR1_TIM4SEC_Msk /*!< secure access mode for TIM4 */ +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Pos (6UL) +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_WWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_WWDGSEC GTZC_TZSC_SECCFGR1_WWDGSEC_Msk /*!< secure access mode for WWDG */ +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Pos (7UL) +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_IWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_IWDGSEC GTZC_TZSC_SECCFGR1_IWDGSEC_Msk /*!< secure access mode for IWDG */ +#define GTZC_TZSC_SECCFGR1_SPI2SEC_Pos (8UL) +#define GTZC_TZSC_SECCFGR1_SPI2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_SPI2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_SPI2SEC GTZC_TZSC_SECCFGR1_SPI2SEC_Msk /*!< secure access mode for IWDG */ +#define GTZC_TZSC_SECCFGR1_USART2SEC_Pos (9UL) +#define GTZC_TZSC_SECCFGR1_USART2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_USART2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_USART2SEC GTZC_TZSC_SECCFGR1_USART2SEC_Msk /*!< secure access mode for USART2 */ +#define GTZC_TZSC_SECCFGR1_USART3SEC_Pos (10UL) +#define GTZC_TZSC_SECCFGR1_USART3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_USART3SEC_Pos) +#define GTZC_TZSC_SECCFGR1_USART3SEC GTZC_TZSC_SECCFGR1_USART3SEC_Msk /*!< secure access mode for USART3 */ +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Pos (13UL) +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C1SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C1SEC GTZC_TZSC_SECCFGR1_I2C1SEC_Msk /*!< secure access mode for I2C1 */ +#define GTZC_TZSC_SECCFGR1_I2C2SEC_Pos (14UL) +#define GTZC_TZSC_SECCFGR1_I2C2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C2SEC GTZC_TZSC_SECCFGR1_I2C2SEC_Msk /*!< secure access mode for I2C2 */ +#define GTZC_TZSC_SECCFGR1_I2C4SEC_Pos (16UL) +#define GTZC_TZSC_SECCFGR1_I2C4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C4SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C4SEC GTZC_TZSC_SECCFGR1_I2C4SEC_Msk /*!< secure access mode for I2C4 */ +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos (17UL) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk /*!< secure access mode for LPTIM2 */ + +/*************** Bits definition for register x=2 (GTZC_TZSC_SECCFGR2) *************/ +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Pos (0UL) +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM1SEC GTZC_TZSC_SECCFGR2_TIM1SEC_Msk /*!< secure access mode for TIM1 */ +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Pos (1UL) +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI1SEC GTZC_TZSC_SECCFGR2_SPI1SEC_Msk /*!< secure access mode for SPI1 */ +#define GTZC_TZSC_SECCFGR2_USART1SEC_Pos (3UL) +#define GTZC_TZSC_SECCFGR2_USART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_USART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_USART1SEC GTZC_TZSC_SECCFGR2_USART1SEC_Msk /*!< secure access mode for USART1 */ +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Pos (5UL) +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM16SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM16SEC GTZC_TZSC_SECCFGR2_TIM16SEC_Msk /*!< secure access mode for TIM16 */ +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Pos (6UL) +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM17SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM17SEC GTZC_TZSC_SECCFGR2_TIM17SEC_Msk /*!< secure access mode for TIM17 */ +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Pos (7UL) +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SAI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SAI1SEC GTZC_TZSC_SECCFGR2_SAI1SEC_Msk /*!< secure access mode for SAI1 */ +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Pos (16UL) +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI3SEC GTZC_TZSC_SECCFGR2_SPI3SEC_Msk /*!< secure access mode for SPI3 */ +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos (17UL) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk /*!< secure access mode for LPUART1 */ +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Pos (18UL) +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_I2C3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_I2C3SEC GTZC_TZSC_SECCFGR2_I2C3SEC_Msk /*!< secure access mode for I2C3 */ +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos (19UL) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk /*!< secure access mode for LPTIM1 */ +#define GTZC_TZSC_SECCFGR2_COMPSEC_Pos (23UL) +#define GTZC_TZSC_SECCFGR2_COMPSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_COMPSEC_Pos) +#define GTZC_TZSC_SECCFGR2_COMPSEC GTZC_TZSC_SECCFGR2_COMPSEC_Msk /*!< secure access mode for COMP */ +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Pos (24UL) +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_ADC4SEC_Pos) +#define GTZC_TZSC_SECCFGR2_ADC4SEC GTZC_TZSC_SECCFGR2_ADC4SEC_Msk /*!< secure access mode for ADC4 */ +#define GTZC_TZSC_SECCFGR2_VREFBUFSEC_Pos (25UL) +#define GTZC_TZSC_SECCFGR2_VREFBUFSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_VREFBUFSEC_Pos) +#define GTZC_TZSC_SECCFGR2_VREFBUFSEC GTZC_TZSC_SECCFGR2_VREFBUFSEC_Msk /*!< secure access mode for VREFBUF */ + +/*************** Bits definition for register x=3 (GTZC_TZSC_SECCFGR3) *************/ +#define GTZC_TZSC_SECCFGR3_CRCSEC_Pos (3UL) +#define GTZC_TZSC_SECCFGR3_CRCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_CRCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_CRCSEC GTZC_TZSC_SECCFGR3_CRCSEC_Msk /*!< secure access mode for CRC */ +#define GTZC_TZSC_SECCFGR3_TSCSEC_Pos (4UL) +#define GTZC_TZSC_SECCFGR3_TSCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_TSCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_TSCSEC GTZC_TZSC_SECCFGR3_TSCSEC_Msk /*!< secure access mode for TSC */ +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos (6UL) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk /*!< secure access mode for ICACHE_REG */ +#define GTZC_TZSC_SECCFGR3_OTGSEC_Pos (10UL) +#define GTZC_TZSC_SECCFGR3_OTGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_OTGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_OTGSEC GTZC_TZSC_SECCFGR3_OTGSEC_Msk /*!< secure access mode for OTG */ +#define GTZC_TZSC_SECCFGR3_AESSEC_Pos (11UL) +#define GTZC_TZSC_SECCFGR3_AESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_AESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_AESSEC GTZC_TZSC_SECCFGR3_AESSEC_Msk /*!< secure access mode for AES */ +#define GTZC_TZSC_SECCFGR3_HASHSEC_Pos (12UL) +#define GTZC_TZSC_SECCFGR3_HASHSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_HASHSEC_Pos) +#define GTZC_TZSC_SECCFGR3_HASHSEC GTZC_TZSC_SECCFGR3_HASHSEC_Msk /*!< secure access mode for HASH */ +#define GTZC_TZSC_SECCFGR3_RNGSEC_Pos (13UL) +#define GTZC_TZSC_SECCFGR3_RNGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RNGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RNGSEC GTZC_TZSC_SECCFGR3_RNGSEC_Msk /*!< secure access mode for RNG */ +#define GTZC_TZSC_SECCFGR3_SAESSEC_Pos (14UL) +#define GTZC_TZSC_SECCFGR3_SAESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_SAESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_SAESSEC GTZC_TZSC_SECCFGR3_SAESSEC_Msk /*!< secure access mode for SAES */ +#define GTZC_TZSC_SECCFGR3_PKASEC_Pos (16UL) +#define GTZC_TZSC_SECCFGR3_PKASEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PKASEC_Pos) +#define GTZC_TZSC_SECCFGR3_PKASEC GTZC_TZSC_SECCFGR3_PKASEC_Msk /*!< secure access mode for PKA */ +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos (22UL) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk /*!< secure access mode for RAMCFG */ +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Pos (23UL) +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RADIOSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RADIOSEC GTZC_TZSC_SECCFGR3_RADIOSEC_Msk /*!< secure access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos (24UL) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk /*!< secure access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos (0UL) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk /*!< privileged access mode for TIM2 */ +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos (1UL) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk /*!< privileged access mode for TIM3 */ +#define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Pos (2UL) +#define GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM4PRIV GTZC_TZSC_PRIVCFGR1_TIM4PRIV_Msk /*!< privileged access mode for TIM4 */ +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos (6UL) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk /*!< privileged access mode for WWDG */ +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos (7UL) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk /*!< privileged access mode for IWDG */ +#define GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Pos (8UL) +#define GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_SPI2PRIV GTZC_TZSC_PRIVCFGR1_SPI2PRIV_Msk /*!< privileged access mode for IWDG */ +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos (9UL) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk /*!< privileged access mode for USART2 */ +#define GTZC_TZSC_PRIVCFGR1_USART3PRIV_Pos (10UL) +#define GTZC_TZSC_PRIVCFGR1_USART3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_USART3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_USART3PRIV GTZC_TZSC_PRIVCFGR1_USART3PRIV_Msk /*!< privileged access mode for USART3 */ +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos (13UL) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk /*!< privileged access mode for I2C1 */ +#define GTZC_TZSC_PRIVCFGR1_I2C2PRIV_Pos (14UL) +#define GTZC_TZSC_PRIVCFGR1_I2C2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C2PRIV GTZC_TZSC_PRIVCFGR1_I2C2PRIV_Msk /*!< privileged access mode for I2C2 */ +#define GTZC_TZSC_PRIVCFGR1_I2C4PRIV_Pos (16UL) +#define GTZC_TZSC_PRIVCFGR1_I2C4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C4PRIV GTZC_TZSC_PRIVCFGR1_I2C4PRIV_Msk /*!< privileged access mode for I2C4 */ +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos (17UL) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk /*!< privileged access mode for LPTIM2 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos (0UL) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk /*!< privileged access mode for TIM1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos (1UL) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk /*!< privileged access mode for SPI1 */ +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos (3UL) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk /*!< privileged access mode for USART1 */ +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos (5UL) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk /*!< privileged access mode for TIM16 */ +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos (6UL) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk /*!< privileged access mode for TIM17 */ +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos (7UL) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk /*!< privileged access mode for SAI1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos (16UL) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk /*!< privileged access mode for SPI3 */ +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos (17UL) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk /*!< privileged access mode for LPUART1 */ +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos (18UL) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk /*!< privileged access mode for I2C3 */ +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos (19UL) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk /*!< privileged access mode for LPTIM1 */ +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos (23UL) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk /*!< privileged access mode for COMP */ +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos (24UL) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk /*!< privileged access mode for ADC4 */ +#define GTZC_TZSC_PRIVCFGR2_VREFBUFPRIV_Pos (25UL) +#define GTZC_TZSC_PRIVCFGR2_VREFBUFPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_VREFBUFPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_VREFBUFPRIV GTZC_TZSC_PRIVCFGR2_VREFBUFPRIV_Msk /*!< privileged access mode for VREFBUF */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos (3UL) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk /*!< privileged access mode for CRC */ +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos (4UL) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk /*!< privileged access mode for TSC */ +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos (6UL) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk /*!< privileged access mode for ICACHE_REG */ +#define GTZC_TZSC_PRIVCFGR3_OTGPRIV_Pos (10UL) +#define GTZC_TZSC_PRIVCFGR3_OTGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_OTGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_OTGPRIV GTZC_TZSC_PRIVCFGR3_OTGPRIV_Msk /*!< privileged access mode for OTG */ +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos (11UL) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk /*!< privileged access mode for AES */ +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos (12UL) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk /*!< privileged access mode for HASH */ +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos (13UL) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk /*!< privileged access mode for RNG */ +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos (14UL) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk /*!< privileged access mode for SAES */ +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos (16UL) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk /*!< privileged access mode for PKA */ +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos (22UL) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk /*!< privileged access mode for RAMCFG */ +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos (23UL) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk /*!< privileged access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos (24UL) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk /*!< privileged access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC_IER1_TIM2IE_Pos (0UL) +#define GTZC_TZIC_IER1_TIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM2IE_Pos) +#define GTZC_TZIC_IER1_TIM2IE GTZC_TZIC_IER1_TIM2IE_Msk /*!< illegal access interrupt enable for TIM2 */ +#define GTZC_TZIC_IER1_TIM3IE_Pos (1UL) +#define GTZC_TZIC_IER1_TIM3IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM3IE_Pos) +#define GTZC_TZIC_IER1_TIM3IE GTZC_TZIC_IER1_TIM3IE_Msk /*!< illegal access interrupt enable for TIM3 */ +#define GTZC_TZIC_IER1_TIM4IE_Pos (2UL) +#define GTZC_TZIC_IER1_TIM4IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM4IE_Pos) +#define GTZC_TZIC_IER1_TIM4IE GTZC_TZIC_IER1_TIM4IE_Msk /*!< illegal access interrupt enable for TIM4 */ +#define GTZC_TZIC_IER1_WWDGIE_Pos (6UL) +#define GTZC_TZIC_IER1_WWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_WWDGIE_Pos) +#define GTZC_TZIC_IER1_WWDGIE GTZC_TZIC_IER1_WWDGIE_Msk /*!< illegal access interrupt enable for WWDG */ +#define GTZC_TZIC_IER1_IWDGIE_Pos (7UL) +#define GTZC_TZIC_IER1_IWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_IWDGIE_Pos) +#define GTZC_TZIC_IER1_IWDGIE GTZC_TZIC_IER1_IWDGIE_Msk /*!< illegal access interrupt enable for IWDG */ +#define GTZC_TZIC_IER1_SPI2IE_Pos (8UL) +#define GTZC_TZIC_IER1_SPI2IE_Msk (0x01UL << GTZC_TZIC_IER1_SPI2IE_Pos) +#define GTZC_TZIC_IER1_SPI2IE GTZC_TZIC_IER1_SPI2IE_Msk /*!< illegal access interrupt enable for IWDG */ +#define GTZC_TZIC_IER1_USART2IE_Pos (9UL) +#define GTZC_TZIC_IER1_USART2IE_Msk (0x01UL << GTZC_TZIC_IER1_USART2IE_Pos) +#define GTZC_TZIC_IER1_USART2IE GTZC_TZIC_IER1_USART2IE_Msk /*!< illegal access interrupt enable for USART2 */ +#define GTZC_TZIC_IER1_USART3IE_Pos (10UL) +#define GTZC_TZIC_IER1_USART3IE_Msk (0x01UL << GTZC_TZIC_IER1_USART3IE_Pos) +#define GTZC_TZIC_IER1_USART3IE GTZC_TZIC_IER1_USART3IE_Msk /*!< illegal access interrupt enable for USART3 */ +#define GTZC_TZIC_IER1_I2C1IE_Pos (13UL) +#define GTZC_TZIC_IER1_I2C1IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C1IE_Pos) +#define GTZC_TZIC_IER1_I2C1IE GTZC_TZIC_IER1_I2C1IE_Msk /*!< illegal access interrupt enable for I2C1 */ +#define GTZC_TZIC_IER1_I2C2IE_Pos (14UL) +#define GTZC_TZIC_IER1_I2C2IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C2IE_Pos) +#define GTZC_TZIC_IER1_I2C2IE GTZC_TZIC_IER1_I2C2IE_Msk /*!< illegal access interrupt enable for I2C2 */ +#define GTZC_TZIC_IER1_I2C4IE_Pos (16UL) +#define GTZC_TZIC_IER1_I2C4IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C4IE_Pos) +#define GTZC_TZIC_IER1_I2C4IE GTZC_TZIC_IER1_I2C4IE_Msk /*!< illegal access interrupt enable for I2C4 */ +#define GTZC_TZIC_IER1_LPTIM2IE_Pos (17UL) +#define GTZC_TZIC_IER1_LPTIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_LPTIM2IE_Pos) +#define GTZC_TZIC_IER1_LPTIM2IE GTZC_TZIC_IER1_LPTIM2IE_Msk /*!< illegal access interrupt enable for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC_IER2_TIM1IE_Pos (0UL) +#define GTZC_TZIC_IER2_TIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM1IE_Pos) +#define GTZC_TZIC_IER2_TIM1IE GTZC_TZIC_IER2_TIM1IE_Msk /*!< illegal access interrupt enable for TIM1 */ +#define GTZC_TZIC_IER2_SPI1IE_Pos (1UL) +#define GTZC_TZIC_IER2_SPI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI1IE_Pos) +#define GTZC_TZIC_IER2_SPI1IE GTZC_TZIC_IER2_SPI1IE_Msk /*!< illegal access interrupt enable for SPI1 */ +#define GTZC_TZIC_IER2_USART1IE_Pos (3UL) +#define GTZC_TZIC_IER2_USART1IE_Msk (0x01UL << GTZC_TZIC_IER2_USART1IE_Pos) +#define GTZC_TZIC_IER2_USART1IE GTZC_TZIC_IER2_USART1IE_Msk /*!< illegal access interrupt enable for USART1 */ +#define GTZC_TZIC_IER2_TIM16IE_Pos (5UL) +#define GTZC_TZIC_IER2_TIM16IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM16IE_Pos) +#define GTZC_TZIC_IER2_TIM16IE GTZC_TZIC_IER2_TIM16IE_Msk /*!< illegal access interrupt enable for TIM16 */ +#define GTZC_TZIC_IER2_TIM17IE_Pos (6UL) +#define GTZC_TZIC_IER2_TIM17IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM17IE_Pos) +#define GTZC_TZIC_IER2_TIM17IE GTZC_TZIC_IER2_TIM17IE_Msk /*!< illegal access interrupt enable for TIM17 */ +#define GTZC_TZIC_IER2_SAI1IE_Pos (7UL) +#define GTZC_TZIC_IER2_SAI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SAI1IE_Pos) +#define GTZC_TZIC_IER2_SAI1IE GTZC_TZIC_IER2_SAI1IE_Msk /*!< illegal access interrupt enable for SAI1 */ +#define GTZC_TZIC_IER2_SPI3IE_Pos (16UL) +#define GTZC_TZIC_IER2_SPI3IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI3IE_Pos) +#define GTZC_TZIC_IER2_SPI3IE GTZC_TZIC_IER2_SPI3IE_Msk /*!< illegal access interrupt enable for SPI3 */ +#define GTZC_TZIC_IER2_LPUART1IE_Pos (17UL) +#define GTZC_TZIC_IER2_LPUART1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPUART1IE_Pos) +#define GTZC_TZIC_IER2_LPUART1IE GTZC_TZIC_IER2_LPUART1IE_Msk /*!< illegal access interrupt enable for LPUART1 */ +#define GTZC_TZIC_IER2_I2C3IE_Pos (18UL) +#define GTZC_TZIC_IER2_I2C3IE_Msk (0x01UL << GTZC_TZIC_IER2_I2C3IE_Pos) +#define GTZC_TZIC_IER2_I2C3IE GTZC_TZIC_IER2_I2C3IE_Msk /*!< illegal access interrupt enable for I2C3 */ +#define GTZC_TZIC_IER2_LPTIM1IE_Pos (19UL) +#define GTZC_TZIC_IER2_LPTIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPTIM1IE_Pos) +#define GTZC_TZIC_IER2_LPTIM1IE GTZC_TZIC_IER2_LPTIM1IE_Msk /*!< illegal access interrupt enable for LPTIM1 */ +#define GTZC_TZIC_IER2_COMPIE_Pos (23UL) +#define GTZC_TZIC_IER2_COMPIE_Msk (0x01UL << GTZC_TZIC_IER2_COMPIE_Pos) +#define GTZC_TZIC_IER2_COMPIE GTZC_TZIC_IER2_COMPIE_Msk /*!< illegal access interrupt enable for COMP */ +#define GTZC_TZIC_IER2_ADC4IE_Pos (24UL) +#define GTZC_TZIC_IER2_ADC4IE_Msk (0x01UL << GTZC_TZIC_IER2_ADC4IE_Pos) +#define GTZC_TZIC_IER2_ADC4IE GTZC_TZIC_IER2_ADC4IE_Msk /*!< illegal access interrupt enable for ADC4 */ +#define GTZC_IER2_VREFBUFIE_Pos (25UL) +#define GTZC_IER2_VREFBUFIE_Msk (0x01UL << GTZC_IER2_VREFBUFPRIV_Pos) +#define GTZC_IER2_VREFBUFIE GTZC_IER2_VREFBUFPRIV_Msk /*!< illegal access interrupt enable for VREFBUF */ + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC_IER3_CRCIE_Pos (3UL) +#define GTZC_TZIC_IER3_CRCIE_Msk (0x01UL << GTZC_TZIC_IER3_CRCIE_Pos) +#define GTZC_TZIC_IER3_CRCIE GTZC_TZIC_IER3_CRCIE_Msk /*!< illegal access interrupt enable for CRC */ +#define GTZC_TZIC_IER3_TSCIE_Pos (4UL) +#define GTZC_TZIC_IER3_TSCIE_Msk (0x01UL << GTZC_TZIC_IER3_TSCIE_Pos) +#define GTZC_TZIC_IER3_TSCIE GTZC_TZIC_IER3_TSCIE_Msk /*!< illegal access interrupt enable for TSC */ +#define GTZC_TZIC_IER3_ICACHE_REGIE_Pos (6UL) +#define GTZC_TZIC_IER3_ICACHE_REGIE_Msk (0x01UL << GTZC_TZIC_IER3_ICACHE_REGIE_Pos) +#define GTZC_TZIC_IER3_ICACHE_REGIE GTZC_TZIC_IER3_ICACHE_REGIE_Msk /*!< illegal access interrupt enable for ICACHE_REG */ +#define GTZC_TZIC_IER3_OTGIE_Pos (10UL) +#define GTZC_TZIC_IER3_OTGIE_Msk (0x01UL << GTZC_TZIC_IER3_OTGIE_Pos) +#define GTZC_TZIC_IER3_OTGIE GTZC_TZIC_IER3_OTGIE_Msk /*!< illegal access interrupt enable for OTG */ +#define GTZC_TZIC_IER3_AESIE_Pos (11UL) +#define GTZC_TZIC_IER3_AESIE_Msk (0x01UL << GTZC_TZIC_IER3_AESIE_Pos) +#define GTZC_TZIC_IER3_AESIE GTZC_TZIC_IER3_AESIE_Msk /*!< illegal access interrupt enable for AES */ +#define GTZC_TZIC_IER3_HASHIE_Pos (12UL) +#define GTZC_TZIC_IER3_HASHIE_Msk (0x01UL << GTZC_TZIC_IER3_HASHIE_Pos) +#define GTZC_TZIC_IER3_HASHIE GTZC_TZIC_IER3_HASHIE_Msk /*!< illegal access interrupt enable for HASH */ +#define GTZC_TZIC_IER3_RNGIE_Pos (13UL) +#define GTZC_TZIC_IER3_RNGIE_Msk (0x01UL << GTZC_TZIC_IER3_RNGIE_Pos) +#define GTZC_TZIC_IER3_RNGIE GTZC_TZIC_IER3_RNGIE_Msk /*!< illegal access interrupt enable for RNG */ +#define GTZC_TZIC_IER3_SAESIE_Pos (14UL) +#define GTZC_TZIC_IER3_SAESIE_Msk (0x01UL << GTZC_TZIC_IER3_SAESIE_Pos) +#define GTZC_TZIC_IER3_SAESIE GTZC_TZIC_IER3_SAESIE_Msk /*!< illegal access interrupt enable for SAES */ +#define GTZC_TZIC_IER3_HSEMIE_Pos (15UL) +#define GTZC_TZIC_IER3_HSEMIE_Msk (0x01UL << GTZC_TZIC_IER3_HSEMIE_Pos) +#define GTZC_TZIC_IER3_HSEMIE GTZC_TZIC_IER3_HSEMIE_Msk /*!< illegal access interrupt enable for HSEM */ +#define GTZC_TZIC_IER3_PKAIE_Pos (16UL) +#define GTZC_TZIC_IER3_PKAIE_Msk (0x01UL << GTZC_TZIC_IER3_PKAIE_Pos) +#define GTZC_TZIC_IER3_PKAIE GTZC_TZIC_IER3_PKAIE_Msk /*!< illegal access interrupt enable for PKA */ +#define GTZC_TZIC_IER3_RAMCFGIE_Pos (22UL) +#define GTZC_TZIC_IER3_RAMCFGIE_Msk (0x01UL << GTZC_TZIC_IER3_RAMCFGIE_Pos) +#define GTZC_TZIC_IER3_RAMCFGIE GTZC_TZIC_IER3_RAMCFGIE_Msk /*!< illegal access interrupt enable for RAMCFG */ +#define GTZC_TZIC_IER3_RADIOIE_Pos (23UL) +#define GTZC_TZIC_IER3_RADIOIE_Msk (0x01UL << GTZC_TZIC_IER3_RADIOIE_Pos) +#define GTZC_TZIC_IER3_RADIOIE GTZC_TZIC_IER3_RADIOIE_Msk /*!< illegal access interrupt enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_IER3_PTACONVIE_Pos (24UL) +#define GTZC_TZIC_IER3_PTACONVIE_Msk (0x01UL << GTZC_TZIC_IER3_PTACONVIE_Pos) +#define GTZC_TZIC_IER3_PTACONVIE GTZC_TZIC_IER3_PTACONVIE_Msk /*!< illegal access interrupt enable for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC_IER4_GPDMA1IE_Pos (0UL) +#define GTZC_TZIC_IER4_GPDMA1IE_Msk (0x01UL << GTZC_TZIC_IER4_GPDMA1IE_Pos) +#define GTZC_TZIC_IER4_GPDMA1IE GTZC_TZIC_IER4_GPDMA1IE_Msk /*!< illegal access interrupt enable for GPDMA1 */ +#define GTZC_TZIC_IER4_FLASHIE_Pos (1UL) +#define GTZC_TZIC_IER4_FLASHIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASHIE_Pos) +#define GTZC_TZIC_IER4_FLASHIE GTZC_TZIC_IER4_FLASHIE_Msk /*!< illegal access interrupt enable for FLASH memory */ +#define GTZC_TZIC_IER4_FLASH_REGIE_Pos (2UL) +#define GTZC_TZIC_IER4_FLASH_REGIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASH_REGIE_Pos) +#define GTZC_TZIC_IER4_FLASH_REGIE GTZC_TZIC_IER4_FLASH_REGIE_Msk /*!< illegal access interrupt enable for FLASH interface */ +#define GTZC_TZIC_IER4_SYSCFGIE_Pos (7UL) +#define GTZC_TZIC_IER4_SYSCFGIE_Msk (0x01UL << GTZC_TZIC_IER4_SYSCFGIE_Pos) +#define GTZC_TZIC_IER4_SYSCFGIE GTZC_TZIC_IER4_SYSCFGIE_Msk /*!< illegal access interrupt enable for SYSCFG interface */ +#define GTZC_TZIC_IER4_RTCIE_Pos (8UL) +#define GTZC_TZIC_IER4_RTCIE_Msk (0x01UL << GTZC_TZIC_IER4_RTCIE_Pos) +#define GTZC_TZIC_IER4_RTCIE GTZC_TZIC_IER4_RTCIE_Msk /*!< illegal access interrupt enable for RTC interface */ +#define GTZC_TZIC_IER4_TAMPIE_Pos (9UL) +#define GTZC_TZIC_IER4_TAMPIE_Msk (0x01UL << GTZC_TZIC_IER4_TAMPIE_Pos) +#define GTZC_TZIC_IER4_TAMPIE GTZC_TZIC_IER4_TAMPIE_Msk /*!< illegal access interrupt enable for TAMP interface */ +#define GTZC_TZIC_IER4_PWRIE_Pos (10UL) +#define GTZC_TZIC_IER4_PWRIE_Msk (0x01UL << GTZC_TZIC_IER4_PWRIE_Pos) +#define GTZC_TZIC_IER4_PWRIE GTZC_TZIC_IER4_PWRIE_Msk /*!< illegal access interrupt enable for PWR interface */ +#define GTZC_TZIC_IER4_RCCIE_Pos (11UL) +#define GTZC_TZIC_IER4_RCCIE_Msk (0x01UL << GTZC_TZIC_IER4_RCCIE_Pos) +#define GTZC_TZIC_IER4_RCCIE GTZC_TZIC_IER4_RCCIE_Msk /*!< illegal access interrupt enable for RCC interface */ +#define GTZC_TZIC_IER4_EXTIIE_Pos (13UL) +#define GTZC_TZIC_IER4_EXTIIE_Msk (0x01UL << GTZC_TZIC_IER4_EXTIIE_Pos) +#define GTZC_TZIC_IER4_EXTIIE GTZC_TZIC_IER4_EXTIIE_Msk /*!< illegal access interrupt enable for EXTI interface */ +#define GTZC_TZIC_IER4_TZSCIE_Pos (14UL) +#define GTZC_TZIC_IER4_TZSCIE_Msk (0x01UL << GTZC_TZIC_IER4_TZSCIE_Pos) +#define GTZC_TZIC_IER4_TZSCIE GTZC_TZIC_IER4_TZSCIE_Msk /*!< illegal access interrupt enable for GTZC TZSC */ +#define GTZC_TZIC_IER4_TZICIE_Pos (15UL) +#define GTZC_TZIC_IER4_TZICIE_Msk (0x01UL << GTZC_TZIC_IER4_TZICIE_Pos) +#define GTZC_TZIC_IER4_TZICIE GTZC_TZIC_IER4_TZICIE_Msk /*!< illegal access interrupt enable for GTZC TZIC */ +#define GTZC_TZIC_IER4_SRAM1IE_Pos (22UL) +#define GTZC_TZIC_IER4_SRAM1IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM1IE_Pos) +#define GTZC_TZIC_IER4_SRAM1IE GTZC_TZIC_IER4_SRAM1IE_Msk /*!< illegal access interrupt enable for SRAM1 memory */ +#define GTZC_TZIC_IER4_MPCBB1IE_Pos (23UL) +#define GTZC_TZIC_IER4_MPCBB1IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB1IE_Pos) +#define GTZC_TZIC_IER4_MPCBB1IE GTZC_TZIC_IER4_MPCBB1IE_Msk /*!< illegal access interrupt enable for MPCBB1 */ +#define GTZC_TZIC_IER4_SRAM2IE_Pos (24UL) +#define GTZC_TZIC_IER4_SRAM2IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM2IE_Pos) +#define GTZC_TZIC_IER4_SRAM2IE GTZC_TZIC_IER4_SRAM2IE_Msk /*!< illegal access interrupt enable for SRAM2 memory */ +#define GTZC_TZIC_IER4_MPCBB2IE_Pos (25UL) +#define GTZC_TZIC_IER4_MPCBB2IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB2IE_Pos) +#define GTZC_TZIC_IER4_MPCBB2IE GTZC_TZIC_IER4_MPCBB2IE_Msk /*!< illegal access interrupt enable for MPCBB2 */ +#define GTZC_TZIC_IER4_SRAM6IE_Pos (30UL) +#define GTZC_TZIC_IER4_SRAM6IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM6IE_Pos) +#define GTZC_TZIC_IER4_SRAM6IE GTZC_TZIC_IER4_SRAM6IE_Msk /*!< illegal access interrupt enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_IER4_MPCBB6IE_Pos (31UL) +#define GTZC_TZIC_IER4_MPCBB6IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB6IE_Pos) +#define GTZC_TZIC_IER4_MPCBB6IE GTZC_TZIC_IER4_MPCBB6IE_Msk /*!< illegal access interrupt enable for MPCBB6 */ + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC_SR1_TIM2F_Pos (0UL) +#define GTZC_TZIC_SR1_TIM2F_Msk (0x01UL << GTZC_TZIC_SR1_TIM2F_Pos) +#define GTZC_TZIC_SR1_TIM2F GTZC_TZIC_SR1_TIM2F_Msk /*!< illegal access flag for TIM2 */ +#define GTZC_TZIC_SR1_TIM3F_Pos (1UL) +#define GTZC_TZIC_SR1_TIM3F_Msk (0x01UL << GTZC_TZIC_SR1_TIM3F_Pos) +#define GTZC_TZIC_SR1_TIM3F GTZC_TZIC_SR1_TIM3F_Msk /*!< illegal access flag for TIM3 */ +#define GTZC_TZIC_SR1_TIM4F_Pos (2UL) +#define GTZC_TZIC_SR1_TIM4F_Msk (0x01UL << GTZC_TZIC_SR1_TIM4F_Pos) +#define GTZC_TZIC_SR1_TIM4F GTZC_TZIC_SR1_TIM4F_Msk /*!< illegal access flag for TIM4 */ +#define GTZC_TZIC_SR1_WWDGF_Pos (6UL) +#define GTZC_TZIC_SR1_WWDGF_Msk (0x01UL << GTZC_TZIC_SR1_WWDGF_Pos) +#define GTZC_TZIC_SR1_WWDGF GTZC_TZIC_SR1_WWDGF_Msk /*!< illegal access flag for WWDG */ +#define GTZC_TZIC_SR1_IWDGF_Pos (7UL) +#define GTZC_TZIC_SR1_IWDGF_Msk (0x01UL << GTZC_TZIC_SR1_IWDGF_Pos) +#define GTZC_TZIC_SR1_IWDGF GTZC_TZIC_SR1_IWDGF_Msk /*!< illegal access flag for IWDG */ +#define GTZC_TZIC_SR1_SPI2F_Pos (8UL) +#define GTZC_TZIC_SR1_SPI2F_Msk (0x01UL << GTZC_TZIC_SR1_SPI2F_Pos) +#define GTZC_TZIC_SR1_SPI2F GTZC_TZIC_SR1_SPI2F_Msk /*!< illegal access flag for IWDG */ +#define GTZC_TZIC_SR1_USART2F_Pos (9UL) +#define GTZC_TZIC_SR1_USART2F_Msk (0x01UL << GTZC_TZIC_SR1_USART2F_Pos) +#define GTZC_TZIC_SR1_USART2F GTZC_TZIC_SR1_USART2F_Msk /*!< illegal access flag for USART2 */ +#define GTZC_TZIC_SR1_USART3F_Pos (10UL) +#define GTZC_TZIC_SR1_USART3F_Msk (0x01UL << GTZC_TZIC_SR1_USART3F_Pos) +#define GTZC_TZIC_SR1_USART3F GTZC_TZIC_SR1_USART3F_Msk /*!< illegal access flag for USART3 */ +#define GTZC_TZIC_SR1_I2C1F_Pos (13UL) +#define GTZC_TZIC_SR1_I2C1F_Msk (0x01UL << GTZC_TZIC_SR1_I2C1F_Pos) +#define GTZC_TZIC_SR1_I2C1F GTZC_TZIC_SR1_I2C1F_Msk /*!< illegal access flag for I2C1 */ +#define GTZC_TZIC_SR1_I2C2F_Pos (14UL) +#define GTZC_TZIC_SR1_I2C2F_Msk (0x01UL << GTZC_TZIC_SR1_I2C2F_Pos) +#define GTZC_TZIC_SR1_I2C2F GTZC_TZIC_SR1_I2C2F_Msk /*!< illegal access flag for I2C2 */ +#define GTZC_TZIC_SR1_I2C4F_Pos (16UL) +#define GTZC_TZIC_SR1_I2C4F_Msk (0x01UL << GTZC_TZIC_SR1_I2C4F_Pos) +#define GTZC_TZIC_SR1_I2C4F GTZC_TZIC_SR1_I2C4F_Msk /*!< illegal access flag for I2C4 */ +#define GTZC_TZIC_SR1_LPTIM2F_Pos (17UL) +#define GTZC_TZIC_SR1_LPTIM2F_Msk (0x01UL << GTZC_TZIC_SR1_LPTIM2F_Pos) +#define GTZC_TZIC_SR1_LPTIM2F GTZC_TZIC_SR1_LPTIM2F_Msk /*!< illegal access flag for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC_SR2_TIM1F_Pos (0UL) +#define GTZC_TZIC_SR2_TIM1F_Msk (0x01UL << GTZC_TZIC_SR2_TIM1F_Pos) +#define GTZC_TZIC_SR2_TIM1F GTZC_TZIC_SR2_TIM1F_Msk /*!< illegal access flag for TIM1 */ +#define GTZC_TZIC_SR2_SPI1F_Pos (1UL) +#define GTZC_TZIC_SR2_SPI1F_Msk (0x01UL << GTZC_TZIC_SR2_SPI1F_Pos) +#define GTZC_TZIC_SR2_SPI1F GTZC_TZIC_SR2_SPI1F_Msk /*!< illegal access flag for SPI1 */ +#define GTZC_TZIC_SR2_USART1F_Pos (3UL) +#define GTZC_TZIC_SR2_USART1F_Msk (0x01UL << GTZC_TZIC_SR2_USART1F_Pos) +#define GTZC_TZIC_SR2_USART1F GTZC_TZIC_SR2_USART1F_Msk /*!< illegal access flag for USART1 */ +#define GTZC_TZIC_SR2_TIM16F_Pos (5UL) +#define GTZC_TZIC_SR2_TIM16F_Msk (0x01UL << GTZC_TZIC_SR2_TIM16F_Pos) +#define GTZC_TZIC_SR2_TIM16F GTZC_TZIC_SR2_TIM16F_Msk /*!< illegal access flag for TIM16 */ +#define GTZC_TZIC_SR2_TIM17F_Pos (6UL) +#define GTZC_TZIC_SR2_TIM17F_Msk (0x01UL << GTZC_TZIC_SR2_TIM17F_Pos) +#define GTZC_TZIC_SR2_TIM17F GTZC_TZIC_SR2_TIM17F_Msk /*!< illegal access flag for TIM17 */ +#define GTZC_TZIC_SR2_SAI1F_Pos (7UL) +#define GTZC_TZIC_SR2_SAI1F_Msk (0x01UL << GTZC_TZIC_SR2_SAI1F_Pos) +#define GTZC_TZIC_SR2_SAI1F GTZC_TZIC_SR2_SAI1F_Msk /*!< illegal access flag for SAI1 */ +#define GTZC_TZIC_SR2_SPI3F_Pos (16UL) +#define GTZC_TZIC_SR2_SPI3F_Msk (0x01UL << GTZC_TZIC_SR2_SPI3F_Pos) +#define GTZC_TZIC_SR2_SPI3F GTZC_TZIC_SR2_SPI3F_Msk /*!< illegal access flag for SPI3 */ +#define GTZC_TZIC_SR2_LPUART1F_Pos (17UL) +#define GTZC_TZIC_SR2_LPUART1F_Msk (0x01UL << GTZC_TZIC_SR2_LPUART1F_Pos) +#define GTZC_TZIC_SR2_LPUART1F GTZC_TZIC_SR2_LPUART1F_Msk /*!< illegal access flag for LPUART1 */ +#define GTZC_TZIC_SR2_I2C3F_Pos (18UL) +#define GTZC_TZIC_SR2_I2C3F_Msk (0x01UL << GTZC_TZIC_SR2_I2C3F_Pos) +#define GTZC_TZIC_SR2_I2C3F GTZC_TZIC_SR2_I2C3F_Msk /*!< illegal access flag for I2C3 */ +#define GTZC_TZIC_SR2_LPTIM1F_Pos (19UL) +#define GTZC_TZIC_SR2_LPTIM1F_Msk (0x01UL << GTZC_TZIC_SR2_LPTIM1F_Pos) +#define GTZC_TZIC_SR2_LPTIM1F GTZC_TZIC_SR2_LPTIM1F_Msk /*!< illegal access flag for LPTIM1 */ +#define GTZC_TZIC_SR2_COMPF_Pos (23UL) +#define GTZC_TZIC_SR2_COMPF_Msk (0x01UL << GTZC_TZIC_SR2_COMPF_Pos) +#define GTZC_TZIC_SR2_COMPF GTZC_TZIC_SR2_COMPF_Msk /*!< illegal access flag for COMP */ +#define GTZC_TZIC_SR2_ADC4F_Pos (24UL) +#define GTZC_TZIC_SR2_ADC4F_Msk (0x01UL << GTZC_TZIC_SR2_ADC4F_Pos) +#define GTZC_TZIC_SR2_ADC4F GTZC_TZIC_SR2_ADC4F_Msk /*!< illegal access flag for ADC4 */ +#define GTZC_TZIC_SR2_VREFBUFF_Pos (25UL) +#define GTZC_TZIC_SR2_VREFBUFF_Msk (0x01UL << GTZC_TZIC_SR2_VREFBUFPRIV_Pos) +#define GTZC_TZIC_SR2_VREFBUFF GTZC_TZIC_SR2_VREFBUFPRIV_Msk /*!< illegal access flag for VREFBUF */ + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC_SR3_CRCF_Pos (3UL) +#define GTZC_TZIC_SR3_CRCF_Msk (0x01UL << GTZC_TZIC_SR3_CRCF_Pos) +#define GTZC_TZIC_SR3_CRCF GTZC_TZIC_SR3_CRCF_Msk /*!< illegal access flag for CRC */ +#define GTZC_TZIC_SR3_TSCF_Pos (4UL) +#define GTZC_TZIC_SR3_TSCF_Msk (0x01UL << GTZC_TZIC_SR3_TSCF_Pos) +#define GTZC_TZIC_SR3_TSCF GTZC_TZIC_SR3_TSCF_Msk /*!< illegal access flag for TSC */ +#define GTZC_TZIC_SR3_ICACHE_REGF_Pos (6UL) +#define GTZC_TZIC_SR3_ICACHE_REGF_Msk (0x01UL << GTZC_TZIC_SR3_ICACHE_REGF_Pos) +#define GTZC_TZIC_SR3_ICACHE_REGF GTZC_TZIC_SR3_ICACHE_REGF_Msk /*!< illegal access flag for ICACHE_REG */ +#define GTZC_TZIC_SR3_OTGF_Pos (10UL) +#define GTZC_TZIC_SR3_OTGF_Msk (0x01UL << GTZC_TZIC_SR3_OTGF_Pos) +#define GTZC_TZIC_SR3_OTGF GTZC_TZIC_SR3_OTGF_Msk /*!< illegal access flag for OTG */ +#define GTZC_TZIC_SR3_AESF_Pos (11UL) +#define GTZC_TZIC_SR3_AESF_Msk (0x01UL << GTZC_TZIC_SR3_AESF_Pos) +#define GTZC_TZIC_SR3_AESF GTZC_TZIC_SR3_AESF_Msk /*!< illegal access flag for AES */ +#define GTZC_TZIC_SR3_HASHF_Pos (12UL) +#define GTZC_TZIC_SR3_HASHF_Msk (0x01UL << GTZC_TZIC_SR3_HASHF_Pos) +#define GTZC_TZIC_SR3_HASHF GTZC_TZIC_SR3_HASHF_Msk /*!< illegal access flag for HASH */ +#define GTZC_TZIC_SR3_RNGF_Pos (13UL) +#define GTZC_TZIC_SR3_RNGF_Msk (0x01UL << GTZC_TZIC_SR3_RNGF_Pos) +#define GTZC_TZIC_SR3_RNGF GTZC_TZIC_SR3_RNGF_Msk /*!< illegal access flag for RNG */ +#define GTZC_TZIC_SR3_SAESF_Pos (14UL) +#define GTZC_TZIC_SR3_SAESF_Msk (0x01UL << GTZC_TZIC_SR3_SAESF_Pos) +#define GTZC_TZIC_SR3_SAESF GTZC_TZIC_SR3_SAESF_Msk /*!< illegal access flag for SAES */ +#define GTZC_TZIC_SR3_HSEMF_Pos (15UL) +#define GTZC_TZIC_SR3_HSEMF_Msk (0x01UL << GTZC_TZIC_SR3_HSEMF_Pos) +#define GTZC_TZIC_SR3_HSEMF GTZC_TZIC_SR3_HSEMF_Msk /*!< illegal access flag for HSEM */ +#define GTZC_TZIC_SR3_PKAF_Pos (16UL) +#define GTZC_TZIC_SR3_PKAF_Msk (0x01UL << GTZC_TZIC_SR3_PKAF_Pos) +#define GTZC_TZIC_SR3_PKAF GTZC_TZIC_SR3_PKAF_Msk /*!< illegal access flag for PKA */ +#define GTZC_TZIC_SR3_RAMCFGF_Pos (22UL) +#define GTZC_TZIC_SR3_RAMCFGF_Msk (0x01UL << GTZC_TZIC_SR3_RAMCFGF_Pos) +#define GTZC_TZIC_SR3_RAMCFGF GTZC_TZIC_SR3_RAMCFGF_Msk /*!< illegal access flag for RAMCFG */ +#define GTZC_TZIC_SR3_RADIOF_Pos (23UL) +#define GTZC_TZIC_SR3_RADIOF_Msk (0x01UL << GTZC_TZIC_SR3_RADIOF_Pos) +#define GTZC_TZIC_SR3_RADIOF GTZC_TZIC_SR3_RADIOF_Msk /*!< illegal access flag for 2.4 GHz RADIO */ +#define GTZC_TZIC_SR3_PTACONVF_Pos (24UL) +#define GTZC_TZIC_SR3_PTACONVF_Msk (0x01UL << GTZC_TZIC_SR3_PTACONVF_Pos) +#define GTZC_TZIC_SR3_PTACONVF GTZC_TZIC_SR3_PTACONVF_Msk /*!< illegal access flag for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC_SR4_GPDMA1F_Pos (0UL) +#define GTZC_TZIC_SR4_GPDMA1F_Msk (0x01UL << GTZC_TZIC_SR4_GPDMA1F_Pos) +#define GTZC_TZIC_SR4_GPDMA1F GTZC_TZIC_SR4_GPDMA1F_Msk /*!< illegal access flag for GPDMA1 */ +#define GTZC_TZIC_SR4_FLASHF_Pos (1UL) +#define GTZC_TZIC_SR4_FLASHF_Msk (0x01UL << GTZC_TZIC_SR4_FLASHF_Pos) +#define GTZC_TZIC_SR4_FLASHF GTZC_TZIC_SR4_FLASHF_Msk /*!< illegal access flag for FLASH memory */ +#define GTZC_TZIC_SR4_FLASH_REGF_Pos (2UL) +#define GTZC_TZIC_SR4_FLASH_REGF_Msk (0x01UL << GTZC_TZIC_SR4_FLASH_REGF_Pos) +#define GTZC_TZIC_SR4_FLASH_REGF GTZC_TZIC_SR4_FLASH_REGF_Msk /*!< illegal access flag for FLASH interface */ +#define GTZC_TZIC_SR4_SYSCFGF_Pos (7UL) +#define GTZC_TZIC_SR4_SYSCFGF_Msk (0x01UL << GTZC_TZIC_SR4_SYSCFGF_Pos) +#define GTZC_TZIC_SR4_SYSCFGF GTZC_TZIC_SR4_SYSCFGF_Msk /*!< illegal access flag for SYSCFG interface */ +#define GTZC_TZIC_SR4_RTCF_Pos (8UL) +#define GTZC_TZIC_SR4_RTCF_Msk (0x01UL << GTZC_TZIC_SR4_RTCF_Pos) +#define GTZC_TZIC_SR4_RTCF GTZC_TZIC_SR4_RTCF_Msk /*!< illegal access flag for RTC interface */ +#define GTZC_TZIC_SR4_TAMPF_Pos (9UL) +#define GTZC_TZIC_SR4_TAMPF_Msk (0x01UL << GTZC_TZIC_SR4_TAMPF_Pos) +#define GTZC_TZIC_SR4_TAMPF GTZC_TZIC_SR4_TAMPF_Msk /*!< illegal access flag for TAMP interface */ +#define GTZC_TZIC_SR4_PWRF_Pos (10UL) +#define GTZC_TZIC_SR4_PWRF_Msk (0x01UL << GTZC_TZIC_SR4_PWRF_Pos) +#define GTZC_TZIC_SR4_PWRF GTZC_TZIC_SR4_PWRF_Msk /*!< illegal access flag for PWR interface */ +#define GTZC_TZIC_SR4_RCCF_Pos (11UL) +#define GTZC_TZIC_SR4_RCCF_Msk (0x01UL << GTZC_TZIC_SR4_RCCF_Pos) +#define GTZC_TZIC_SR4_RCCF GTZC_TZIC_SR4_RCCF_Msk /*!< illegal access flag for RCC interface */ +#define GTZC_TZIC_SR4_EXTIF_Pos (13UL) +#define GTZC_TZIC_SR4_EXTIF_Msk (0x01UL << GTZC_TZIC_SR4_EXTIF_Pos) +#define GTZC_TZIC_SR4_EXTIF GTZC_TZIC_SR4_EXTIF_Msk /*!< illegal access flag for EXTI interface */ +#define GTZC_TZIC_SR4_TZSCF_Pos (14UL) +#define GTZC_TZIC_SR4_TZSCF_Msk (0x01UL << GTZC_TZIC_SR4_TZSCF_Pos) +#define GTZC_TZIC_SR4_TZSCF GTZC_TZIC_SR4_TZSCF_Msk /*!< illegal access flag for GTZC TZSC */ +#define GTZC_TZIC_SR4_TZICF_Pos (15UL) +#define GTZC_TZIC_SR4_TZICF_Msk (0x01UL << GTZC_TZIC_SR4_TZICF_Pos) +#define GTZC_TZIC_SR4_TZICF GTZC_TZIC_SR4_TZICF_Msk /*!< illegal access flag for GTZC TZIC */ +#define GTZC_TZIC_SR4_SRAM1F_Pos (22UL) +#define GTZC_TZIC_SR4_SRAM1F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM1F_Pos) +#define GTZC_TZIC_SR4_SRAM1F GTZC_TZIC_SR4_SRAM1F_Msk /*!< illegal access flag for SRAM1 memory */ +#define GTZC_TZIC_SR4_MPCBB1F_Pos (23UL) +#define GTZC_TZIC_SR4_MPCBB1F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB1F_Pos) +#define GTZC_TZIC_SR4_MPCBB1F GTZC_TZIC_SR4_MPCBB1F_Msk /*!< illegal access flag for MPCBB1 */ +#define GTZC_TZIC_SR4_SRAM2F_Pos (24UL) +#define GTZC_TZIC_SR4_SRAM2F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM2F_Pos) +#define GTZC_TZIC_SR4_SRAM2F GTZC_TZIC_SR4_SRAM2F_Msk /*!< illegal access flag for SRAM2 memory */ +#define GTZC_TZIC_SR4_MPCBB2F_Pos (25UL) +#define GTZC_TZIC_SR4_MPCBB2F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB2F_Pos) +#define GTZC_TZIC_SR4_MPCBB2F GTZC_TZIC_SR4_MPCBB2F_Msk /*!< illegal access flag for MPCBB2 */ +#define GTZC_TZIC_SR4_SRAM6F_Pos (30UL) +#define GTZC_TZIC_SR4_SRAM6F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM6F_Pos) +#define GTZC_TZIC_SR4_SRAM6F GTZC_TZIC_SR4_SRAM6F_Msk /*!< illegal access flag for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_SR4_MPCBB6F_Pos (31UL) +#define GTZC_TZIC_SR4_MPCBB6F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB6F_Pos) +#define GTZC_TZIC_SR4_MPCBB6F GTZC_TZIC_SR4_MPCBB6F_Msk /*!< illegal access flag for MPCBB6 */ + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC_FCR1_CTIM2F_Pos (0UL) +#define GTZC_TZIC_FCR1_CTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM2F_Pos) +#define GTZC_TZIC_FCR1_CTIM2F GTZC_TZIC_FCR1_CTIM2F_Msk /*!< clear the illegal access flag for TIM2 */ +#define GTZC_TZIC_FCR1_CTIM3F_Pos (1UL) +#define GTZC_TZIC_FCR1_CTIM3F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM3F_Pos) +#define GTZC_TZIC_FCR1_CTIM3F GTZC_TZIC_FCR1_CTIM3F_Msk /*!< clear the illegal access flag for TIM3 */ +#define GTZC_TZIC_FCR1_CTIM4F_Pos (2UL) +#define GTZC_TZIC_FCR1_CTIM4F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM4F_Pos) +#define GTZC_TZIC_FCR1_CTIM4F GTZC_TZIC_FCR1_CTIM4F_Msk /*!< clear the illegal access flag for TIM4 */ +#define GTZC_TZIC_FCR1_CWWDGF_Pos (6UL) +#define GTZC_TZIC_FCR1_CWWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CWWDGF_Pos) +#define GTZC_TZIC_FCR1_CWWDGF GTZC_TZIC_FCR1_CWWDGF_Msk /*!< clear the illegal access flag for WWDG */ +#define GTZC_TZIC_FCR1_CIWDGF_Pos (7UL) +#define GTZC_TZIC_FCR1_CIWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CIWDGF_Pos) +#define GTZC_TZIC_FCR1_CIWDGF GTZC_TZIC_FCR1_CIWDGF_Msk /*!< clear the illegal access flag for IWDG */ +#define GTZC_TZIC_FCR1_CSPI2F_Pos (8UL) +#define GTZC_TZIC_FCR1_CSPI2F_Msk (0x01UL << GTZC_TZIC_FCR1_CSPI2F_Pos) +#define GTZC_TZIC_FCR1_CSPI2F GTZC_TZIC_FCR1_CSPI2F_Msk /*!< clear the illegal access flag for IWDG */ +#define GTZC_TZIC_FCR1_CUSART2F_Pos (9UL) +#define GTZC_TZIC_FCR1_CUSART2F_Msk (0x01UL << GTZC_TZIC_FCR1_CUSART2F_Pos) +#define GTZC_TZIC_FCR1_CUSART2F GTZC_TZIC_FCR1_CUSART2F_Msk /*!< clear the illegal access flag for USART2 */ +#define GTZC_TZIC_FCR1_CUSART3F_Pos (10UL) +#define GTZC_TZIC_FCR1_CUSART3F_Msk (0x01UL << GTZC_TZIC_FCR1_CUSART3F_Pos) +#define GTZC_TZIC_FCR1_CUSART3F GTZC_TZIC_FCR1_CUSART3F_Msk /*!< clear the illegal access flag for USART3 */ +#define GTZC_TZIC_FCR1_CI2C1F_Pos (13UL) +#define GTZC_TZIC_FCR1_CI2C1F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C1F_Pos) +#define GTZC_TZIC_FCR1_CI2C1F GTZC_TZIC_FCR1_CI2C1F_Msk /*!< clear the illegal access flag for I2C1 */ +#define GTZC_TZIC_FCR1_CI2C2F_Pos (14UL) +#define GTZC_TZIC_FCR1_CI2C2F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C2F_Pos) +#define GTZC_TZIC_FCR1_CI2C2F GTZC_TZIC_FCR1_CI2C2F_Msk /*!< clear the illegal access flag for I2C2 */ +#define GTZC_TZIC_FCR1_CI2C4F_Pos (16UL) +#define GTZC_TZIC_FCR1_CI2C4F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C4F_Pos) +#define GTZC_TZIC_FCR1_CI2C4F GTZC_TZIC_FCR1_CI2C4F_Msk /*!< clear the illegal access flag for I2C4 */ +#define GTZC_TZIC_FCR1_CLPTIM2F_Pos (17UL) +#define GTZC_TZIC_FCR1_CLPTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CLPTIM2F_Pos) +#define GTZC_TZIC_FCR1_CLPTIM2F GTZC_TZIC_FCR1_CLPTIM2F_Msk /*!< clear the illegal access flag for LPTIM2 */ + +/****************** Bits definition for GTZC_TZIC_FCR2 register ****************/ +#define GTZC_TZIC_FCR2_CTIM1F_Pos (0UL) +#define GTZC_TZIC_FCR2_CTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM1F_Pos) +#define GTZC_TZIC_FCR2_CTIM1F GTZC_TZIC_FCR2_CTIM1F_Msk /*!< clear the illegal access flag for TIM1 */ +#define GTZC_TZIC_FCR2_CSPI1F_Pos (1UL) +#define GTZC_TZIC_FCR2_CSPI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI1F_Pos) +#define GTZC_TZIC_FCR2_CSPI1F GTZC_TZIC_FCR2_CSPI1F_Msk /*!< clear the illegal access flag for SPI1 */ +#define GTZC_TZIC_FCR2_CUSART1F_Pos (3UL) +#define GTZC_TZIC_FCR2_CUSART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CUSART1F_Pos) +#define GTZC_TZIC_FCR2_CUSART1F GTZC_TZIC_FCR2_CUSART1F_Msk /*!< clear the illegal access flag for USART1 */ +#define GTZC_TZIC_FCR2_CTIM16F_Pos (5UL) +#define GTZC_TZIC_FCR2_CTIM16F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM16F_Pos) +#define GTZC_TZIC_FCR2_CTIM16F GTZC_TZIC_FCR2_CTIM16F_Msk /*!< clear the illegal access flag for TIM16 */ +#define GTZC_TZIC_FCR2_CTIM17F_Pos (6UL) +#define GTZC_TZIC_FCR2_CTIM17F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM17F_Pos) +#define GTZC_TZIC_FCR2_CTIM17F GTZC_TZIC_FCR2_CTIM17F_Msk /*!< clear the illegal access flag for TIM17 */ +#define GTZC_TZIC_FCR2_CSAI1F_Pos (7UL) +#define GTZC_TZIC_FCR2_CSAI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSAI1F_Pos) +#define GTZC_TZIC_FCR2_CSAI1F GTZC_TZIC_FCR2_CSAI1F_Msk /*!< clear the illegal access flag for SAI1 */ +#define GTZC_TZIC_FCR2_CSPI3F_Pos (16UL) +#define GTZC_TZIC_FCR2_CSPI3F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI3F_Pos) +#define GTZC_TZIC_FCR2_CSPI3F GTZC_TZIC_FCR2_CSPI3F_Msk /*!< clear the illegal access flag for SPI3 */ +#define GTZC_TZIC_FCR2_CLPUART1F_Pos (17UL) +#define GTZC_TZIC_FCR2_CLPUART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPUART1F_Pos) +#define GTZC_TZIC_FCR2_CLPUART1F GTZC_TZIC_FCR2_CLPUART1F_Msk /*!< clear the illegal access flag for LPUART1 */ +#define GTZC_TZIC_FCR2_CI2C3F_Pos (18UL) +#define GTZC_TZIC_FCR2_CI2C3F_Msk (0x01UL << GTZC_TZIC_FCR2_CI2C3F_Pos) +#define GTZC_TZIC_FCR2_CI2C3F GTZC_TZIC_FCR2_CI2C3F_Msk /*!< clear the illegal access flag for I2C3 */ +#define GTZC_TZIC_FCR2_CLPTIM1F_Pos (19UL) +#define GTZC_TZIC_FCR2_CLPTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPTIM1F_Pos) +#define GTZC_TZIC_FCR2_CLPTIM1F GTZC_TZIC_FCR2_CLPTIM1F_Msk /*!< clear the illegal access flag for LPTIM1 */ +#define GTZC_TZIC_FCR2_CCOMPF_Pos (23UL) +#define GTZC_TZIC_FCR2_CCOMPF_Msk (0x01UL << GTZC_TZIC_FCR2_CCOMPF_Pos) +#define GTZC_TZIC_FCR2_CCOMPF GTZC_TZIC_FCR2_CCOMPF_Msk /*!< clear the illegal access flag for COMP */ +#define GTZC_TZIC_FCR2_CADC4F_Pos (24UL) +#define GTZC_TZIC_FCR2_CADC4F_Msk (0x01UL << GTZC_TZIC_FCR2_CADC4F_Pos) +#define GTZC_TZIC_FCR2_CADC4F GTZC_TZIC_FCR2_CADC4F_Msk /*!< clear the illegal access flag for ADC4 */ +#define GTZC_TZIC_FCR2_CVREFBUFF_Pos (25UL) +#define GTZC_TZIC_FCR2_CVREFBUFF_Msk (0x01UL << GTZC_FCR2_CVREFBUFF_Pos) +#define GTZC_TZIC_FCR2_CVREFBUFF GTZC_TZIC_FCR2_CVREFBUFF_Msk /*!< clear the illegal access flag for VREFBUF */ + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC_FCR3_CCRCF_Pos (3UL) +#define GTZC_TZIC_FCR3_CCRCF_Msk (0x01UL << GTZC_TZIC_FCR3_CCRCF_Pos) +#define GTZC_TZIC_FCR3_CCRCF GTZC_TZIC_FCR3_CCRCF_Msk /*!< clear the illegal access flag enable for CRC */ +#define GTZC_TZIC_FCR3_CTSCF_Pos (4UL) +#define GTZC_TZIC_FCR3_CTSCF_Msk (0x01UL << GTZC_TZIC_FCR3_CTSCF_Pos) +#define GTZC_TZIC_FCR3_CTSCF GTZC_TZIC_FCR3_CTSCF_Msk /*!< clear the illegal access flag enable for TSC */ +#define GTZC_TZIC_FCR3_CICACHE_REGF_Pos (6UL) +#define GTZC_TZIC_FCR3_CICACHE_REGF_Msk (0x01UL << GTZC_TZIC_FCR3_CICACHE_REGF_Pos) +#define GTZC_TZIC_FCR3_CICACHE_REGF GTZC_TZIC_FCR3_CICACHE_REGF_Msk /*!< clear the illegal access flag enable for ICACHE_REG */ +#define GTZC_TZIC_FCR3_COTGF_Pos (10UL) +#define GTZC_TZIC_FCR3_COTGF_Msk (0x01UL << GTZC_TZIC_FCR3_COTGF_Pos) +#define GTZC_TZIC_FCR3_COTGF GTZC_TZIC_FCR3_COTGF_Msk /*!< clear the illegal access flag for OTG */ +#define GTZC_TZIC_FCR3_CAESF_Pos (11UL) +#define GTZC_TZIC_FCR3_CAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CAESF_Pos) +#define GTZC_TZIC_FCR3_CAESF GTZC_TZIC_FCR3_CAESF_Msk /*!< clear the illegal access flag enable for AES */ +#define GTZC_TZIC_FCR3_CHASHF_Pos (12UL) +#define GTZC_TZIC_FCR3_CHASHF_Msk (0x01UL << GTZC_TZIC_FCR3_CHASHF_Pos) +#define GTZC_TZIC_FCR3_CHASHF GTZC_TZIC_FCR3_CHASHF_Msk /*!< clear the illegal access flag enable for HASH */ +#define GTZC_TZIC_FCR3_CRNGF_Pos (13UL) +#define GTZC_TZIC_FCR3_CRNGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRNGF_Pos) +#define GTZC_TZIC_FCR3_CRNGF GTZC_TZIC_FCR3_CRNGF_Msk /*!< clear the illegal access flag enable for RNG */ +#define GTZC_TZIC_FCR3_CSAESF_Pos (14UL) +#define GTZC_TZIC_FCR3_CSAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CSAESF_Pos) +#define GTZC_TZIC_FCR3_CSAESF GTZC_TZIC_FCR3_CSAESF_Msk /*!< clear the illegal access flag enable for SAES */ +#define GTZC_TZIC_FCR3_CHSEMF_Pos (15UL) +#define GTZC_TZIC_FCR3_CHSEMF_Msk (0x01UL << GTZC_TZIC_FCR3_CHSEMF_Pos) +#define GTZC_TZIC_FCR3_CHSEMF GTZC_TZIC_FCR3_CHSEMF_Msk /*!< clear the illegal access flag enable for HSEM */ +#define GTZC_TZIC_FCR3_CPKAF_Pos (16UL) +#define GTZC_TZIC_FCR3_CPKAF_Msk (0x01UL << GTZC_TZIC_FCR3_CPKAF_Pos) +#define GTZC_TZIC_FCR3_CPKAF GTZC_TZIC_FCR3_CPKAF_Msk /*!< clear the illegal access flag enable for PKA */ +#define GTZC_TZIC_FCR3_CRAMCFGF_Pos (22UL) +#define GTZC_TZIC_FCR3_CRAMCFGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRAMCFGF_Pos) +#define GTZC_TZIC_FCR3_CRAMCFGF GTZC_TZIC_FCR3_CRAMCFGF_Msk /*!< clear the illegal access flag enable for RAMCFG */ +#define GTZC_TZIC_FCR3_CRADIOF_Pos (23UL) +#define GTZC_TZIC_FCR3_CRADIOF_Msk (0x01UL << GTZC_TZIC_FCR3_CRADIOF_Pos) +#define GTZC_TZIC_FCR3_CRADIOF GTZC_TZIC_FCR3_CRADIOF_Msk /*!< clear the illegal access flag enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_FCR3_CPTACONVF_Pos (24UL) +#define GTZC_TZIC_FCR3_CPTACONVF_Msk (0x01UL << GTZC_TZIC_FCR3_CPTACONVF_Pos) +#define GTZC_TZIC_FCR3_CPTACONVF GTZC_TZIC_FCR3_CPTACONVF_Msk /*!< clear the illegal access flag enable for PTACONV */ + +/****************** Bits definition for GTZC_TZIC_FCR4 register ****************/ +#define GTZC_TZIC_FCR4_CGPDMA1F_Pos (0UL) +#define GTZC_TZIC_FCR4_CGPDMA1F_Msk (0x01UL << GTZC_TZIC_FCR4_CGPDMA1F_Pos) +#define GTZC_TZIC_FCR4_CGPDMA1F GTZC_TZIC_FCR4_CGPDMA1F_Msk /*!< clear the illegal access flag enable for GPDMA1 */ +#define GTZC_TZIC_FCR4_CFLASHF_Pos (1UL) +#define GTZC_TZIC_FCR4_CFLASHF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASHF_Pos) +#define GTZC_TZIC_FCR4_CFLASHF GTZC_TZIC_FCR4_CFLASHF_Msk /*!< clear the illegal access flag enable for FLASH memory */ +#define GTZC_TZIC_FCR4_CFLASH_REGF_Pos (2UL) +#define GTZC_TZIC_FCR4_CFLASH_REGF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASH_REGF_Pos) +#define GTZC_TZIC_FCR4_CFLASH_REGF GTZC_TZIC_FCR4_CFLASH_REGF_Msk /*!< clear the illegal access flag enable for FLASH interface */ +#define GTZC_TZIC_FCR4_CSYSCFGF_Pos (7UL) +#define GTZC_TZIC_FCR4_CSYSCFGF_Msk (0x01UL << GTZC_TZIC_FCR4_CSYSCFGF_Pos) +#define GTZC_TZIC_FCR4_CSYSCFGF GTZC_TZIC_FCR4_CSYSCFGF_Msk /*!< clear the illegal access flag enable for SYSCFG interface */ +#define GTZC_TZIC_FCR4_CRTCF_Pos (8UL) +#define GTZC_TZIC_FCR4_CRTCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRTCF_Pos) +#define GTZC_TZIC_FCR4_CRTCF GTZC_TZIC_FCR4_CRTCF_Msk /*!< clear the illegal access flag enable for RTC interface */ +#define GTZC_TZIC_FCR4_CTAMPF_Pos (9UL) +#define GTZC_TZIC_FCR4_CTAMPF_Msk (0x01UL << GTZC_TZIC_FCR4_CTAMPF_Pos) +#define GTZC_TZIC_FCR4_CTAMPF GTZC_TZIC_FCR4_CTAMPF_Msk /*!< clear the illegal access flag enable for TAMP interface */ +#define GTZC_TZIC_FCR4_CPWRF_Pos (10UL) +#define GTZC_TZIC_FCR4_CPWRF_Msk (0x01UL << GTZC_TZIC_FCR4_CPWRF_Pos) +#define GTZC_TZIC_FCR4_CPWRF GTZC_TZIC_FCR4_CPWRF_Msk /*!< clear the illegal access flag enable for PWR interface */ +#define GTZC_TZIC_FCR4_CRCCF_Pos (11UL) +#define GTZC_TZIC_FCR4_CRCCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRCCF_Pos) +#define GTZC_TZIC_FCR4_CRCCF GTZC_TZIC_FCR4_CRCCF_Msk /*!< clear the illegal access flag enable for RCC interface */ +#define GTZC_TZIC_FCR4_CEXTIF_Pos (13UL) +#define GTZC_TZIC_FCR4_CEXTIF_Msk (0x01UL << GTZC_TZIC_FCR4_CEXTIF_Pos) +#define GTZC_TZIC_FCR4_CEXTIF GTZC_TZIC_FCR4_CEXTIF_Msk /*!< clear the illegal access flag enable for EXTI interface */ +#define GTZC_TZIC_FCR4_CTZSCF_Pos (14UL) +#define GTZC_TZIC_FCR4_CTZSCF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZSCF_Pos) +#define GTZC_TZIC_FCR4_CTZSCF GTZC_TZIC_FCR4_CTZSCF_Msk /*!< clear the illegal access flag enable for GTZC TZSC */ +#define GTZC_TZIC_FCR4_CTZICF_Pos (15UL) +#define GTZC_TZIC_FCR4_CTZICF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZICF_Pos) +#define GTZC_TZIC_FCR4_CTZICF GTZC_TZIC_FCR4_CTZICF_Msk /*!< clear the illegal access flag enable for GTZC TZIC */ +#define GTZC_TZIC_FCR4_CSRAM1F_Pos (22UL) +#define GTZC_TZIC_FCR4_CSRAM1F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM1F_Pos) +#define GTZC_TZIC_FCR4_CSRAM1F GTZC_TZIC_FCR4_CSRAM1F_Msk /*!< clear the illegal access flag enable for SRAM1 memory */ +#define GTZC_TZIC_FCR4_CMPCBB1F_Pos (23UL) +#define GTZC_TZIC_FCR4_CMPCBB1F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB1F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB1F GTZC_TZIC_FCR4_CMPCBB1F_Msk /*!< clear the illegal access flag enable for MPCBB1 */ +#define GTZC_TZIC_FCR4_CSRAM2F_Pos (24UL) +#define GTZC_TZIC_FCR4_CSRAM2F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM2F_Pos) +#define GTZC_TZIC_FCR4_CSRAM2F GTZC_TZIC_FCR4_CSRAM2F_Msk /*!< clear the illegal access flag enable for SRAM2 memory */ +#define GTZC_TZIC_FCR4_CMPCBB2F_Pos (25UL) +#define GTZC_TZIC_FCR4_CMPCBB2F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB2F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB2F GTZC_TZIC_FCR4_CMPCBB2F_Msk /*!< clear the illegal access flag enable for MPCBB2 */ +#define GTZC_TZIC_FCR4_CSRAM6F_Pos (30UL) +#define GTZC_TZIC_FCR4_CSRAM6F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM6F_Pos) +#define GTZC_TZIC_FCR4_CSRAM6F GTZC_TZIC_FCR4_CSRAM6F_Msk /*!< clear the illegal access flag enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_FCR4_CMPCBB6F_Pos (31UL) +#define GTZC_TZIC_FCR4_CMPCBB6F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB6F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB6F GTZC_TZIC_FCR4_CMPCBB6F_Msk /*!< clear the illegal access flag enable for MPCBB6 */ + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0UL) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_GLOCK GTZC_MPCBB_CR_GLOCK_Msk /*!< lock the control register of the MPCBB until next reset */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30UL) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_INVSECSTATE GTZC_MPCBB_CR_INVSECSTATE_Msk /*!< SRAM clocks security state */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31UL) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_CR_SRWILADIS GTZC_MPCBB_CR_SRWILADIS_Msk /*!< secure read/write illegal access disable */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCK register ************/ +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Pos (0UL) +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK0 GTZC_MPCBB_CFGLOCK_SPLCK0_Msk /*!< Security/privilege configuration lock super-block 0 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Pos (1UL) +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1 GTZC_MPCBB_CFGLOCK_SPLCK1_Msk /*!< Security/privilege configuration lock super-block 1 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Pos (2UL) +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2 GTZC_MPCBB_CFGLOCK_SPLCK2_Msk /*!< Security/privilege configuration lock super-block 2 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Pos (3UL) +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3 GTZC_MPCBB_CFGLOCK_SPLCK3_Msk /*!< Security/privilege configuration lock super-block 3 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR0 register ************/ +#define GTZC_MPCBB_SECCFGR0_SEC0_Pos (0UL) +#define GTZC_MPCBB_SECCFGR0_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR0_SEC0 GTZC_MPCBB_SECCFGR0_SEC0_Msk /*!< Security configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC1_Pos (1UL) +#define GTZC_MPCBB_SECCFGR0_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR0_SEC1 GTZC_MPCBB_SECCFGR0_SEC1_Msk /*!< Security configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC2_Pos (2UL) +#define GTZC_MPCBB_SECCFGR0_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR0_SEC2 GTZC_MPCBB_SECCFGR0_SEC2_Msk /*!< Security configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC3_Pos (3UL) +#define GTZC_MPCBB_SECCFGR0_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR0_SEC3 GTZC_MPCBB_SECCFGR0_SEC3_Msk /*!< Security configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC4_Pos (4UL) +#define GTZC_MPCBB_SECCFGR0_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR0_SEC4 GTZC_MPCBB_SECCFGR0_SEC4_Msk /*!< Security configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC5_Pos (5UL) +#define GTZC_MPCBB_SECCFGR0_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR0_SEC5 GTZC_MPCBB_SECCFGR0_SEC5_Msk /*!< Security configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC6_Pos (6UL) +#define GTZC_MPCBB_SECCFGR0_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR0_SEC6 GTZC_MPCBB_SECCFGR0_SEC6_Msk /*!< Security configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC7_Pos (7UL) +#define GTZC_MPCBB_SECCFGR0_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR0_SEC7 GTZC_MPCBB_SECCFGR0_SEC7_Msk /*!< Security configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC8_Pos (8UL) +#define GTZC_MPCBB_SECCFGR0_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR0_SEC8 GTZC_MPCBB_SECCFGR0_SEC8_Msk /*!< Security configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC9_Pos (9UL) +#define GTZC_MPCBB_SECCFGR0_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR0_SEC9 GTZC_MPCBB_SECCFGR0_SEC9_Msk /*!< Security configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC10_Pos (10UL) +#define GTZC_MPCBB_SECCFGR0_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR0_SEC10 GTZC_MPCBB_SECCFGR0_SEC10_Msk /*!< Security configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC11_Pos (11UL) +#define GTZC_MPCBB_SECCFGR0_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR0_SEC11 GTZC_MPCBB_SECCFGR0_SEC11_Msk /*!< Security configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC12_Pos (12UL) +#define GTZC_MPCBB_SECCFGR0_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR0_SEC12 GTZC_MPCBB_SECCFGR0_SEC12_Msk /*!< Security configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC13_Pos (13UL) +#define GTZC_MPCBB_SECCFGR0_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR0_SEC13 GTZC_MPCBB_SECCFGR0_SEC13_Msk /*!< Security configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC14_Pos (14UL) +#define GTZC_MPCBB_SECCFGR0_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR0_SEC14 GTZC_MPCBB_SECCFGR0_SEC14_Msk /*!< Security configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC15_Pos (15UL) +#define GTZC_MPCBB_SECCFGR0_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR0_SEC15 GTZC_MPCBB_SECCFGR0_SEC15_Msk /*!< Security configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC16_Pos (16UL) +#define GTZC_MPCBB_SECCFGR0_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR0_SEC16 GTZC_MPCBB_SECCFGR0_SEC16_Msk /*!< Security configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC17_Pos (17UL) +#define GTZC_MPCBB_SECCFGR0_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR0_SEC17 GTZC_MPCBB_SECCFGR0_SEC17_Msk /*!< Security configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC18_Pos (18UL) +#define GTZC_MPCBB_SECCFGR0_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR0_SEC18 GTZC_MPCBB_SECCFGR0_SEC18_Msk /*!< Security configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC19_Pos (19UL) +#define GTZC_MPCBB_SECCFGR0_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR0_SEC19 GTZC_MPCBB_SECCFGR0_SEC19_Msk /*!< Security configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC20_Pos (20UL) +#define GTZC_MPCBB_SECCFGR0_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR0_SEC20 GTZC_MPCBB_SECCFGR0_SEC20_Msk /*!< Security configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC21_Pos (21UL) +#define GTZC_MPCBB_SECCFGR0_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR0_SEC21 GTZC_MPCBB_SECCFGR0_SEC21_Msk /*!< Security configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC22_Pos (22UL) +#define GTZC_MPCBB_SECCFGR0_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR0_SEC22 GTZC_MPCBB_SECCFGR0_SEC22_Msk /*!< Security configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC23_Pos (23UL) +#define GTZC_MPCBB_SECCFGR0_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR0_SEC23 GTZC_MPCBB_SECCFGR0_SEC23_Msk /*!< Security configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC24_Pos (24UL) +#define GTZC_MPCBB_SECCFGR0_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC24 GTZC_MPCBB_SECCFGR0_SEC24_Msk /*!< Security configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC25_Pos (25UL) +#define GTZC_MPCBB_SECCFGR0_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC25 GTZC_MPCBB_SECCFGR0_SEC25_Msk /*!< Security configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC26_Pos (26UL) +#define GTZC_MPCBB_SECCFGR0_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC26 GTZC_MPCBB_SECCFGR0_SEC26_Msk /*!< Security configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC27_Pos (27UL) +#define GTZC_MPCBB_SECCFGR0_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC27 GTZC_MPCBB_SECCFGR0_SEC27_Msk /*!< Security configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC28_Pos (28UL) +#define GTZC_MPCBB_SECCFGR0_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC28 GTZC_MPCBB_SECCFGR0_SEC28_Msk /*!< Security configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC29_Pos (29UL) +#define GTZC_MPCBB_SECCFGR0_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC29 GTZC_MPCBB_SECCFGR0_SEC29_Msk /*!< Security configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC30_Pos (30UL) +#define GTZC_MPCBB_SECCFGR0_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC30 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC31_Pos (31UL) +#define GTZC_MPCBB_SECCFGR0_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC31 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR1 register ************/ +#define GTZC_MPCBB_SECCFGR1_SEC0_Pos (0UL) +#define GTZC_MPCBB_SECCFGR1_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR1_SEC0 GTZC_MPCBB_SECCFGR1_SEC0_Msk /*!< Security configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC1_Pos (1UL) +#define GTZC_MPCBB_SECCFGR1_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR1_SEC1 GTZC_MPCBB_SECCFGR1_SEC1_Msk /*!< Security configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC2_Pos (2UL) +#define GTZC_MPCBB_SECCFGR1_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR1_SEC2 GTZC_MPCBB_SECCFGR1_SEC2_Msk /*!< Security configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC3_Pos (3UL) +#define GTZC_MPCBB_SECCFGR1_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR1_SEC3 GTZC_MPCBB_SECCFGR1_SEC3_Msk /*!< Security configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC4_Pos (4UL) +#define GTZC_MPCBB_SECCFGR1_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR1_SEC4 GTZC_MPCBB_SECCFGR1_SEC4_Msk /*!< Security configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC5_Pos (5UL) +#define GTZC_MPCBB_SECCFGR1_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR1_SEC5 GTZC_MPCBB_SECCFGR1_SEC5_Msk /*!< Security configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC6_Pos (6UL) +#define GTZC_MPCBB_SECCFGR1_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR1_SEC6 GTZC_MPCBB_SECCFGR1_SEC6_Msk /*!< Security configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC7_Pos (7UL) +#define GTZC_MPCBB_SECCFGR1_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR1_SEC7 GTZC_MPCBB_SECCFGR1_SEC7_Msk /*!< Security configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC8_Pos (8UL) +#define GTZC_MPCBB_SECCFGR1_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR1_SEC8 GTZC_MPCBB_SECCFGR1_SEC8_Msk /*!< Security configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC9_Pos (9UL) +#define GTZC_MPCBB_SECCFGR1_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR1_SEC9 GTZC_MPCBB_SECCFGR1_SEC9_Msk /*!< Security configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC10_Pos (10UL) +#define GTZC_MPCBB_SECCFGR1_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR1_SEC10 GTZC_MPCBB_SECCFGR1_SEC10_Msk /*!< Security configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC11_Pos (11UL) +#define GTZC_MPCBB_SECCFGR1_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR1_SEC11 GTZC_MPCBB_SECCFGR1_SEC11_Msk /*!< Security configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC12_Pos (12UL) +#define GTZC_MPCBB_SECCFGR1_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR1_SEC12 GTZC_MPCBB_SECCFGR1_SEC12_Msk /*!< Security configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC13_Pos (13UL) +#define GTZC_MPCBB_SECCFGR1_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR1_SEC13 GTZC_MPCBB_SECCFGR1_SEC13_Msk /*!< Security configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC14_Pos (14UL) +#define GTZC_MPCBB_SECCFGR1_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR1_SEC14 GTZC_MPCBB_SECCFGR1_SEC14_Msk /*!< Security configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC15_Pos (15UL) +#define GTZC_MPCBB_SECCFGR1_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR1_SEC15 GTZC_MPCBB_SECCFGR1_SEC15_Msk /*!< Security configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC16_Pos (16UL) +#define GTZC_MPCBB_SECCFGR1_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR1_SEC16 GTZC_MPCBB_SECCFGR1_SEC16_Msk /*!< Security configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC17_Pos (17UL) +#define GTZC_MPCBB_SECCFGR1_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR1_SEC17 GTZC_MPCBB_SECCFGR1_SEC17_Msk /*!< Security configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC18_Pos (18UL) +#define GTZC_MPCBB_SECCFGR1_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR1_SEC18 GTZC_MPCBB_SECCFGR1_SEC18_Msk /*!< Security configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC19_Pos (19UL) +#define GTZC_MPCBB_SECCFGR1_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR1_SEC19 GTZC_MPCBB_SECCFGR1_SEC19_Msk /*!< Security configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC20_Pos (20UL) +#define GTZC_MPCBB_SECCFGR1_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR1_SEC20 GTZC_MPCBB_SECCFGR1_SEC20_Msk /*!< Security configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC21_Pos (21UL) +#define GTZC_MPCBB_SECCFGR1_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR1_SEC21 GTZC_MPCBB_SECCFGR1_SEC21_Msk /*!< Security configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC22_Pos (22UL) +#define GTZC_MPCBB_SECCFGR1_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR1_SEC22 GTZC_MPCBB_SECCFGR1_SEC22_Msk /*!< Security configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC23_Pos (23UL) +#define GTZC_MPCBB_SECCFGR1_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR1_SEC23 GTZC_MPCBB_SECCFGR1_SEC23_Msk /*!< Security configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC24_Pos (24UL) +#define GTZC_MPCBB_SECCFGR1_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC24 GTZC_MPCBB_SECCFGR1_SEC24_Msk /*!< Security configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC25_Pos (25UL) +#define GTZC_MPCBB_SECCFGR1_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC25 GTZC_MPCBB_SECCFGR1_SEC25_Msk /*!< Security configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC26_Pos (26UL) +#define GTZC_MPCBB_SECCFGR1_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC26 GTZC_MPCBB_SECCFGR1_SEC26_Msk /*!< Security configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC27_Pos (27UL) +#define GTZC_MPCBB_SECCFGR1_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC27 GTZC_MPCBB_SECCFGR1_SEC27_Msk /*!< Security configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC28_Pos (28UL) +#define GTZC_MPCBB_SECCFGR1_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC28 GTZC_MPCBB_SECCFGR1_SEC28_Msk /*!< Security configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC29_Pos (29UL) +#define GTZC_MPCBB_SECCFGR1_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC29 GTZC_MPCBB_SECCFGR1_SEC29_Msk /*!< Security configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC30_Pos (30UL) +#define GTZC_MPCBB_SECCFGR1_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC30 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC31_Pos (31UL) +#define GTZC_MPCBB_SECCFGR1_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC31 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR2 register ************/ +#define GTZC_MPCBB_SECCFGR2_SEC0_Pos (0UL) +#define GTZC_MPCBB_SECCFGR2_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR2_SEC0 GTZC_MPCBB_SECCFGR2_SEC0_Msk /*!< Security configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC1_Pos (1UL) +#define GTZC_MPCBB_SECCFGR2_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR2_SEC1 GTZC_MPCBB_SECCFGR2_SEC1_Msk /*!< Security configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC2_Pos (2UL) +#define GTZC_MPCBB_SECCFGR2_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR2_SEC2 GTZC_MPCBB_SECCFGR2_SEC2_Msk /*!< Security configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC3_Pos (3UL) +#define GTZC_MPCBB_SECCFGR2_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR2_SEC3 GTZC_MPCBB_SECCFGR2_SEC3_Msk /*!< Security configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC4_Pos (4UL) +#define GTZC_MPCBB_SECCFGR2_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR2_SEC4 GTZC_MPCBB_SECCFGR2_SEC4_Msk /*!< Security configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC5_Pos (5UL) +#define GTZC_MPCBB_SECCFGR2_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR2_SEC5 GTZC_MPCBB_SECCFGR2_SEC5_Msk /*!< Security configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC6_Pos (6UL) +#define GTZC_MPCBB_SECCFGR2_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR2_SEC6 GTZC_MPCBB_SECCFGR2_SEC6_Msk /*!< Security configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC7_Pos (7UL) +#define GTZC_MPCBB_SECCFGR2_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR2_SEC7 GTZC_MPCBB_SECCFGR2_SEC7_Msk /*!< Security configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC8_Pos (8UL) +#define GTZC_MPCBB_SECCFGR2_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR2_SEC8 GTZC_MPCBB_SECCFGR2_SEC8_Msk /*!< Security configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC9_Pos (9UL) +#define GTZC_MPCBB_SECCFGR2_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR2_SEC9 GTZC_MPCBB_SECCFGR2_SEC9_Msk /*!< Security configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC10_Pos (10UL) +#define GTZC_MPCBB_SECCFGR2_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR2_SEC10 GTZC_MPCBB_SECCFGR2_SEC10_Msk /*!< Security configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC11_Pos (11UL) +#define GTZC_MPCBB_SECCFGR2_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR2_SEC11 GTZC_MPCBB_SECCFGR2_SEC11_Msk /*!< Security configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC12_Pos (12UL) +#define GTZC_MPCBB_SECCFGR2_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR2_SEC12 GTZC_MPCBB_SECCFGR2_SEC12_Msk /*!< Security configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC13_Pos (13UL) +#define GTZC_MPCBB_SECCFGR2_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR2_SEC13 GTZC_MPCBB_SECCFGR2_SEC13_Msk /*!< Security configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC14_Pos (14UL) +#define GTZC_MPCBB_SECCFGR2_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR2_SEC14 GTZC_MPCBB_SECCFGR2_SEC14_Msk /*!< Security configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC15_Pos (15UL) +#define GTZC_MPCBB_SECCFGR2_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR2_SEC15 GTZC_MPCBB_SECCFGR2_SEC15_Msk /*!< Security configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC16_Pos (16UL) +#define GTZC_MPCBB_SECCFGR2_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR2_SEC16 GTZC_MPCBB_SECCFGR2_SEC16_Msk /*!< Security configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC17_Pos (17UL) +#define GTZC_MPCBB_SECCFGR2_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR2_SEC17 GTZC_MPCBB_SECCFGR2_SEC17_Msk /*!< Security configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC18_Pos (18UL) +#define GTZC_MPCBB_SECCFGR2_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR2_SEC18 GTZC_MPCBB_SECCFGR2_SEC18_Msk /*!< Security configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC19_Pos (19UL) +#define GTZC_MPCBB_SECCFGR2_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR2_SEC19 GTZC_MPCBB_SECCFGR2_SEC19_Msk /*!< Security configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC20_Pos (20UL) +#define GTZC_MPCBB_SECCFGR2_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR2_SEC20 GTZC_MPCBB_SECCFGR2_SEC20_Msk /*!< Security configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC21_Pos (21UL) +#define GTZC_MPCBB_SECCFGR2_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR2_SEC21 GTZC_MPCBB_SECCFGR2_SEC21_Msk /*!< Security configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC22_Pos (22UL) +#define GTZC_MPCBB_SECCFGR2_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR2_SEC22 GTZC_MPCBB_SECCFGR2_SEC22_Msk /*!< Security configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC23_Pos (23UL) +#define GTZC_MPCBB_SECCFGR2_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR2_SEC23 GTZC_MPCBB_SECCFGR2_SEC23_Msk /*!< Security configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC24_Pos (24UL) +#define GTZC_MPCBB_SECCFGR2_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC24 GTZC_MPCBB_SECCFGR2_SEC24_Msk /*!< Security configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC25_Pos (25UL) +#define GTZC_MPCBB_SECCFGR2_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC25 GTZC_MPCBB_SECCFGR2_SEC25_Msk /*!< Security configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC26_Pos (26UL) +#define GTZC_MPCBB_SECCFGR2_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC26 GTZC_MPCBB_SECCFGR2_SEC26_Msk /*!< Security configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC27_Pos (27UL) +#define GTZC_MPCBB_SECCFGR2_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC27 GTZC_MPCBB_SECCFGR2_SEC27_Msk /*!< Security configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC28_Pos (28UL) +#define GTZC_MPCBB_SECCFGR2_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC28 GTZC_MPCBB_SECCFGR2_SEC28_Msk /*!< Security configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC29_Pos (29UL) +#define GTZC_MPCBB_SECCFGR2_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC29 GTZC_MPCBB_SECCFGR2_SEC29_Msk /*!< Security configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC30_Pos (30UL) +#define GTZC_MPCBB_SECCFGR2_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC30 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC31_Pos (31UL) +#define GTZC_MPCBB_SECCFGR2_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC31 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR3 register ************/ +#define GTZC_MPCBB_SECCFGR3_SEC0_Pos (0UL) +#define GTZC_MPCBB_SECCFGR3_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR3_SEC0 GTZC_MPCBB_SECCFGR3_SEC0_Msk /*!< Security configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC1_Pos (1UL) +#define GTZC_MPCBB_SECCFGR3_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR3_SEC1 GTZC_MPCBB_SECCFGR3_SEC1_Msk /*!< Security configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC2_Pos (2UL) +#define GTZC_MPCBB_SECCFGR3_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR3_SEC2 GTZC_MPCBB_SECCFGR3_SEC2_Msk /*!< Security configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC3_Pos (3UL) +#define GTZC_MPCBB_SECCFGR3_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR3_SEC3 GTZC_MPCBB_SECCFGR3_SEC3_Msk /*!< Security configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC4_Pos (4UL) +#define GTZC_MPCBB_SECCFGR3_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR3_SEC4 GTZC_MPCBB_SECCFGR3_SEC4_Msk /*!< Security configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC5_Pos (5UL) +#define GTZC_MPCBB_SECCFGR3_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR3_SEC5 GTZC_MPCBB_SECCFGR3_SEC5_Msk /*!< Security configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC6_Pos (6UL) +#define GTZC_MPCBB_SECCFGR3_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR3_SEC6 GTZC_MPCBB_SECCFGR3_SEC6_Msk /*!< Security configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC7_Pos (7UL) +#define GTZC_MPCBB_SECCFGR3_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR3_SEC7 GTZC_MPCBB_SECCFGR3_SEC7_Msk /*!< Security configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC8_Pos (8UL) +#define GTZC_MPCBB_SECCFGR3_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR3_SEC8 GTZC_MPCBB_SECCFGR3_SEC8_Msk /*!< Security configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC9_Pos (9UL) +#define GTZC_MPCBB_SECCFGR3_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR3_SEC9 GTZC_MPCBB_SECCFGR3_SEC9_Msk /*!< Security configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC10_Pos (10UL) +#define GTZC_MPCBB_SECCFGR3_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR3_SEC10 GTZC_MPCBB_SECCFGR3_SEC10_Msk /*!< Security configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC11_Pos (11UL) +#define GTZC_MPCBB_SECCFGR3_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR3_SEC11 GTZC_MPCBB_SECCFGR3_SEC11_Msk /*!< Security configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC12_Pos (12UL) +#define GTZC_MPCBB_SECCFGR3_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR3_SEC12 GTZC_MPCBB_SECCFGR3_SEC12_Msk /*!< Security configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC13_Pos (13UL) +#define GTZC_MPCBB_SECCFGR3_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR3_SEC13 GTZC_MPCBB_SECCFGR3_SEC13_Msk /*!< Security configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC14_Pos (14UL) +#define GTZC_MPCBB_SECCFGR3_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR3_SEC14 GTZC_MPCBB_SECCFGR3_SEC14_Msk /*!< Security configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC15_Pos (15UL) +#define GTZC_MPCBB_SECCFGR3_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR3_SEC15 GTZC_MPCBB_SECCFGR3_SEC15_Msk /*!< Security configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC16_Pos (16UL) +#define GTZC_MPCBB_SECCFGR3_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR3_SEC16 GTZC_MPCBB_SECCFGR3_SEC16_Msk /*!< Security configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC17_Pos (17UL) +#define GTZC_MPCBB_SECCFGR3_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR3_SEC17 GTZC_MPCBB_SECCFGR3_SEC17_Msk /*!< Security configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC18_Pos (18UL) +#define GTZC_MPCBB_SECCFGR3_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR3_SEC18 GTZC_MPCBB_SECCFGR3_SEC18_Msk /*!< Security configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC19_Pos (19UL) +#define GTZC_MPCBB_SECCFGR3_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR3_SEC19 GTZC_MPCBB_SECCFGR3_SEC19_Msk /*!< Security configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC20_Pos (20UL) +#define GTZC_MPCBB_SECCFGR3_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR3_SEC20 GTZC_MPCBB_SECCFGR3_SEC20_Msk /*!< Security configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC21_Pos (21UL) +#define GTZC_MPCBB_SECCFGR3_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR3_SEC21 GTZC_MPCBB_SECCFGR3_SEC21_Msk /*!< Security configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC22_Pos (22UL) +#define GTZC_MPCBB_SECCFGR3_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR3_SEC22 GTZC_MPCBB_SECCFGR3_SEC22_Msk /*!< Security configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC23_Pos (23UL) +#define GTZC_MPCBB_SECCFGR3_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR3_SEC23 GTZC_MPCBB_SECCFGR3_SEC23_Msk /*!< Security configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC24_Pos (24UL) +#define GTZC_MPCBB_SECCFGR3_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC24 GTZC_MPCBB_SECCFGR3_SEC24_Msk /*!< Security configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC25_Pos (25UL) +#define GTZC_MPCBB_SECCFGR3_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC25 GTZC_MPCBB_SECCFGR3_SEC25_Msk /*!< Security configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC26_Pos (26UL) +#define GTZC_MPCBB_SECCFGR3_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC26 GTZC_MPCBB_SECCFGR3_SEC26_Msk /*!< Security configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC27_Pos (27UL) +#define GTZC_MPCBB_SECCFGR3_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC27 GTZC_MPCBB_SECCFGR3_SEC27_Msk /*!< Security configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC28_Pos (28UL) +#define GTZC_MPCBB_SECCFGR3_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC28 GTZC_MPCBB_SECCFGR3_SEC28_Msk /*!< Security configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC29_Pos (29UL) +#define GTZC_MPCBB_SECCFGR3_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC29 GTZC_MPCBB_SECCFGR3_SEC29_Msk /*!< Security configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC30_Pos (30UL) +#define GTZC_MPCBB_SECCFGR3_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC30 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC31_Pos (31UL) +#define GTZC_MPCBB_SECCFGR3_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC31 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 31 in super block 3 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR0 register ************/ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos (0UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0 GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos (1UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1 GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos (2UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2 GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos (3UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3 GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos (4UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4 GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos (5UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5 GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos (6UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6 GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos (7UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7 GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos (8UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8 GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos (9UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9 GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos (10UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10 GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos (11UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11 GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos (12UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12 GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos (13UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13 GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos (14UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14 GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos (15UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15 GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos (16UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16 GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos (17UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17 GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos (18UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18 GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos (19UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19 GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos (20UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20 GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos (21UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21 GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos (22UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22 GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos (23UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23 GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos (24UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24 GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos (25UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25 GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos (26UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26 GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos (27UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27 GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos (28UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28 GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos (29UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29 GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos (30UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos (31UL) +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR1 register ************/ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos (0UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0 GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos (1UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1 GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos (2UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2 GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos (3UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3 GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos (4UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4 GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos (5UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5 GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos (6UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6 GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos (7UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7 GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos (8UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8 GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos (9UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9 GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos (10UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10 GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos (11UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11 GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos (12UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12 GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos (13UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13 GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos (14UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14 GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos (15UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15 GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos (16UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16 GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos (17UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17 GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos (18UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18 GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos (19UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19 GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos (20UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20 GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos (21UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21 GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos (22UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22 GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos (23UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23 GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos (24UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24 GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos (25UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25 GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos (26UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26 GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos (27UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27 GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos (28UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28 GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos (29UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29 GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos (30UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos (31UL) +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR2 register ************/ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos (0UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0 GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos (1UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1 GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos (2UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2 GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos (3UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3 GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos (4UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4 GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos (5UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5 GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos (6UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6 GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos (7UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7 GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos (8UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8 GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos (9UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9 GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos (10UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10 GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos (11UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11 GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos (12UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12 GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos (13UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13 GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos (14UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14 GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos (15UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15 GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos (16UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16 GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos (17UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17 GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos (18UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18 GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos (19UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19 GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos (20UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20 GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos (21UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21 GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos (22UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22 GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos (23UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23 GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos (24UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24 GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos (25UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25 GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos (26UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26 GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos (27UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27 GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos (28UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28 GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos (29UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29 GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos (30UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos (31UL) +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR3 register ************/ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos (0UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0 GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos (1UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1 GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos (2UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2 GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos (3UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3 GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos (4UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4 GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos (5UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5 GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos (6UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6 GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos (7UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7 GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos (8UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8 GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos (9UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9 GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos (10UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10 GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos (11UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11 GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos (12UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12 GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos (13UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13 GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos (14UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14 GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos (15UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15 GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos (16UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16 GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos (17UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17 GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos (18UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18 GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos (19UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19 GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos (20UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20 GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos (21UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21 GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos (22UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22 GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos (23UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23 GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos (24UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24 GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos (25UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25 GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos (26UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26 GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos (27UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27 GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos (28UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28 GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos (29UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29 GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos (30UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos (31UL) +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 3 */ + + +/******************************************************************************/ +/* */ +/* HASH */ +/* */ +/******************************************************************************/ +/****************** Bits definition for HASH_CR register ********************/ +#define HASH_CR_INIT_Pos (2UL) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk +#define HASH_CR_DMAE_Pos (3UL) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk +#define HASH_CR_DATATYPE_Pos (4UL) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6UL) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk +#define HASH_CR_NBW_Pos (8UL) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12UL) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk +#define HASH_CR_MDMAT_Pos (13UL) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk +#define HASH_CR_LKEY_Pos (16UL) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk +#define HASH_CR_ALGO_Pos (17UL) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/****************** Bits definition for HASH_STR register *******************/ +#define HASH_STR_NBLW_Pos (0UL) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk +#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8UL) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk + +/****************** Bits definition for HASH_IMR register *******************/ +#define HASH_IMR_DINIE_Pos (0UL) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk +#define HASH_IMR_DCIE_Pos (1UL) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk + +/****************** Bits definition for HASH_SR register ********************/ +#define HASH_SR_DINIS_Pos (0UL) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk +#define HASH_SR_DCIS_Pos (1UL) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk +#define HASH_SR_DMAS_Pos (2UL) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk +#define HASH_SR_BUSY_Pos (3UL) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk +#define HASH_SR_NBWE_Pos (16UL) +#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk +#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_DINNE_Pos (15UL) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk +#define HASH_SR_NBWP_Pos (9UL) +#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk +#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ +#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ + + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0UL) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* PTA Converter */ +/* */ +/******************************************************************************/ +/****************** Bit definition for PTACONV_ACTCR register ***************/ +#define PTACONV_ACTCR_TACTIVE_Pos (0UL) +#define PTACONV_ACTCR_TACTIVE_Msk (0xFFUL << PTACONV_ACTCR_TACTIVE_Pos) /*!< 0x000000FF */ +#define PTACONV_ACTCR_TACTIVE PTACONV_ACTCR_TACTIVE_Msk /*!< PTA_ACTIVE setup time in us */ +#define PTACONV_ACTCR_ACTPOL_Pos (15UL) +#define PTACONV_ACTCR_ACTPOL_Msk (0x1UL << PTACONV_ACTCR_ACTPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_ACTCR_ACTPOL PTACONV_ACTCR_ACTPOL_Msk /*!< PTA_ACTIVE polarity */ +#define PTACONV_ACTCR_TABORT_Pos (16UL) +#define PTACONV_ACTCR_TABORT_Msk (0xFUL << PTACONV_ACTCR_TABORT_Pos) /*!< 0x000F0000 */ +#define PTACONV_ACTCR_TABORT PTACONV_ACTCR_TABORT_Msk /*!< PTA_ACTIVE delay to cease an ongoing transmission in us */ +#define PTACONV_ACTCR_ABORTDIS_Pos (20UL) +#define PTACONV_ACTCR_ABORTDIS_Msk (0x1UL << PTACONV_ACTCR_ABORTDIS_Pos) /*!< 0x00100000 */ +#define PTACONV_ACTCR_ABORTDIS PTACONV_ACTCR_ABORTDIS_Msk /*!< Disable PTA_ACTIVE deny to abort an ongoing transmission */ + +/****************** Bit definition for PTACONV_PRICR register ***************/ +#define PTACONV_PRICR_TPRIORITY_Pos (0UL) +#define PTACONV_PRICR_TPRIORITY_Msk (0x1FUL << PTACONV_PRICR_TPRIORITY_Pos) /*!< 0x0000001F */ +#define PTACONV_PRICR_TPRIORITY PTACONV_PRICR_TPRIORITY_Msk /*!< Priority valid time in us */ +#define PTACONV_PRICR_PRIPOL_Pos (15UL) +#define PTACONV_PRICR_PRIPOL_Msk (0x1UL << PTACONV_PRICR_PRIPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_PRICR_PRIPOL PTACONV_PRICR_PRIPOL_Msk /*!< Priority polarity */ + +/****************** Bit definition for PTACONV_CR register ******************/ +#define PTACONV_CR_TXRXPOL_Pos (15UL) +#define PTACONV_CR_TXRXPOL_Msk (0x1UL << PTACONV_CR_TXRXPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_CR_TXRXPOL PTACONV_CR_TXRXPOL_Msk /*!< PTA_STATUS transmit and receive polarity */ +#define PTACONV_CR_GRANTPOL_Pos (31UL) +#define PTACONV_CR_GRANTPOL_Msk (0x1UL << PTACONV_CR_GRANTPOL_Pos) /*!< 0x80000000 */ +#define PTACONV_CR_GRANTPOL PTACONV_CR_GRANTPOL_Msk /*!< PTA_GRANT polarity */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +#define PWR_STOP2_SUPPORT +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_LPMS_Pos (0UL) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection field */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ +#define PWR_CR1_R2RSB1_Pos (5UL) +#define PWR_CR1_R2RSB1_Msk (0x1UL << PWR_CR1_R2RSB1_Pos) /*!< 0x00000020 */ +#define PWR_CR1_R2RSB1 PWR_CR1_R2RSB1_Msk /*!< SRAM2 Retention in Standby */ +#define PWR_CR1_ULPMEN_Pos (7UL) +#define PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) /*!< 0x00000080 */ +#define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-low power mode in Standby/Shutdown */ +#define PWR_CR1_RADIORSB_Pos (9UL) +#define PWR_CR1_RADIORSB_Msk (0x1UL << PWR_CR1_RADIORSB_Pos) /*!< 0x00000200 */ +#define PWR_CR1_RADIORSB PWR_CR1_RADIORSB_Msk /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ +#define PWR_CR1_R1RSB567_Pos (11UL) +#define PWR_CR1_R1RSB567_Msk (0x1UL << PWR_CR1_R1RSB567_Pos) /*!< 0x00000800 */ +#define PWR_CR1_R1RSB567 PWR_CR1_R1RSB567_Msk /*!< SRAM1 Pages 5-6-7 Retention in Standby */ +#define PWR_CR1_R1RSB1_Pos (12UL) +#define PWR_CR1_R1RSB1_Msk (0x1UL << PWR_CR1_R1RSB1_Pos) /*!< 0x00001000 */ +#define PWR_CR1_R1RSB1 PWR_CR1_R1RSB1_Msk /*!< SRAM1 Page 1 Retention in Standby */ +#define PWR_CR1_R1RSB2_Pos (13UL) +#define PWR_CR1_R1RSB2_Msk (0x1UL << PWR_CR1_R1RSB2_Pos) /*!< 0x00002000 */ +#define PWR_CR1_R1RSB2 PWR_CR1_R1RSB2_Msk /*!< SRAM1 Page 2 Retention in Standby */ +#define PWR_CR1_R1RSB3_Pos (14UL) +#define PWR_CR1_R1RSB3_Msk (0x1UL << PWR_CR1_R1RSB3_Pos) /*!< 0x00004000 */ +#define PWR_CR1_R1RSB3 PWR_CR1_R1RSB3_Msk /*!< SRAM1 Page 3 Retention in Standby */ +#define PWR_CR1_R1RSB4_Pos (15UL) +#define PWR_CR1_R1RSB4_Msk (0x1UL << PWR_CR1_R1RSB4_Pos) /*!< 0x00008000 */ +#define PWR_CR1_R1RSB4 PWR_CR1_R1RSB4_Msk /*!< SRAM1 Page 4 Retention in Standby */ + +/******************** Bit definition for PWR_CR2 register *******************/ +#define PWR_CR2_SRAM1PDS1_Pos (0UL) +#define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ +#define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 Page 1 power-down in Stop modes */ +#define PWR_CR2_SRAM1PDS2_Pos (1UL) +#define PWR_CR2_SRAM1PDS2_Msk (0x1UL << PWR_CR2_SRAM1PDS2_Pos) /*!< 0x00000002 */ +#define PWR_CR2_SRAM1PDS2 PWR_CR2_SRAM1PDS2_Msk /*!< SRAM1 Page 2 power-down in Stop modes */ +#define PWR_CR2_SRAM1PDS3_Pos (2UL) +#define PWR_CR2_SRAM1PDS3_Msk (0x1UL << PWR_CR2_SRAM1PDS3_Pos) /*!< 0x00000004 */ +#define PWR_CR2_SRAM1PDS3 PWR_CR2_SRAM1PDS3_Msk /*!< SRAM1 Page 3 power-down in Stop modes */ +#define PWR_CR2_SRAM1PDS4_Pos (3UL) +#define PWR_CR2_SRAM1PDS4_Msk (0x1UL << PWR_CR2_SRAM1PDS4_Pos) /*!< 0x00000008 */ +#define PWR_CR2_SRAM1PDS4 PWR_CR2_SRAM1PDS4_Msk /*!< SRAM1 Page 4 power-down in Stop modes */ +#define PWR_CR2_SRAM2PDS1_Pos (4UL) +#define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010 */ +#define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 power-down in Stop modes */ +#define PWR_CR2_SRAM1PDS567_Pos (6UL) +#define PWR_CR2_SRAM1PDS567_Msk (0x1UL << PWR_CR2_SRAM1PDS567_Pos) /*!< 0x00000040 */ +#define PWR_CR2_SRAM1PDS567 PWR_CR2_SRAM1PDS567_Msk /*!< SRAM1 Page 5-6-7 power-down in Stop modes */ +#define PWR_CR2_ICRAMPDS_Pos (8UL) +#define PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) /*!< 0x00000100 */ +#define PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes */ +#define PWR_CR2_PRAMPDS_Pos (11UL) +#define PWR_CR2_PRAMPDS_Msk (0x1UL << PWR_CR2_PRAMPDS_Pos) /*!< 0x00000800 */ +#define PWR_CR2_PRAMPDS PWR_CR2_PRAMPDS_Msk /*!< USB OTG_HS SRAM power-down in Stop modes */ +#define PWR_CR2_PKARAMPDS_Pos (12UL) +#define PWR_CR2_PKARAMPDS_Msk (0x1UL << PWR_CR2_PKARAMPDS_Pos) /*!< 0x00001000 */ +#define PWR_CR2_PKARAMPDS PWR_CR2_PKARAMPDS_Msk /*!< PKA SRAM power-down in Stop modes */ +#define PWR_CR2_FLASHFWU_Pos (14UL) +#define PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) /*!< 0x00004000 */ +#define PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk /*!< Flash low-power mode in Stop modes */ +#define PWR_CR2_FPWM_Pos (30UL) +#define PWR_CR2_FPWM_Msk (0x1UL << PWR_CR2_FPWM_Pos) /*!< 0x40000000 */ +#define PWR_CR2_FPWM PWR_CR2_FPWM_Msk /*!< SMPS PWM mode */ + +/******************** Bit definition for PWR_CR3 register *******************/ +#define PWR_CR3_REGSEL_Pos (1UL) +#define PWR_CR3_REGSEL_Msk (0x1UL << PWR_CR3_REGSEL_Pos) /*!< 0x00000002 */ +#define PWR_CR3_REGSEL PWR_CR3_REGSEL_Msk /*!< Regulator selection */ +#define PWR_CR3_FSTEN_Pos (2UL) +#define PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) /*!< 0x00000004 */ +#define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft start */ + +/******************* Bit definition for PWR_VOSR register *******************/ +#define PWR_VOSR_VDD11USBRDY_Pos (12UL) +#define PWR_VOSR_VDD11USBRDY_Msk (0x1UL << PWR_VOSR_VDD11USBRDY_Pos) /*!< 0x00001000 */ +#define PWR_VOSR_VDD11USBRDY PWR_VOSR_VDD11USBRDY_Msk /*!< USB OTG_HS VDD11 ready */ +#define PWR_VOSR_USBBOOSTRDY_Pos (13UL) +#define PWR_VOSR_USBBOOSTRDY_Msk (0x1UL << PWR_VOSR_USBBOOSTRDY_Pos) /*!< 0x00002000 */ +#define PWR_VOSR_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY_Msk /*!< USB OTG_HS booster ready */ +#define PWR_VOSR_VOSRDY_Pos (15UL) +#define PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk /*!< Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSR_VOS_Pos (16UL) +#define PWR_VOSR_VOS_Msk (0x1UL << PWR_VOSR_VOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSR_VOS PWR_VOSR_VOS_Msk /*!< Voltage scaling range selection */ +#define PWR_VOSR_USBPWREN_Pos (19UL) +#define PWR_VOSR_USBPWREN_Msk (0x1UL << PWR_VOSR_USBPWREN_Pos) /*!< 0x00080000 */ +#define PWR_VOSR_USBPWREN PWR_VOSR_USBPWREN_Msk /*!< USB OTG_HS power enable */ +#define PWR_VOSR_USBBOOSTEN_Pos (20UL) +#define PWR_VOSR_USBBOOSTEN_Msk (0x1UL << PWR_VOSR_USBBOOSTEN_Pos) /*!< 0x00100000 */ +#define PWR_VOSR_USBBOOSTEN PWR_VOSR_USBBOOSTEN_Msk /*!< USB OTG_HS booster enable */ +#define PWR_VOSR_VDD11USBDIS_Pos (21UL) +#define PWR_VOSR_VDD11USBDIS_Msk (0x1UL << PWR_VOSR_VDD11USBDIS_Pos) /*!< 0x00200000 */ +#define PWR_VOSR_VDD11USBDIS PWR_VOSR_VDD11USBDIS_Msk /*!< USB OTG_HS VDD11USB disable */ +#define PWR_VOSR_VDD11USBSWDLY_Pos (22UL) +#define PWR_VOSR_VDD11USBSWDLY_Msk (0x3FFUL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0xFFC00000 */ +#define PWR_VOSR_VDD11USBSWDLY PWR_VOSR_VDD11USBSWDLY_Msk /*!< VDD11USBSWDLY[9:0] USB OTG_HS VDD11USB switch delay */ +#define PWR_VOSR_VDD11USBSWDLY_0 (0x1UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x00400000 */ +#define PWR_VOSR_VDD11USBSWDLY_1 (0x2UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x00800000 */ +#define PWR_VOSR_VDD11USBSWDLY_2 (0x4UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x01000000 */ +#define PWR_VOSR_VDD11USBSWDLY_3 (0x8UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x02000000 */ +#define PWR_VOSR_VDD11USBSWDLY_4 (0x10UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x04000000 */ +#define PWR_VOSR_VDD11USBSWDLY_5 (0x20UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x08000000 */ +#define PWR_VOSR_VDD11USBSWDLY_6 (0x40UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x10000000 */ +#define PWR_VOSR_VDD11USBSWDLY_7 (0x80UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x20000000 */ +#define PWR_VOSR_VDD11USBSWDLY_8 (0x100UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x80000000 */ +#define PWR_VOSR_VDD11USBSWDLY_9 (0x200UL << PWR_VOSR_VDD11USBSWDLY_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for PWR_SVMCR register ******************/ +#define PWR_SVMCR_PVDE_Pos (4UL) +#define PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk /*!< Power voltage detector enable */ +#define PWR_SVMCR_PVDLS_Pos (5UL) +#define PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x000000E0 */ +#define PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk /*!< PVDLS[2:0] Power voltage detector level selection field */ +#define PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000020 */ +#define PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000040 */ +#define PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000080 */ +#define PWR_SVMCR_USV_Pos (28UL) +#define PWR_SVMCR_USV_Msk (0x1UL << PWR_SVMCR_USV_Pos) /*!< 0x10000000 */ +#define PWR_SVMCR_USV PWR_SVMCR_USV_Msk /*!< VDDUSB supply valid */ +#define PWR_SVMCR_IO2SV_Pos (29UL) +#define PWR_SVMCR_IO2SV_Msk (0x1UL << PWR_SVMCR_IO2SV_Pos) /*!< 0x20000000 */ +#define PWR_SVMCR_IO2SV PWR_SVMCR_IO2SV_Msk /*!< VDDIO2 supply valid */ + +/******************* Bit definition for PWR_WUCR1 register ******************/ +#define PWR_WUCR1_WUPEN1_Pos (0UL) +#define PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk /*!< Wakeup pin WKUP1 enable */ +#define PWR_WUCR1_WUPEN2_Pos (1UL) +#define PWR_WUCR1_WUPEN2_Msk (0x1UL << PWR_WUCR1_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR1_WUPEN2 PWR_WUCR1_WUPEN2_Msk /*!< Wakeup pin WKUP2 enable */ +#define PWR_WUCR1_WUPEN3_Pos (2UL) +#define PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk /*!< Wakeup pin WKUP3 enable */ +#define PWR_WUCR1_WUPEN4_Pos (3UL) +#define PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk /*!< Wakeup pin WKUP4 enable */ +#define PWR_WUCR1_WUPEN5_Pos (4UL) +#define PWR_WUCR1_WUPEN5_Msk (0x1UL << PWR_WUCR1_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR1_WUPEN5 PWR_WUCR1_WUPEN5_Msk /*!< Wakeup pin WKUP5 enable */ +#define PWR_WUCR1_WUPEN6_Pos (5UL) +#define PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk /*!< Wakeup pin WKUP6 enable */ +#define PWR_WUCR1_WUPEN7_Pos (6UL) +#define PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk /*!< Wakeup pin WKUP7 enable */ +#define PWR_WUCR1_WUPEN8_Pos (7UL) +#define PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk /*!< Wakeup pin WKUP8 enable */ + +/******************* Bit definition for PWR_WUCR2 register ******************/ +#define PWR_WUCR2_WUPP1_Pos (0UL) +#define PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk /*!< Wakeup pin WKUP1 polarity */ +#define PWR_WUCR2_WUPP2_Pos (1UL) +#define PWR_WUCR2_WUPP2_Msk (0x1UL << PWR_WUCR2_WUPP2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR2_WUPP2 PWR_WUCR2_WUPP2_Msk /*!< Wakeup pin WKUP2 polarity */ +#define PWR_WUCR2_WUPP3_Pos (2UL) +#define PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk /*!< Wakeup pin WKUP3 polarity */ +#define PWR_WUCR2_WUPP4_Pos (3UL) +#define PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk /*!< Wakeup pin WKUP4 polarity */ +#define PWR_WUCR2_WUPP5_Pos (4UL) +#define PWR_WUCR2_WUPP5_Msk (0x1UL << PWR_WUCR2_WUPP5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR2_WUPP5 PWR_WUCR2_WUPP5_Msk /*!< Wakeup pin WKUP5 polarity */ +#define PWR_WUCR2_WUPP6_Pos (5UL) +#define PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk /*!< Wakeup pin WKUP6 polarity */ +#define PWR_WUCR2_WUPP7_Pos (6UL) +#define PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk /*!< Wakeup pin WKUP7 polarity */ +#define PWR_WUCR2_WUPP8_Pos (7UL) +#define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup pin WKUP8 polarity */ + +/******************* Bit definition for PWR_WUCR3 register ******************/ +#define PWR_WUCR3_WUSEL1_Pos (0UL) +#define PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000003 */ +#define PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk /*!< Wakeup pin WKUP1 selection field */ +#define PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000002 */ +#define PWR_WUCR3_WUSEL2_Pos (2UL) +#define PWR_WUCR3_WUSEL2_Msk (0x3UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x0000000C */ +#define PWR_WUCR3_WUSEL2 PWR_WUCR3_WUSEL2_Msk /*!< Wakeup pin WKUP2 selection field */ +#define PWR_WUCR3_WUSEL2_0 (0x1UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000004 */ +#define PWR_WUCR3_WUSEL2_1 (0x2UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000008 */ +#define PWR_WUCR3_WUSEL3_Pos (4UL) +#define PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000030 */ +#define PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk /*!< Wakeup pin WKUP3 selection field */ +#define PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000010 */ +#define PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000020 */ +#define PWR_WUCR3_WUSEL4_Pos (6UL) +#define PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x000000C0 */ +#define PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk /*!< Wakeup pin WKUP4 selection field */ +#define PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000040 */ +#define PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000080 */ +#define PWR_WUCR3_WUSEL5_Pos (8UL) +#define PWR_WUCR3_WUSEL5_Msk (0x3UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000300 */ +#define PWR_WUCR3_WUSEL5 PWR_WUCR3_WUSEL5_Msk /*!< Wakeup pin WKUP5 selection field */ +#define PWR_WUCR3_WUSEL5_0 (0x1UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000100 */ +#define PWR_WUCR3_WUSEL5_1 (0x2UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000200 */ +#define PWR_WUCR3_WUSEL6_Pos (10UL) +#define PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000C00 */ +#define PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk /*!< Wakeup pin WKUP6 selection field */ +#define PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000400 */ +#define PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000800 */ +#define PWR_WUCR3_WUSEL7_Pos (12UL) +#define PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00003000 */ +#define PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk /*!< Wakeup pin WKUP7 selection field */ +#define PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00001000 */ +#define PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00002000 */ +#define PWR_WUCR3_WUSEL8_Pos (14UL) +#define PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x0000C000 */ +#define PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk /*!< Wakeup pin WKUP8 selection field */ +#define PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00004000 */ +#define PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_DBPR register ******************/ +#define PWR_DBPR_DBP_Pos (0UL) +#define PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPR_DBP PWR_DBPR_DBP_Msk /*!< Disable backup domain write protection */ + +/******************* Bit definition for PWR_SECCFGR register ****************/ +#define PWR_SECCFGR_WUP1SEC_Pos (0UL) +#define PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk /*!< WUP1 secure protection */ +#define PWR_SECCFGR_WUP2SEC_Pos (1UL) +#define PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk /*!< WUP2 secure protection */ +#define PWR_SECCFGR_WUP3SEC_Pos (2UL) +#define PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk /*!< WUP3 secure protection */ +#define PWR_SECCFGR_WUP4SEC_Pos (3UL) +#define PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk /*!< WUP4 secure protection */ +#define PWR_SECCFGR_WUP5SEC_Pos (4UL) +#define PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk /*!< WUP5 secure protection */ +#define PWR_SECCFGR_WUP6SEC_Pos (5UL) +#define PWR_SECCFGR_WUP6SEC_Msk (0x1UL << PWR_SECCFGR_WUP6SEC_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_WUP6SEC PWR_SECCFGR_WUP6SEC_Msk /*!< WUP6 secure protection */ +#define PWR_SECCFGR_WUP7SEC_Pos (6UL) +#define PWR_SECCFGR_WUP7SEC_Msk (0x1UL << PWR_SECCFGR_WUP7SEC_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_WUP7SEC PWR_SECCFGR_WUP7SEC_Msk /*!< WUP7 secure protection */ +#define PWR_SECCFGR_WUP8SEC_Pos (7UL) +#define PWR_SECCFGR_WUP8SEC_Msk (0x1UL << PWR_SECCFGR_WUP8SEC_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_WUP8SEC PWR_SECCFGR_WUP8SEC_Msk /*!< WUP8 secure protection */ +#define PWR_SECCFGR_LPMSEC_Pos (12UL) +#define PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) /*!< 0x00001000 */ +#define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power modes secure protection */ +#define PWR_SECCFGR_VDMSEC_Pos (13UL) +#define PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) /*!< 0x00002000 */ +#define PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk /*!< Voltage detection and monitoring secure protection */ +#define PWR_SECCFGR_VBSEC_Pos (14UL) +#define PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) /*!< 0x00004000 */ +#define PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk /*!< Backup domain secure protection */ + +/******************* Bit definition for PWR_PRIVCFGR register ***************/ +#define PWR_PRIVCFGR_SPRIV_Pos (0UL) +#define PWR_PRIVCFGR_SPRIV_Msk (0x1UL << PWR_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_SPRIV PWR_PRIVCFGR_SPRIV_Msk /*!< RCC secure functions privilege configuration */ +#define PWR_PRIVCFGR_NSPRIV_Pos (1UL) +#define PWR_PRIVCFGR_NSPRIV_Msk (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-secure functions privilege configuration */ + +/********************** Bit definition for PWR_SR register ******************/ +#define PWR_SR_CSSF_Pos (0UL) +#define PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) /*!< 0x00000001 */ +#define PWR_SR_CSSF PWR_SR_CSSF_Msk /*!< Clear Stop and Standby/Shutdown flags */ +#define PWR_SR_STOPF_Pos (1UL) +#define PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) /*!< 0x00000002 */ +#define PWR_SR_STOPF PWR_SR_STOPF_Msk /*!< Stop flag */ +#define PWR_SR_SBF_Pos (2UL) +#define PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) /*!< 0x00000004 */ +#define PWR_SR_SBF PWR_SR_SBF_Msk /*!< Standby/Shutdown flag */ +#define PWR_SR_STOP2F_Pos (3UL) +#define PWR_SR_STOP2F_Msk (0x1UL << PWR_SR_STOP2F_Pos) /*!< 0x00000008 */ +#define PWR_SR_STOP2F PWR_SR_STOP2F_Msk /*!< Stop 2 flag */ + +/******************** Bit definition for PWR_SVMSR register *****************/ +#define PWR_SVMSR_REGS_Pos (1UL) +#define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002 */ +#define PWR_SVMSR_REGS PWR_SVMSR_REGS_Msk /*!< Regulator status */ +#define PWR_SVMSR_PVDO_Pos (4UL) +#define PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk /*!< VDD voltage detector output */ +#define PWR_SVMSR_ACTVOSRDY_Pos (15UL) +#define PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk /*!< Voltage level ready for currently used VOS */ +#define PWR_SVMSR_ACTVOS_Pos (16UL) +#define PWR_SVMSR_ACTVOS_Msk (0x1UL << PWR_SVMSR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk /*!< Voltage Output Scaling currently applied to VCORE */ + +/********************* Bit definition for PWR_WUSR register *****************/ +#define PWR_WUSR_WUF1_Pos (0UL) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< Wakeup flag 1 */ +#define PWR_WUSR_WUF2_Pos (1UL) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< Wakeup flag 2 */ +#define PWR_WUSR_WUF3_Pos (2UL) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< Wakeup flag 3 */ +#define PWR_WUSR_WUF4_Pos (3UL) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< Wakeup flag 4 */ +#define PWR_WUSR_WUF5_Pos (4UL) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< Wakeup flag 5 */ +#define PWR_WUSR_WUF6_Pos (5UL) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< Wakeup flag 6 */ +#define PWR_WUSR_WUF7_Pos (6UL) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< Wakeup flag 7 */ +#define PWR_WUSR_WUF8_Pos (7UL) +#define PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk /*!< Wakeup flag 8 */ +#define PWR_WUSR_WUF_Pos (0UL) +#define PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) /*!< 0x000000FF */ +#define PWR_WUSR_WUF PWR_WUSR_WUF_Msk /*!< all Wakeup flag */ + +/********************* Bit definition for PWR_WUSCR register ****************/ +#define PWR_WUSCR_CWUF1_Pos (0UL) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001*/ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< Wakeup clear flag 1 */ +#define PWR_WUSCR_CWUF2_Pos (1UL) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< Wakeup clear flag 2 */ +#define PWR_WUSCR_CWUF3_Pos (2UL) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< Wakeup clear flag 3 */ +#define PWR_WUSCR_CWUF4_Pos (3UL) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< Wakeup clear flag 4 */ +#define PWR_WUSCR_CWUF5_Pos (4UL) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< Wakeup clear flag 5 */ +#define PWR_WUSCR_CWUF6_Pos (5UL) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< Wakeup clear flag 6 */ +#define PWR_WUSCR_CWUF7_Pos (6UL) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< Wakeup clear flag 7 */ +#define PWR_WUSCR_CWUF8_Pos (7UL) +#define PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk /*!< Wakeup clear flag 8 */ +#define PWR_WUSCR_CWUF_Pos (0UL) +#define PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF1_Pos) /*!< 0x000000FF */ +#define PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk /*!< all Wakeup clear flag */ + +/******************** Bit definition for PWR_IORETENRA register *****************/ +#define PWR_IORETENRA_EN0_Pos (0UL) +#define PWR_IORETENRA_EN0_Msk (0x1UL << PWR_IORETENRA_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRA_EN0 PWR_IORETENRA_EN0_Msk /*!< Standby GPIO retention enable for PA0 */ +#define PWR_IORETENRA_EN1_Pos (1UL) +#define PWR_IORETENRA_EN1_Msk (0x1UL << PWR_IORETENRA_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRA_EN1 PWR_IORETENRA_EN1_Msk /*!< Standby GPIO retention enable for PA1 */ +#define PWR_IORETENRA_EN2_Pos (2UL) +#define PWR_IORETENRA_EN2_Msk (0x1UL << PWR_IORETENRA_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRA_EN2 PWR_IORETENRA_EN2_Msk /*!< Standby GPIO retention enable for PA2 */ +#define PWR_IORETENRA_EN3_Pos (3UL) +#define PWR_IORETENRA_EN3_Msk (0x1UL << PWR_IORETENRA_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRA_EN3 PWR_IORETENRA_EN3_Msk /*!< Standby GPIO retention enable for PA3 */ +#define PWR_IORETENRA_EN4_Pos (4UL) +#define PWR_IORETENRA_EN4_Msk (0x1UL << PWR_IORETENRA_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRA_EN4 PWR_IORETENRA_EN4_Msk /*!< Standby GPIO retention enable for PA4 */ +#define PWR_IORETENRA_EN5_Pos (5UL) +#define PWR_IORETENRA_EN5_Msk (0x1UL << PWR_IORETENRA_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRA_EN5 PWR_IORETENRA_EN5_Msk /*!< Standby GPIO retention enable for PA5 */ +#define PWR_IORETENRA_EN6_Pos (6UL) +#define PWR_IORETENRA_EN6_Msk (0x1UL << PWR_IORETENRA_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRA_EN6 PWR_IORETENRA_EN6_Msk /*!< Standby GPIO retention enable for PA6 */ +#define PWR_IORETENRA_EN7_Pos (7UL) +#define PWR_IORETENRA_EN7_Msk (0x1UL << PWR_IORETENRA_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRA_EN7 PWR_IORETENRA_EN7_Msk /*!< Standby GPIO retention enable for PA7 */ +#define PWR_IORETENRA_EN8_Pos (8UL) +#define PWR_IORETENRA_EN8_Msk (0x1UL << PWR_IORETENRA_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRA_EN8 PWR_IORETENRA_EN8_Msk /*!< Standby GPIO retention enable for PA8 */ +#define PWR_IORETENRA_EN9_Pos (9UL) +#define PWR_IORETENRA_EN9_Msk (0x1UL << PWR_IORETENRA_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRA_EN9 PWR_IORETENRA_EN9_Msk /*!< Standby GPIO retention enable for PA9 */ +#define PWR_IORETENRA_EN10_Pos (10UL) +#define PWR_IORETENRA_EN10_Msk (0x1UL << PWR_IORETENRA_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRA_EN10 PWR_IORETENRA_EN10_Msk /*!< Standby GPIO retention enable for PA10 */ +#define PWR_IORETENRA_EN11_Pos (11UL) +#define PWR_IORETENRA_EN11_Msk (0x1UL << PWR_IORETENRA_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRA_EN11 PWR_IORETENRA_EN11_Msk /*!< Standby GPIO retention enable for PA11 */ +#define PWR_IORETENRA_EN12_Pos (12UL) +#define PWR_IORETENRA_EN12_Msk (0x1UL << PWR_IORETENRA_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRA_EN12 PWR_IORETENRA_EN12_Msk /*!< Standby GPIO retention enable for PA12 */ +#define PWR_IORETENRA_EN13_Pos (13UL) +#define PWR_IORETENRA_EN13_Msk (0x1UL << PWR_IORETENRA_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRA_EN13 PWR_IORETENRA_EN13_Msk /*!< Standby GPIO retention enable for PA13 */ +#define PWR_IORETENRA_EN14_Pos (14UL) +#define PWR_IORETENRA_EN14_Msk (0x1UL << PWR_IORETENRA_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRA_EN14 PWR_IORETENRA_EN14_Msk /*!< Standby GPIO retention enable for PA14 */ +#define PWR_IORETENRA_EN15_Pos (15UL) +#define PWR_IORETENRA_EN15_Msk (0x1UL << PWR_IORETENRA_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRA_EN15 PWR_IORETENRA_EN15_Msk /*!< Standby GPIO retention enable for PA15 */ + +/******************** Bit definition for PWR_IORETRA register *****************/ +#define PWR_IORETRA_RET0_Pos (0UL) +#define PWR_IORETRA_RET0_Msk (0x1UL << PWR_IORETRA_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRA_RET0 PWR_IORETRA_RET0_Msk /*!< Standby GPIO retention status for PA0 */ +#define PWR_IORETRA_RET1_Pos (1UL) +#define PWR_IORETRA_RET1_Msk (0x1UL << PWR_IORETRA_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRA_RET1 PWR_IORETRA_RET1_Msk /*!< Standby GPIO retention status for PA1 */ +#define PWR_IORETRA_RET2_Pos (2UL) +#define PWR_IORETRA_RET2_Msk (0x1UL << PWR_IORETRA_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRA_RET2 PWR_IORETRA_RET2_Msk /*!< Standby GPIO retention status for PA2 */ +#define PWR_IORETRA_RET3_Pos (3UL) +#define PWR_IORETRA_RET3_Msk (0x1UL << PWR_IORETRA_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRA_RET3 PWR_IORETRA_RET3_Msk /*!< Standby GPIO retention status for PA3 */ +#define PWR_IORETRA_RET4_Pos (4UL) +#define PWR_IORETRA_RET4_Msk (0x1UL << PWR_IORETRA_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRA_RET4 PWR_IORETRA_RET4_Msk /*!< Standby GPIO retention status for PA4 */ +#define PWR_IORETRA_RET5_Pos (5UL) +#define PWR_IORETRA_RET5_Msk (0x1UL << PWR_IORETRA_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRA_RET5 PWR_IORETRA_RET5_Msk /*!< Standby GPIO retention status for PA5 */ +#define PWR_IORETRA_RET6_Pos (6UL) +#define PWR_IORETRA_RET6_Msk (0x1UL << PWR_IORETRA_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRA_RET6 PWR_IORETRA_RET6_Msk /*!< Standby GPIO retention status for PA6 */ +#define PWR_IORETRA_RET7_Pos (7UL) +#define PWR_IORETRA_RET7_Msk (0x1UL << PWR_IORETRA_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRA_RET7 PWR_IORETRA_RET7_Msk /*!< Standby GPIO retention status for PA7 */ +#define PWR_IORETRA_RET8_Pos (8UL) +#define PWR_IORETRA_RET8_Msk (0x1UL << PWR_IORETRA_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRA_RET8 PWR_IORETRA_RET8_Msk /*!< Standby GPIO retention status for PA8 */ +#define PWR_IORETRA_RET9_Pos (9UL) +#define PWR_IORETRA_RET9_Msk (0x1UL << PWR_IORETRA_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRA_RET9 PWR_IORETRA_RET9_Msk /*!< Standby GPIO retention status for PA9 */ +#define PWR_IORETRA_RET10_Pos (10UL) +#define PWR_IORETRA_RET10_Msk (0x1UL << PWR_IORETRA_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRA_RET10 PWR_IORETRA_RET10_Msk /*!< Standby GPIO retention status for PA10 */ +#define PWR_IORETRA_RET11_Pos (11UL) +#define PWR_IORETRA_RET11_Msk (0x1UL << PWR_IORETRA_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRA_RET11 PWR_IORETRA_RET11_Msk /*!< Standby GPIO retention status for PA11 */ +#define PWR_IORETRA_RET12_Pos (12UL) +#define PWR_IORETRA_RET12_Msk (0x1UL << PWR_IORETRA_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRA_RET12 PWR_IORETRA_RET12_Msk /*!< Standby GPIO retention status for PA12 */ +#define PWR_IORETRA_RET13_Pos (13UL) +#define PWR_IORETRA_RET13_Msk (0x1UL << PWR_IORETRA_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRA_RET13 PWR_IORETRA_RET13_Msk /*!< Standby GPIO retention status for PA13 */ +#define PWR_IORETRA_RET14_Pos (14UL) +#define PWR_IORETRA_RET14_Msk (0x1UL << PWR_IORETRA_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRA_RET14 PWR_IORETRA_RET14_Msk /*!< Standby GPIO retention status for PA14 */ +#define PWR_IORETRA_RET15_Pos (15UL) +#define PWR_IORETRA_RET15_Msk (0x1UL << PWR_IORETRA_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRA_RET15 PWR_IORETRA_RET15_Msk /*!< Standby GPIO retention status for PA15 */ + +/******************** Bit definition for PWR_IORETENRB register *****************/ +#define PWR_IORETENRB_EN0_Pos (0UL) +#define PWR_IORETENRB_EN0_Msk (0x1UL << PWR_IORETENRB_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRB_EN0 PWR_IORETENRB_EN0_Msk /*!< Standby GPIO retention enable for PB0 */ +#define PWR_IORETENRB_EN1_Pos (1UL) +#define PWR_IORETENRB_EN1_Msk (0x1UL << PWR_IORETENRB_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRB_EN1 PWR_IORETENRB_EN1_Msk /*!< Standby GPIO retention enable for PB1 */ +#define PWR_IORETENRB_EN2_Pos (2UL) +#define PWR_IORETENRB_EN2_Msk (0x1UL << PWR_IORETENRB_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRB_EN2 PWR_IORETENRB_EN2_Msk /*!< Standby GPIO retention enable for PB2 */ +#define PWR_IORETENRB_EN3_Pos (3UL) +#define PWR_IORETENRB_EN3_Msk (0x1UL << PWR_IORETENRB_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRB_EN3 PWR_IORETENRB_EN3_Msk /*!< Standby GPIO retention enable for PB3 */ +#define PWR_IORETENRB_EN4_Pos (4UL) +#define PWR_IORETENRB_EN4_Msk (0x1UL << PWR_IORETENRB_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRB_EN4 PWR_IORETENRB_EN4_Msk /*!< Standby GPIO retention enable for PB4 */ +#define PWR_IORETENRB_EN5_Pos (5UL) +#define PWR_IORETENRB_EN5_Msk (0x1UL << PWR_IORETENRB_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRB_EN5 PWR_IORETENRB_EN5_Msk /*!< Standby GPIO retention enable for PB5 */ +#define PWR_IORETENRB_EN6_Pos (6UL) +#define PWR_IORETENRB_EN6_Msk (0x1UL << PWR_IORETENRB_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRB_EN6 PWR_IORETENRB_EN6_Msk /*!< Standby GPIO retention enable for PB6 */ +#define PWR_IORETENRB_EN7_Pos (7UL) +#define PWR_IORETENRB_EN7_Msk (0x1UL << PWR_IORETENRB_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRB_EN7 PWR_IORETENRB_EN7_Msk /*!< Standby GPIO retention enable for PB7 */ +#define PWR_IORETENRB_EN8_Pos (8UL) +#define PWR_IORETENRB_EN8_Msk (0x1UL << PWR_IORETENRB_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRB_EN8 PWR_IORETENRB_EN8_Msk /*!< Standby GPIO retention enable for PB8 */ +#define PWR_IORETENRB_EN9_Pos (9UL) +#define PWR_IORETENRB_EN9_Msk (0x1UL << PWR_IORETENRB_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRB_EN9 PWR_IORETENRB_EN9_Msk /*!< Standby GPIO retention enable for PB9 */ +#define PWR_IORETENRB_EN10_Pos (10UL) +#define PWR_IORETENRB_EN10_Msk (0x1UL << PWR_IORETENRB_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRB_EN10 PWR_IORETENRB_EN10_Msk /*!< Standby GPIO retention enable for PB10 */ +#define PWR_IORETENRB_EN11_Pos (11UL) +#define PWR_IORETENRB_EN11_Msk (0x1UL << PWR_IORETENRB_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRB_EN11 PWR_IORETENRB_EN11_Msk /*!< Standby GPIO retention enable for PB11 */ +#define PWR_IORETENRB_EN12_Pos (12UL) +#define PWR_IORETENRB_EN12_Msk (0x1UL << PWR_IORETENRB_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRB_EN12 PWR_IORETENRB_EN12_Msk /*!< Standby GPIO retention enable for PB12 */ +#define PWR_IORETENRB_EN13_Pos (13UL) +#define PWR_IORETENRB_EN13_Msk (0x1UL << PWR_IORETENRB_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRB_EN13 PWR_IORETENRB_EN13_Msk /*!< Standby GPIO retention enable for PB13 */ +#define PWR_IORETENRB_EN14_Pos (14UL) +#define PWR_IORETENRB_EN14_Msk (0x1UL << PWR_IORETENRB_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRB_EN14 PWR_IORETENRB_EN14_Msk /*!< Standby GPIO retention enable for PB14 */ +#define PWR_IORETENRB_EN15_Pos (15UL) +#define PWR_IORETENRB_EN15_Msk (0x1UL << PWR_IORETENRB_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRB_EN15 PWR_IORETENRB_EN15_Msk /*!< Standby GPIO retention enable for PB15 */ + +/******************** Bit definition for PWR_IORETRB register *****************/ +#define PWR_IORETRB_RET0_Pos (0UL) +#define PWR_IORETRB_RET0_Msk (0x1UL << PWR_IORETRB_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRB_RET0 PWR_IORETRB_RET0_Msk /*!< Standby GPIO retention status for PB0 */ +#define PWR_IORETRB_RET1_Pos (1UL) +#define PWR_IORETRB_RET1_Msk (0x1UL << PWR_IORETRB_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRB_RET1 PWR_IORETRB_RET1_Msk /*!< Standby GPIO retention status for PB1 */ +#define PWR_IORETRB_RET2_Pos (2UL) +#define PWR_IORETRB_RET2_Msk (0x1UL << PWR_IORETRB_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRB_RET2 PWR_IORETRB_RET2_Msk /*!< Standby GPIO retention status for PB2 */ +#define PWR_IORETRB_RET3_Pos (3UL) +#define PWR_IORETRB_RET3_Msk (0x1UL << PWR_IORETRB_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRB_RET3 PWR_IORETRB_RET3_Msk /*!< Standby GPIO retention status for PB3 */ +#define PWR_IORETRB_RET4_Pos (4UL) +#define PWR_IORETRB_RET4_Msk (0x1UL << PWR_IORETRB_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRB_RET4 PWR_IORETRB_RET4_Msk /*!< Standby GPIO retention status for PB4 */ +#define PWR_IORETRB_RET5_Pos (5UL) +#define PWR_IORETRB_RET5_Msk (0x1UL << PWR_IORETRB_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRB_RET5 PWR_IORETRB_RET5_Msk /*!< Standby GPIO retention status for PB5 */ +#define PWR_IORETRB_RET6_Pos (6UL) +#define PWR_IORETRB_RET6_Msk (0x1UL << PWR_IORETRB_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRB_RET6 PWR_IORETRB_RET6_Msk /*!< Standby GPIO retention status for PB6 */ +#define PWR_IORETRB_RET7_Pos (7UL) +#define PWR_IORETRB_RET7_Msk (0x1UL << PWR_IORETRB_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRB_RET7 PWR_IORETRB_RET7_Msk /*!< Standby GPIO retention status for PB7 */ +#define PWR_IORETRB_RET8_Pos (8UL) +#define PWR_IORETRB_RET8_Msk (0x1UL << PWR_IORETRB_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRB_RET8 PWR_IORETRB_RET8_Msk /*!< Standby GPIO retention status for PB8 */ +#define PWR_IORETRB_RET9_Pos (9UL) +#define PWR_IORETRB_RET9_Msk (0x1UL << PWR_IORETRB_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRB_RET9 PWR_IORETRB_RET9_Msk /*!< Standby GPIO retention status for PB9 */ +#define PWR_IORETRB_RET10_Pos (10UL) +#define PWR_IORETRB_RET10_Msk (0x1UL << PWR_IORETRB_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRB_RET10 PWR_IORETRB_RET10_Msk /*!< Standby GPIO retention status for PB10 */ +#define PWR_IORETRB_RET11_Pos (11UL) +#define PWR_IORETRB_RET11_Msk (0x1UL << PWR_IORETRB_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRB_RET11 PWR_IORETRB_RET11_Msk /*!< Standby GPIO retention status for PB11 */ +#define PWR_IORETRB_RET12_Pos (12UL) +#define PWR_IORETRB_RET12_Msk (0x1UL << PWR_IORETRB_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRB_RET12 PWR_IORETRB_RET12_Msk /*!< Standby GPIO retention status for PB12 */ +#define PWR_IORETRB_RET13_Pos (13UL) +#define PWR_IORETRB_RET13_Msk (0x1UL << PWR_IORETRB_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRB_RET13 PWR_IORETRB_RET13_Msk /*!< Standby GPIO retention status for PB13 */ +#define PWR_IORETRB_RET14_Pos (14UL) +#define PWR_IORETRB_RET14_Msk (0x1UL << PWR_IORETRB_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRB_RET14 PWR_IORETRB_RET14_Msk /*!< Standby GPIO retention status for PB14 */ +#define PWR_IORETRB_RET15_Pos (15UL) +#define PWR_IORETRB_RET15_Msk (0x1UL << PWR_IORETRB_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRB_RET15 PWR_IORETRB_RET15_Msk /*!< Standby GPIO retention status for PB15 */ + +/******************** Bit definition for PWR_IORETENRC register *****************/ +#define PWR_IORETENRC_EN0_Pos (0UL) +#define PWR_IORETENRC_EN0_Msk (0x1UL << PWR_IORETENRC_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRC_EN0 PWR_IORETENRC_EN0_Msk /*!< Standby GPIO retention enable for PC0 */ +#define PWR_IORETENRC_EN1_Pos (1UL) +#define PWR_IORETENRC_EN1_Msk (0x1UL << PWR_IORETENRC_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRC_EN1 PWR_IORETENRC_EN1_Msk /*!< Standby GPIO retention enable for PC1 */ +#define PWR_IORETENRC_EN2_Pos (2UL) +#define PWR_IORETENRC_EN2_Msk (0x1UL << PWR_IORETENRC_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRC_EN2 PWR_IORETENRC_EN2_Msk /*!< Standby GPIO retention enable for PC2 */ +#define PWR_IORETENRC_EN3_Pos (3UL) +#define PWR_IORETENRC_EN3_Msk (0x1UL << PWR_IORETENRC_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRC_EN3 PWR_IORETENRC_EN3_Msk /*!< Standby GPIO retention enable for PC3 */ +#define PWR_IORETENRC_EN4_Pos (4UL) +#define PWR_IORETENRC_EN4_Msk (0x1UL << PWR_IORETENRC_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRC_EN4 PWR_IORETENRC_EN4_Msk /*!< Standby GPIO retention enable for PC4 */ +#define PWR_IORETENRC_EN5_Pos (5UL) +#define PWR_IORETENRC_EN5_Msk (0x1UL << PWR_IORETENRC_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRC_EN5 PWR_IORETENRC_EN5_Msk /*!< Standby GPIO retention enable for PC5 */ +#define PWR_IORETENRC_EN6_Pos (6UL) +#define PWR_IORETENRC_EN6_Msk (0x1UL << PWR_IORETENRC_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRC_EN6 PWR_IORETENRC_EN6_Msk /*!< Standby GPIO retention enable for PC6 */ +#define PWR_IORETENRC_EN7_Pos (7UL) +#define PWR_IORETENRC_EN7_Msk (0x1UL << PWR_IORETENRC_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRC_EN7 PWR_IORETENRC_EN7_Msk /*!< Standby GPIO retention enable for PC7 */ +#define PWR_IORETENRC_EN8_Pos (8UL) +#define PWR_IORETENRC_EN8_Msk (0x1UL << PWR_IORETENRC_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRC_EN8 PWR_IORETENRC_EN8_Msk /*!< Standby GPIO retention enable for PC8 */ +#define PWR_IORETENRC_EN9_Pos (9UL) +#define PWR_IORETENRC_EN9_Msk (0x1UL << PWR_IORETENRC_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRC_EN9 PWR_IORETENRC_EN9_Msk /*!< Standby GPIO retention enable for PC9 */ +#define PWR_IORETENRC_EN10_Pos (10UL) +#define PWR_IORETENRC_EN10_Msk (0x1UL << PWR_IORETENRC_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRC_EN10 PWR_IORETENRC_EN10_Msk /*!< Standby GPIO retention enable for PC10 */ +#define PWR_IORETENRC_EN11_Pos (11UL) +#define PWR_IORETENRC_EN11_Msk (0x1UL << PWR_IORETENRC_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRC_EN11 PWR_IORETENRC_EN11_Msk /*!< Standby GPIO retention enable for PC11 */ +#define PWR_IORETENRC_EN12_Pos (12UL) +#define PWR_IORETENRC_EN12_Msk (0x1UL << PWR_IORETENRC_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRC_EN12 PWR_IORETENRC_EN12_Msk /*!< Standby GPIO retention enable for PC12 */ +#define PWR_IORETENRC_EN13_Pos (13UL) +#define PWR_IORETENRC_EN13_Msk (0x1UL << PWR_IORETENRC_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRC_EN13 PWR_IORETENRC_EN13_Msk /*!< Standby GPIO retention enable for PC13 */ +#define PWR_IORETENRC_EN14_Pos (14UL) +#define PWR_IORETENRC_EN14_Msk (0x1UL << PWR_IORETENRC_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRC_EN14 PWR_IORETENRC_EN14_Msk /*!< Standby GPIO retention enable for PC14 */ +#define PWR_IORETENRC_EN15_Pos (15UL) +#define PWR_IORETENRC_EN15_Msk (0x1UL << PWR_IORETENRC_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRC_EN15 PWR_IORETENRC_EN15_Msk /*!< Standby GPIO retention enable for PC15 */ + +/******************** Bit definition for PWR_IORETRC register *****************/ +#define PWR_IORETRC_RET0_Pos (0UL) +#define PWR_IORETRC_RET0_Msk (0x1UL << PWR_IORETRC_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRC_RET0 PWR_IORETRC_RET0_Msk /*!< Standby GPIO retention status for PC0 */ +#define PWR_IORETRC_RET1_Pos (1UL) +#define PWR_IORETRC_RET1_Msk (0x1UL << PWR_IORETRC_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRC_RET1 PWR_IORETRC_RET1_Msk /*!< Standby GPIO retention status for PC1 */ +#define PWR_IORETRC_RET2_Pos (2UL) +#define PWR_IORETRC_RET2_Msk (0x1UL << PWR_IORETRC_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRC_RET2 PWR_IORETRC_RET2_Msk /*!< Standby GPIO retention status for PC2 */ +#define PWR_IORETRC_RET3_Pos (3UL) +#define PWR_IORETRC_RET3_Msk (0x1UL << PWR_IORETRC_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRC_RET3 PWR_IORETRC_RET3_Msk /*!< Standby GPIO retention status for PC3 */ +#define PWR_IORETRC_RET4_Pos (4UL) +#define PWR_IORETRC_RET4_Msk (0x1UL << PWR_IORETRC_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRC_RET4 PWR_IORETRC_RET4_Msk /*!< Standby GPIO retention status for PC4 */ +#define PWR_IORETRC_RET5_Pos (5UL) +#define PWR_IORETRC_RET5_Msk (0x1UL << PWR_IORETRC_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRC_RET5 PWR_IORETRC_RET5_Msk /*!< Standby GPIO retention status for PC5 */ +#define PWR_IORETRC_RET6_Pos (6UL) +#define PWR_IORETRC_RET6_Msk (0x1UL << PWR_IORETRC_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRC_RET6 PWR_IORETRC_RET6_Msk /*!< Standby GPIO retention status for PC6 */ +#define PWR_IORETRC_RET7_Pos (7UL) +#define PWR_IORETRC_RET7_Msk (0x1UL << PWR_IORETRC_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRC_RET7 PWR_IORETRC_RET7_Msk /*!< Standby GPIO retention status for PC7 */ +#define PWR_IORETRC_RET8_Pos (8UL) +#define PWR_IORETRC_RET8_Msk (0x1UL << PWR_IORETRC_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRC_RET8 PWR_IORETRC_RET8_Msk /*!< Standby GPIO retention status for PC8 */ +#define PWR_IORETRC_RET9_Pos (9UL) +#define PWR_IORETRC_RET9_Msk (0x1UL << PWR_IORETRC_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRC_RET9 PWR_IORETRC_RET9_Msk /*!< Standby GPIO retention status for PC9 */ +#define PWR_IORETRC_RET10_Pos (10UL) +#define PWR_IORETRC_RET10_Msk (0x1UL << PWR_IORETRC_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRC_RET10 PWR_IORETRC_RET10_Msk /*!< Standby GPIO retention status for PC10 */ +#define PWR_IORETRC_RET11_Pos (11UL) +#define PWR_IORETRC_RET11_Msk (0x1UL << PWR_IORETRC_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRC_RET11 PWR_IORETRC_RET11_Msk /*!< Standby GPIO retention status for PC11 */ +#define PWR_IORETRC_RET12_Pos (12UL) +#define PWR_IORETRC_RET12_Msk (0x1UL << PWR_IORETRC_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRC_RET12 PWR_IORETRC_RET12_Msk /*!< Standby GPIO retention status for PC12 */ +#define PWR_IORETRC_RET13_Pos (13UL) +#define PWR_IORETRC_RET13_Msk (0x1UL << PWR_IORETRC_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRC_RET13 PWR_IORETRC_RET13_Msk /*!< Standby GPIO retention status for PC13 */ +#define PWR_IORETRC_RET14_Pos (14UL) +#define PWR_IORETRC_RET14_Msk (0x1UL << PWR_IORETRC_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRC_RET14 PWR_IORETRC_RET14_Msk /*!< Standby GPIO retention status for PC14 */ +#define PWR_IORETRC_RET15_Pos (15UL) +#define PWR_IORETRC_RET15_Msk (0x1UL << PWR_IORETRC_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRC_RET15 PWR_IORETRC_RET15_Msk /*!< Standby GPIO retention status for PC15 */ +/******************** Bit definition for PWR_IORETENRD register *****************/ +#define PWR_IORETENRD_EN0_Pos (0UL) +#define PWR_IORETENRD_EN0_Msk (0x1UL << PWR_IORETENRD_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRD_EN0 PWR_IORETENRD_EN0_Msk /*!< Standby GPIO retention enable for PD0 */ +#define PWR_IORETENRD_EN1_Pos (1UL) +#define PWR_IORETENRD_EN1_Msk (0x1UL << PWR_IORETENRD_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRD_EN1 PWR_IORETENRD_EN1_Msk /*!< Standby GPIO retention enable for PD1 */ +#define PWR_IORETENRD_EN2_Pos (2UL) +#define PWR_IORETENRD_EN2_Msk (0x1UL << PWR_IORETENRD_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRD_EN2 PWR_IORETENRD_EN2_Msk /*!< Standby GPIO retention enable for PD2 */ +#define PWR_IORETENRD_EN3_Pos (3UL) +#define PWR_IORETENRD_EN3_Msk (0x1UL << PWR_IORETENRD_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRD_EN3 PWR_IORETENRD_EN3_Msk /*!< Standby GPIO retention enable for PD3 */ +#define PWR_IORETENRD_EN4_Pos (4UL) +#define PWR_IORETENRD_EN4_Msk (0x1UL << PWR_IORETENRD_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRD_EN4 PWR_IORETENRD_EN4_Msk /*!< Standby GPIO retention enable for PD4 */ +#define PWR_IORETENRD_EN5_Pos (5UL) +#define PWR_IORETENRD_EN5_Msk (0x1UL << PWR_IORETENRD_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRD_EN5 PWR_IORETENRD_EN5_Msk /*!< Standby GPIO retention enable for PD5 */ +#define PWR_IORETENRD_EN6_Pos (6UL) +#define PWR_IORETENRD_EN6_Msk (0x1UL << PWR_IORETENRD_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRD_EN6 PWR_IORETENRD_EN6_Msk /*!< Standby GPIO retention enable for PD6 */ +#define PWR_IORETENRD_EN7_Pos (7UL) +#define PWR_IORETENRD_EN7_Msk (0x1UL << PWR_IORETENRD_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRD_EN7 PWR_IORETENRD_EN7_Msk /*!< Standby GPIO retention enable for PD7 */ +#define PWR_IORETENRD_EN8_Pos (8UL) +#define PWR_IORETENRD_EN8_Msk (0x1UL << PWR_IORETENRD_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRD_EN8 PWR_IORETENRD_EN8_Msk /*!< Standby GPIO retention enable for PD8 */ +#define PWR_IORETENRD_EN9_Pos (9UL) +#define PWR_IORETENRD_EN9_Msk (0x1UL << PWR_IORETENRD_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRD_EN9 PWR_IORETENRD_EN9_Msk /*!< Standby GPIO retention enable for PD9 */ +#define PWR_IORETENRD_EN10_Pos (10UL) +#define PWR_IORETENRD_EN10_Msk (0x1UL << PWR_IORETENRD_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRD_EN10 PWR_IORETENRD_EN10_Msk /*!< Standby GPIO retention enable for PD10 */ +#define PWR_IORETENRD_EN11_Pos (11UL) +#define PWR_IORETENRD_EN11_Msk (0x1UL << PWR_IORETENRD_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRD_EN11 PWR_IORETENRD_EN11_Msk /*!< Standby GPIO retention enable for PD11 */ +#define PWR_IORETENRD_EN12_Pos (12UL) +#define PWR_IORETENRD_EN12_Msk (0x1UL << PWR_IORETENRD_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRD_EN12 PWR_IORETENRD_EN12_Msk /*!< Standby GPIO retention enable for PD12 */ +#define PWR_IORETENRD_EN13_Pos (13UL) +#define PWR_IORETENRD_EN13_Msk (0x1UL << PWR_IORETENRD_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRD_EN13 PWR_IORETENRD_EN13_Msk /*!< Standby GPIO retention enable for PD13 */ +#define PWR_IORETENRD_EN14_Pos (14UL) +#define PWR_IORETENRD_EN14_Msk (0x1UL << PWR_IORETENRD_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRD_EN14 PWR_IORETENRD_EN14_Msk /*!< Standby GPIO retention enable for PD14 */ +#define PWR_IORETENRD_EN15_Pos (15UL) +#define PWR_IORETENRD_EN15_Msk (0x1UL << PWR_IORETENRD_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRD_EN15 PWR_IORETENRD_EN15_Msk /*!< Standby GPIO retention enable for PD14 */ + +/******************** Bit definition for PWR_IORETRD register *****************/ + +#define PWR_IORETRD_RET0_Pos (0UL) +#define PWR_IORETRD_RET0_Msk (0x1UL << PWR_IORETRD_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRD_RET0 PWR_IORETRD_RET0_Msk /*!< Standby GPIO retention status for PD0 */ +#define PWR_IORETRD_RET1_Pos (1UL) +#define PWR_IORETRD_RET1_Msk (0x1UL << PWR_IORETRD_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRD_RET1 PWR_IORETRD_RET1_Msk /*!< Standby GPIO retention status for PD1 */ +#define PWR_IORETRD_RET2_Pos (2UL) +#define PWR_IORETRD_RET2_Msk (0x1UL << PWR_IORETRD_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRD_RET2 PWR_IORETRD_RET2_Msk /*!< Standby GPIO retention status for PD2 */ +#define PWR_IORETRD_RET3_Pos (3UL) +#define PWR_IORETRD_RET3_Msk (0x1UL << PWR_IORETRD_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRD_RET3 PWR_IORETRD_RET3_Msk /*!< Standby GPIO retention status for PD3 */ +#define PWR_IORETRD_RET4_Pos (4UL) +#define PWR_IORETRD_RET4_Msk (0x1UL << PWR_IORETRD_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRD_RET4 PWR_IORETRD_RET4_Msk /*!< Standby GPIO retention status for PD4 */ +#define PWR_IORETRD_RET5_Pos (5UL) +#define PWR_IORETRD_RET5_Msk (0x1UL << PWR_IORETRD_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRD_RET5 PWR_IORETRD_RET5_Msk /*!< Standby GPIO retention status for PD5 */ +#define PWR_IORETRD_RET6_Pos (6UL) +#define PWR_IORETRD_RET6_Msk (0x1UL << PWR_IORETRD_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRD_RET6 PWR_IORETRD_RET6_Msk /*!< Standby GPIO retention status for PD6 */ +#define PWR_IORETRD_RET7_Pos (7UL) +#define PWR_IORETRD_RET7_Msk (0x1UL << PWR_IORETRD_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRD_RET7 PWR_IORETRD_RET7_Msk /*!< Standby GPIO retention status for PD7 */ +#define PWR_IORETRD_RET8_Pos (8UL) +#define PWR_IORETRD_RET8_Msk (0x1UL << PWR_IORETRD_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRD_RET8 PWR_IORETRD_RET8_Msk /*!< Standby GPIO retention status for PD8 */ +#define PWR_IORETRD_RET9_Pos (9UL) +#define PWR_IORETRD_RET9_Msk (0x1UL << PWR_IORETRD_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRD_RET9 PWR_IORETRD_RET9_Msk /*!< Standby GPIO retention status for PD9 */ +#define PWR_IORETRD_RET10_Pos (10UL) +#define PWR_IORETRD_RET10_Msk (0x1UL << PWR_IORETRD_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRD_RET10 PWR_IORETRD_RET10_Msk /*!< Standby GPIO retention status for PD10 */ +#define PWR_IORETRD_RET11_Pos (11UL) +#define PWR_IORETRD_RET11_Msk (0x1UL << PWR_IORETRD_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRD_RET11 PWR_IORETRD_RET11_Msk /*!< Standby GPIO retention status for PD11 */ +#define PWR_IORETRD_RET12_Pos (12UL) +#define PWR_IORETRD_RET12_Msk (0x1UL << PWR_IORETRD_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRD_RET12 PWR_IORETRD_RET12_Msk /*!< Standby GPIO retention status for PD12 */ +#define PWR_IORETRD_RET13_Pos (13UL) +#define PWR_IORETRD_RET13_Msk (0x1UL << PWR_IORETRD_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRD_RET13 PWR_IORETRD_RET13_Msk /*!< Standby GPIO retention status for PD13 */ +#define PWR_IORETRD_RET14_Pos (14UL) +#define PWR_IORETRD_RET14_Msk (0x1UL << PWR_IORETRD_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRD_RET14 PWR_IORETRD_RET14_Msk /*!< Standby GPIO retention status for PD14 */ +#define PWR_IORETRD_RET15_Pos (15UL) +#define PWR_IORETRD_RET15_Msk (0x1UL << PWR_IORETRD_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRD_RET15 PWR_IORETRD_RET15_Msk /*!< Standby GPIO retention status for PD15 */ +/******************** Bit definition for PWR_IORETENRE register *****************/ +#define PWR_IORETENRE_EN0_Pos (0UL) +#define PWR_IORETENRE_EN0_Msk (0x1UL << PWR_IORETENRE_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRE_EN0 PWR_IORETENRE_EN0_Msk /*!< Standby GPIO retention enable for PE0 */ +#define PWR_IORETENRE_EN1_Pos (1UL) +#define PWR_IORETENRE_EN1_Msk (0x1UL << PWR_IORETENRE_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRE_EN1 PWR_IORETENRE_EN1_Msk /*!< Standby GPIO retention enable for PE1 */ +#define PWR_IORETENRE_EN2_Pos (2UL) +#define PWR_IORETENRE_EN2_Msk (0x1UL << PWR_IORETENRE_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRE_EN2 PWR_IORETENRE_EN2_Msk /*!< Standby GPIO retention enable for PE2 */ +#define PWR_IORETENRE_EN3_Pos (3UL) +#define PWR_IORETENRE_EN3_Msk (0x1UL << PWR_IORETENRE_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRE_EN3 PWR_IORETENRE_EN3_Msk /*!< Standby GPIO retention enable for PE3 */ +#define PWR_IORETENRE_EN4_Pos (4UL) +#define PWR_IORETENRE_EN4_Msk (0x1UL << PWR_IORETENRE_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRE_EN4 PWR_IORETENRE_EN4_Msk /*!< Standby GPIO retention enable for PE4 */ +#define PWR_IORETENRE_EN5_Pos (5UL) +#define PWR_IORETENRE_EN5_Msk (0x1UL << PWR_IORETENRE_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRE_EN5 PWR_IORETENRE_EN5_Msk /*!< Standby GPIO retention enable for PE5 */ +#define PWR_IORETENRE_EN6_Pos (6UL) +#define PWR_IORETENRE_EN6_Msk (0x1UL << PWR_IORETENRE_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRE_EN6 PWR_IORETENRE_EN6_Msk /*!< Standby GPIO retention enable for PE6 */ + +/******************** Bit definition for PWR_IORETRE register *****************/ +#define PWR_IORETRE_RET0_Pos (0UL) +#define PWR_IORETRE_RET0_Msk (0x1UL << PWR_IORETRE_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRE_RET0 PWR_IORETRE_RET0_Msk /*!< Standby GPIO retention status for PE0 */ +#define PWR_IORETRE_RET1_Pos (1UL) +#define PWR_IORETRE_RET1_Msk (0x1UL << PWR_IORETRE_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRE_RET1 PWR_IORETRE_RET1_Msk /*!< Standby GPIO retention status for PE1 */ +#define PWR_IORETRE_RET2_Pos (2UL) +#define PWR_IORETRE_RET2_Msk (0x1UL << PWR_IORETRE_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRE_RET2 PWR_IORETRE_RET2_Msk /*!< Standby GPIO retention status for PE2 */ +#define PWR_IORETRE_RET3_Pos (3UL) +#define PWR_IORETRE_RET3_Msk (0x1UL << PWR_IORETRE_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRE_RET3 PWR_IORETRE_RET3_Msk /*!< Standby GPIO retention status for PE3 */ +#define PWR_IORETRE_RET4_Pos (4UL) +#define PWR_IORETRE_RET4_Msk (0x1UL << PWR_IORETRE_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRE_RET4 PWR_IORETRE_RET4_Msk /*!< Standby GPIO retention status for PE4 */ +#define PWR_IORETRE_RET5_Pos (5UL) +#define PWR_IORETRE_RET5_Msk (0x1UL << PWR_IORETRE_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRE_RET5 PWR_IORETRE_RET5_Msk /*!< Standby GPIO retention status for PE5 */ +#define PWR_IORETRE_RET6_Pos (6UL) +#define PWR_IORETRE_RET6_Msk (0x1UL << PWR_IORETRE_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRE_RET6 PWR_IORETRE_RET6_Msk /*!< Standby GPIO retention status for PE6 */ + +/******************** Bit definition for PWR_IORETENRG register *****************/ +#define PWR_IORETENRG_EN2_Pos (2UL) +#define PWR_IORETENRG_EN2_Msk (0x1UL << PWR_IORETENRG_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRG_EN2 PWR_IORETENRG_EN2_Msk /*!< Standby GPIO retention enable for PG2 */ +#define PWR_IORETENRG_EN3_Pos (3UL) +#define PWR_IORETENRG_EN3_Msk (0x1UL << PWR_IORETENRG_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRG_EN3 PWR_IORETENRG_EN3_Msk /*!< Standby GPIO retention enable for PG3 */ +#define PWR_IORETENRG_EN4_Pos (4UL) +#define PWR_IORETENRG_EN4_Msk (0x1UL << PWR_IORETENRG_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRG_EN4 PWR_IORETENRG_EN4_Msk /*!< Standby GPIO retention enable for PG4 */ +#define PWR_IORETENRG_EN5_Pos (5UL) +#define PWR_IORETENRG_EN5_Msk (0x1UL << PWR_IORETENRG_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRG_EN5 PWR_IORETENRG_EN5_Msk /*!< Standby GPIO retention enable for PG5 */ +#define PWR_IORETENRG_EN6_Pos (6UL) +#define PWR_IORETENRG_EN6_Msk (0x1UL << PWR_IORETENRG_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRG_EN6 PWR_IORETENRG_EN6_Msk /*!< Standby GPIO retention enable for PG6 */ +#define PWR_IORETENRG_EN7_Pos (7UL) +#define PWR_IORETENRG_EN7_Msk (0x1UL << PWR_IORETENRG_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRG_EN7 PWR_IORETENRG_EN7_Msk /*!< Standby GPIO retention enable for PG7 */ +#define PWR_IORETENRG_EN8_Pos (8UL) +#define PWR_IORETENRG_EN8_Msk (0x1UL << PWR_IORETENRG_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRG_EN8 PWR_IORETENRG_EN8_Msk /*!< Standby GPIO retention enable for PG8 */ +#define PWR_IORETENRG_EN9_Pos (9UL) +#define PWR_IORETENRG_EN9_Msk (0x1UL << PWR_IORETENRG_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRG_EN9 PWR_IORETENRG_EN9_Msk /*!< Standby GPIO retention enable for PG9 */ +#define PWR_IORETENRG_EN10_Pos (10UL) +#define PWR_IORETENRG_EN10_Msk (0x1UL << PWR_IORETENRG_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRG_EN10 PWR_IORETENRG_EN10_Msk /*!< Standby GPIO retention enable for PG10 */ +#define PWR_IORETENRG_EN11_Pos (11UL) +#define PWR_IORETENRG_EN11_Msk (0x1UL << PWR_IORETENRG_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRG_EN11 PWR_IORETENRG_EN11_Msk /*!< Standby GPIO retention enable for PG11 */ +#define PWR_IORETENRG_EN12_Pos (12UL) +#define PWR_IORETENRG_EN12_Msk (0x1UL << PWR_IORETENRG_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRG_EN12 PWR_IORETENRG_EN12_Msk /*!< Standby GPIO retention enable for PG12 */ +#define PWR_IORETENRG_EN13_Pos (13UL) +#define PWR_IORETENRG_EN13_Msk (0x1UL << PWR_IORETENRG_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRG_EN13 PWR_IORETENRG_EN13_Msk /*!< Standby GPIO retention enable for PG13 */ +#define PWR_IORETENRG_EN14_Pos (14UL) +#define PWR_IORETENRG_EN14_Msk (0x1UL << PWR_IORETENRG_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRG_EN14 PWR_IORETENRG_EN14_Msk /*!< Standby GPIO retention enable for PG14 */ +#define PWR_IORETENRG_EN15_Pos (15UL) +#define PWR_IORETENRG_EN15_Msk (0x1UL << PWR_IORETENRG_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRG_EN15 PWR_IORETENRG_EN15_Msk /*!< Standby GPIO retention enable for PG15 */ + +/******************** Bit definition for PWR_IORETRG register *****************/ +#define PWR_IORETRG_EN2_Pos (2UL) +#define PWR_IORETRG_EN2_Msk (0x1UL << PWR_IORETRG_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRG_EN2 PWR_IORETRG_EN2_Msk /*!< Standby GPIO retention status for PG2 */ +#define PWR_IORETRG_EN3_Pos (3UL) +#define PWR_IORETRG_EN3_Msk (0x1UL << PWR_IORETRG_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRG_EN3 PWR_IORETRG_EN3_Msk /*!< Standby GPIO retention status for PG3 */ +#define PWR_IORETRG_EN4_Pos (4UL) +#define PWR_IORETRG_EN4_Msk (0x1UL << PWR_IORETRG_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRG_EN4 PWR_IORETRG_EN4_Msk /*!< Standby GPIO retention status for PG4 */ +#define PWR_IORETRG_EN5_Pos (5UL) +#define PWR_IORETRG_EN5_Msk (0x1UL << PWR_IORETRG_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRG_EN5 PWR_IORETRG_EN5_Msk /*!< Standby GPIO retention status for PG5 */ +#define PWR_IORETRG_EN6_Pos (6UL) +#define PWR_IORETRG_EN6_Msk (0x1UL << PWR_IORETRG_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRG_EN6 PWR_IORETRG_EN6_Msk /*!< Standby GPIO retention status for PG6 */ +#define PWR_IORETRG_EN7_Pos (7UL) +#define PWR_IORETRG_EN7_Msk (0x1UL << PWR_IORETRG_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRG_EN7 PWR_IORETRG_EN7_Msk /*!< Standby GPIO retention status for PG7 */ +#define PWR_IORETRG_EN8_Pos (8UL) +#define PWR_IORETRG_EN8_Msk (0x1UL << PWR_IORETRG_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRG_EN8 PWR_IORETRG_EN8_Msk /*!< Standby GPIO retention status for PG8 */ +#define PWR_IORETRG_EN9_Pos (9UL) +#define PWR_IORETRG_EN9_Msk (0x1UL << PWR_IORETRG_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRG_EN9 PWR_IORETRG_EN9_Msk /*!< Standby GPIO retention status for PG9 */ +#define PWR_IORETRG_EN10_Pos (10UL) +#define PWR_IORETRG_EN10_Msk (0x1UL << PWR_IORETRG_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRG_EN10 PWR_IORETRG_EN10_Msk /*!< Standby GPIO retention status for PG10 */ +#define PWR_IORETRG_EN11_Pos (11UL) +#define PWR_IORETRG_EN11_Msk (0x1UL << PWR_IORETRG_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRG_EN11 PWR_IORETRG_EN11_Msk /*!< Standby GPIO retention status for PG11 */ +#define PWR_IORETRG_EN12_Pos (12UL) +#define PWR_IORETRG_EN12_Msk (0x1UL << PWR_IORETRG_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRG_EN12 PWR_IORETRG_EN12_Msk /*!< Standby GPIO retention status for PG12 */ +#define PWR_IORETRG_EN13_Pos (13UL) +#define PWR_IORETRG_EN13_Msk (0x1UL << PWR_IORETRG_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRG_EN13 PWR_IORETRG_EN13_Msk /*!< Standby GPIO retention status for PG13 */ +#define PWR_IORETRG_EN14_Pos (14UL) +#define PWR_IORETRG_EN14_Msk (0x1UL << PWR_IORETRG_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRG_EN14 PWR_IORETRG_EN14_Msk /*!< Standby GPIO retention status for PG14 */ +#define PWR_IORETRG_EN15_Pos (15UL) +#define PWR_IORETRG_EN15_Msk (0x1UL << PWR_IORETRG_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRG_EN15 PWR_IORETRG_EN15_Msk /*!< Standby GPIO retention status for PG15 */ + +/******************** Bit definition for PWR_IORETENRH register *****************/ +#define PWR_IORETENRH_EN3_Pos (3UL) +#define PWR_IORETENRH_EN3_Msk (0x1UL << PWR_IORETENRH_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRH_EN3 PWR_IORETENRH_EN3_Msk /*!< Standby GPIO retention enable for PH3 */ + +/******************** Bit definition for PWR_IORETRH register *****************/ +#define PWR_IORETRH_RET3_Pos (3UL) +#define PWR_IORETRH_RET3_Msk (0x1UL << PWR_IORETRH_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRH_RET3 PWR_IORETRH_RET3_Msk /*!< Standby GPIO retention status for PH3 */ + +/******************** Bit definition for PWR_RADIOSCR register *****************/ +#define PWR_RADIOSCR_MODE_Pos (0UL) +#define PWR_RADIOSCR_MODE_Msk (0x3UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000003 */ +#define PWR_RADIOSCR_MODE PWR_RADIOSCR_MODE_Msk /*!< 2.4 GHz RADIO operating mode */ +#define PWR_RADIOSCR_MODE_0 (0x1UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000001 */ +#define PWR_RADIOSCR_MODE_1 (0x2UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000002 */ +#define PWR_RADIOSCR_PHYMODE_Pos (2UL) +#define PWR_RADIOSCR_PHYMODE_Msk (0x1UL << PWR_RADIOSCR_PHYMODE_Pos) /*!< 0x00000004 */ +#define PWR_RADIOSCR_PHYMODE PWR_RADIOSCR_PHYMODE_Msk /*!< 2.4 GHz RADIO PHY operating mode */ +#define PWR_RADIOSCR_ENCMODE_Pos (3UL) +#define PWR_RADIOSCR_ENCMODE_Msk (0x1UL << PWR_RADIOSCR_ENCMODE_Pos) /*!< 0x00000008 */ +#define PWR_RADIOSCR_ENCMODE PWR_RADIOSCR_ENCMODE_Msk /*!< 2.4 GHz RADIO encryption function operating mode */ +#define PWR_RADIOSCR_RFVDDHPA_Pos (8UL) +#define PWR_RADIOSCR_RFVDDHPA_Msk (0x1FUL << PWR_RADIOSCR_RFVDDHPA_Pos) /*!< 0x00001F00 */ +#define PWR_RADIOSCR_RFVDDHPA PWR_RADIOSCR_RFVDDHPA_Msk /*!< 2.4 GHz RADIO VDDHPA control word */ +#define PWR_RADIOSCR_REGPARDYV11_Pos (14UL) +#define PWR_RADIOSCR_REGPARDYV11_Msk (0x1UL << PWR_RADIOSCR_REGPARDYV11_Pos) /*!< 0x00004000 */ +#define PWR_RADIOSCR_REGPARDYV11 PWR_RADIOSCR_REGPARDYV11_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Pos (15UL) +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Msk (0x1UL << PWR_RADIOSCR_REGPARDYVDDRFPA_Pos) /*!< 0x00008000 */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA PWR_RADIOSCR_REGPARDYVDDRFPA_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_RADIOSCR_REGPASEL_Pos (23UL) +#define PWR_RADIOSCR_REGPASEL_Msk (0x1UL << PWR_RADIOSCR_REGPASEL_Pos) /*!< 0x00800000 */ +#define PWR_RADIOSCR_REGPASEL PWR_RADIOSCR_REGPASEL_Msk /*!< Regulator REG_VDDHPA input supply selection */ +#define PWR_RADIOSCR_REGPABYPEN_Pos (24UL) +#define PWR_RADIOSCR_REGPABYPEN_Msk (0x1UL << PWR_RADIOSCR_REGPABYPEN_Pos) /*!< 0x01000000 */ +#define PWR_RADIOSCR_REGPABYPEN PWR_RADIOSCR_REGPABYPEN_Msk /*!< Regulator REG_VDDHPA bypass enable.*/ + +/******************** Bit definition for PWR_S2RETR register *****************/ +#define PWR_S2RETR_PTASREN_Pos (0UL) +#define PWR_S2RETR_PTASREN_Msk (0x1UL << PWR_S2RETR_PTASREN_Pos) /*!< 0x00000001 */ +#define PWR_S2RETR_PTASREN PWR_S2RETR_PTASREN_Msk /*!< PTA output signals Stop 2 mode retention enable */ +#define PWR_S2RETR_PTASR_Pos (16UL) +#define PWR_S2RETR_PTASR_Msk (0x1UL << PWR_S2RETR_PTASR_Pos) /*!< 0x00010000 */ +#define PWR_S2RETR_PTASR PWR_S2RETR_PTASR_Msk /*!< PTA interface output signals state retention in Stop 2 mode active */ + +/******************************************************************************/ +/* */ +/* SRAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_MxCR register ******************/ +#define RAMCFG_CR_ALE_Pos (4UL) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8UL) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_WSC_Pos (16UL) +#define RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) /*!< 0x00070000 */ +#define RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk /*!< WSC[18:16] Wait State Configuration field */ +#define RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) /*!< 0x00040000 */ + +/******************* Bit definition for RAMCFG_MxISR register ******************/ +#define RAMCFG_ISR_PED_Pos (1UL) +#define RAMCFG_ISR_PED_Msk (0x1UL << RAMCFG_ISR_PED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_PED RAMCFG_ISR_PED_Msk /*!< Parity error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8UL) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/***************** Bit definition for RAMCFG_MxERKEYR register ***************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0UL) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/******************* Bit definition for RAMCFG_MxIER register ******************/ +#define RAMCFG_IER_PEIE_Pos (1UL) +#define RAMCFG_IER_PEIE_Msk (0x1UL << RAMCFG_IER_PEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_PEIE RAMCFG_IER_PEIE_Msk /*!< Parity error interrupt enable */ +#define RAMCFG_IER_PENMI_Pos (3UL) +#define RAMCFG_IER_PENMI_Msk (0x1UL << RAMCFG_IER_PENMI_Pos) /*!< 0x00000004 */ +#define RAMCFG_IER_PENMI RAMCFG_IER_PENMI_Msk /*!< Parity error NMI */ + +/******************* Bit definition for RAMCFG_MxPEAR register ******************/ +#define RAMCFG_PEAR_PEA_Pos (0UL) +#define RAMCFG_PEAR_PEA_Msk (0xFFFFUL << RAMCFG_PEAR_PEA_Pos) /*!< 0x0000FFFF */ +#define RAMCFG_PEAR_PEA RAMCFG_PEAR_PEA_Msk /*!< Parity error SRAM word aligned address offset */ +#define RAMCFG_PEAR_ID_Pos (24UL) +#define RAMCFG_PEAR_ID_Msk (0xFUL << RAMCFG_PEAR_ID_Pos) /*!< 0x0F000000 */ +#define RAMCFG_PEAR_ID RAMCFG_PEAR_ID_Msk /*!< Parity error AHB bus master ID */ +#define RAMCFG_PEAR_BYTE_Pos (28UL) +#define RAMCFG_PEAR_BYTE_Msk (0xFUL << RAMCFG_PEAR_BYTE_Pos) /*!< 0xF0000000 */ +#define RAMCFG_PEAR_BYTE RAMCFG_PEAR_BYTE_Msk /*!< Byte parity error flag */ + +/******************* Bit definition for RAMCFG_MxICR register *****************/ +#define RAMCFG_ICR_CPED_Pos (1UL) +#define RAMCFG_ICR_CPED_Msk (0x1UL << RAMCFG_ICR_CPED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CPED RAMCFG_ICR_CPED_Msk /*!< Clear parity error detect bit */ + +/****************** Bit definition for RAMCFG_MxWPR1 register *****************/ +#define RAMCFG_WPR1_P0WP_Pos (0UL) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1UL) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2UL) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3UL) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4UL) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5UL) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6UL) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7UL) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8UL) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9UL) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10UL) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11UL) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12UL) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13UL) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14UL) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15UL) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16UL) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17UL) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18UL) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19UL) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20UL) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21UL) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22UL) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23UL) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24UL) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25UL) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26UL) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27UL) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28UL) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29UL) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30UL) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31UL) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/****************** Bit definition for RAMCFG_MxWPR2 register ****************/ +#define RAMCFG_WPR2_P32WP_Pos (0UL) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1UL) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2UL) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3UL) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4UL) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5UL) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6UL) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7UL) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8UL) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9UL) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10UL) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11UL) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12UL) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13UL) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14UL) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15UL) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16UL) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17UL) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18UL) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19UL) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20UL) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21UL) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22UL) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23UL) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25UL) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26UL) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27UL) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28UL) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29UL) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30UL) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31UL) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31UL) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +#define RCC_LSI2_SUPPORT + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (8UL) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9UL) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10UL) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSEON_Pos (16UL) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17UL) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_HSECSSON_Pos (19UL) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< External High Speed oscillator (HSE) clock security system enable */ +#define RCC_CR_HSEPRE_Pos (20UL) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< External High Speed oscillator (HSE) clock for sysclk prescaler */ +#define RCC_CR_PLL1ON_Pos (24UL) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25UL) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */ + +/******************** Bit definition for RCC_ICSCR3 register ***************/ +#define RCC_ICSCR3_HSICAL_Pos (0UL) +#define RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_ICSCR3_HSICAL_0 (0x01UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR3_HSITRIM_Pos (16UL) +#define RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00010000 */ +#define RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00020000 */ +#define RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00040000 */ +#define RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00080000 */ +#define RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00100000 */ + +/******************** Bit definition for RCC_CFGR1 register *****************/ +#define RCC_CFGR1_SW_Pos (0UL) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (2UL) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_MCOSEL_Pos (24UL) +#define RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk /*!< MCOSEL[3:0] bits (Clock output selection) */ +#define RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCOPRE_Pos (28UL) +#define RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk /*!< MCO[220] (Prescaler) */ +#define RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CFGR2 register ******************/ +#define RCC_CFGR2_HPRE_Pos (0UL) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< HPRE[2:0] bits (AHB prescaler) */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE1_Pos (4UL) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< PPRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8UL) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< PPRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_PPRE7_Pos (4UL) +#define RCC_CFGR3_PPRE7_Msk (0x7UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000070 */ +#define RCC_CFGR3_PPRE7 RCC_CFGR3_PPRE7_Msk /*!< PPRE7[2:0] bits (APB7 prescaler) */ +#define RCC_CFGR3_PPRE7_0 (0x1UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000010 */ +#define RCC_CFGR3_PPRE7_1 (0x2UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000020 */ +#define RCC_CFGR3_PPRE7_2 (0x4UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for RCC_PLL1CFGR register ***************/ +#define RCC_PLL1CFGR_PLL1SRC_Pos (0UL) +#define RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000003 */ +#define RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk +#define RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR_PLL1RGE_Pos (2UL) +#define RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x0000000C */ +#define RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk +#define RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR_PLL1FRACEN_Pos (4UL) +#define RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk +#define RCC_PLL1CFGR_PLL1M_Pos (8UL) +#define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700 */ +#define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk +#define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR_PLL1PEN_Pos (16UL) +#define RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk +#define RCC_PLL1CFGR_PLL1QEN_Pos (17UL) +#define RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk +#define RCC_PLL1CFGR_PLL1REN_Pos (18UL) +#define RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRE_Pos (20UL) +#define RCC_PLL1CFGR_PLL1RCLKPRE_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRE_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRE RCC_PLL1CFGR_PLL1RCLKPRE_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos (21UL) +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos (22UL) +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRERDY RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk + +/******************** Bit definition for RCC_PLL1DIVR register ***************/ +#define RCC_PLL1DIVR_PLL1N_Pos (0UL) +#define RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk +#define RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000100 */ +#define RCC_PLL1DIVR_PLL1P_Pos (9UL) +#define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk +#define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000 */ +#define RCC_PLL1DIVR_PLL1Q_Pos (16UL) +#define RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk +#define RCC_PLL1DIVR_PLL1Q_0 (0x01UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR_PLL1Q_1 (0x02UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR_PLL1Q_2 (0x04UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR_PLL1Q_3 (0x08UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR_PLL1Q_4 (0x10UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR_PLL1Q_5 (0x20UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00200020 */ +#define RCC_PLL1DIVR_PLL1Q_6 (0x40UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00400000 */ +#define RCC_PLL1DIVR_PLL1R_Pos (24UL) +#define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk +#define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register ***************/ +#define RCC_PLL1FRACR_PLL1FRACN_Pos (3UL) +#define RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSI1RDYIE_Pos (0UL) +#define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1UL) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3UL) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4UL) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6UL) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_LSI2RDYIE_Pos (16UL) +#define RCC_CIER_LSI2RDYIE_Msk (0x1UL << RCC_CIER_LSI2RDYIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ****************/ +#define RCC_CIFR_LSI1RDYF_Pos (0UL) +#define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1UL) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3UL) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4UL) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6UL) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_HSECSSF_Pos (10UL) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk +#define RCC_CIFR_LSI2RDYF_Pos (16UL) +#define RCC_CIFR_LSI2RDYF_Msk (0x1UL << RCC_CIFR_LSI2RDYF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF_Msk + +/******************** Bit definition for RCC_CICR register ****************/ +#define RCC_CICR_LSI1RDYC_Pos (0UL) +#define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1UL) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3UL) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4UL) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6UL) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_HSECSSC_Pos (10UL) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk +#define RCC_CICR_LSI2RDYC_Pos (16UL) +#define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (0UL) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12UL) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_TSCRST_Pos (16UL) +#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0UL) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1UL) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2UL) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIODRST_Pos (3UL) +#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk +#define RCC_AHB2RSTR_GPIOERST_Pos (4UL) +#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk +#define RCC_AHB2RSTR_GPIOGRST_Pos (6UL) +#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7UL) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk +#define RCC_AHB2RSTR_OTGRST_Pos (14UL) +#define RCC_AHB2RSTR_OTGRST_Msk (0x1UL << RCC_AHB2RSTR_OTGRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_OTGRST RCC_AHB2RSTR_OTGRST_Msk +#define RCC_AHB2RSTR_AESRST_Pos (16UL) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk +#define RCC_AHB2RSTR_HASHRST_Pos (17UL) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk +#define RCC_AHB2RSTR_RNGRST_Pos (18UL) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk +#define RCC_AHB2RSTR_SAESRST_Pos (19UL) +#define RCC_AHB2RSTR_SAESRST_Msk (0x1UL << RCC_AHB2RSTR_SAESRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_SAESRST RCC_AHB2RSTR_SAESRST_Msk +#define RCC_AHB2RSTR_HSEMRST_Pos (20UL) +#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk +#define RCC_AHB2RSTR_PKARST_Pos (21UL) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_ADC4RST_Pos (5UL) +#define RCC_AHB4RSTR_ADC4RST_Msk (0x1UL << RCC_AHB4RSTR_ADC4RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_ADC4RST RCC_AHB4RSTR_ADC4RST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_RADIORST_Pos (0UL) +#define RCC_AHB5RSTR_RADIORST_Msk (0x1UL << RCC_AHB5RSTR_RADIORST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_RADIORST RCC_AHB5RSTR_RADIORST_Msk +#define RCC_AHB5RSTR_PTACONVRST_Pos (1UL) +#define RCC_AHB5RSTR_PTACONVRST_Msk (0x1UL << RCC_AHB5RSTR_PTACONVRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_PTACONVRST RCC_AHB5RSTR_PTACONVRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0UL) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1UL) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2UL) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14UL) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17UL) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18UL) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21UL) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22UL) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_I2C4RST_Pos (1UL) +#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5UL) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (11UL) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12UL) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14UL) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17UL) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18UL) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (21UL) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk + +/******************** Bit definition for RCC_APB7RSTR register **************/ +#define RCC_APB7RSTR_SYSCFGRST_Pos (1UL) +#define RCC_APB7RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB7RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */ +#define RCC_APB7RSTR_SYSCFGRST RCC_APB7RSTR_SYSCFGRST_Msk +#define RCC_APB7RSTR_SPI3RST_Pos (5UL) +#define RCC_APB7RSTR_SPI3RST_Msk (0x1UL << RCC_APB7RSTR_SPI3RST_Pos) /*!< 0x00000020 */ +#define RCC_APB7RSTR_SPI3RST RCC_APB7RSTR_SPI3RST_Msk +#define RCC_APB7RSTR_LPUART1RST_Pos (6UL) +#define RCC_APB7RSTR_LPUART1RST_Msk (0x1UL << RCC_APB7RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB7RSTR_LPUART1RST RCC_APB7RSTR_LPUART1RST_Msk +#define RCC_APB7RSTR_I2C3RST_Pos (7UL) +#define RCC_APB7RSTR_I2C3RST_Msk (0x1UL << RCC_APB7RSTR_I2C3RST_Pos) /*!< 0x00000080 */ +#define RCC_APB7RSTR_I2C3RST RCC_APB7RSTR_I2C3RST_Msk +#define RCC_APB7RSTR_LPTIM1RST_Pos (11UL) +#define RCC_APB7RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB7RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB7RSTR_LPTIM1RST RCC_APB7RSTR_LPTIM1RST_Msk +#define RCC_APB7RSTR_COMPRST_Pos (15UL) +#define RCC_APB7RSTR_COMPRST_Msk (0x1UL << RCC_APB7RSTR_COMPRST_Pos) /*!< 0x00008000 */ +#define RCC_APB7RSTR_COMPRST RCC_APB7RSTR_COMPRST_Msk +#define RCC_APB7RSTR_VREFRST_Pos (20UL) +#define RCC_APB7RSTR_VREFRST_Msk (0x1UL << RCC_APB7RSTR_VREFRST_Pos) /*!< 0x00100000 */ +#define RCC_APB7RSTR_VREFRST RCC_APB7RSTR_VREFRST_Msk + +/******************** Bit definition for RCC_AHB1ENR register **************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (0UL) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_FLASHEN_Pos (8UL) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12UL) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_TSCEN_Pos (16UL) +#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk +#define RCC_AHB1ENR_RAMCFGEN_Pos (17UL) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk +#define RCC_AHB1ENR_GTZC1EN_Pos (24UL) +#define RCC_AHB1ENR_GTZC1EN_Msk (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1ENR_GTZC1EN RCC_AHB1ENR_GTZC1EN_Msk +#define RCC_AHB1ENR_SRAM1EN_Pos (31UL) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register **************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0UL) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1UL) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2UL) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIODEN_Pos (3UL) +#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk +#define RCC_AHB2ENR_GPIOEEN_Pos (4UL) +#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk +#define RCC_AHB2ENR_GPIOGEN_Pos (6UL) +#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7UL) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk +#define RCC_AHB2ENR_OTGEN_Pos (14UL) +#define RCC_AHB2ENR_OTGEN_Msk (0x1UL << RCC_AHB2ENR_OTGEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_OTGEN RCC_AHB2ENR_OTGEN_Msk +#define RCC_AHB2ENR_OTGHSPHYEN_Pos (15UL) +#define RCC_AHB2ENR_OTGHSPHYEN_Msk (0x1UL << RCC_AHB2ENR_OTGHSPHYEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB2ENR_OTGHSPHYEN RCC_AHB2ENR_OTGHSPHYEN_Msk +#define RCC_AHB2ENR_AESEN_Pos (16UL) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk +#define RCC_AHB2ENR_HASHEN_Pos (17UL) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk +#define RCC_AHB2ENR_RNGEN_Pos (18UL) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk +#define RCC_AHB2ENR_SAESEN_Pos (19UL) +#define RCC_AHB2ENR_SAESEN_Msk (0x1UL << RCC_AHB2ENR_SAESEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_SAESEN RCC_AHB2ENR_SAESEN_Msk +#define RCC_AHB2ENR_HSEMEN_Pos (20UL) +#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk +#define RCC_AHB2ENR_PKAEN_Pos (21UL) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30UL) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB4ENR register **************/ +#define RCC_AHB4ENR_PWREN_Pos (2UL) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk +#define RCC_AHB4ENR_ADC4EN_Pos (5UL) +#define RCC_AHB4ENR_ADC4EN_Msk (0x1UL << RCC_AHB4ENR_ADC4EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_ADC4EN RCC_AHB4ENR_ADC4EN_Msk + +/******************** Bit definition for RCC_AHB5ENR register **************/ +#define RCC_AHB5ENR_RADIOEN_Pos (0UL) +#define RCC_AHB5ENR_RADIOEN_Msk (0x1UL << RCC_AHB5ENR_RADIOEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_RADIOEN RCC_AHB5ENR_RADIOEN_Msk +#define RCC_AHB5ENR_PTACONVEN_Pos (1UL) +#define RCC_AHB5ENR_PTACONVEN_Msk (0x1UL << RCC_AHB5ENR_PTACONVEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_PTACONVEN RCC_AHB5ENR_PTACONVEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0UL) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1UL) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2UL) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11UL) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14UL) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17UL) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18UL) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21UL) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22UL) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_I2C4EN_Pos (1UL) +#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk +#define RCC_APB1ENR2_LPTIM2EN_Pos (5UL) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_TIM1EN_Pos (11UL) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12UL) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14UL) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17UL) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18UL) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (21UL) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk + +/******************** Bit definition for RCC_APB7ENR register **************/ +#define RCC_APB7ENR_SYSCFGEN_Pos (1UL) +#define RCC_APB7ENR_SYSCFGEN_Msk (0x1UL << RCC_APB7ENR_SYSCFGEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7ENR_SYSCFGEN RCC_APB7ENR_SYSCFGEN_Msk +#define RCC_APB7ENR_SPI3EN_Pos (5UL) +#define RCC_APB7ENR_SPI3EN_Msk (0x1UL << RCC_APB7ENR_SPI3EN_Pos) /*!< 0x00000020 */ +#define RCC_APB7ENR_SPI3EN RCC_APB7ENR_SPI3EN_Msk +#define RCC_APB7ENR_LPUART1EN_Pos (6UL) +#define RCC_APB7ENR_LPUART1EN_Msk (0x1UL << RCC_APB7ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB7ENR_LPUART1EN RCC_APB7ENR_LPUART1EN_Msk +#define RCC_APB7ENR_I2C3EN_Pos (7UL) +#define RCC_APB7ENR_I2C3EN_Msk (0x1UL << RCC_APB7ENR_I2C3EN_Pos) /*!< 0x00000080 */ +#define RCC_APB7ENR_I2C3EN RCC_APB7ENR_I2C3EN_Msk +#define RCC_APB7ENR_LPTIM1EN_Pos (11UL) +#define RCC_APB7ENR_LPTIM1EN_Msk (0x1UL << RCC_APB7ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB7ENR_LPTIM1EN RCC_APB7ENR_LPTIM1EN_Msk +#define RCC_APB7ENR_COMPEN_Pos (15UL) +#define RCC_APB7ENR_COMPEN_Msk (0x1UL << RCC_APB7ENR_COMPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7ENR_COMPEN RCC_APB7ENR_COMPEN_Msk +#define RCC_APB7ENR_VREFEN_Pos (20UL) +#define RCC_APB7ENR_VREFEN_Msk (0x1UL << RCC_APB7ENR_VREFEN_Pos) /*!< 0x00100000 */ +#define RCC_APB7ENR_VREFEN RCC_APB7ENR_VREFEN_Msk +#define RCC_APB7ENR_RTCAPBEN_Pos (21UL) +#define RCC_APB7ENR_RTCAPBEN_Msk (0x1UL << RCC_APB7ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7ENR_RTCAPBEN RCC_APB7ENR_RTCAPBEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register **************/ +#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0UL) +#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/ +#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk +#define RCC_AHB1SMENR_FLASHSMEN_Pos (8UL) +#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12UL) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk +#define RCC_AHB1SMENR_TSCSMEN_Pos (16UL) +#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk +#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17UL) +#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk +#define RCC_AHB1SMENR_GTZC1SMEN_Pos (24UL) +#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk +#define RCC_AHB1SMENR_ICACHESMEN_Pos (29UL) +#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk +#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31UL) +#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register **************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0UL) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1UL) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2UL) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIODSMEN_Pos (3UL) +#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk +#define RCC_AHB2SMENR_GPIOESMEN_Pos (4UL) +#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk +#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6UL) +#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7UL) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk +#define RCC_AHB2SMENR_OTGSMEN_Pos (14UL) +#define RCC_AHB2SMENR_OTGSMEN_Msk (0x1UL << RCC_AHB2SMENR_OTGSMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2SMENR_OTGSMEN RCC_AHB2SMENR_OTGSMEN_Msk +#define RCC_AHB2SMENR_OTGHSPHYSMEN_Pos (15UL) +#define RCC_AHB2SMENR_OTGHSPHYSMEN_Msk (0x1UL << RCC_AHB2SMENR_OTGHSPHYSMEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB2SMENR_OTGHSPHYSMEN RCC_AHB2SMENR_OTGHSPHYSMEN_Msk +#define RCC_AHB2SMENR_AESSMEN_Pos (16UL) +#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk +#define RCC_AHB2SMENR_HASHSMEN_Pos (17UL) +#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk +#define RCC_AHB2SMENR_RNGSMEN_Pos (18UL) +#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk +#define RCC_AHB2SMENR_SAESSMEN_Pos (19UL) +#define RCC_AHB2SMENR_SAESSMEN_Msk (0x1UL << RCC_AHB2SMENR_SAESSMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2SMENR_SAESSMEN RCC_AHB2SMENR_SAESSMEN_Msk +#define RCC_AHB2SMENR_PKASMEN_Pos (21UL) +#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk +#define RCC_AHB2SMENR_SRAM2SMEN_Pos (30UL) +#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk + +/******************** Bit definition for RCC_AHB4SMENR register **************/ +#define RCC_AHB4SMENR_PWRSMEN_Pos (2UL) +#define RCC_AHB4SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB4SMENR_PWRSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4SMENR_PWRSMEN RCC_AHB4SMENR_PWRSMEN_Msk +#define RCC_AHB4SMENR_ADC4SMEN_Pos (5UL) +#define RCC_AHB4SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB4SMENR_ADC4SMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4SMENR_ADC4SMEN RCC_AHB4SMENR_ADC4SMEN_Msk + +/******************** Bit definition for RCC_AHB5SMENR register **************/ +#define RCC_AHB5SMENR_RADIOSMEN_Pos (0UL) +#define RCC_AHB5SMENR_RADIOSMEN_Msk (0x1UL << RCC_AHB5SMENR_RADIOSMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5SMENR_RADIOSMEN RCC_AHB5SMENR_RADIOSMEN_Msk +#define RCC_AHB5SMENR_PTACONVSMEN_Pos (1UL) +#define RCC_AHB5SMENR_PTACONVSMEN_Msk (0x1UL << RCC_AHB5SMENR_PTACONVSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5SMENR_PTACONVSMEN RCC_AHB5SMENR_PTACONVSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0UL) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_TIM3SMEN_Pos (1UL) +#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk +#define RCC_APB1SMENR1_TIM4SMEN_Pos (2UL) +#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11UL) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_SPI2SMEN_Pos (14UL) +#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17UL) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_USART3SMEN_Pos (18UL) +#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21UL) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk +#define RCC_APB1SMENR1_I2C2SMEN_Pos (22UL) +#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_I2C4SMEN_Pos (1UL) +#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5UL) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_TIM1SMEN_Pos (11UL) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12UL) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14UL) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17UL) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18UL) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk +#define RCC_APB2SMENR_SAI1SMEN_Pos (21UL) +#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk + +/******************** Bit definition for RCC_APB7SMENR register **************/ +#define RCC_APB7SMENR_SYSCFGSMEN_Pos (1UL) +#define RCC_APB7SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB7SMENR_SYSCFGSMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7SMENR_SYSCFGSMEN RCC_APB7SMENR_SYSCFGSMEN_Msk +#define RCC_APB7SMENR_SPI3SMEN_Pos (5UL) +#define RCC_APB7SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB7SMENR_SPI3SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB7SMENR_SPI3SMEN RCC_APB7SMENR_SPI3SMEN_Msk +#define RCC_APB7SMENR_LPUART1SMEN_Pos (6UL) +#define RCC_APB7SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */ +#define RCC_APB7SMENR_LPUART1SMEN RCC_APB7SMENR_LPUART1SMEN_Msk +#define RCC_APB7SMENR_I2C3SMEN_Pos (7UL) +#define RCC_APB7SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB7SMENR_I2C3SMEN_Pos) /*!< 0x00000080 */ +#define RCC_APB7SMENR_I2C3SMEN RCC_APB7SMENR_I2C3SMEN_Msk +#define RCC_APB7SMENR_LPTIM1SMEN_Pos (11UL) +#define RCC_APB7SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPTIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB7SMENR_LPTIM1SMEN RCC_APB7SMENR_LPTIM1SMEN_Msk +#define RCC_APB7SMENR_COMPSMEN_Pos (15UL) +#define RCC_APB7SMENR_COMPSMEN_Msk (0x1UL << RCC_APB7SMENR_COMPSMEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7SMENR_COMPSMEN RCC_APB7SMENR_COMPSMEN_Msk +#define RCC_APB7SMENR_VREFSMEN_Pos (20UL) +#define RCC_APB7SMENR_VREFSMEN_Msk (0x1UL << RCC_APB7SMENR_VREFSMEN_Pos) /*!< 0x00100000 */ +#define RCC_APB7SMENR_VREFSMEN RCC_APB7SMENR_VREFSMEN_Msk +#define RCC_APB7SMENR_RTCAPBSMEN_Pos (21UL) +#define RCC_APB7SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB7SMENR_RTCAPBSMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7SMENR_RTCAPBSMEN RCC_APB7SMENR_RTCAPBSMEN_Msk + +/******************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_USART1SEL_Pos (0UL) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2UL) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_USART3SEL_Pos (4UL) +#define RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk +#define RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR1_I2C1SEL_Pos (10UL) +#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk +#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_I2C2SEL_Pos (12UL) +#define RCC_CCIPR1_I2C2SEL_Msk (0x3UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_I2C2SEL RCC_CCIPR1_I2C2SEL_Msk +#define RCC_CCIPR1_I2C2SEL_0 (0x1UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_I2C2SEL_1 (0x2UL << RCC_CCIPR1_I2C2SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR1_I2C4SEL_Pos (14UL) +#define RCC_CCIPR1_I2C4SEL_Msk (0x3UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_I2C4SEL RCC_CCIPR1_I2C4SEL_Msk +#define RCC_CCIPR1_I2C4SEL_0 (0x1UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_I2C4SEL_1 (0x2UL << RCC_CCIPR1_I2C4SEL_Pos) /*!< 0x00008000 */ +#define RCC_CCIPR1_SPI2SEL_Pos (16UL) +#define RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk +#define RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR1_LPTIM2SEL_Pos (18UL) +#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk +#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (20UL) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_SYSTICKSEL_Pos (22UL) +#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk +#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */ +#define RCC_CCIPR1_TIMICSEL_Pos (31UL) +#define RCC_CCIPR1_TIMICSEL_Msk (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */ +#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk + +/******************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_SAI1SEL_Pos (5UL) +#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */ +#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk +#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_RNGSEL_Pos (12UL) +#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk +#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR2_OTGHSSEL_Pos (28UL) +#define RCC_CCIPR2_OTGHSSEL_Msk (0x3UL << RCC_CCIPR2_OTGHSSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR2_OTGHSSEL RCC_CCIPR2_OTGHSSEL_Msk +#define RCC_CCIPR2_OTGHSSEL_0 (0x1UL << RCC_CCIPR2_OTGHSSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR2_OTGHSSEL_1 (0x2UL << RCC_CCIPR2_OTGHSSEL_Pos) /*!< 0x20000000 */ +#define RCC_CCIPR2_ASSEL_Pos (30UL) +#define RCC_CCIPR2_ASSEL_Msk (0x1UL << RCC_CCIPR2_ASSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_ASSEL RCC_CCIPR2_ASSEL_Msk + +/******************** Bit definition for RCC_CCIPR3 register ***************/ +#define RCC_CCIPR3_LPUART1SEL_Pos (0UL) +#define RCC_CCIPR3_LPUART1SEL_Msk (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk +#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_SPI3SEL_Pos (3UL) +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ +#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk +#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_I2C3SEL_Pos (6UL) +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR3_LPTIM1SEL_Pos (10UL) +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR3_ADCSEL_Pos (12UL) +#define RCC_CCIPR3_ADCSEL_Msk (0x7UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR3_ADCSEL RCC_CCIPR3_ADCSEL_Msk +#define RCC_CCIPR3_ADCSEL_0 (0x1UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCSEL_1 (0x2UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCSEL_2 (0x4UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_BDCR1 register ******************/ +#define RCC_BDCR1_LSEON_Pos (0UL) +#define RCC_BDCR1_LSEON_Msk (0x1UL << RCC_BDCR1_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR1_LSEON RCC_BDCR1_LSEON_Msk +#define RCC_BDCR1_LSERDY_Pos (1UL) +#define RCC_BDCR1_LSERDY_Msk (0x1UL << RCC_BDCR1_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR1_LSERDY RCC_BDCR1_LSERDY_Msk +#define RCC_BDCR1_LSEBYP_Pos (2UL) +#define RCC_BDCR1_LSEBYP_Msk (0x1UL << RCC_BDCR1_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR1_LSEBYP RCC_BDCR1_LSEBYP_Msk +#define RCC_BDCR1_LSEDRV_Pos (3UL) +#define RCC_BDCR1_LSEDRV_Msk (0x3UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR1_LSEDRV RCC_BDCR1_LSEDRV_Msk +#define RCC_BDCR1_LSEDRV_0 (0x1UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR1_LSEDRV_1 (0x2UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR1_LSECSSON_Pos (5UL) +#define RCC_BDCR1_LSECSSON_Msk (0x1UL << RCC_BDCR1_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR1_LSECSSON RCC_BDCR1_LSECSSON_Msk +#define RCC_BDCR1_LSECSSD_Pos (6UL) +#define RCC_BDCR1_LSECSSD_Msk (0x1UL << RCC_BDCR1_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR1_LSECSSD RCC_BDCR1_LSECSSD_Msk +#define RCC_BDCR1_LSESYSEN_Pos (7UL) +#define RCC_BDCR1_LSESYSEN_Msk (0x1UL << RCC_BDCR1_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR1_LSESYSEN RCC_BDCR1_LSESYSEN_Msk +#define RCC_BDCR1_RTCSEL_Pos (8UL) +#define RCC_BDCR1_RTCSEL_Msk (0x3UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR1_RTCSEL RCC_BDCR1_RTCSEL_Msk +#define RCC_BDCR1_RTCSEL_0 (0x1UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR1_RTCSEL_1 (0x2UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR1_LSESYSRDY_Pos (11UL) +#define RCC_BDCR1_LSESYSRDY_Msk (0x1UL << RCC_BDCR1_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR1_LSESYSRDY RCC_BDCR1_LSESYSRDY_Msk +#define RCC_BDCR1_LSEGFON_Pos (12UL) +#define RCC_BDCR1_LSEGFON_Msk (0x1UL << RCC_BDCR1_LSEGFON_Pos) /*!< 0x00001000 */ +#define RCC_BDCR1_LSEGFON RCC_BDCR1_LSEGFON_Msk +#define RCC_BDCR1_LSETRIM_Pos (13UL) +#define RCC_BDCR1_LSETRIM_Msk (0x3UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00006000 */ +#define RCC_BDCR1_LSETRIM RCC_BDCR1_LSETRIM_Msk +#define RCC_BDCR1_LSETRIM_0 (0x1UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00002000 */ +#define RCC_BDCR1_LSETRIM_1 (0x2UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00004000 */ +#define RCC_BDCR1_BDRST_Pos (16UL) +#define RCC_BDCR1_BDRST_Msk (0x1UL << RCC_BDCR1_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR1_BDRST RCC_BDCR1_BDRST_Msk +#define RCC_BDCR1_RADIOSTSEL_Pos (18UL) +#define RCC_BDCR1_RADIOSTSEL_Msk (0x3UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x000C0000 */ +#define RCC_BDCR1_RADIOSTSEL RCC_BDCR1_RADIOSTSEL_Msk +#define RCC_BDCR1_RADIOSTSEL_0 (0x1UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00040000 */ +#define RCC_BDCR1_RADIOSTSEL_1 (0x2UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00080000 */ +#define RCC_BDCR1_LSCOEN_Pos (24UL) +#define RCC_BDCR1_LSCOEN_Msk (0x1UL << RCC_BDCR1_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR1_LSCOEN RCC_BDCR1_LSCOEN_Msk +#define RCC_BDCR1_LSCOSEL_Pos (25UL) +#define RCC_BDCR1_LSCOSEL_Msk (0x1UL << RCC_BDCR1_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR1_LSCOSEL RCC_BDCR1_LSCOSEL_Msk +#define RCC_BDCR1_LSI1ON_Pos (26UL) +#define RCC_BDCR1_LSI1ON_Msk (0x1UL << RCC_BDCR1_LSI1ON_Pos) /*!< 0x04000000 */ +#define RCC_BDCR1_LSI1ON RCC_BDCR1_LSI1ON_Msk +#define RCC_BDCR1_LSI1RDY_Pos (27UL) +#define RCC_BDCR1_LSI1RDY_Msk (0x1UL << RCC_BDCR1_LSI1RDY_Pos) /*!< 0x08000000 */ +#define RCC_BDCR1_LSI1RDY RCC_BDCR1_LSI1RDY_Msk +#define RCC_BDCR1_LSI1PREDIV_Pos (28UL) +#define RCC_BDCR1_LSI1PREDIV_Msk (0x1UL << RCC_BDCR1_LSI1PREDIV_Pos) /*!< 0x10000000 */ +#define RCC_BDCR1_LSI1PREDIV RCC_BDCR1_LSI1PREDIV_Msk +#define RCC_BDCR1_LSI2ON_Pos (29UL) +#define RCC_BDCR1_LSI2ON_Msk (0x1UL << RCC_BDCR1_LSI2ON_Pos) /*!< 0x20000000 */ +#define RCC_BDCR1_LSI2ON RCC_BDCR1_LSI2ON_Msk +#define RCC_BDCR1_LSI2RDY_Pos (30UL) +#define RCC_BDCR1_LSI2RDY_Msk (0x1UL << RCC_BDCR1_LSI2RDY_Pos) /*!< 0x40000000 */ +#define RCC_BDCR1_LSI2RDY RCC_BDCR1_LSI2RDY_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_RMVF_Pos (23UL) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25UL) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26UL) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27UL) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28UL) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29UL) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30UL) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31UL) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_BDCR2 register *******************/ +#define RCC_BDCR2_LSI2MODE_Pos (0UL) +#define RCC_BDCR2_LSI2MODE_Msk (0x7UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000007 */ +#define RCC_BDCR2_LSI2MODE RCC_BDCR2_LSI2MODE_Msk +#define RCC_BDCR2_LSI2MODE_0 (0x1UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000001 */ +#define RCC_BDCR2_LSI2MODE_1 (0x2UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000002 */ +#define RCC_BDCR2_LSI2MODE_2 (0x4UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000004 */ +#define RCC_BDCR2_LSI2CFG_Pos (4UL) +#define RCC_BDCR2_LSI2CFG_Msk (0xFUL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x000000F0 */ +#define RCC_BDCR2_LSI2CFG RCC_BDCR2_LSI2CFG_Msk +#define RCC_BDCR2_LSI2CFG_0 (0x1UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000010 */ +#define RCC_BDCR2_LSI2CFG_1 (0x2UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000020 */ +#define RCC_BDCR2_LSI2CFG_2 (0x4UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000040 */ +#define RCC_BDCR2_LSI2CFG_3 (0x8UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000080 */ + +/******************** Bit definition for RCC_SECCFGR register **************/ +#define RCC_SECCFGR_HSISEC_Pos (0UL) +#define RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk +#define RCC_SECCFGR_HSESEC_Pos (1UL) +#define RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk +#define RCC_SECCFGR_LSISEC_Pos (3UL) +#define RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk +#define RCC_SECCFGR_LSESEC_Pos (4UL) +#define RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk +#define RCC_SECCFGR_SYSCLKSEC_Pos (5UL) +#define RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk +#define RCC_SECCFGR_PRESCSEC_Pos (6UL) +#define RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk +#define RCC_SECCFGR_PLL1SEC_Pos (7UL) +#define RCC_SECCFGR_PLL1SEC_Msk (0x1UL << RCC_SECCFGR_PLL1SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR_PLL1SEC RCC_SECCFGR_PLL1SEC_Msk +#define RCC_SECCFGR_RMVFSEC_Pos (12UL) +#define RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk + +/******************** Bit definition for RCC_PRIVCFGR register **************/ +#define RCC_PRIVCFGR_SPRIV_Pos (0UL) +#define RCC_PRIVCFGR_SPRIV_Msk (0x1UL << RCC_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR_SPRIV RCC_PRIVCFGR_SPRIV_Msk +#define RCC_PRIVCFGR_NSPRIV_Pos (1UL) +#define RCC_PRIVCFGR_NSPRIV_Msk (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk + +/******************** Bit definition for RCC_ASCR register **************/ +#define RCC_ASCR_CEN_Pos (0UL) +#define RCC_ASCR_CEN RCC_ASCR_CEN_Msk +#define RCC_ASCR_CEN_Msk (0x1UL << RCC_ASCR_CEN_Pos) /*!< 0x00000001 */ +#define RCC_ASCR_PSC_Pos (8UL) +#define RCC_ASCR_PSC_Msk (0x7FUL << RCC_ASCR_PSC_Pos) /*!< 0x00007F00 */ +#define RCC_ASCR_PSC RCC_ASCR_PSC_Msk +#define RCC_ASCR_CPS_Pos (16UL) +#define RCC_ASCR_CPS_Msk (0x7FUL << RCC_ASCR_CPS_Pos) /*!< 0x007F0000 */ +#define RCC_ASCR_CPS RCC_ASCR_CPS_Msk + +/******************** Bit definition for RCC_ASIER register **************/ +#define RCC_ASIER_CAIE_Pos (0UL) +#define RCC_ASIER_CAIE_Msk (0x1UL << RCC_ASIER_CAIE_Pos) /*!< 0x00000001 */ +#define RCC_ASIER_CAIE RCC_ASIER_CAIE_Msk +#define RCC_ASIER_COIE_Pos (1UL) +#define RCC_ASIER_COIE_Msk (0x1UL << RCC_ASIER_COIE_Pos) /*!< 0x00000002 */ +#define RCC_ASIER_COIE RCC_ASIER_COIE_Msk +#define RCC_ASIER_CAEIE_Pos (2UL) +#define RCC_ASIER_CAEIE_Msk (0x1UL << RCC_ASIER_CAEIE_Pos) /*!< 0x00000004 */ +#define RCC_ASIER_CAEIE RCC_ASIER_CAEIE_Msk + +/******************** Bit definition for RCC_ASSR register **************/ +#define RCC_ASSR_CAF_Pos (0UL) +#define RCC_ASSR_CAF_Msk (0x1UL << RCC_ASSR_CAF_Pos) /*!< 0x00000001 */ +#define RCC_ASSR_CAF RCC_ASSR_CAF_Msk +#define RCC_ASSR_COF_Pos (1UL) +#define RCC_ASSR_COF_Msk (0x1UL << RCC_ASSR_COF_Pos) /*!< 0x00000002 */ +#define RCC_ASSR_COF RCC_ASSR_COF_Msk +#define RCC_ASSR_CAEF_Pos (2UL) +#define RCC_ASSR_CAEF_Msk (0x1UL << RCC_ASSR_CAEF_Pos) /*!< 0x00000004 */ +#define RCC_ASSR_CAEF RCC_ASSR_CAEF_Msk + +/******************** Bit definition for RCC_ASCNTR register **************/ +#define RCC_ASCNTR_CNT_Pos (0UL) +#define RCC_ASCNTR_CNT_Msk (0xFFFFFUL << RCC_ASCNTR_CNT_Pos) /*!< 0x000FFFFF */ +#define RCC_ASCNTR_CNT RCC_ASCNTR_CNT_Msk + +/******************** Bit definition for RCC_ASARR register **************/ +#define RCC_ASARR_AR_Pos (0UL) +#define RCC_ASARR_AR_Msk (0xFFFFFUL << RCC_ASARR_AR_Pos) /*!< 0x000FFFFF */ +#define RCC_ASARR_AR RCC_ASARR_AR_Msk + +/******************** Bit definition for RCC_ASCAR register **************/ +#define RCC_ASCAR_CA_Pos (0UL) +#define RCC_ASCAR_CA_Msk (0x7FFFFFFUL << RCC_ASCAR_CA_Pos) /*!< 0x07FFFFFF */ +#define RCC_ASCAR_CA RCC_ASCAR_CA_Msk + +/******************** Bit definition for RCC_ASCOR register **************/ +#define RCC_ASCOR_CO_Pos (0UL) +#define RCC_ASCOR_CO_Msk (0xFFFFFUL << RCC_ASCOR_CO_Pos) /*!< 0x000FFFFF */ +#define RCC_ASCOR_CO RCC_ASCOR_CO_Msk + +/******************** Bit definition for RCC_CFGR4 register *******************/ +#define RCC_CFGR4_HPRE5_Pos (0UL) +#define RCC_CFGR4_HPRE5_Msk (0x7UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000007 */ +#define RCC_CFGR4_HPRE5 RCC_CFGR4_HPRE5_Msk +#define RCC_CFGR4_HPRE5_0 (0x1UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000001 */ +#define RCC_CFGR4_HPRE5_1 (0x2UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000002 */ +#define RCC_CFGR4_HPRE5_2 (0x4UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR4_HDIV5_Pos (4UL) +#define RCC_CFGR4_HDIV5_Msk (0x1UL << RCC_CFGR4_HDIV5_Pos) /*!< 0x00000080 */ +#define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk + +/******************** Bit definition for RCC_RADIOENR register **************/ +#define RCC_RADIOENR_BBCLKEN_Pos (1UL) +#define RCC_RADIOENR_BBCLKEN_Msk (0x1UL << RCC_RADIOENR_BBCLKEN_Pos) /*!< 0x00000002 */ +#define RCC_RADIOENR_BBCLKEN RCC_RADIOENR_BBCLKEN_Msk +#define RCC_RADIOENR_STRADIOCLKON_Pos (16UL) +#define RCC_RADIOENR_STRADIOCLKON_Msk (0x1UL << RCC_RADIOENR_STRADIOCLKON_Pos) /*!< 0x00010000 */ +#define RCC_RADIOENR_STRADIOCLKON RCC_RADIOENR_STRADIOCLKON_Msk +#define RCC_RADIOENR_RADIOCLKRDY_Pos (17UL) +#define RCC_RADIOENR_RADIOCLKRDY_Msk (0x1UL << RCC_RADIOENR_RADIOCLKRDY_Pos) /*!< 0x00020000 */ +#define RCC_RADIOENR_RADIOCLKRDY RCC_RADIOENR_RADIOCLKRDY_Msk + +/******************** Bit definition for RCC_ECSCR1 register *******************/ +#define RCC_ECSCR1_HSETRIM_Pos (16UL) +#define RCC_ECSCR1_HSETRIM_Msk (0x3FUL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x003F0000 */ +#define RCC_ECSCR1_HSETRIM RCC_ECSCR1_HSETRIM_Msk +#define RCC_ECSCR1_HSETRIM_0 (0x1UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00010000 */ +#define RCC_ECSCR1_HSETRIM_1 (0x2UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00020000 */ +#define RCC_ECSCR1_HSETRIM_2 (0x4UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00040000 */ +#define RCC_ECSCR1_HSETRIM_3 (0x8UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00080000 */ +#define RCC_ECSCR1_HSETRIM_4 (0x10UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00100000 */ +#define RCC_ECSCR1_HSETRIM_5 (0x20UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00200000 */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_BUSY_Pos (4UL) +#define RNG_SR_BUSY_Msk (0x1U << RNG_SR_BUSY_Pos) /*!< 0x00000010 */ +#define RNG_SR_BUSY RNG_SR_BUSY_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0UL) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00200F00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0UL) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4UL) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8UL) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12UL) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16UL) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20UL) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22UL) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0UL) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4UL) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8UL) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12UL) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13UL) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16UL) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20UL) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0UL) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2UL) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3UL) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4UL) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5UL) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6UL) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7UL) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8UL) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10UL) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16UL) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0UL) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16UL) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0UL) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16UL) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0UL) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3UL) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4UL) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5UL) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6UL) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7UL) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8UL) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9UL) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10UL) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11UL) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12UL) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13UL) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14UL) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15UL) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16UL) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17UL) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18UL) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19UL) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20UL) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21UL) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23UL) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_TAMPTS_Pos (25UL) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0UL) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OTG HS Instances ******************************/ +#define IS_OTG_HS_INSTANCE(INSTANCE) (((INSTANCE) == OTG_HS_NS) || ((INSTANCE) == OTG_HS_S)) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** USB OTG PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/*********************** USB OTG HCD Instances ********************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/**************************** VREFBUF Instances *******************************/ +#define IS_VREFBUF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == VREFBUF_NS) || ((INSTANCE) == VREFBUF_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* Instances allowed from Non-Secure state - only alias Non-Secure */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_NS) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_COMMON_NS) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS)) + +/***************************** RAMCFG PED Instances *****************************/ +#define IS_RAMCFG_PED_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Erase Instances ********************************/ +#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \ + ((INSTANCE) == GPIOB_NS) || \ + ((INSTANCE) == GPIOC_NS) || \ + ((INSTANCE) == GPIOD_NS) || \ + ((INSTANCE) == GPIOE_NS) || \ + ((INSTANCE) == GPIOG_NS) || \ + ((INSTANCE) == GPIOH_NS)) + +/******************************* GPIO AF Instances ****************************/ +/* On WBA, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On WBA, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** HSEM Lock Instances *****************************/ +#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM_NS) + +#define HSEM_CPU1_LOCKID (HSEM_CR_LOCKID_CURRENT >> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C4_NS)) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS) || \ + ((INSTANCE) == I2C4_NS)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/****************************** OTG HS Instances ******************************/ +#define IS_OTG_HS_INSTANCE(INSTANCE) (((INSTANCE) == OTG_HS_NS)) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_B_NS)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C4_NS)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS) || \ + ((INSTANCE) == I2C4_NS)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || \ + ((INSTANCE) == SPI3_NS)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS)) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || \ + ((INSTANCE) == SPI3_NS)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM2_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM4_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM4_NS)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == USART3_NS)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == USART3_NS)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS) + +/*********************** USB OTG PCD Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS_NS) + +/*********************** USB OTG HCD Instances ********************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS_NS) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS) + +/**************************** VREFBUF Instances *******************************/ +#define IS_VREFBUF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == VREFBUF_NS)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS) + +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** @} */ /* End of group STM32WBAxx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32WBA6Mxx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBA6Mxx_H */ diff --git a/stm32cube/stm32wbaxx/soc/stm32wbaxx.h b/stm32cube/stm32wbaxx/soc/stm32wbaxx.h index 9a61d429d..bc2cfcc0b 100644 --- a/stm32cube/stm32wbaxx/soc/stm32wbaxx.h +++ b/stm32cube/stm32wbaxx/soc/stm32wbaxx.h @@ -58,7 +58,7 @@ #if !defined(STM32WBA50xx) && !defined(STM32WBA52xx) && !defined(STM32WBA54xx) && !defined(STM32WBA55xx) && \ !defined(STM32WBA5Mxx) && !defined(STM32WBA62xx) && !defined(STM32WBA63xx) && !defined(STM32WBA64xx) && \ - !defined(STM32WBA65xx) + !defined(STM32WBA65xx) && !defined(STM32WBA6Mxx) /* #define STM32WBA50xx */ /*!< STM32WBA50xx Devices */ /* #define STM32WBA52xx */ /*!< STM32WBA52xx Devices */ /* #define STM32WBA54xx */ /*!< STM32WBA54xx Devices */ @@ -68,6 +68,7 @@ /* #define STM32WBA63xx */ /*!< STM32WBA63xx Devices */ /* #define STM32WBA64xx */ /*!< STM32WBA64xx Devices */ /* #define STM32WBA65xx */ /*!< STM32WBA65xx Devices */ + /* #define STM32WBA6Mxx */ /*!< STM32WBA6Mxx Devices */ #endif /* !STM32WBA50xx && !STM32WBA52xx ...*/ /* Tip: To avoid modifying this file each time you need to switch between these @@ -86,7 +87,7 @@ * @brief CMSIS Device version number */ #define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WBA_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ @@ -120,6 +121,8 @@ #include "stm32wba64xx.h" #elif defined(STM32WBA65xx) #include "stm32wba65xx.h" +#elif defined(STM32WBA6Mxx) + #include "stm32wba6mxx.h" #else #error "Please select first the target STM32WBAxx device used in your application (in stm32wbaxx.h file)" #endif /* STM32WBA50xx */ diff --git a/stm32cube/stm32wbaxx/soc/system_stm32wbaxx.c b/stm32cube/stm32wbaxx/soc/system_stm32wbaxx.c index fd8a82365..ede3f757d 100644 --- a/stm32cube/stm32wbaxx/soc/system_stm32wbaxx.c +++ b/stm32cube/stm32wbaxx/soc/system_stm32wbaxx.c @@ -104,29 +104,19 @@ #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -/*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ +/*!< The VTOR location information is based on information from the linker with a dependency + on the IDE, the cortex register is updated using the INTVECT_START. +*/ +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)& __vector_table) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void * __Vectors; +#define INTVECT_START ((uint32_t) & __Vectors) +#elif defined(__GNUC__) +extern void * g_pfnVectors; +#define INTVECT_START ((uint32_t)& g_pfnVectors) +#endif /* __ICCARM__*/ /******************************************************************************/ @@ -195,9 +185,7 @@ void SystemInit(void) #endif /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ -#endif /* USER_VECT_TAB_ADDRESS */ + SCB->VTOR = INTVECT_START; #if defined(STM32WBAXX_SI_CUT1_0) /* Work-around for ADC peripheral issue possibly impacting system diff --git a/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_ns.c b/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_ns.c index faed2e672..63da3d463 100644 --- a/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_ns.c +++ b/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_ns.c @@ -78,29 +78,19 @@ #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -/*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#else -#define VECT_TAB_BASE_ADDRESS (FLASH_BASE + 0x00080000U) /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ +/*!< The VTOR location information is based on information from the linker with a dependency + on the IDE, the cortex register is updated using the INTVECT_START. +*/ +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)& __vector_table) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void * __Vectors; +#define INTVECT_START ((uint32_t) & __Vectors) +#elif defined(__GNUC__) +extern void * g_pfnVectors; +#define INTVECT_START ((uint32_t)& g_pfnVectors) +#endif /* __ICCARM__*/ /******************************************************************************/ @@ -162,9 +152,7 @@ void SystemInit(void) #endif /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ -#endif /* USER_VECT_TAB_ADDRESS */ + SCB->VTOR = INTVECT_START; /* Non-secure main application shall call SystemCoreClockUpdate() to update */ /* the SystemCoreClock variable to insure non-secure application relies on */ diff --git a/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_s.c b/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_s.c index 243410f5d..5e2566382 100644 --- a/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_s.c +++ b/stm32cube/stm32wbaxx/soc/system_stm32wbaxx_s.c @@ -118,29 +118,19 @@ #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -/*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ +/*!< The VTOR location information is based on information from the linker with a dependency + on the IDE, the cortex register is updated using the INTVECT_START. +*/ +#if defined(__ICCARM__) +extern uint32_t __vector_table; +#define INTVECT_START ((uint32_t)& __vector_table) +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern void * __Vectors; +#define INTVECT_START ((uint32_t) & __Vectors) +#elif defined(__GNUC__) +extern void * g_pfnVectors; +#define INTVECT_START ((uint32_t)& g_pfnVectors) +#endif /* __ICCARM__*/ /******************************************************************************/ @@ -212,9 +202,7 @@ void SystemInit(void) #endif /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ -#endif /* USER_VECT_TAB_ADDRESS */ + SCB->VTOR = INTVECT_START; #if defined(STM32WBAXX_SI_CUT1_0) /* Work-around for ADC peripheral issue possibly impacting system diff --git a/zephyr/module.yml b/zephyr/module.yml index 7c052c25e..4a319c5dc 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -5,46 +5,46 @@ build: dts_root: . blobs: - path: stm32wba/lib/WBA6_LinkLayer_BLE_Full_lib.a - sha256: fda0c5a80d65e859c249f270b297117f8cff1f38c0ee4fbe0ad9d5b3bfc2813e + sha256: df808d759035bc80d4dd5af10a1ab82593099d144a51d153a559053af1bbeb8e type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.6.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/WBA6_LinkLayer_BLE_Full_lib.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/WBA6_LinkLayer_BLE_Full_lib.a description: "Binary Link Layer library for the STM32WBA6 Bluetooth subsystem" - path: stm32wba/lib/WBA6_LinkLayer_BLE_Basic_lib.a - sha256: aefc7ce2360d12bac52ff38741fcd40cfb0fecf4eff657b2d32b2986dd4165e2 + sha256: 2003891dccf5a9767d283a1176aeb2e4ca3c454a158cdd75c318d9978b712923 type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.6.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/WBA6_LinkLayer_BLE_Basic_lib.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/WBA6_LinkLayer_BLE_Basic_lib.a description: "Binary Link Layer library for the STM32WBA6 Bluetooth subsystem" - path: stm32wba/lib/LinkLayer_BLE_Full_lib.a - sha256: c935072ee0d98ddaec3b7f4a1e502ade9768c3fe8056101823a3f19327a1b148 + sha256: 67d9e6c1690a93190a7766304031069d0672cd4b69a518350bab80f3aa6dc2f9 type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.6.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/LinkLayer_BLE_Full_lib.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/LinkLayer_BLE_Full_lib.a description: "Binary Link Layer library for the STM32WBA5 Bluetooth subsystem" - path: stm32wba/lib/LinkLayer_BLE_Basic_lib.a - sha256: 6a028bba47a11e96d7a63b906d2f1c3c2c5b2d8b0227859f94803c746a1d74b0 + sha256: f525eccdc0a0ce9fb08b29e89dde75eff9a531e8f15ea9eb380e4eeb25d87880 type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.6.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/LinkLayer_BLE_Basic_lib.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/link_layer/ll_cmd_lib/lib/LinkLayer_BLE_Basic_lib.a description: "Binary Link Layer library for the STM32WBA5 Bluetooth subsystem" - path: stm32wba/lib/stm32wba_ble_stack_llo.a - sha256: 70c881f8492ba712c658ab2c4682b60d62bf14d3d55822a611702b32b286c9b1 + sha256: 85eeea0f8986dab87a4e22c00564ed1110759c582b2224ec35baf0ed87ff69d9 type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.6.0/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llo.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llo.a description: "Binary Stack library for the STM32WBA Bluetooth subsystem" - path: stm32wba/lib/stm32wba_ble_stack_llobasic.a - sha256: e4008830f7d3284a8e2634e80120e4f5fb145ec0fdbfa96a0be0b4363b605411 + sha256: d18866746ab0a5aeac209d9613dfba37338d0b051b8f524c9f9cefa970f8065f type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.6.0/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llobasic.a + url: https://github.com/STMicroelectronics/STM32CubeWBA/raw/v1.7.0/Middlewares/ST/STM32_WPAN/ble/stack/lib/stm32wba_ble_stack_llobasic.a description: "Binary Stack library for the STM32WBA Bluetooth subsystem" - path: stm32wb0/lib/stm32wb0x_ble_stack_controller_only.a sha256: 54bf69acaa59afc368132f8170e9910858a2c801538494d8de96fa567c02e233 @@ -54,16 +54,16 @@ blobs: url: https://github.com/STMicroelectronics/STM32CubeWB0/raw/v1.0.0/Middlewares/ST/STM32_BLE/stack/lib/stm32wb0x_ble_stack_controller_only.a description: "Binary Stack library for the STM32WB0 Bluetooth subsystem" - path: stm32wba/lib/WBA6_LinkLayer15_4_Zephyr.a - sha256: e89b955174e4aa65d9867bdc7bfc5c1ad198fc5f4912b01bea768f2b7a891b40 + sha256: e67f4270429f3e6399b26aea82a302e85576efb43a47b194648f98b9e9c7805b type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_6_0/WBA6_LinkLayer15_4_Zephyr.a + url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_7_0/WBA6_LinkLayer15_4_Zephyr.a description: "Binary Link Layer library for the STM32WBA6 802.15.4 subsystem" - path: stm32wba/lib/WBA6_LinkLayer_Thread_lib_Zephyr.a - sha256: 2b8c46d3d8afbe99f89fc4e6cf9a155d28ee273ee5a334a53f6b3f6e4718a944 + sha256: 23e377b1ef70119f1115c57d162065168d860dd71477c3e247fb295f7a728989 type: lib - version: '1.6.0' + version: '1.7.0' license-path: zephyr/blobs/stm32wba/lib/license.md - url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_6_0/WBA6_LinkLayer_Thread_lib_Zephyr.a + url: https://github.com/stm32-hotspot/STM32WBA-Zephyr-custom-binaries/raw/main/lib/1_7_0/WBA6_LinkLayer_Thread_lib_Zephyr.a description: "Binary Link Layer library for the STM32WBA6 Thread subsystem"