cpu

126 Articles

Homebrew CPU Gets A Beautiful Rotating Cube Demo

February 19, 2025 by 10 Comments

[James Sharman] designed and built his own 8-bit computer from scratch using TTL logic chips, including a VGA adapter, and you can watch it run a glorious rotating cube demo in the video below.

The rotating cube is the product of roughly 3,500 lines of custom assembly code and looks fantastic, running at 30 frames per second with shading effects from multiple light sources. Great results considering the computing power of his system is roughly on par with vintage 8-bit home computers, and the graphics capabilities are limited. [James]’s computer uses a tile map instead of a frame buffer, so getting 3D content rendered was a challenge.

The video is about 20 seconds of demo followed by a detailed technical discussion on how exactly one implements everything required for a 3D cube, from basic math to optimization. If a deep dive into that sort of thing is up your alley, give it a watch!

We’ve featured [James]’ fascinating work on his homebrew computer before. Here’s more detail on his custom VGA adapter, and his best shot at making it (kinda) run DOOM.

Continue reading “Homebrew CPU Gets A Beautiful Rotating Cube Demo” →

Going Minimal: 64×4, The Fun In Functional Computing

January 22, 2025 by 38 Comments

If you’ve ever wondered what makes a computer tick, the Minimal 64×4 by [Slu4] is bound to grab your attention. It’s not a modern powerhouse, but a thoughtfully crafted throwback to the essence of computing. With just 61 logic ICs, VGA output, PS/2 input, and SSD storage, this DIY wonder packs four times the processing power of a Commodore 64.

What sets [Slu4]’s efforts apart is his refusal to follow the beaten track of CPU development. He imposes strict complexity limits on his designs, sticking to an ultra-minimalist Von Neumann architecture. His journey began with the ‘Minimal Ur-CPU’, a logic-chip-based computer that could crunch numbers but little else. Next came the ‘Minimal 64’, featuring VGA graphics and Space Invaders-level performance. The latest ‘Minimal 64×4’ takes it further, adding incredible speed while keeping the design so simple it’s almost ridiculous. It’s computing stripped to its rawest form—no fancy sound, no dazzling graphics, just raw resourcefulness.

For enthusiasts of retro-tech and DIY builds, this project is a treasure trove. From text editors to starfield simulations to Sokoban, [Slu4] proves you don’t need complexity to make magic. Continue reading “Going Minimal: 64×4, The Fun In Functional Computing” →

Regular (Expression) Chess

January 7, 2025 by 17 Comments

[Nicholas Carlini] found some extra time on his hands over the holiday, so he decide to do something with “entirely no purpose.” The result: 84,688 regular expressions that can play chess using a 2-ply minmax strategy. No kidding. We think we can do some heavy-duty regular expressions, but this is a whole other level.

As you might expect, the code to play is extremely simple as it just runs the board through series of regular expressions that implement the game logic. Of course, that doesn’t count the thousands of strings containing the regular expressions.

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High Performance RISC-V

January 3, 2025 by 12 Comments

From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan.

In the Git repository, you’ll find several branches including at least two stable branches: Yanqihu and Nanhu. The currently developed architecture, Kunminghu, is impressive, with a sophisticated instruction fetch unit, a reorder buffer, and a register renaming scheme.

The point of these types of circuits in a CPU is to allow multiple instructions to process at once. This also implies that instructions can be executed out of order. A cursory glance didn’t show any branch prediction logic, but that may be a limitation of the documentation. If there isn’t one, that would be an interesting thing to add in a fork if you are looking for a project.

On the computing side, the processor contains an integer block, a floating point unit, and a vector processor. Clearly, this isn’t a toy processor and has the capability to compete with serious modern CPUs.

There is a separate GitHub for documentation. It looks like they try to keep documentation in both Mandarin and English. You can also find some of the academic papers about the architecture there, too.

We love CPU design, and this is an interesting chance to contribute to an open CPU while there are still interesting things to do. If you need to start with something easier, plenty of small CPUs exist for educational purposes.

RISC CPU Lives In Excel

November 24, 2024 by 13 Comments

Last time we checked in on [Inkbox], he had made a 16-bit CPU in Excel. Impressive, but not really practical. Presumably, his latest project isn’t any more practical, but we suspect an 8-bit RISC CPU was easier to implement in Excel and probably runs faster, too. The new machine uses a stack architecture with a simplified instruction set of ten instructions. You can follow along with his Excel adventure in the video below.

If you think about it, you may decide that doing something like this in Excel is easy because you could just script it and use Excel as the user interface. That’s true, but that’s not how [Inkbox] does it. He won’t use scripts or IF statements in a cell. That makes things much harder.

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Close-up of a CPU

Register Renaming: The Art Of Parallel Processing

November 16, 2024 by 12 Comments

In the quest for faster computing, modern CPUs have turned to innovative techniques to optimize instruction execution. One such technique, register renaming, is a crucial component that helps us achieve the impressive multi-tasking abilities of modern processors. If you’re keen on hacking or tinkering with how CPUs manage tasks, this is one concept you’ll want to understand. Here’s a breakdown of how it works and you can watch the video, below.

In a nutshell, register renaming allows CPUs to bypass the restrictions imposed by a limited number of registers. Consider a scenario where two operations need to access the same register at once: without renaming, the CPU would be stuck, having to wait for one task to complete before starting another. Enter the renaming trick—registers are reassigned on the fly, so different tasks can use the same logical register but physically reside in different slots. This drastically reduces idle time and boosts parallel tasking. Of course, you also have to ensure that the register you are using has the correct contents at the time you are using it, but there are many ways to solve that problem. The basic technique dates back to some IBM System/360 computers and other high-performance mainframes.

Register renaming isn’t the only way to solve this problem. There’s a lot that goes into a superscalar CPU.

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Tridora: A Full-Custom CPU Designed For Pascal

October 23, 2024 by 13 Comments

[Sebastian Lederer] has created Tridora: an unusual stack-based CPU core intended for FPGA deployment, co-developed with its own Pascal compiler. The 32-bit word machine is unusual in that it has not one but three stacks, 16-bit instruction words, and a limited ISA, more like those of the 8-bit world. No multiply or divide instructions will be found in this CPU.

The design consists of about 500 lines of Verilog targeting the Digilent Arty-A7 FPGA board, which is based around the Xilinx Artix-7 FPGA line. [Sebastian] plans to support the Nexys A7 board, which boasts a larger FPGA array but has less RAM onboard. The CPU clocks in at 83 MHz with four clock cycles per instruction, so over 20 MIPS, which is not so shabby for a homebrew design. Wrapped around that core are a few simple peripherals, such as the all-important UART, an SD card controller and a VGA display driver. On the software side, the Pascal implementation is created from scratch with quite a few restrictions, but it can compile itself, so that’s a milestone achieved. [Sebastian] also says there is a rudimentary operating system, but at the moment, it’s a little more than a loader that’s bundled with the program image.

The Tridora Gitlab project hosts the Verilog source, an emulator (written in Golang, not Pascal) and a suite of example applications. We see quite a few custom CPUs, often using older or less popular programming languages. Here’s an FPGA-based Forth machine to get you started. Implementing programming languages from scratch is also a surprisingly common hack. Check out this from-scratch compiler for the Pretty Laughable Programming language.