The FPGA Programming Handbook: An essential guide to FPGA design for transforming ideas into hardware using SystemVerilog and VHDL

The FPGA Programming Handbook

Second Edition

An essential guide to FPGA design for transforming your ideas into hardware using SystemVerilog and VHDL

Frank Bruno

Guy Eschemann

The FPGA Programming Handbook

Second Edition

Copyright © 2024 Packt Publishing

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First published: March 2021

Second edition: April 2024

Production reference: 1220424

Published by Packt Publishing Ltd.

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ISBN: 978-1-80512-559-4

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In loving memory of Guy Eschemann, whose expertise and dedication significantly enriched this book. He generously served as both a technical reviewer and co-author, offering invaluable insights that guided us throughout the writing journey. His contributions will forever be cherished and reflected within these pages.

Contributors

About the authors

Frank Bruno is an experienced high-performance design engineer specializing in FPGAs and ASICs. He has over thirty years of experience working for companies such as SpaceX, GM Cruise, Belvedere Trading, and Allston Trading. He is currently working as an FPGA engineer for Belvedere Trading and is available for FPGA consulting. He is the author of FPGA Programming for Beginners, Packt 2022. In his limited spare time, he contributes to retro computing projects such as MiSTer and MiSTeX.

I’d like to thank my family for giving me the time to work on the book, my parents for being there to support my dreams of being an engineer, and Guy Eschemann for stepping up and helping with the VHDL portion of the book. I’d also like to thank my cats, my constant companions and adventure partners, for sitting by my side and making sure I took breaks from working.

Guy Eschemann was an electrical engineer with over twenty years of experience in designing FP­GA-based embedded systems for automotive, industrial, medical, aerospace, military and telecom applications. He was working as an FPGA engineer at plc2 Design GmbH, and ran airhdl.com, a popular, web-based AXI4 register generator as a side business.

About the reviewers

Dr. Yang Yang Lee, graduated with a Bachelor (Hons) in Mechatronic Engineering and an MSc and PhD in Electrical and Electronic Engineering from the University of Science Malaysia and has over 10 years of experience in embedded systems. Research focuses on AI algorithms, AI hardware acceleration architecture, and FPGA hardware-software co-design. Other research interests include data analytics, embedded systems, machine vision and automation.

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Contents

Preface

Who this book is for

What this book covers

To get the most out of this book

Get in touch

Introduction to FPGA Architectures

Technical requirements

What is an ASIC?

Why an ASIC or FPGA?

How does a company create a programmable device using an ASIC process?

Introduction to HDLs

Logical versus bitwise operations

Creating gates using HDL

Assign statement (SystemVerilog/Verilog)

Assign statement equivalent (VHDL)

Single line comments

Multiline comments

if statement

Fundamental logic gates

Logical NOT

Logical AND

Logical OR

XOR

More complex operations

Introducing FPGAs

Exploring the Xilinx Artix-7 and 7 series devices

Combinational logic blocks

Storage

Clocking

I/Os

DSP48E1 – Xilinx DSP core in 7 series devices

ASMBL architecture

Evaluation boards

Nexys A7 100T (or 50T)

Summary

Questions

Answers

Further reading

FPGA Programming Languages and Tools

Technical requirements

Hardware

Information on the Nexys A7

Software

Hardware Description Languages (HDLs)

SystemVerilog versus Verilog

SystemVerilog versus VHDL

Introducing Vitis and Vivado

Vivado installation

Design flow

Design definition/specification

Design entry/constraints

Simulation

Synthesis

Implementation

Running the example

Loading the design

Directory structure

Testbench

VHDL testbench

Running a simulation

Implementation

Program the board

Summary

Questions

Answers

Challenge

Further reading

Combinational Logic

Technical requirements

Creating FPGA designs

How to create reusable code – parameters and generics

Understanding the basics of HDL design

Introducing data types

Creating arrays

Querying arrays

Assigning to arrays

Handling multiple-driven nets

Handling signed and unsigned numbers

Adding bits to a signal by concatenating

Casting signed and unsigned numbers

Creating user-defined types

Accessing signals using values with enumerated types

Packaging up code using functions

Creating combinational logic

Handling assignment operators

Incrementing signals

Making decisions – if-then-else

Introducing the case statement (SystemVerilog)

Using the conditional operator to select data

Introducing the case statement (VHDL)

Using custom data types

Creating structures

Creating unions (SystemVerilog)

Project 2 – Creating combinational logic

Testbench

Simulating using targeted testing

Simulating using randomized testing

Simulating using constrained randomization

Implementing an LOD using the case statement (SystemVerilog)

Controlling implementation using generate

Designing a reusable LOD using a for loop

Setting SELECTOR = DOWN_FOR

Setting SELECTOR = UP_FOR

Counting the number of ones

Implementing an adder/subtractor

Adder

Subtractor

Implementing a Multiplier

Bringing it all together

Adding a latch

Summary

Questions

Answers

Challenge

Further reading

Counting Button Presses

Technical requirements

What is a sequential element?

Clocking your design

Looking at a basic register

Creating a Flip-Flops using SystemVerilog

Creating a flip-flop using VHDL

When to use always @() for FF generation

Using non-blocking assignments

Registers in the Artix 7

How to retain state using clock enables

Resetting the FF

Project 3 – Counting Button Presses

Introducing the seven-segment display

Detecting button presses

Analyzing timing

Looking at asynchronous issues

Using the asynchronous signal directly

Problem with push buttons

Designing a safe implementation

Switching to decimal representation

Introducing the ILA

What about simulation?

Deep dive into synchronization

Why use multiple clocks?

Two-stage synchronizer

Synchronizing control signals

Passing data

Summary

Questions

Answers

Challenge

Further reading

Let’s Build a Calculator

Technical requirements

What is a state machine?

Writing a purely sequential state machine

Splitting combination and sequential logic in a state machine

Designing a calculator interface

Designing a Moore state machine

Implementing a Mealy state machine

Practical state machine design

Project 4 – Building a Simple Calculator

Packaging for reuse

Coding the top level

Changing frequencies by using a PLL or MMCM

Investigating the divider

Building a non-restoring divider state machine

Simulating the divider

Sizing the intermediate remainder

Project 5 – Keeping cars in line

Creating the state diagram

Displaying our traffic lights

Pulse width modulation

Implementing delays with a counter

Summary

Questions

Answers

Challenge

Extra challenge

Further reading

FPGA Resources and How to Use Them

Technical requirements

What is a digital microphone?

What is PDM?

Project 6 – Listening and learning

Simulating the microphone

Introducing storage

Inferring, instantiating, or using the IP catalog to generate RAM

Basic RAM types

Using xpm_cdc for clock domain crossing

Instantiating memories using xpm_memory

Vivado language templates

Using the IP catalog to create memory

Capturing audio data

Project 7 – Using the temperature sensor

Processing and displaying the data

Smoothing out the data (oversampling)

A deeper dive into FIFOs

Constraints

Generating our FIFO

Summary

Questions

Answers

Further reading

Math, Parallelism, and Pipelined Design

Technical requirements

Introduction to fixed-point numbers

Project 8 – Using fixed-point arithmetic in our temperature sensor

Using fixed-point arithmetic to clean up the bring-up time

Temperature conversion using fixed-point arithmetic

What about floating-point numbers?

Floating-point addition and subtraction

Floating-point multiplication

Floating-point reciprocal

A more practical floating-point operation library

A quick look at the AXI streaming interface

Project 9 – Updating the temperature sensor project to a pipelined floating-point implementation

Fixed-to-floating-point conversion

Floating-point math operations

Float-to-fixed-point conversion

Simulation

Simulation environment

Parallel designs

ML and AI and massive parallelism

Parallel design – a quick example

Summary

Questions

Answers

Challenge

Further reading

Introduction to AXI

Technical requirements

AXI streaming interfaces

Project 10 – Creating IP for Vivado using AXI streaming interfaces

Seven-segment display streaming interface

Developing the adt7420 IP

Understanding the flt_temp core

Introduction to the IP Integrator

IP Integrator debugging

Packaging the project

AXI4 interfaces (full and AXI-Lite)

Developing IPs – AXI-Lite, full, and streaming

Adding an unpackaged IP to the IP Integrator

Summary

Questions

Answers

Completed designs

Further reading

Lots of Data? MIG and DDR2

Technical requirements

Note on VHDL

Project 11 – Introducing external memory

Introduction to DDR2

Generating a DDR2 controller using the Xilinx MIG

Setting AXI parameters

Setting memory options

Defining the FPGA options

Modifying the design for use on the board

Introducing a few other external memory types

QDR SRAM

HyperRAM

SPI RAM

Summary

Questions

Answers

Challenge

Further reading

A Better Way to Display – VGA

Technical requirements

Project 12 – Introducing the VGA

Defining registers

Coding a simple AXI-Lite interface

Generating timing for the VGA

The VGA monitor timing generator

Displaying text

Requesting memory

Testing the VGA controller

Examining the constraints

Summary

Questions

Answer

Challenge

Further reading

Bringing It All Together

Technical requirements

Investigating the keyboard interface

Project 13 – Handling the keyboard

Testing the PS/2

Project 14 – Bringing it all together

Displaying PS/2 keycodes on the VGA screen

Displaying the temperature sensor data

Adding a custom character to the text ROM

Displaying audio data

Summary

Questions

Answers

Challenge

Further reading

Using the PMOD Connectors – SPI and UART

Technical requirements

UART PMOD

ACL2 PMOD

Understanding Peripheral Modules (PMODs)

PMOD Type 1 and 1A

PMOD Type 2 and 2A

PMOD Type 3 and 3A

PMOD Type 4, 5, and 5A

PMOD Type 6 and 6A

PMOD Type 7 and 7A

Introduction to Universal Asynchronous Receiver-Transmitter (UART)

Bus interface

Waveform

Register interface

RBR – Receive Buffer Register

THR – Transmit Holding Register

IER – Interrupt Enable Register

ISR – Interrupt Status Register

FCR – FIFO Control Register

LCR – Line Control Register

MCR – Modem Control Register

LSR – Line Status Register

MSR – Modem Status Register

SCRATCH – Scratch Pad Register

DLL, DLM – Divisor Register LSB and MSB

UART Implementation

CPU Interface

UART Core

My UART origins

Testing

Simulation

On-board testing

Understanding Serial Peripheral Interface (SPI)

ACL2 PMOD

Generic SPI

SPI physical interface

SPI protocol interface

Constructing the SPI

SPI state machine

Summary

Questions

Answers

Further reading

Embedded Microcontrollers Using the Xilinx MicroBlaze

Technical requirements

Understanding Embedded Microcontrollers

Soft vs hard processors

Creating the MicroBlaze project

Block Design

MicroBlaze Peripherals

Exporting the design

The Software Project

GPIOs

Our Software Application

Summary

Questions

Answers

Challenge

Advanced Topics

Technical requirements

Exploring more advanced SystemVerilog constructs

Interfacing components using the interface construct

Using structures

Block labels

Looping using for loops

Looping using do…while

Exiting a loop using disable

Skipping code using continue

Using constants

Packing operators

Indexed part select, +:, -:

Streaming operators

Exploring some more advanced verification constructs

Introducing SystemVerilog queues

Display formatting enhancements

A quick introduction to assertions

Using $error or $fatal in synthesis

Other gotchas and how to avoid them

Inferring single-bit wires

Bit-width mismatches

Upgrading or downgrading Vivado messages

Handling timing closure

How to pipeline a design

Summary

Questions

Answers

Further reading

Other Books You May Enjoy

Index

Landmarks

Cover

Index

Preface

Prepare yourself for some fun. I have been designing ASICs and FPGAs for over 30 years and every day brings new challenges and excitement as I push technology to develop new applications. Over the course of my career, I’ve developed ASICs that powered military aircrafts, graphics that ran on high-end workstations and mainstream PCs, technology to power the next generation of software-defined radios, supplied space-based internet to the globe, and worked on self-driving cars and high-frequency automated trading systems. I believe in paying it forward and I want to give some of my experience back to you.

Who this book is for

This book is for someone interested in learning about FPGA technology and how you might use it in your own projects. We assume that you know nothing about digital logic and start by introducing basic gates and their functions, and then eventually develop full systems. A little programming or hardware knowledge is helpful but not necessary. If you can install software, plug in a USB cable, and follow the projects you will learn a lot.

What this book covers

Chapter 1, Introduction to FPGA Architectures, explains what an ASIC and an FPGA are and gives some background on Boolean logic that will be the building blocks for your designs.

Chapter 2, FPGA Programming Languages and Tools, introduces Hardware Description Language (HDL) and Vivado/ Vitis. A sample design is introduced to showcase the flow and demonstrate the development of a testbench for verification.

Chapter 3, Combinational Logic, looks at writing a complete SystemVerilog module from scratch to perform some basic operations to show how to use combinational logic in your own designs. We’ll also introduce testbenches and how to write one that self-checks.

Chapter 4, Counting Button Presses, builds upon the previous chapter’s combination logic, adding storage—sequential elements. We’ll learn about the capabilities of the Artix-7 and other FPGA devices to store data and design a simple project to count button presses. We’ll also take a look at using clocks and synchronization, one of the few things that can break a design completely if not done correctly.

Chapter 5, Let’s Build a Calculator, looks at how to create more complex design. Inevitably, you need to keep track of the design state. In this chapter, we’ll learn about state machines and use a classic staple of engineering, the traffic light controller. We’ll also enhance our calculator and show how we can design a divider using a state-based design.

Chapter 6, FPGA Resources and How to Use Them, takes a step back after having quickly dived into FPGA designs, examining some of the FPGA resources in more detail. To use these resources, we’ll introduce some of the board resources, the PDM microphone and i2c temperature sensor attached to the FPGA and use them in projects.

Chapter 7, Math, Parallelism, and Pipelined Design, takes a deeper dive into fixed-point and floating-point numbers. We’ll also look at pipelined designs and parallelism for performance.

Chapter 8, Introduction to AXI, covers how Xilinx has adopted the AXI standard to interface its IP and has developed a tool, IP integrator, to easily connect the IP graphically. In this chapter, we’ll look at AXI by taking our temperature sensor and using the IP integrator to integrate the design.

Chapter 9, Lots of Data? MIG and DDR2, looks at how the Artix-7 provides a good amount of memory, but what happens if we need access to megabytes or gigabytes of temporary storage? Our board has DDR2 on it and in anticipation of implementing a display controller, we’ll look at the Xilinx Memory Interface Generator to implement the DDR2 interface and test it in simulation and on the board.

Chapter 10, A Better Way to Display – VGA, looks at implementing a VGA and an easy way to display text. We’ve used LEDs and a seven-segment display to output information from our projects. This does limit us to what can be shown; for example, we can’t display our captured audio data and text.

Chapter 11, Bringing It All Together, covers adding to our inputs. We’ve covered the output with VGA, but we’ll add to our inputs by interfacing to the keyboard using PS/2. We’ll take our temperature sensor and PDM microphone and create a project that uses the VGA to display this data.

Chapter 12, Using the PMOD Connectors – SPI and UART, will explore the PMOD connectors on the Nexys A7 board. By the end of this chapter, we will have created AXI reusable components for a Universal Asynchronous Receiver-Transmitter (UART) and a Serial Peripheral Interface (SPI) bus.

Chapter 13, Embedded Microcontrollers Using the Xilinx MicroBlaze, will introduce the Xilinx Microblaze processor, how to implement one using Vivado and how to develop software for it using Vitis.

Chapter 14, Advanced Topics, wraps things up by looking at some SystemVerilog concepts that I skipped over but you may still find them useful. We’ll look at some of the more advanced verification constructs and finally look at some other gotchas and how to avoid them.

To get the most out of this book

If you are using the digital version of this book, we advise you to type the code yourself or access the code via the GitHub repository (link available in the next section). Doing so will help you avoid any potential errors related to the copying and pasting of code.

Download the example code files

The code bundle for the book is also hosted on GitHub at https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition. In case there’s an update to the code, it will be updated on the existing GitHub repository.

We also have other code bundles from our rich catalog of books and videos available at https://github.com/PacktPublishing/. Check them out!

Download the color images

We also provide a PDF file that has color images of the screenshots/diagrams used in this book. You can download it here: https://packt.link/gbp/9781805125594

Conventions used

There are a number of text conventions used throughout this book.

Code in text

: Indicates code words in text, database table names, folder names, filenames, file extensions, pathnames, dummy URLs, user input, and Twitter handles. Here is an example: "

adt7420_i2c_bd.v

provides the Verilog wrapper."

A block of code is set as follows:

always

@(

posedge

CK)

begin

stage = D; Q = stage;

end

When we wish to draw your attention to a particular part of a code block, the relevant lines or items are set in bold:

module

dff (

input

wire

D, CK,

output

logic

Q);

initial Q = 1;

always_ff @(posedge CK) Q <= D;

endmodule

Any command-line input or output is written as follows:

'timescale 1ps/100fs

Bold: Indicates a new term, an important word, or words that you see onscreen. For example, words in menus or dialog boxes appear in the text like this. Here is an example: "In the block design, right-click and select Add Module."

Warnings or important notes appear like this.

Tips and tricks appear like this.

Get in touch

Feedback from our readers is always welcome.

General feedback: If you have questions about any aspect of this book, mention the book title in the subject of your message and email us at [email protected].

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1

Introduction to FPGA Architectures

Whether you want to accelerate mathematically complex operations such as machine learning or artificial intelligence, or simply want to do some projects for fun, such as retro computing or reproducing obsolete video game machines (https://github.com/MiSTer-devel/Main_MiSTer/wiki), this book will jumpstart your journey. There couldn’t be a better time to get into this field than the present, even if only as a hobby. Development boards are cheap and plentiful, and vendors have started making their tools available for free because of their low-cost, smaller parts.

In this book, we are going to build some example designs to introduce you to FPGA development, culminating in a CPU-based project that can drive a Video Graphics Array (VGA) monitor. Along the way, we’ll interface with Double Data Rate (DDR) memory, temperature sensors, microphones, speakers, and serial ports, often referred to as Universal Asynchronous Receivers/Transmitters (UARTs).

In the this chapter, we will be exploring Field Programmable Gate Arrays (FPGAs) and the underlying technology that creates them. This underlying technology allows companies such as AMD (formerly Xilinx) to produce a reprogrammable chip from an Application-Specific Integrated Circuit (ASIC) process. By the end of this chapter, you should have a good understanding of an FPGA and its components, having covered the following topics:

What is an ASIC?

Introducing FPGAs

Evaluation boards

Technical requirements

This chapter is an optional overview chapter and doesn’t have any technical requirements. We will look at the underlying FPGA and ASIC technology and primitive logic gates in this chapter. If you are already comfortable with this information, please feel free to use this as a reference and jump ahead to Chapter 2, FPGA Programming Languages and Tools.

What is an ASIC?

ASICs are the fundamental building blocks of modern electronics – your laptop or PC, TV, cell phone, digital watch, almost everything you use on a day-to-day basis. It is also the fundamental building block upon which the FPGA we will be looking at is built. In short, an ASIC is a custom-built chip designed using the same language and methods we will be introducing in this book.

Note: This section is for reference and an introduction to basic digital electronics. ASICs and FPGAs are both developed using similar Hardware Descriptive Language (HDL) coding methods. This opens up additional career opportunities for someone with this knowledge.

FPGAs came about as the technology to create ASICs followed Moore’s law (Gordon E. Moore, Cramming More Components Onto Integrated Circuits, Electronics, Volume 38, Number 8, https://archive.computerhistory.org/resources/access/text/2017/03/102770822-05-01-acc.pdf) – the idea that the number of transistors on a chip doubles every 2 years. This has both allowed for very cheap electronics, in the case of mass-produced items containing ASICs, and led to the proliferation of lower-cost FPGAs.

The first commercial FPGA was introduced by Xilinx in 1985, the XC2064. This part is only slightly larger than the Combination Logic Block (CLB)s we’ll look at later, but at the time, it was revolutionary. Prior to this, the only programmable logic was based on Erasable Programmable Memory (EPROM) arrays to implement small logic functions, sometimes with storage elements included on the chip. This was long before HDL languages were used to program the devices and they were often configured with a much simpler syntaxed language.

FPGAs are an ASIC at heart. Xilinx has used an ASIC process to create a reconfigurable chip. However, we must consider the trade-offs in choosing an FPGA or ASIC.

Why an ASIC or FPGA?

ASICs can be an inexpensive part when manufactured in high volumes. You can buy a disposable calculator, a flash drive for pennies/cents per gigabyte, or an inexpensive cell phone; they are all powered by at least one ASIC. ASICs are also sometimes a necessity when speed is of the utmost importance, or the amount of logic that is needed is very large. However, in these cases, they are typically only used when cost is not a factor.

We can break down the costs of developing a product based on an ASIC or FPGA into Non-Recurring Engineering (NRE), the one-time cost to develop a chip, and the piece price for every chip, excluding NRE. Ed Sperling stated the following in CEO Outlook: It Gets Much Harder From Here, Semiconductor Engineering, June 3, 2019, https://semiengineering.com/ceo-outlook-the-easy-stuff-is-over/: "The NRE for a 7nm chip is $25 million to $30 million, including mask set and labor."

These costs are a necessity to build a chip and the main reason why ASICs, especially very advanced ones, are very expensive to produce. They include more than just the mask sets, the blueprint for the ASIC, if you will, that is used to deposit the materials on the silicon wafers that build the chip. These costs also include the salaries for teams of design, implementation, and verification engineers that can number into the hundreds. Re-spins, or bug fixes, are usually factored into ASIC costs because large, complex devices struggle with first-time success.

Compare this to an FPGA, where complex chips can be developed by a single person or small teams. Most of the NRE has been shouldered by the FPGA vendor in the design of the FPGA chips, which are known good quantities. The little NRE expense left is for tools and engineering. Re-spins are free, except for time, since the chip can be reprogrammed using flash memory, without million-dollar mask sets.

The trade-off is the per-part cost. High-volume ASICs with low complexity, like the one inside a pocket calculator or a digital watch, can cost pennies. CPUs can run into the hundreds or thousands of dollars. Compare that to FPGAs where even the most inexpensive Spartan-7 starts at a few dollars, and the largest and fastest can stretch into tens of thousands of dollars.

Another factor is tool costs. As we will see in Chapter 2, FPGA Programming Languages and Tools, AMD provides the Xilinx Vivado tool suite for free for the smaller parts. Other FPGA vendors, such as Intel (formerly Altera), also offer free versions for lower-end parts. This speeds up adoption, where the barrier to entry is now a computer and a development board. Even the cost of developing more expensive parts is only a few thousand dollars if you need to purchase a professional copy of Vivado for AMD or Quartus for Intel. In contrast, ASIC tools can run into millions of dollars and require years of training since the risk of failure is extremely high. As we will see in our projects, we’ll make mistakes, sometimes to demonstrate a concept, but the cost to fix it will only be a few minutes, mostly spent on understanding why it actually failed.

Figure 1.1: Simple ASIC versus FPGA flow

The flow for an ASIC or FPGA is essentially the same as shown above in Figure 1.1. ASIC flows tend to be more linear in that you have one chance to make a working part. With an FPGA, things such as simulation can become an option, although strongly suggested for complex designs. One difference is that the lab debug stage can also act as a form of simulation by using ChipScope, or similar on-chip debugging techniques, to monitor internal signals for debugging. The main difference is that each iteration through the steps costs only time in an FPGA flow. In this situation, any changes to a fabricated ASIC design would require some number of new mask sets, the costs of which could run into the millions of dollars.

We summarize the choice between an ASIC and FPGA in Table 1.1 below:

Table 1.1: FPGA versus ASIC summary

We’ve briefly looked at what an ASIC is and why we might choose an ASIC or an FPGA for a given application. Now, let’s look at how an FPGA is created using an ASIC process.

How does a company create a programmable device using an ASIC process?

The basis of any ASIC technology is the transistor, with the largest devices made up of billions of transistors. Multiple ASIC processes have been developed over the years, and they all rely on transistors, which can be on or off, represented as 1s and 0s. These can be thought of as Booleans, true or false values.

The basis of Boolean algebra was developed by George Bool in 1847. The fundamentals of Boolean algebra make up the basis of the logic gates upon which all digital logic is formed. The code that we will be writing is at a high level of abstraction from the actual hardware implementation and the tools will convert our design into a physical implementation. It is important to understand the basics and will give us a good springboard for a first project. Thousands of engineers have struggled to build efficient logic by hand in the past using individual ICs on a breadboard. I want to get you past that with a minimum of fuss since modern tools are very good at what they do.

An FPGA company, such as AMD or Intel, develops an FPGA by creating configurable structures that can be loaded at the initialization of the device or modified during runtime. The same techniques we will talk about here are used to design blocks that are then synthesized directly into transistors rather than mapped to lookup tables and routing resources. The interesting thing about the fact that the same design techniques are used for FPGAs and ASICs is that many ASICs are prototyped on FPGAs to minimize logic errors and re-spins.

We’ll need to know a little Hardware Description Language (HDL) such as Very High Speed Integrated Circuit HDL (VHDL) or SystemVerilog to go through this section.

Introduction to HDLs

We’ll need to define some terminology for discussing HDLs.

Logical versus bitwise operations

Logical functions operate on Boolean values. A Boolean is an object that can hold one of two values: true or false for VHDL, and

1

or

0

for SystemVerilog/Verilog. SystemVerilog/Verilog has no concept of

true

and

false

. Note that this can be viewed as an advantage of SystemVerilog as it behaves like hardware in that there is no difference between a 1 and true or 0 and false when you implement hardware. VHDL proponents view the strong typing of VHDL as an important feature since it clarifies intent by forcing the correct types to be used.

A bitwise function operates on a 1 or 0 (or as we will discuss later in the book, other values representing unknown, tri-state or different drive strengths). Both VHDL and SystemVerilog/Verilog have objects that hold these values and are operated on in a bitwise function. We will dive deeper into this in Chapter 3, Combinational Logic, but we’ll be using

if

statements in some of the examples below to demonstrate the logic gates.

Bitwise functions also have the ability to act as reduction operators in SystemVerilog/Verilog and there are similar functions in VHDL. These will be discussed in Chapter 2, FPGA Programming Languages and Tools.

In this section, we are primarily discussing logical functions. In SystemVerilog and Verilog, logical and bitwise functions can be intermixed as they are weakly typed languages. VHDL is strongly typed and you will run into problems mixing them up. This will be discussed further in Chapter 3.

Armed with this knowledge, let’s dip our toes into some HDL code.

Creating gates using HDL

In this section, we’ll take a look at some basic HDL code that will