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Instruction Execution and Interrupts

The document discusses instruction execution and interrupts in a computer system. It describes the fetch-execute cycle where the program counter fetches instructions from memory and increments. For execution, the instruction is loaded into the instruction register and the required actions are performed. Interrupts can suspend program execution to handle higher priority events, by saving the context and jumping to an interrupt handler before restoring the context. The interrupt cycle is added to the normal instruction cycle, and interrupts can be handled sequentially or through nested interrupts based on their priority.

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6K views

Instruction Execution and Interrupts

The document discusses instruction execution and interrupts in a computer system. It describes the fetch-execute cycle where the program counter fetches instructions from memory and increments. For execution, the instruction is loaded into the instruction register and the required actions are performed. Interrupts can suspend program execution to handle higher priority events, by saving the context and jumping to an interrupt handler before restoring the context. The interrupt cycle is added to the normal instruction cycle, and interrupts can be handled sequentially or through nested interrupts based on their priority.

Uploaded by

ather_88
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Instruction Execution and Interrupts

Program Concept
• Hardwired systems are inflexible
• General purpose hardware can do
different tasks, given correct control
signals
• Instead of re-wiring, supply a new set of
control signals
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals

• We have a computer!
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
The illustrated fetch cycle above can be summarised by the following points:
PC => MAR
MAR => memory => MBR
MBR => IR
PC incremented
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
LOAD ACC, memory

This operation loads the


accumulator (ACC) with data
that is stored in the memory
location specified in the
instruction.

IR [address portion] => MAR


MAR => memory => MBR
MBR => ACC
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Program
—e.g. overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
• I/O
—from I/O controller
• Hardware failure
—e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts

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