Basic Computer Organization
TE 091335 Computer Organization and Architecture
Memory Unit 4096 x 16 AR
S0 S1 S2
Bus 7 1 2
PC
DR Adder & Logic E INPR IR TR OUTR
2 2
3
4
AC
5 6
Registers
AR
LD INR CLR
Memory Unit 4096 x 16
Write Read
PC
LD INR CLR LD
DR
INR CLR
IR
LD LD
AC
INR CLR
TR
LD INR CLR
OUTR
LD
INPR
Clock
3 3
Memory Reference Instructions
Symbol AND ADD I=0 0xxx 1xxx I=1 8xxx 9xxx Description AND memory word to AC Add memory word to AC
LDA
STA BUN BSA ISZ
2xxx
3xxx 4xxx 5xxx 6xxx
Axxx
Bxxx Cxxx Dxxx Exxx
Load memory word to AC
Store content of AC to memory Branch unconditionally Branch and save return address Increment and skip if zero
Register Reference Instructions
Symbol CLA CLE CMA CME CIR CIL INC SPA SNA SZA SZE Code 7800 7400 7200 7100 7080 7040 7020 7010 7008 7004 7002 Clear AC Clear E Complement AC Complement E Circulate right AC and E Circulate left AC and E Increment AC Skip next instruction if AC positive Skip next instruction if AC negative Skip next instruction if AC zero Skip next instruction if E is zero Description
HLT
5
7001
Halt computer
Input Output Instructions
Symbol
INP OUT
Code
F800 F400
Description
Input character to AC Output character from AC
SKI
SKO ION IOF
F200
F100 F080 F040
Skip on input flag
Skip on output flag Interrupt on Interrupt off
15
14
13
12
11
3x8 Decoder 7 6 5 4 3 2 1 0 Control Logic Gates 15 14 13 12 11 10 9 8 7 6 5 4x16 Decoder 0 Control output
4-bit Sequence Counter (SC)
7
Increment (INR) Clear (CLR) Clock
T1 T0
S0 S1 Bus
S2
Memory Unit
Read
AR
LD
PC
INR
IR
LD
8
Instruction Cycle
Fetch an instruction from memory Decode the instruction Read the effective address from memory if the instruction has an indirect address Execute the instruction
T0: AR PC T1: IR M[AR], PC PC + 1 T2: D0, , D7 Decode IR(12-14), AR IR(0-11), I IR(15)
Start SC 0 T0 AR PC T1 IR M[AR], PC PC + 1 T2 Decode IR(12-14), AR IR(0-11), I IR(15) D7 I I
T3
Execute I/O Instruction SC 0 Execute RRI SC 0
T3
T3
AR M[AR] Nothing T4 Execute MRI SC 0
T3
10
RRI
Symbol r CLA CLE CMA
D7IT3 = r (common to all RRI) IR(i) = Bi (bit in IR(0-11) that specifies the operation) Signal Stages SC 0 AC 0 E0 AC AC Clear SC Clear AC Clear E Complement AC
rB11 rB10 rB9
CME
CIR CIL INC SPA SNA
rB8
rB7 rB6 rB5 rB4 rB3
E E
AC shrAC, AC(15) E, E AC(0) AC shlAC, AC(0) E, E AC(15) AC AC + 1 If(AC(15) = 0) then PC PC + 1 If(AC(15) = 1) then PC PC + 1
Complement E
Circulate right Circulate left Increment AC Skip if positive Skip if negative
SZA
11
rB2
rB1
If(AC = 0) then PC PC + 1
If(E = 0) then PC PC + 1
Skip if AC zero
Skip if E zero
SZE
MRI (1)
AND
D0T4: DR M[AR] D0T5: AC AC DR, SC 0
ADD
D1T4: DR M[AR] D1T5: AC AC + DR, E Cout, SC 0
D2T4: DR M[AR] D2T5: AC DR, SC 0 D3T4: M[AR] AC, SC 0
LDA
STA
BUN
12
D4T4: PC AR, SC 0
MRI (2)
BSA D5T4: M[AR] PC, AR AR + 1 D5T5: PC AR, SC 0 ISZ D6T4: DR M[AR] D6T5: DR DR + 1 D6T6: M[AR] DR, if(DR = 0) then (PC PC + 1), SC 0
20 PC = 21
0 BSA 135 Next Instruction
20 21
0 BSA 135 Next Instruction 21 Subroutine 1 BUN 135
AR = 135 136
Subroutine 1 BUN 135
135 PC = 136
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Exercise (1)
A computer uses a memory unit with 256K words of 332 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers, and an address part.
How many bits are there in the operation code, the register code part, and the address part? Draw the instruction word format and indicate the number of bits in each part. How many bits are there in the data and address inputs of the memory?
14
Exercise (2)
The following register transfers are to be executed in the basic computer. For each transfer specify: (1) the binary value that must be applied to bus select input S2, S1, S0; (2) the register whose LD control input must be active (if any); (3) a memory read or write operation (if needed); and (4) the operation in the adder and logic circuit (if any).
AR PC IR M[AR] M[AR] TR AC DR, DR AC (done simultaneously)
15
Exercise (3)
Explain why each of the following micro operations cannot be executed during a single clock pulse in the basic computer. Specify a sequence of micro operations that will perform the operation.
IR M[PC] AC AC + TR DR DR + AC (AC does not change)
16
Exercise (4)
Consider the instruction format and the list of instruction in the basic computer. For each of the following 16-bit instructions, give the equivalent four digit hexadecimal code and explain in your own words what the instruction is going to perform.
0001 0000 0010 0100 1011 0001 0010 0100 0111 0000 0010 0000
17
Exercise (5)
The content of AC in the basic computer is A937 and the initial value of E is 1. Determine the contents of AC, E, PC, AR, and IR in hexadecimal after the execution of the CLA instruction. Repeat 11 more times, starting from each one of the register reference instructions. The initial value of PC is hexadecimal 021.
18
Exercise (6)
The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The content of AC is 7EC3.The content of memory at address 3AF is 932E. The content of memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F.
What is the instruction that will be fetched and executed next? Show the binary operation that will be performed in the AC when the instruction is executed. Give the contents of PC, AR, DR, AC and IR (hexadecimal) and the values of E, I and SC (binary) at the end of the instruction cycle.
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