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AMBA Advanced Peripheral Bus (APB) Protocol: BY: Nitin Mathur

The document describes the Advanced Peripheral Bus (APB) protocol. It is designed for low bandwidth peripherals to reduce interface complexity and power consumption. It uses a single master and has signals for address, data, clock and control. Transfers take a minimum of two clock cycles and can insert wait states. It uses a state machine with Idle, Setup and Access states to perform read and write transfers with optional wait states. It also provides protection for normal, privileged, secure and instruction transaction types.

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Nitin Mathur
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2K views

AMBA Advanced Peripheral Bus (APB) Protocol: BY: Nitin Mathur

The document describes the Advanced Peripheral Bus (APB) protocol. It is designed for low bandwidth peripherals to reduce interface complexity and power consumption. It uses a single master and has signals for address, data, clock and control. Transfers take a minimum of two clock cycles and can insert wait states. It uses a state machine with Idle, Setup and Access states to perform read and write transfers with optional wait states. It also provides protection for normal, privileged, secure and instruction transaction types.

Uploaded by

Nitin Mathur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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AMBA Advanced

Peripheral Bus (APB)


Protocol
BY:
NITIN MATHUR

AMBA 2.0 System-Level


View

APB Features

Low cost interface

Minimal power consumption

Reduce interface complexity

Non pipelined

Ideal for Low Bandwidth peripherals

Every Transfer takes at least two clock cycles

Only one master is allowed

APB Signal Definitions

PCLK

PRESETn : the bus (and typically system) reset signal (active


low)

PADDR

: the APB address bus (can be up to 32-bits wide)

PSELx

: the select line for each slave device

PENABLE : indicates the 2nd and subsequent cycles of an APB


transfer

PWRITE

PWDATA : the write data bus (can be up to 32-bits wide)

PREADY : used to extend a transfer

PRDATA : the read data bus (can be up to 32-bits wide)

PSLVERR : indicates a transfer error (OKAY=L, ERROR=H)


PPROT : indicates the normal, privileged, or secure
protection level of the transaction and whether the transaction
is a data access or an instruction access.

: the bus clock source (rising-edge triggered)

: indicates transfer direction (Write=H, Read=L)

PSLVERR
PPROT

APB State Machine

IDLE

Default APB state

SETUP

When transfer required

PSELx is asserted

Only one cycle

ACCESS

PENABLE is asserted

Addr, write, select, and write data


remain stable

Stay if PREADY = L

Goto IDLE if PREADY = H and no more


data

Goto SETUP is PREADY = H and more


data pending

Write Transfer with no Wait States


Setup phase begins
with this rising edge

Setup
Phase

Access
Phase

Write Transfer with Wait States


Setup phase begins
with this rising edge

Setup
Phase

Wait
State

Wait
State

Access
Phase

Read Transfer with no Wait States


Setup phase begins
with this rising edge

Setup
Phase

Access
Phase

Read Transfer with Wait States

Setup phase begins


with this rising edge

Setup
Phase

Wait
State

Wait
State

Access
Phase

Protection unit support

to provide protection against illegal transactions.

protection is provided by the PPROT[2:0] signals.

1.

Normal or Privileged, PPROT[0]


LOW indicates a normal access, HIGH indicates a privileged access.

2.

Secure or Non-Secure, PPROT[1]


LOW indicates a secure access, HIGH indicates a non-secure access

3.

Data or Instruction, PPROT[2]


LOW indicates a data access, HIGH indicates an instruction access.

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