Introduction to Logic
Gates
Logic Gates
The Inverter
The AND Gate
The OR Gate
The NAND Gate
The NOR Gate
The XOR Gate
The XNOR Gate
Drawing Logic Circuit
Analysing Logic Circuit
Introduction to Logic
Gates
Universal Gates: NAND and NOR
NAND Gate
NOR Gate
Implementation using NAND Gates
Implementation using NOR Gates
Implementation of SOP Expressions
Implementation of POS Expressions
Positive and Negative Logic
Integrated Circuit Logic Families
Logic Gates
Gate Symbols Symbol set 1 Symbol set 2
(ANSI/IEEE Standard 91-1984)
a a
AND a.b & a.b
b b
a a
OR a+b ≥1 a+b
b b
NOT a a' a 1 a'
a a
(a.b)' & (a.b)'
NAND b b
a a
NOR (a+b)' ≥1 (a+b)'
b b
a a
EXCLUSIVE OR a⊕b =1 a⊕b
b b
Logic Gates: The Inverter
The Inverter
A A'
A A' A A' 0 1
1 0
Application of the inverter: complement.
Binary number
1 1 0 1 0 0 0 1
0 0 1 0 1 1 1 0
1’s Complement
Logic Gates: The AND
Gate
The AND Gate
A A &
A.B A.B
B B
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
Logic Gates: The AND
Gate
Application of the AND Gate
1 sec
A A
Counter
Enable
Enable
1 sec
Register,
Reset to zero decode
between and
frequency
Enable pulses
display
Logic Gates: The OR Gate
The OR Gate
A A ≥
A+B 1 A+B
B B
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
Logic Gates: The NAND
Gate
The NAND Gate
A
(A.B)' ≡ A
(A.B)'
A &
(A.B)'
B B B
A B (A.B)'
0 0 1
0 1 1 ≡
1 0 1
1 1 0 NAND Negative-OR
Logic Gates: The NOR
Gate
The NOR Gate
A
(A+B)' ≡ A
(A+B)'
A ≥
1
(A+B)'
B B B
A B (A+B)'
0 0 1
0 1 0 ≡
1 0 0
1 1 0 NOR Negative-AND
Logic Gates: The XOR
Gate
The XOR Gate
A A =1
A⊕B A⊕B
B B
A B A ⊕B
0 0 0
0 1 1
1 0 1
1 1 0
Logic Gates: The XNOR
Gate
The XNOR Gate
A A =1
(A ⊕ B)' (A ⊕ B)'
B B
A B (A ⊕ B) '
0 0 1
0 1 0
1 0 0
1 1 1
Drawing Logic Circuit
When a Boolean expression is provided, we
can easily draw the logic circuit.
Examples:
(i) F1 = xyz' (note the use of a 3-input AND
gate)
x
y F1
z z'
Drawing Logic Circuit
(ii) F2 = x + y'z (can assume that variables and
their complements are
available)
x
F2
y'
z y'z
(iii) F3 = xy' + x'z x xy'
y'
F3
x'
z x'z
Problem
Q1. Draw a logic circuit for BD + BE + D’F
Q2. Draw a logic circuit for
A’BC + B’CD + BC’D + ABD’
Analysing Logic Circuit
When a logic circuit is provided, we can
analyse the circuit to obtain the logic
expression.
Example: What is the Boolean expression of
F4? A'B'
A'
B' A'B'+C (A'B'+C)'
F4
C
F4 = (A'B'+C)' = (A+B).C'
Problem
What is Boolean expression of F5?
y F5
z
Universal Gates: NAND
and NOR
AND/OR/NOT gates are sufficient for building
any Boolean functions.
However, other gates are also used because:
(i) usefulness
(ii) economical on transistors
(iii) self-sufficient
NAND/NOR: economical, self-sufficient
XOR: useful (e.g. parity bit generation)
NAND Gate
NAND gate is self-sufficient (can build any
logic circuit with it).
Can be used to implement AND/OR/NOT.
Implementing an inverter using NAND gate:
x x'
(x.x)' = x' (T1: idempotency)
NAND Gate
Implementing AND using NAND gates:
(x.y)'
x
x.y
y
((xy)'(xy)')' = ((xy)')' idempotency
= (xy) involution
Implementing OR using NAND gates:
x'
x ((xx)'(yy)')' = (x'y')' idempotency
x+y = x''+y'' DeMorgan
= x+y involution
y
y'
NOR Gate
NOR gate is also self-sufficient.
Can be used to implement AND/OR/NOT.
Implementing an inverter using NOR gate:
x x'
(x+x)' = x' (T1: idempotency)
NOR Gate
Implementing AND using NOR gates:
x'
x
x.y
((x+x)'+(y+y)')'=(x'+y')' idempotency
y
y' = x''.y'' DeMorgan
= x.y involution
Implementing OR using NOR gates:
(x+y)'
x
x+y
y
((x+y)'+(x+y)')' = ((x+y)')' idempotency
= (x+y) involution
Implementation using
NAND gates
Possible to implement any Boolean expression
using NAND gates.
Procedure:
(i) Obtain sum-of-products Boolean
expression:
e.g. F3 = xy'+x'z
(ii) Use DeMorgan theorem to obtain
expression using 2-level NAND gates
e.g. F3 = xy'+x'z
= (xy'+x'z)' ' involution
= ((xy')' . (x'z)')' DeMorgan
Implementation using
NAND gates
x (xy')'
y'
F3
x'
z (x'z)'
F3 = ((xy')'.(x'z)') ' = xy' + x'z
Implementation using
NOR gates
Possible to implement boolean expression
using NOR gates.
Procedure:
(i) Obtain product-of-sums Boolean
expression:
e.g. F6 = (x+y').(x'+z)
(ii) Use DeMorgan theorem to obtain
expression using 2-level NOR gates.
e.g. F6 = (x+y').(x'+z)
= ((x+y').(x'+z))' ' involution
= ((x+y')'+(x'+z)')'
DeMorgan
Implementation using
NOR gates
x (x+y')'
y'
F6
x'
z (x'+z)'
F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)
Implementation of SOP
Expressions
Sum-of-Products expressions can be
implemented using:
2-level AND-OR logic circuits
2-level NAND logic circuits
AND-OR logic circuit
A
B F = AB + CD + E
C
F
D
E
Implementation of SOP
Expressions
NAND-NAND circuit (by A
circuit transformation) B
C
a) add double bubbles F
D
b) change OR-with-
inverted-inputs to E
NAND
& bubbles at inputs to
A
their complements
B
C
F
D
E'
Implementation of POS
Expressions
Product-of-Sums expressions can be
implemented using:
2-level OR-AND logic circuits
2-level NOR logic circuits
OR-AND logic circuit
A
B G = (A+B).(C+D).E
C
G
D
E
Implementation of POS
Expressions
NOR-NOR circuit (by A
circuit B
transformation): C
G
D
a) add double bubbles
E
b) changed AND-with-
inverted-inputs to
NOR A
& bubbles at inputs B
to C
G
their complements D
E'
Solve it yourself (Exercise
4.3)
Q1. Draw a logic circuit for BD + BE + D’F using only
NAND gates. Use both DeMorgan method and SOP
method.
Q2. Transform the following AND-OR Circuit to NAND
circuit. x
y F
Q3. Using only NOR gates, draw a logic circuit using POS
method for (A+B+C’)(B’+C’+D)
Positive & Negative Logic
In logic gates, usually:
H (high voltage, 5V) = 1
L (low voltage, 0V) = 0
This convention – positive logic.
However, the reverse convention, negative
logic possible:
H (high voltage) = 0
L (low voltage) = 1
Depending on convention, same gate may
denote different Boolean function.
Positive & Negative Logic
A signal that is set to logic 1 is said to be asserted, or active,
or true.
A signal that is set to logic 0 is said to be deasserted, or
negated, or false.
Active-high signal names are usually written in
uncomplemented form.
Active-low signal names are usually written in complemented
form.
Positive & Negative Logic
Positive logic:
Active High:
Enable 0: Disabled
1: Enabled
Negative logic:
Active Low:
Enable 0: Enabled
1: Disabled
Integrated Circuit Logic
Families
Some digital integrated circuit families: TTL, CMOS, ECL.
TTL: Transistor-Transistor Logic.
Uses bipolar junction transistors
Consists of a series of logic circuits: standard TTL, low-power TTL,
Schottky TTL, low-power Schottky TTL, advanced Schottky TTL,
etc.
Integrated Circuit Logic
Families
TTL Series Prefix Designation Example of Device
Standard TTL 54 or 74 7400 (quad NAND gates)
Low-power TTL 54L or 74L 74L00 (quad NAND gates)
Schottky TTL 54S or 74S 74S00 (quad NAND gates)
Low-power 54LS or 74LS 74LS00 (quad NAND gates)
Schottky TTL
Integrated Circuit Logic
Families
CMOS: Complementary Metal-Oxide Semiconductor.
Uses field-effect transistors
ECL: Emitter Coupled Logic.
Uses bipolar circuit technology.
Has fastest switching speed but high power consumption.
Integrated Circuit Logic
Families
Performance characteristics
Propagation delay time.
Power dissipation.
Fan-out: Fan-out of a gate is the maximum number of inputs that
the gate can drive.
Speed-power product (SPP): product of the propagation delay time
and the power dissipation.
Summary
Logic Gates Drawing Logic Analyzing
Circuit Logic Circuit
AND, NAND Given a Boolean Given a circuit, find
OR, expression, draw the the function.
NOT NOR circuit.
Implementation Positive and
Implementation of a of SOP and POS Negative Logic
Boolean expression Expressions
using these
Universal gates. Concept of Minterm
and Maxterm
