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Gate Simulation

Gate level simulation verifies that a synthesized gate level netlist functions correctly and meets timing requirements. It checks that the RTL is synthesizable, the gate level design passes tests, and identifies any timing violations or uninitialized outputs. Gate level simulation requires a gate level netlist, simulation library, SDF file containing gate delays, and testbench. It can be run with or without delay to check functionality and timing respectively. Issues include long simulation time, difficult debugging, memory usage, and environment configuration.

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Mahmoud Wafa
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318 views

Gate Simulation

Gate level simulation verifies that a synthesized gate level netlist functions correctly and meets timing requirements. It checks that the RTL is synthesizable, the gate level design passes tests, and identifies any timing violations or uninitialized outputs. Gate level simulation requires a gate level netlist, simulation library, SDF file containing gate delays, and testbench. It can be run with or without delay to check functionality and timing respectively. Issues include long simulation time, difficult debugging, memory usage, and environment configuration.

Uploaded by

Mahmoud Wafa
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Gate Level Simulation

WHAT IS GATE LEVEL SIMULATION !


RTL Unverified RTL FUNCTIONAL VERIFICATION Functionally Correct RTL SYNTHESIS Gate Level Netlist GATE LEVEL SIMULATION VERIFIED NETLIST

GATE LEVEL SIMULATION CHECKS !


Checks IF the RTL written is SYNTHESIZABLE. Checks IF the Gate Level Hardware (Netlist) passes all your test cases. Checks IF you have any un-initialized outputs. Checks IF the design works at the targeted FREQUENCY. Checks IF you have any timing violations. Checks Power estimate.

REQUIREMENTS

Gate Level Netlist Gate Level Simulation Library SDF (Standard Delay Format) Test bench For Gate Level Simulation Models For Blocks Like Memory

TYPES OF SIMULATIONS

ZERO DELAY SIMULATION (Without SDF). SIMULATION WITH SDF (Standard Delay Format).

ZERO DELAY SIMULATION

Gate Level Simulation Without DELAY. Check Only Functionality NOT Frequency. Check Mapping Of RTL To Gates. Much Easier To Debug.

SIMULATION WITH SDF

Gate Level Simulation With DELAY. SDF File Includes All The Delay For Gates. Check Functionality At Given Frequency. Identify Timing Issues. Check Multicycle Path. Check False Path.

EXAMPLE OF SDF
(DELAYFILE (SDFVERSION "3.0") (DESIGN "top_cpld_gp7000") (DATE "[Thu Mar 25 16:26:41 2004] ") (VENDOR "Xilinx") (PROGRAM "Xilinx SDF Writer") (VERSION "F.28") (DIVIDER /) (VOLTAGE 5.00:5.00:5.00) (PROCESS "best=1.0:nom=1.0:worst=1.0") (TEMPERATURE 25.00:25.00:25.00) (TIMESCALE 1 ps) (CELL (CELLTYPE "X_BUF") (INSTANCE hsp_o_0) (DELAY (ABSOLUTE (IOPATH I O (2000:2000:2000)(2000:2000:2000)) )

ISSUES WITH GATE LEVEL SIMULATION

Simulation Time. Gate Level Debug. Simulation Memory. Bug Fixes. Simulation Environment.

THANK YOU!

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