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SYSC 4405 - Quiz5b Solution

The document describes specifications for implementing a band-pass filter to demodulate an AM radio station in the range of 726-734kHz using a DSP system with a sampling frequency of 2MHz. It discusses calculating the ideal filter parameters, choosing a windowing function, calculating the FIR filter expression, determining processing requirements for the FIR and block processing implementations, and selecting the minimum DSP clock speed needed. Implementing using block processing of size 2048 samples with a 500MHz DSP would require 148 clocks/sample and have a processing delay of 0.803ms.

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Aleksandra Diotte
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207 views4 pages

SYSC 4405 - Quiz5b Solution

The document describes specifications for implementing a band-pass filter to demodulate an AM radio station in the range of 726-734kHz using a DSP system with a sampling frequency of 2MHz. It discusses calculating the ideal filter parameters, choosing a windowing function, calculating the FIR filter expression, determining processing requirements for the FIR and block processing implementations, and selecting the minimum DSP clock speed needed. Implementing using block processing of size 2048 samples with a 500MHz DSP would require 148 clocks/sample and have a processing delay of 0.803ms.

Uploaded by

Aleksandra Diotte
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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We wish to implement a band-pass filter to demodulate an AM radio station with frequency content in the range 726734kHz (content in this

range should be accepted 1%). We need to reject frequencies below 720kHz and above 740kHz by at least 40dB. We use a DSP system with a sampling frequency of 2MHz. Our DSP takes 1 clk cycle for addition and 5 clk cycles for multiplication (assume other operations are zero cost). This DSP is available in versions with clk speeds of: 1MHz, 2Mhz, 5Mhz, 10MHz, 20Mhz, 50Mhz, 100MHz, 200Mhz, 500Mhz, 1Ghz, 2GHz. Faster DSPs are more expensive and use up batteries faster. A. Sketch the filter specifications. What are p,L, p,H and s,L, s,H. Answer:
1+p 1 1+p

s S,L P,L O P,H S,H

fS,L = 720kHz fS,Lnorm= 720kHz/2MHz = .360 cyc/sample S,Lnorm= .360 (2) rad/sample fP,L = 726kHz fP,Lnorm= 726kHz/2MHz = .363 cyc/sample P,Lnorm= .363 (2) rad/sample fP,H = 734kHz fP,Hnorm= 734kHz/2MHz = .367 cyc/sample P,Hnorm= .367 (2) rad/sample fS,H = 740kHz fS,Hnorm= 740kHz/2MHz = .370 cyc/sample S,Hnorm= .370 (2) rad/sample S given by 40dB spec S = 10-40/20 = .01 P 1% so P 0.01

B. Calculate c, 0 for the BPF. Calculate the ideal BPF. Answer lower cutoff = (S,Lnorm + P,Lnorm)/2 = .3615(2) rad/sample upper cutoff = (P,Hnorm + S,Hnorm)/2 = .3685(2) rad/sample O = (c,L + c,H)/2 = .365(2) rad/sample c,L = O - lower cutoff = .0035(2) c,H = upper cutoff - O = .0035(2) TBWL = (P,Lnorm - S,Lnorm) = .003(2) rad/sample .003 cyc/sample TBWH = (S,Hnorm - P,Hnorm) = .003(2) rad/sample .003 cyc/sample hBP,IDEAL[n] = 2cos[no][c/]sinc[nc/] per slide 20.17 = 2cos[n(0.730)][.007]sinc[n(.007)] Note filter is symmetric (Transition bands have same specification)

C. Choose a windowing function and window length for this filter. Answer 40dB stop band specification Hann is acceptable window (per slide 22.14) For Hann: 1.56/L = TBW = .003

L = 1.56/.001 = 520 M = 2L+1 = 1041

D. Calculate the expression for the FIR filter to implement this specification. Answer hBP[n] = hwindow[n] hBP,IDEAL[n] = (0.5 + 0.5cos((n-L)/L))(2cos[(n-L)o][c/]sinc[(n-L)c/]) = (0.5 + 0.5cos((n-520)/520))(2cos[(n-520)(0.730)][.007]sinc[(n-520)(.007)]) E. To implement this filter as an FIR convolution, how many multiplies and additions are required per output sample. Answer: M = 1041 So convolution requires M multiplies per sample M-1 additions per sample Total 1041*5 clk/mult = 5205 1040*1 clk/add = 1040 6245 clks/sample

F. What is the slowest clock speed DSP that can be used for this application using FIR convolution? Answer: 2MHz sampling Need processor > 6245*2MHz = 12.49GHz None of the available processors will meet the need.

G. To implement this filter using FFT block processing, calculate how many multiplies and additions are required per output sample: i. for N= 2048 ii. for N= 4096 Answer: N=2048 M=1041 B=N-M+1 = 2048-1041+1 = 1008 - processing 1008 sample length blocks FFT Mults FFT Adds Filter Mults IFFT Mults IFFT Adds Overlap Adds (N/2)(log2N-2)+1 Nlog2N N (N/2)(log2N-2)+1 Nlog2N N (2048/2)(log22048-2)+1 2048log22048 2048 (2048/2)(log22048-2)+1 2048log22048 2048 9217 22528 2048 9217 22528 2048 *5 *1 *5 *5 *1 *1 46085 22528 10240 46085 22528 2048 149.5K =149.5K/B = 149.5K/1008 = 148.3 clocks/sample

Total clocks per Blocks Clocks / samples

N=4096 M=1041 B=N-M+1 = 4096-1041+1 = 3056 - processing 3056 sample length blocks FFT Mults FFT Adds Filter Mults IFFT Mults IFFT Adds Overlap Adds (N/2)(log2N-2)+1 Nlog2N N (N/2)(log2N-2)+1 Nlog2N N (4096/2)(log24096-2)+1 4096log24096 4096 (4096/2)(log24096-2)+1 4096log24096 4096 20481 49152 4096 20481 49152 4096 *5 *1 *5 *5 *1 *1 102405 49152 20480 102405 49152 4096 327.7K =327.7K/B = 327.7K/3056 = 107.2 clocks/sample

Total clocks per Blocks Clocks / samples

H. What is the slowest clock speed DSP that can be used for this application using DSP block processing? Answer: At N = 2048 min processor = 148.3*2MHz = ~0.3GHz so use 500Mhz (1GHz more likely) At N = 4096 min processor = 107.2*2MHz = ~0.2GHz so use 500Mhz (likely do not need 1G)

I. What is the processing delay for the FIR? Answer: N=2048 ; CPUf = 500MHz Fs = 2MHz Ts = 0.5x10-6 secs CPUt = 2x10-9 secs Processing delay Block delay = B* Ts = 1008 * 0.5x10-6 = .504msec Filter delay = CLKS * CPUt = 149.5 x103 * 2x10-9 =.299 msec Delay = .803 msec N=4096; CPUf = 500MHz Fs = 2MHz Ts = 0.5x10-6 secs CPUt = 2x10-9 secs Processing delay Block delay = B* Ts = 3056 * 0.5x10-6 = 1.528msec Filter delay = CLKS * CPUt = 327.7x103 * 2x10-9 =.655 msec Delay = 2.183 msec

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