Assembly Language

Coding
for
TPF
500

Assembly Language
Reference for TPF
Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Assembler Language Reference

for TPF Applications Programmers
This reference is an alphabetical lexicon of assembly language tools and topics used in the TPF applications programming
environment. Although it is not an all inclusive text regarding assembler instructions, it contains sufficient information to
allow the assembler programmer to determine how and when to use the various instructions.

Copyright Galileo International Partnership 1996

This course material may not be reproduced in whole or part without prior written permission from:
Galileo International Partnership
Technical Training
5350 South Valentia Way
Englewood, CO 80111
USA
Any products listed are trademarks or registered trademarks of their respective owners and are used here for informational
purposes only.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 2 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Table of Contents by Title

Add..........................................................................................................................................................................................9
Address Constants..................................................................................................................................................................10
Add Halfword........................................................................................................................................................................12
Add Registers.........................................................................................................................................................................13
Branch and Link.....................................................................................................................................................................14
Branch and Link Register......................................................................................................................................................15
Branch and Save....................................................................................................................................................................16
Branch and Save Register......................................................................................................................................................17
Branch on Condition..............................................................................................................................................................18
Branch on Condition _...........................................................................................................................................................20
Branch on Condition Register................................................................................................................................................22
Branch on Condition _ Register.............................................................................................................................................24
Branch on Count....................................................................................................................................................................26
Branch on Count Register......................................................................................................................................................27
BEGIN Macro........................................................................................................................................................................28
Compare (Arithmetic)............................................................................................................................................................31
Compare Halfword (Arithmetic)............................................................................................................................................32
Compare Logical....................................................................................................................................................................33
Compare Logical Characters..................................................................................................................................................34
Compare Logical Immediate..................................................................................................................................................35
Compare Logical Characters Under Mask.............................................................................................................................36
Compare Logical Registers....................................................................................................................................................37
Compare Registers (Arithmetic)............................................................................................................................................38
Define Control Section..........................................................................................................................................................39
Convert to Binary...................................................................................................................................................................40
Convert to Decimal................................................................................................................................................................41
Divide....................................................................................................................................................................................42
Define Constant.....................................................................................................................................................................43
Divide Registers.....................................................................................................................................................................45
Drop Base Register(s) Directive............................................................................................................................................46
Define Storage.......................................................................................................................................................................47
Define Dummy Section..........................................................................................................................................................49
Edit.........................................................................................................................................................................................50
Skip to a New Page Directive................................................................................................................................................54
END Source Module Directive..............................................................................................................................................55
Equate Directive....................................................................................................................................................................56
Execute..................................................................................................................................................................................58
FINIS Macro..........................................................................................................................................................................62
Insert Character......................................................................................................................................................................63
Insert Characters Under Mask...............................................................................................................................................64
Load.......................................................................................................................................................................................65
Load Address.........................................................................................................................................................................66
Load Halfword.......................................................................................................................................................................67
Load Multiple........................................................................................................................................................................68
Load Register.........................................................................................................................................................................69
Literal Origin Directive.........................................................................................................................................................70
Load and Test Register..........................................................................................................................................................71
Multiply.................................................................................................................................................................................72
Multiply Halfword.................................................................................................................................................................73
Multiply Registers..................................................................................................................................................................74
Move Characters....................................................................................................................................................................75
Move Immediate....................................................................................................................................................................76
AND.......................................................................................................................................................................................77
AND Characters.....................................................................................................................................................................78
AND Immediate.....................................................................................................................................................................79
And Registers.........................................................................................................................................................................80
500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 3 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

OR..........................................................................................................................................................................................81
OR Characters........................................................................................................................................................................82
OR Immediate........................................................................................................................................................................83
OR Registers..........................................................................................................................................................................84
Origin Directive.....................................................................................................................................................................85
Pack........................................................................................................................................................................................86
Print Directive........................................................................................................................................................................88
Subtract..................................................................................................................................................................................90
Subtract Halfword..................................................................................................................................................................91
Shift Left Algebraic...............................................................................................................................................................92
Shift Left Double Algebraic...................................................................................................................................................93
Shift Left Double Logical......................................................................................................................................................94
Shift Left Logical...................................................................................................................................................................95
Insert Blank Lines Directive..................................................................................................................................................96
Subtract Registers..................................................................................................................................................................97
Shift Right Algebraic.............................................................................................................................................................98
Shift Right Logical.................................................................................................................................................................99
Shift Right Double Algebraic..............................................................................................................................................100
Shift Right Double Logical..................................................................................................................................................101
Store.....................................................................................................................................................................................102
Store Character....................................................................................................................................................................103
Store Characters Under Mask..............................................................................................................................................104
Store Halfword.....................................................................................................................................................................105
Store Multiple......................................................................................................................................................................106
Test Under Mask..................................................................................................................................................................107
Translate..............................................................................................................................................................................108
Translate and Test................................................................................................................................................................109
Unpack.................................................................................................................................................................................110
Declare Base Register Directive..........................................................................................................................................111
Exclusive OR.......................................................................................................................................................................112
Exclusive OR Characters.....................................................................................................................................................113
Exclusive OR Immediate.....................................................................................................................................................114
Exclusive OR Registers.......................................................................................................................................................115

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 4 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Table of Contents by Mnemonic

A..............................................................................................................................................................................................9
Add......................................................................................................................................................................................9
AD CON'S.............................................................................................................................................................................10
Address Constants..............................................................................................................................................................10
AH..........................................................................................................................................................................................12
Add Halfword....................................................................................................................................................................12
AR..........................................................................................................................................................................................13
Add Registers.....................................................................................................................................................................13
BAL.......................................................................................................................................................................................14
Branch and Link.................................................................................................................................................................14
BALR.....................................................................................................................................................................................15
Branch and Link Register..................................................................................................................................................15
BAS........................................................................................................................................................................................16
Branch and Save................................................................................................................................................................16
BASR.....................................................................................................................................................................................17
Branch and Save Register..................................................................................................................................................17
BC..........................................................................................................................................................................................18
Branch on Condition..........................................................................................................................................................18
B_...........................................................................................................................................................................................20
Branch on Condition _.......................................................................................................................................................20
BCR.......................................................................................................................................................................................22
Branch on Condition Register............................................................................................................................................22
B_R........................................................................................................................................................................................24
Branch on Condition _ Register.........................................................................................................................................24
BCT.......................................................................................................................................................................................26
Branch on Count................................................................................................................................................................26
BCTR.....................................................................................................................................................................................27
Branch on Count Register..................................................................................................................................................27
BEGIN...................................................................................................................................................................................28
BEGIN Macro....................................................................................................................................................................28
Boolean Algebra....................................................................................................................................................................29
Boolean Operations...............................................................................................................................................................30
C.............................................................................................................................................................................................31
Compare (Arithmetic)........................................................................................................................................................31
CH..........................................................................................................................................................................................32
Compare Halfword (Arithmetic)........................................................................................................................................32
CL..........................................................................................................................................................................................33
Compare Logical................................................................................................................................................................33
CLC........................................................................................................................................................................................34
Compare Logical Characters..............................................................................................................................................34
CLI.........................................................................................................................................................................................35
Compare Logical Immediate..............................................................................................................................................35
CLM.......................................................................................................................................................................................36
Compare Logical Characters Under Mask.........................................................................................................................36
CLR........................................................................................................................................................................................37
Compare Logical Registers................................................................................................................................................37
CR..........................................................................................................................................................................................38
Compare Registers (Arithmetic)........................................................................................................................................38
CSECT...................................................................................................................................................................................39
Define Control Section......................................................................................................................................................39
CVB.......................................................................................................................................................................................40
Convert to Binary...............................................................................................................................................................40
CVD.......................................................................................................................................................................................41
Convert to Decimal............................................................................................................................................................41
D............................................................................................................................................................................................42
Divide................................................................................................................................................................................42
500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 5 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DC..........................................................................................................................................................................................43
Define Constant.................................................................................................................................................................43
DR..........................................................................................................................................................................................45
Divide Registers.................................................................................................................................................................45
DROP.....................................................................................................................................................................................46
Drop Base Register(s) Directive........................................................................................................................................46
DS..........................................................................................................................................................................................47
Define Storage...................................................................................................................................................................47
DSECT...................................................................................................................................................................................49
Define Dummy Section......................................................................................................................................................49
ED..........................................................................................................................................................................................50
Edit.....................................................................................................................................................................................50
EJECT....................................................................................................................................................................................54
Skip to a New Page Directive............................................................................................................................................54
END.......................................................................................................................................................................................55
END Source Module Directive..........................................................................................................................................55
EQU.......................................................................................................................................................................................56
Equate Directive................................................................................................................................................................56
EX..........................................................................................................................................................................................58
Execute..............................................................................................................................................................................58
Expressions............................................................................................................................................................................61
FINIS.....................................................................................................................................................................................62
FINIS Macro......................................................................................................................................................................62
IC...........................................................................................................................................................................................63
Insert Character..................................................................................................................................................................63
ICM........................................................................................................................................................................................64
Insert Characters Under Mask...........................................................................................................................................64
L.............................................................................................................................................................................................65
Load...................................................................................................................................................................................65
LA..........................................................................................................................................................................................66
Load Address.....................................................................................................................................................................66
LH..........................................................................................................................................................................................67
Load Halfword...................................................................................................................................................................67
LM.........................................................................................................................................................................................68
Load Multiple....................................................................................................................................................................68
LR..........................................................................................................................................................................................69
Load Register.....................................................................................................................................................................69
LTORG..................................................................................................................................................................................70
Literal Origin Directive.....................................................................................................................................................70
LTR........................................................................................................................................................................................71
Load and Test Register......................................................................................................................................................71
M............................................................................................................................................................................................72
Multiply.............................................................................................................................................................................72
MH.........................................................................................................................................................................................73
Multiply Halfword.............................................................................................................................................................73
MR.........................................................................................................................................................................................74
Multiply Registers..............................................................................................................................................................74
MVC......................................................................................................................................................................................75
Move Characters................................................................................................................................................................75
MVI........................................................................................................................................................................................76
Move Immediate................................................................................................................................................................76
N............................................................................................................................................................................................77
AND...................................................................................................................................................................................77
NC..........................................................................................................................................................................................78
AND Characters.................................................................................................................................................................78
NI...........................................................................................................................................................................................79
AND Immediate.................................................................................................................................................................79
NR..........................................................................................................................................................................................80
And Registers.....................................................................................................................................................................80
500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 6 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

O............................................................................................................................................................................................81
OR......................................................................................................................................................................................81
OC..........................................................................................................................................................................................82
OR Characters....................................................................................................................................................................82
OI...........................................................................................................................................................................................83
OR Immediate....................................................................................................................................................................83
OR..........................................................................................................................................................................................84
OR Registers......................................................................................................................................................................84
ORG.......................................................................................................................................................................................85
Origin Directive.................................................................................................................................................................85
PACK.....................................................................................................................................................................................86
Pack....................................................................................................................................................................................86
PRINT....................................................................................................................................................................................88
Print Directive....................................................................................................................................................................88
Register Usage.......................................................................................................................................................................89
S.............................................................................................................................................................................................90
Subtract..............................................................................................................................................................................90
SH..........................................................................................................................................................................................91
Subtract Halfword..............................................................................................................................................................91
SLA........................................................................................................................................................................................92
Shift Left Algebraic...........................................................................................................................................................92
SLDA.....................................................................................................................................................................................93
Shift Left Double Algebraic...............................................................................................................................................93
SLDL.....................................................................................................................................................................................94
Shift Left Double Logical..................................................................................................................................................94
SLL........................................................................................................................................................................................95
Shift Left Logical...............................................................................................................................................................95
SPACE...................................................................................................................................................................................96
Insert Blank Lines Directive..............................................................................................................................................96
SR..........................................................................................................................................................................................97
Subtract Registers..............................................................................................................................................................97
SRA........................................................................................................................................................................................98
Shift Right Algebraic.........................................................................................................................................................98
SRL........................................................................................................................................................................................99
Shift Right Logical.............................................................................................................................................................99
SRDA...................................................................................................................................................................................100
Shift Right Double Algebraic..........................................................................................................................................100
SRDL...................................................................................................................................................................................101
Shift Right Double Logical..............................................................................................................................................101
ST.........................................................................................................................................................................................102
Store.................................................................................................................................................................................102
STC......................................................................................................................................................................................103
Store Character................................................................................................................................................................103
STCM..................................................................................................................................................................................104
Store Characters Under Mask..........................................................................................................................................104
STH......................................................................................................................................................................................105
Store Halfword.................................................................................................................................................................105
STM.....................................................................................................................................................................................106
Store Multiple..................................................................................................................................................................106
TM.......................................................................................................................................................................................107
Test Under Mask..............................................................................................................................................................107
TR........................................................................................................................................................................................108
Translate..........................................................................................................................................................................108
TRT......................................................................................................................................................................................109
Translate and Test............................................................................................................................................................109
UNPK..................................................................................................................................................................................110
Unpack.............................................................................................................................................................................110
USING.................................................................................................................................................................................111
Declare Base Register Directive......................................................................................................................................111
500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 7 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

X..........................................................................................................................................................................................112
Exclusive OR...................................................................................................................................................................112
XC........................................................................................................................................................................................113
Exclusive OR Characters.................................................................................................................................................113
XI.........................................................................................................................................................................................114
Exclusive OR Immediate.................................................................................................................................................114
XR........................................................................................................................................................................................115
Exclusive OR Registers...................................................................................................................................................115

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 8 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

A
Add
RX Type

Op code = 5A

Adds contents of a 4-byte storage area to the contents of a register. The result in placed in the register. The storage
location is unchanged.

label

R1,D2(X2,B2)

Use
Format
Spec

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

5A

5AR1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results
ZERO
MINUS
PLUS
OVERFLOW

Cond code
0
1
2
3

Examples:
R2 = X'00000010'
Addr 012816
=
or

A
A

R8 = 010816
LABEL1
= DC

R2,32(R0,R8)
R2,LABEL1

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

R2
0 0 0 0 0 0 1 C

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

After:
(hex bytes)

X'0000000C'

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 9 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

AD CON'S
Address Constants
Address Constants allow you to define a constant using a storage address or an absolute expression. An A CON defines
a fullword constant. A Y CON defines a halfword constant. When referencing an address, you must use the A CON.
When referencing the length of the data at an address, you can use the A CON or the Y CON. When specifying an
absolute expression, the address constant is equal to the value of the expression. The ADCON is allocated in storage
during LTORG generation.

dALn(c)
where

d =
A =
Ln =
(c) =

Duplication factor (decimal number)

A or Y
Length. Not normally used when (c) is a relocatable expression. If (c) is an absolute
expression, n can be 1 to 4 and no boundary alignment is forced.
expression, either absolute or relocatable

Defining a halfword constant as the data length of a relocatable expression

Example 1a:
LH
R1,=Y(L'LABEL1)
LABEL1

DC

C'MY NAME'

(length = 7)

This example loads the two least significant bytes of R1 with the halfword X'0007', which is the length of the
relocatable value LABEL1.
Example 1b:
UI2CNF
MSG

MVC

UI2CNF,=AL2(LMSG)

DS
DC

CL2
CGALILEO INTERNATIONAL(length = 7)

This example loads the 2 byte storage area UI2CNF with X0015, the length of the relocatable symbol MSG. No
boundary alignment is forced since a length specifier is used.
Defining a fullword constant as the address of a relocatable expression.
Example 2a:
L
R1,=A(LABEL1)
0140

LABEL1

DC

C'MY NAME'

(length = 7)

This example loads R1 with the fullword X00000140, which is the address of LABEL1. A fullword boundary
alignment is forced on the ADCON.
Example 2b:
0140

.
LABEL1

R1,=A(LABEL1+20)

DC

C'MY NAME'

(length = 7)

This example loads R1 with the fullword X00000154, which is the address of LABEL1 + 1416. A fullword
boundary alignment is forced on the ADCON.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 10 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

AD CON'S
Address Constants
(cont.)
Example 2c:
0140

.
ADDR1

R1,ADDR1

DC

A(*)

This example loads R1 with the fullword X00000140, which is the address of ADDR1. ADDR1 is forced to a fullword
boundary.
Defining a constant using an absolute expression.
Example 3a:
LABEL1
DC

AL2(51)

This example defines LABEL1 as the value X0033 (5110). No boundary alignment is forced since the length
specifier is used.
Example 3b:

LABEL1
FACTOR

DC
EQU

AL2(3*FACTOR-1)
4

This example has the same meaning as a constant defined by X000B. No boundary alignment is forced.
Example 3b:

MVC
LABEL1
ETX
LENTX

LABEL1(LENTX),ETX

DS
CL3
AL1(#CAR)
AL1(#SOM)
AL1(#EOM)
EQU *-ETX

This example loads the value X156E4E into the storage area LABEL1. The # denotes the use of the system
equates CAR, SOM and EOM which are absolute values ( #CAR = X15, #SOM = X6E, and #EOM =
X4E ). Note that since the expressions in the adcon statements resolve to absolute values, the address constants
take on the value of the expressions.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 11 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

AH
Add Halfword
RX Type

Op code = 4A

Adds contents of a 2-byte storage area to the contents of a register. The results are placed in the register. The storage
location is unchanged.

label

AH

R1,D2(X2,B2)
Operand 1
Destination
Register No.

Use
Format
Spec

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

R = Register #
or Symbolic Name
of Register

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

4A

4AR1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results
ZERO
MINUS
PLUS
OVERFLOW

Cond code
0
1
2
3

Example:
R2 = X'00000010'
Addr 012816
=
or
or

AH
AH
AH

R8 = 010816
LABEL1
= DC

R2,32(R0,R8) or R2,32(R8) or R2,32(,R8)

R2,LABEL1
R2,=H'12'

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

Addr 12816
LABEL1
0 0 0 C

R2
0 0 0 0 0 0 1 C

Addr 012816
LABEL1
0 0 0 C

After:
(hex bytes)

H'12'

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 12 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

AR
Add Registers
RR Type

Op code = 1A

Adds contents of a two Registers. The result in placed in the register specified in operand 1. The register specified in
operand 2 is unchanged.

label

AR
Use
Format
Spec

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Operand 2
Source
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

1A

1AR1R2
The condition code is set according to the results in Operand 1 as follows:
Results
ZERO
MINUS
PLUS
OVERFLOW

Cond code
0
1
2
3

Example:
R2 = X'00000010'
AR

R8 = X'00000023'

R2,R8

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

R8
0 0 0 0 0 0 2 3

R2
0 0 0 0 0 0 3 3

R8
0 0 0 0 0 0 2 3

After:
(hex bytes)

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 13 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BAL
Branch and Link
RX Type

Op code = 45

Saves the address of the next sequential instruction in the register specified in operand 1 and branches to the subroutine
specified in operand 2. In order to return from the subroutine, it should end with a branch instruction, such as the BR
(Branch Register), that references the address in the operand 1 register. This allows you to utilize subroutines for common
routines. The BAS instruction replaces the BAL instruction which was used in programs designed for 24-bit
architecture.

label

BAL
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Return address
(next instruction
after BAS)
Register No.
R = Register #
or Symbolic Name
of Register

Operand 2
Subroutine address
Base/Index/Displac
or symbolic label
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

45

45R1X2B2DDD2
Example:
0078

BACKIN

SUBRTNE

BAL
.
.
.
.
.
.
.
.
BR

R2,SUBRTNE

Save X78 in R2 & Branch to subroutine

Return here from subroutine

Start of subroutine

R2

Return to mainline (BACKIN)

Note: If you see BAL in any Galileo assembler coding, it should be

replaced with BAS.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 14 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BALR
Branch and Link Register
RR Type

Op code = 05

Saves the address of the next sequential instruction in the register specified in operand 1 and branches to the subroutine
whose address is in the register specified in operand 2. In order to return from the subroutine, it should end with a branch
instruction, such as the BR (Branch Register), that references the address in the operand 1 register. This allows you to
utilize subroutines for common routines. The BASR instruction replaces the BALR instruction which was used in
programs designed for 24-bit architecture.

label

BALR
Use
Format
Spec

R1,R2

Operand 1
Return address
(next instruction
after BAL)
Register No.
R = Register #
or Symbolic Name
of Register

Operand 2
Subroutine address
Register No
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

05

05R1R2
Examples:
R3 =
0078

BACKIN

01C2

SUBRTNE

01C216
BALR
.
.
.
.
.
.
.
.
BR

R2,R3

Save X78 in R2 & Branch to subroutine

Return here from subroutine

Start of subroutine

R2

Return to mainline (BACKIN)

Note: If you see BALR in any Galileo assembler coding, it should be

replaced with BASR.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 15 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BAS
Branch and Save
RX Type

Op code = 4D

Saves the address of the next sequential instruction in the register specified in operand 1 and branches to the subroutine
specified in operand 2. In order to return from the subroutine, it should end with a branch instruction, such as the BR
(Branch Register), that references the address in the operand 1 register. This allows you to utilize subroutines for common
routines. The BAS instruction replaces the BAL instruction which was used in programs designed for 24-bit architecture.

label

BAS
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Return address
(next instruction
after BAS)
Register No.
R = Register #
or Symbolic Name
of Register

Operand 2
Subroutine address
Base/Index/Displac
or symbolic label
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

4D

4DR1X2B2DDD2
Example:
0078

BACKIN

SUBRTNE

BAS
.
.
.
.
.
.
.
.
BR

R2,SUBRTNE

Save X78 in R2 & Branch to subroutine

Return here from subroutine

Start of subroutine

R2

Return to mainline (BACKIN)

Note: If you see BAL in any Galileo assembler coding, it should be

replaced with BAS.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 16 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BASR
Branch and Save Register
RR Type

Op code = 0D

Saves the address of the next sequential instruction in the register specified in operand 1 and branches to the subroutine
whose address is in the register specified in operand 2. In order to return from the subroutine, it should end with a branch
instruction, such as the BR (Branch Register), that references the address in the operand 1 register. This allows you to
utilize subroutines for common routines. The BASR instruction replaces the BALR instruction which was used in
programs designed for 24-bit architecture.

label

BASR R1,R2
Use
Format
Spec

Operand 1
Return address
(next instruction
after BAL)
Register No.
R = Register #
or Symbolic Name
of Register

Operand 2
Subroutine address
Register No
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

0D

0DR1R2
Examples:
R3 =
0078

BACKIN

01C2

SUBRTNE

01C216
BASR
.
.
.
.
.
.
.
.
BR

R2,R3

Save X78 in R2 & Branch to subroutine

Return here from subroutine

Start of subroutine

R2

Return to mainline (BACKIN)

Note: If you see BALR in any Galileo assembler coding, it should be

replaced with BASR.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 17 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BC
Branch on Condition
RX Type

Op code = 47

Branch to the address specified in operand 2 if the condition code in the PSW satisfies the mask specified in operand 1.

label

BC

M1,D2(X2,B2)
Operand 1
Mask
Halfword
or Binary
Decimal value or
Halfword literal
or Binary Number

Use
Format
Spec

Operand 2
Address
Base/Index/Displac
or symbolic label
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE M1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

47

47M1X2B2DDD2
The condition code (CC) in the PSW indicates the condition after the last compare, arithmetic, or Test Under Mask
operation. The CC also determines which of 4 test bits are to be matched or (non-matched) to the mask, as follows:
Condition(s)
(bit number to
match)
Condition
code
00
01
10
11

Equal
or Zero
Bit
0
1
0
0
0

Low
or
Minus
Bit
1
0
1
0
0

High
or
Plus
Bit
2
0
0
1
0

Overflow
or
Ones
Bit
3
0
0
0
1

Mask
(Decimal)
8
4
2
1

The following table shows the branch condition, mask specifier, and machine code for each of the possible conditions
used for BC instruction.
Branch
Condition
Unconditional
NOP
High
Low
Equal
Not High
Not Low
Not Equal
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
Ones
Mixed
Zero's
Not Ones
Not Mixed
Not Zero's
Not Zero
Zero

Mask
(Decimal)
15
0
2
4
8
13
11
7
2
4
8
1
13
11
7
14
1
4
8
14
11
7
4
8

Mask
(Binary)
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1

1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0

1
0
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
0
1
0
0

1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
0
0

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 18 ]

Machine code

Operation which
set condition

47F
470
472
474
478
47D
47B
477
472
474
478
471
47D
47B
477
47E
471
474
478
47E
47B
477
474
478

General
"
Compare
"
"
'
"
"
Arithmetic
"
"
"
"
"
"
"
Test Under Mask
"
"
"
'
"
Boolean
"

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BC
Branch on Condition
(cont.)
Example 1:
(Arithmetic)

PGM40100

DATA1

.
SR
S.
BC
.
B
EQU
.
.
B
DC

R2,R2
R2,DATA
4,PGM40100
NEXTSEG1
*
NEXTSEG2
F'21'

Set R2 to zero
Subtract F'21' from zero
Branch to PGM40100 if result is minus
Else continue here.
Branch to next segment

.
Branch to next segment
Set LABEL1=21

In this example the branch will be taken since the result of the subtract operation is a negative number.
Example 2:
(Compare)

PGM40100

DATA1

L
ST
CLC
BC
.
B
EQU
.
.
B
DS

R3,F'12'
R3,DATA1
DATA1,F'12'
8,PGM40100
NEXTSEG1
*
NEXTSEG2
F

Set R3 = 12
Save R3 in DATA1
Compare DATA1 to F'12'
Branch to PGM40100 if DATA1 = F'12'
Else continue here.
Branch to next segment

.
Branch to next segment
Define fullword variable

In this example the branch will be taken since the result of the compare operation is equal.
Example 3:
(Test Under Mask)

PGM40100

DATA1

LH
STH
TM
BC
.
B
EQU
.
.
B
DS

R3,H'146'
Set R3 = 146 (X'0092') (B'10010010')
R3,DATA1
Save H'146' in DATA1
DATA1,B'00000010'
Test under mask using H'2'
1,PGM40100
Branch if TM left any one's
Else continue here.
NEXTSEG1
Branch to next segment
*
.
NEXTSEG2
H

Branch to next segment

Define fullword variable

In this example the branch will be taken since the result of the test under mask operation leaves a one in bit 6:
DATA1
10010010
Mask
00000010
____________
TM Result 0 0 0 0 0 0 1 0

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 19 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

B_
Branch on Condition _
RX Type

Op code = 47

Branch to the address specified in operand if the condition code in the PSW satisfies the condition specified in the branch
mnemonic.

label

B_
Use
Format
Spec

D(X,B)
B_
Branch Mnemonic
See Branch Mnemonic
Table
Characters (see table
below)

Operand
Address
Base/Index/Displac
or symbolic label
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE
_
X
B
D
0-7

8-11

12-15

16-19

20-31

47

47_XBDDD
The following table shows the branch condition, branch mnemonic, and machine code for each of the possible branch
conditions.
Branch
Condition
(Branch if...)
Unconditional
NOP
High
Low
Equal
Not High
Not Low
Not Equal
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
Ones
Mixed
Zero's
Not Ones
Not Mixed
Not Zero's
Not Zero
Zero

Branch
Mnemonic
(B_)

Machine code
(47_)

Operation which
set condition

B
NOP
BH
BL
BE
BNH
BNL
BNE
BP
BM
BZ
BO
BNP
BNM
BNZ
BNO
BO
BM
BZ
BNO
BNM
BNZ
BNZ
BZ

47F
470
472
474
478
47D
47B
477
472
474
478
471
47D
47B
477
47E
471
474
478
47E
47B
477
474
478

General
"
Compare
"
"
'
"
"
Arithmetic
"
"
"
"
"
"
"
Test Under Mask
"
"
"
'
"
Boolean"
"

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 20 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

B_
Branch on Condition _
(cont.)
Example 1:
(Arithmetic)

PGM40100

DATA1

SR
S
BM
.
B
EQU
.
.
B
DC

R2,R2
R2,DATA1
PGM40100
NEXTSEG1
*
NEXTSEG2
F'21'

Set R2 to zero
Subtract F'21' from zero
Branch to PGM40100 if result is minus
Else continue here.
Branch to next segment

.
Branch to next segment
Set LABEL1=21

In this example the branch will be taken since the result of the subtract operation is a negative number.
Example 2:
(Compare)

PGM40100

DATA1

L
ST
CLC
BE
.
B
EQU
.
.
B
DS

R3,F'12'
R3,DATA1
DATA1,F'12'
PGM40100
NEXTSEG1
*
NEXTSEG2
F

Set R3 = 12
Save R3 in DATA1
Compare DATA1 to F'12'
Branch to PGM40100 if DATA1 = F'12'
Else continue here.
Branch to next segment

.
Branch to next segment
Define fullword variable

In this example the branch will be taken since the result of the compare operation is equal.
Example 3:
(Test Under Mask)

PGM40100

DATA1

LH
STH
TM
BO
.
B
EQU
.
.
B
DS

R3,H'146'
Set R3 = 146 (X'0092') (B'10010010')
R3,DATA1
Save H'146' in DATA1
DATA1,B'00000010'
Test under mask using H'2'
PGM40100
Branch if TM left any one's
Else continue here.
NEXTSEG1
Branch to next segment
*
.
NEXTSEG2
H

Branch to next segment

Define fullword variable

In this example the branch will be taken since the result of the test under mask operation leaves a one in bit 6:
DATA1
10010010
Mask
00000010
____________
TM Result 0 0 0 0 0 0 1 0

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 21 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BCR
Branch on Condition Register
RR Type

Op code = 07

Branch to the address contained in the register in operand 2 if the condition code in the PSW satisfies the mask specified
in operand 1.

label

BCR

M,R
Operand 1
Mask
Halfword
or Binary
Decimal value for
Halfword literal
or Binary Number

Use
Format
Spec

Operand 2
Address
Register No
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE
M
R
0-7

8-11

12-15

07

07MR
The condition code (CC) in the PSW indicates the condition after the last compare, arithmetic, or Test Under Mask
operation. The CC also determines which of 4 test bits are to be matched or (non-matched) to the mask, as follows:
Condition
code
00
01
10
11

Bit
0
1
0
0
0

Bit
1
0
1
0
0

Bit
2
0
0
1
0

Bit
3
0
0
0
1

Mask
8
4
2
1

The following table shows the branch condition, mask specifier, and machine code for each of the possible conditions
used for BCR instruction.
Branch
Condition
Unconditional
NOP
High
Low
Equal
Not High
Not Low
Not Equal
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
Ones
Mixed
Zero's
Not Ones
Not Mixed
Not Zero's
Not Zero
Zero

Mask
(Decimal)
15
0
2
4
8
13
11
7
2
4
8
1
13
11
7
14
1
4
8
14
11
7
4
8

Mask
(Binary)
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
1
1
0
0
1

1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0

1
0
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
0
1
0
0

1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
0
0
1
1
0
0

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 22 ]

Machine code

Operation which
set condition

07F
070
072
074
078
07D
07B
077
072
074
078
071
07D
07B
077
07E
071
074
078
07E
07B
077
074
078

General
"
Compare
"
"
'
"
"
Arithmetic
"
"
"
"
"
"
"
Test Under Mask
"
"
"
'
"
Boolean
"

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BCR
Branch on Condition Register
(cont.)
Example 1:
(Arithmetic)

PGM40100

DATA1

LA
SR
S.
BCR
.
B
EQU
.
.
B
DC

R4,PGM40100
R2,R2
R2,DATA
4,R4
NEXTSEG1
*
NEXTSEG2
F'21'

Load R4 with addr of PGM40100

Set R2 to zero
Subtract F'21' from zero
Branch to PGM40100 if result is minus
Else continue here.
Branch to next segment

.
Branch to next segment
Set LABEL1=21

In this example the branch will be taken since the result of the subtract operation is a negative number.
Example 2:
(Compare)

PGM40100

DATA1

LA
L
ST
CLC
BCR
.
B
EQU
.
.
B
DS

R4,PGM40100
R3,F'12'
R3,DATA1
DATA1,F'12'
8,R4
NEXTSEG1
*
NEXTSEG2
F

Load R4 with addr of PGM40100

set R3 = 12
Save R3 in DATA1
Compare DATA1 to F'12'
Branch to PGM40100 if DATA1 = F'12'
Else continue here.
Branch to next segment

.
Branch to next segment
Define fullword variable

In this example the branch will be taken since the result of the compare operation is equal.
Example 3:
(Test Under Mask)

PGM40100

DATA1

LA
LH
STH
TM
BCR
.
B
EQU
.
.
B
DS

R4,PGM40100
Load R4 with addr of PGM40100
R3,H'146'
set R3 = 146 (X'0092') (B'10010010')
R3,DATA1
Save H'146' in DATA1
DATA1,B'00000010'
Test under mask using H'2'
1,R4
Branch if TM left any one's
Else continue here.
NEXTSEG1
Branch to next segment
*
.
NEXTSEG2
H

Branch to next segment

Define fullword variable

In this example the branch will be taken since the result of the test under mask operation leaves a one in bit 6:
DATA1
10010010
Mask
00000010
____________
TM Result 0 0 0 0 0 0 1 0

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 23 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

B_R
Branch on Condition _ Register
RR Type

Op code = 07

Branch to the address contained in the register in operand 2 if the condition code in the PSW satisfies the branch
mnemonic.

label

B_R
Use
Format
Spec

R
B_
Branch Mnemonic
See Branch Mnemonic
Table
Characters (see table
below)

Operand
Address
Register No
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE
_
R
0-7

8-11

12-15

07

07_R
The following table shows the branch condition, branch mnemonic, and machine code for each of the possible branch
conditions.
Branch
Condition
(Branch if...)
Unconditional
NOP
High
Low
Equal
Not High
Not Low
Not Equal
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
Ones
Mixed
Zero's
Not Ones
Not Mixed
Not Zero's
Not Zero
Zero

Branch
Mnemonic
(B_R

Machine code
(07_)

Operation which
set condition

BR
NOP
BHR
BLR
BER
BNHR
BNLR
BNER
BPR
BMR
BZR
BOR
BNPR
BNMR
BNZR
BNOR
BOR
BMR
BZR
BNOR
BNMR
BNZR
BNZR
BZR

07F
070
072
074
078
07D
07B
077
072
074
078
071
07D
07B
077
07E
071
074
078
07E
07B
077
074
078

General
"
Compare
"
"
'
"
"
Arithmetic
"
"
"
"
"
"
"
Test Under Mask
"
"
"
'
"
Boolean
"

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 24 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

B_R
Branch on Condition _Register
(cont.)
Example 1:
(Arithmetic)

PGM40100

DATA1

LA
SR
S.
BMR
.
B
EQU
.
.
B
DC

R4,PGM40100
R2,R2
R2,DATA
R4
NEXTSEG1
*
NEXTSEG2
F'21'

Load R4 with addr of PGM40100

Set R2 to zero
Subtract F'21' from zero
Branch to PGM40100 if result is minus
Else continue here.
Branch to next segment

.
Branch to next segment
Set LABEL1=21

In this example the branch will be taken since the result of the subtract operation is a negative number.
Example 2:
(Compare)

PGM40100

DATA1

LA
L
ST
CLC
BER
.
B
EQU
.
.
B
DS

R4,PGM40100
R3,F'12'
R3,DATA1
DATA1,F'12'
R4
NEXTSEG1
*
NEXTSEG2
F

Load R4 with addr of PGM40100

Set R3 = 12
Save R3 in DATA1
Compare DATA1 to F'12'
Branch to PGM40100 if DATA1 = F'12'
Else continue here.
Branch to next segment

.
Branch to next segment
Define fullword variable

In this example the branch will be taken since the result of the compare operation is equal.
Example 3:
(Test Under Mask)

PGM40100

DATA1

LA
LH
STH
TM
BOR
.
B
EQU
.
.
B
DS

R4,PGM40100
Load R4 with addr of PGM40100
R3,H'146'
Set R3 = 146 (X'0092') (B'10010010')
R3,DATA1
Save H'146' in DATA1
DATA1,B'00000010'
Test under mask using H'2'
R4
Branch if TM left any one's
Else continue here.
NEXTSEG1
Branch to next segment
*
.
NEXTSEG2
H

Branch to next segment

Define fullword variable

In this example the branch will be taken since the result of the test under mask operation leaves a one in bit 6:
DATA1
10010010
Mask
00000010
____________
TM Result 0 0 0 0 0 0 1 0

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 25 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BCT
Branch on Count
RX Type

Op code = 46

Branches to the address specified in operand 2 as long as the value in the register specified in operand 1 is not 0. Used for
executing loops a given number of times. The register gets decremented and tested for 0 after each time through the loop.

label

BCT
Use
Format
Spec

R,D(X,B)
Operand 1
No. of times to loop
Register No.
R = Register #
or Symbolic Name
of Register

Operand 2
Branch to Addr
Base/Index/Displac
or label
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE
R
X
B
D
0-7

8-11

12-15

16-19

20-31

46

46RXBDDD
Example:
LOOPSTRT

PGM40100

LA
EQU
.
.
.
BCT
EQU
.
.

R4,4
*

Load R4 with decimal 4

Start of loop

R4,LOOPSTRT
*

Branch to start of loop if R4 not = 0

In this example the LOOPSTRT routine will be executed 4 times. Each time the BCT is executed, R4 is
decremented by 1 and tested for 0. If R4 is not 0 , the program branches back to LOOPSTRT. Once R4 is
decremented to 0, the program logic falls through to the PGM40100 routine. Below is a pictorial representation
of the example.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 26 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BCTR
Branch on Count Register
RR Type

Op code = 06

Branches to the address contained in the register specified in operand 2 as long as the value in the register specified in
operand 1 is not 0. Used for executing loops a given number of times. The register gets decremented and tested for 0
after each time through the loop. No branch occurs if the value in the contents of the second register equal 0.

label

BCTR R1,R2
Use
Format
Spec

Operand 1
No. of times to loop
Register No.
R = Register #
or Symbolic Name
of Register

Operand 2
Branch to Addr
Register No.
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

06

06AR1R2
Example 1:
LOOPSTRT

PGM40100

LA
LA
EQU
.
.
.
BCTR
EQU
.
.

R2,LOOPSTRT
R4,4
*

Load R2 with addr of LOOPSTRT

Load R4 with decimal 4
Start of loop

R4,R2
*

Branch to start of loop if R4 not = 0

In this example the LOOPSTRT routine will be executed 4 times. Each time the BCT is executed, R4 is
decremented by 1 and tested for 0. If R4 is not 0 , the program branches back to LOOPSTRT. Once R4 is
decremented to 0, the program logic falls through to the PGM40100 routine. Below is a pictorial representation
of the example.
This instruction can also be used to subtract 1 from a register, since no branch occurs if the contents of the second register
equals 0.
Example 2:

BCTR
R7,R0
..........

Decrement R7 and don't branch since R0=0

Next Instruction performed

BCTR

Decrement R7 and don't branch since 2nd

operand = 0
Next Instruction performed

similarly
R7,0

..........

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 27 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

BEGIN
BEGIN Macro
BEGIN NAME=Program Name
where Program Name = 6 character Component (Segment) name and version number of your
program.
The BEGIN macro establishes the standard base registers and linkages for your program. The BEGIN statement must be
the first statement in your source code beginning at column 10. The program name must start at column 16.
Example:
1
2
3
STMT 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
0
0
0
0
0
0
0

0
0
0
0
0
0
0

1
2
3
4
5
6
7

*
*
*
*
*

B
P
* * * * * * * * *
T H I S
P R O
O F
T H E
I
* * * * * * * * *

E
R
*
G
N
*

G
I
*
R
C
*

I
N
*
A
O
*

N
N A M
T
N O G
* * * * *
M
C H E
M I N G
* * * * *

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 28 ]

E
E
*
C
M
*

=
N
*
K
E
*

P G M 4 T 3
* * * * * * * * *
S
T H E
S T A
S S A G E
A F T
* * * * * * * * *

*
T
E
*

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Boolean Algebra
LOGICAL 'OR' TRUTH TABLE
SOURCE BIT
(Mask)

"OR"ed
AGAINST

TARGET BIT

Equals

RESULTING
TARGET BIT

LOGICAL 'AND' TRUTH TABLE

SOURCE BIT
(Mask)

"AND"ed
AGAINST

TARGET BIT

Equals

RESULTING
TARGET BIT

LOGICAL 'XOR' (Exclusive OR) TRUTH TABLE

SOURCE BIT
RESULTING
"XOR"ed
AGAINST
Equals
(Mask)
TARGET BIT
TARGET BIT

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 29 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Boolean Operations
Use OR to selectively turn target bits ON. A 1 turns the target bit on, and a 0 leaves the target bit as it was.
Example:

LABEL1

DC
OI

Before:

B'10100110'
LABEL1,H'16'

OR Immediate LABEL1 with B'00010000'

LABEL1

Bit #
(bits)

After:
6

1 0 1 0 0 1 1 0
0 0 0 1 0 0 0 0

OR H16

LABEL1

Bit #
(bits)

1 0 1 1 0 1 1 0

This example turns on bit 3 of the LABEL1 storage area.

____________________________________________________________________________________________
Use AND to selectively turn target bits OFF. A 0 turns the target bit off, and a 1 leaves the target bit as it was.
Example:

LABEL1

DC
NI

B'11111011'

Before:

B'10100110'
LABEL1,H'251'

LABEL1

Bit #
(bits)

After:
6

1 0 1 0 0 1 1 0
1 1 1 1 1 0 1 1

AND H251

AND Immediate LABEL1 with

LABEL1

Bit #
(bits)

1 0 1 0 0 0 1 0

This example turns off bit 5 of the LABEL1 storage area.

____________________________________________________________________________________________
Use XOR to selectively TOGGLE target bits. A 1 toggles the target bit, and a 0 leaves the target bit as it was.
Example:

LABEL1

DC
XI

B'00000011'

Before:
Bit #
(bits)
XOR H3

B'10100110'
LABEL1,H'3'

LABEL1
0

XOR Immediate LABEL1 with

After:
6

Bit #
(bits)

1 0 1 0 0 1 1 0
0 0 0 0 0 0 1 1

LABEL1
0

1 0 1 0 0 1 0 1

This example toggles bits 7 & 8 of the LABEL1 storage area.

____________________________________________________________________________________________
The XOR operation can be used to SWAP the contents of two storage areas (XC instruction), two registers (XR
instruction), or between a register and storage (X instruction).
Example:

DOG
CAT

DC
DC
XC
XC
XC

C'DOG'
C'CAT'
DOG,CAT
CAT,DOG
DOG,CAT

This example swaps the contents of the storage areas DOG and CAT.
____________________________________________________________________________________________
The XOR operation can also be used to CLEAR a storage area
Example:

XC

DOG,DOG

This example clears the storage area DOG.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 30 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

C
Compare (Arithmetic)
RX Type

Op code = 59

Compares the contents of a 4-byte storage area to the contents of a register. The compare treats the two numbers as signed
binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is unchanged.

label

R1,D2(X2,B2)

Use
Format
Spec

Operand 1
Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Storage Area
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

59

59R1X2B2DDD2
The condition code is set according to the results as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
R2 = X'00000010'
Addr 012816
=
or

C
C

R8 = 010816
LABEL1
= DC

X'00000010' (or F'16')

R2,32(R8)
R2,LABEL1

In this example, the condition code would be set to 0 since the contents of R2 and LABEL1 are equal.
Example 2:
R2 = F'27'
Addr 012816
or

C
C

R8 = 010816
= LABEL1

DC

F'-27'

R2,32(R8)
R2,LABEL1

In this example, the condition code would be set to 2 since the contents of R2 is greater then the contents of
LABEL1.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 31 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CH
Compare Halfword (Arithmetic)
RX Type

Op code = 49

Compares the contents of a 2-byte storage area to the 2 low-order bytes of a register. The compare treats the two numbers
as signed binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is unchanged.

label

CH
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Storage Area
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

49

49R1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example1:
R2 = X'00000010'
Addr 012816
=
or

CH
CH

R8 = 010816
LABEL1
= DC

X'0010' (or H'16')

R2,32(R8)
R2,LABEL1

In this example, the condition code would be set to 0 since the contents of R2 (2 low-order bytes) and LABEL1
are equal.
Example2:
R2 = X'00000010'
Addr 012816
=
or

CH
CH

R8 = 010816
LABEL1
= DC

H'-16'

R2,32(R8)
R2,LABEL1

In this example, the condition code would be set to 2 since the contents of R2 (2 low-order bytes) is greater then
the contents of LABEL1.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 32 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CL
Compare Logical
RX Type

Op code = 55

Compares the contents of a 4-byte storage area to the contents of a register. The compare is made left to right, bit for bit.
The two numbers are treated as unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The
storage location is unchanged.

label

CL
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Storage Area
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

55

55R1X2B2DDD2
The condition code is set according to the results as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
R2 = CABCD'
Addr 012816
=
or

CL
CL

R8 = 010816
LABEL1
= DC

CABCD

R2,32(R8)
R2,LABEL1

In this example, the condition code would be set to 0 since the contents of R2 and LABEL1 are equal.
Example 2:
R2 = C'ABCD' (XC1C2C3C4)
Addr 012816
= LABEL1
=
or

CL
CL

DC

R8 = 010816
C1234 (XF1F2F3F4)

R2,32(R8)
R2,LABEL1

In this example, the condition code would be set to 1 since the contents of R2 is less then the contents of
LABEL1. Note that the sign of the number in LABEL1 is negative, but since sign is not taken into consideration,
the contents of LABEL1 are greater then the contents of R2.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 33 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CLC
Compare Logical Characters
SS Type

Op code = D5

Compares the contents of two storage areas. The compare is made left to right, bit for bit. The two numbers are treated as
unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage locations are
unchanged.

label

CLC

D1(L,B1),D2(B2)

Operand 1
Operand 2
Storage Area 1
Storage Area 2
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.
Use
Format

Machine code Instruction Length = Fullword

L
B2
D1
B2

OP CODE
0-7

8-15

16-19

20-31

D2

32-35 36-48

D5

D5LLB1DDD1B2DDD2
The condition code is set according to the results as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
R8 = 000A16
Addr 010A16
Addr 012816
CLC

=
=

LABEL1
LABEL2

=
=

DC
DC

C'CODE'
C'CODED'

256(4,R8),286(R8)

In this example, the condition code would be set to 0 since the first 4 bytes of LABEL1 and the first 4 bytes of
LABEL2 are equal. The length of the compare is 4 bytes.
Example 2:
=
=
CLC

LABEL1
LABEL2

=
=

DC
DC

C'DEAR'
C'DEER'

LABEL1,LABEL2

In this example, the condition code would be set to 1 since the first 4 bytes of LABEL1 are lower in value than
first 4 bytes of LABEL2. The length of the compare defaults to the length of LABEL1 as it was defined (4
bytes)..
Example 3:
=
=

LABEL1
LABEL2

=
=

DC
DC

C'DEAR'
C'DEER'

CLC

LABEL1(2),LABEL2

CLC

LABEL1(L'LABEL2-2),LABEL2

or
In this example, the condition code would be set to 0 since the first 2 bytes of LABEL1 are equal to the first 2
bytes of LABEL2. The length of the compare is 2 bytes.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 34 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CLI
Compare Logical Immediate
SI Type

Op code = 95

Compares the 1-byte of storage area to immediate data. The compare is made left to right, bit for bit. The two numbers
are treated as unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage location
is unchanged.

label

CLI

D1(B1),I2
Operand 1
Storage Area

Use
Format
Spec

Operand 2
Source Data
(Immediate)
Literal

Base/Displacement
or Label
D = Decimal value
B = Register # or
symbolic Reg name

Absolute expression
such as:
C.., X.., B.., or a
decimal value.

* Length is fixed at 1 byte.

Machine code Instruction Length = Fullword
OP CODE
I
I
B2
D2
0-7

8-15

16-19

20-31

95

95II2B1DDD1
The condition code is set according to the results as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
R8 = 010816
or

CLI
CLI

LABEL1

DC

X'0F'

0(R8),X'0F'
LABEL1,X'0F'

In this example, the condition code would be set to 0 since the contents of LABEL1 is equal to the immediate
data, X'0F'
( Notice, the immediate data is specified as X0Fand not with an equal sign, i.e. =X0F )
Example 2:
R8 = 010816
or

CLI
CLI

addr of LABEL1

DC

C'B'

0(R8),C'A'
LABEL1,C'A'

In this example, the condition code would be set to 2 since the immediate data ('A'=EBCDIC C1) is less then the
contents of LABEL1 ('B'=EBCDIC C2).

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 35 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CLM
Compare Logical Characters Under Mask
RS Type

Op code = BD

Compares the contents of selected bytes of a register with the left most 1 to 4 bytes of a storage area. The two numbers
are treated as unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage location
is unchanged. The bits of the mask correspond one-to-one with the bytes of the register.

label

CLM

R1,M,D3(B3)

Operand 1
Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Use
Format
Spec

Operand 2
Mask
Binary, Hex, or Decimal
Value
0-15
Binary, Hex, or Decimal
Value
0-15

Operand 3
Storage Area
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
M
B3
D3
0-7

8-11

12-15

16-19

20-31

BD

BDR1X2B3DDD3
The condition code is set according to the results as follows:
Results
EQUAL
or
Mask = 0
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
or

CLM

R2,B'1010',LABEL1

Mask

R2

0
compare these bytes

LABEL1

In this example, the condition code would be set to 0 since the bytes 1 and 3 of R2 are equal to the first two bytes
of LABEL1.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 36 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CLR
Compare Logical Registers
RR Type

Op code = 15

Compares the contents of two registers. The compare is made left to right, bit for bit. The two numbers are treated as
unsigned binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is unchanged..

label

CLR
Use
Format
Spec

R1,R2
Operand 1
Address
Register No
R = Register #
or Symbolic Name
of Register

Operand 2
Address
Register No
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

15

15R1R2
The condition code is set according to the results as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
R2 = X'000000FF'
CLR

R3 = X000000FF

R2,R3

In this example, the condition code would be set to 0 since the contents of R2 and R3 are equal.
Example 2:
R2 = X'000000FF'
CLR

R3 = XF00000F4

R2,R3

In this example, the condition code would be set to 1 since the contents of R2 is less than the contents of R3.
Note that the sign of the number in R3 is negative, but since sign is not taken into consideration, the contents of
R3 are greater then the contents of R2.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 37 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CR
Compare Registers (Arithmetic)
RR Type

Op code = 19

Compares the contents of a register to the contents of another register. The compare treats the two numbers as signed
binary numbers. The result is saved in the Condition code bits of the PSW. The storage location is unchanged.

label

CR
Use
Format
Spec

R1,R2
Operand 1
Address
Register No
R = Register #
or Symbolic Name
of Register

Operand 2
Address
Register No
R = Register #
or Symbolic Name
of Register

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

19

19R1R2
The condition code is set according to the results as follows:
Results
EQUAL
1st Opr LOW
1st Opr HIGH
N/A

Cond code
0
1
2
3

Example 1:
R2 = X'000000FF'
CR

R3 = X000000FF

R2,R3

In this example, the condition code would be set to 0 since the contents of R2 and R3 are equal.
Example 2:
R2 = X'000000FF'
CR

R3 = XF00000F4

R2,R3

In this example, the condition code would be set to 2 since the contents of R2 is greater than the contents of R3.
Note that the sign of the number in R3 is negative.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 38 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CSECT
Define Control Section
(Assembler Directive)
The CSECT directive indicates the beginning of the program. When preceded by a dummy section (DSECT), CSECT
also indicates the end of the DESCT and the beginning of the program. The CSECT directive statement must contain a
label, and the label must the same as the program name, for example, PGM4.

label

CSECT

Example:
BEGIN NAME=PGM4,VER=T3
PRINT NOGEN
*
PROGRAM DESCRIPTION AREA
*
*
.
*
*
.
*
*
.
*
***********************************************************************
***********************************************************************
*
FLIGHT RECORD DSECT
*
*
.
*
***********************************************************************
FLTREC
DSECT
FFHDR
DS
CL18
HEADER INFO
.
.
.
.
*---------------------------------------------------------------------*
PASSENGER INFORMATION
*
*---------------------------------------------------------------------FPITM
DS
XL140
10 PASSENGER ITEMS
*
(14 BYTES PER ITEM)
ORG
FPITM
*
FPIND1
DS
XL1
SWITCH BYTE NUMBER 1
.
.
.
.
.
FPLEN
EQU
*-FPIND1
*---------------------------------------------------------------------*
END OF FLIGHT RECORD DSECT
*
*---------------------------------------------------------------------***********************************************************************
PGM4
CSECT
***********************************************************************
*
BEGIN MAINLINE PORTION OF PROGRAM
*
***********************************************************************
PGM40000 EQU
*
USING FLTREC,R7
.
.

This example show the use of the CSECT directive to end the DSECT and begin the control section of the
program Note the label of the CSECT statement is PGM4, the same as the program name.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 39 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CVB
Convert to Binary
RX Type

Op code = 4F

Converts a packed decimal storage area specified in Operand 2 to binary and places it in the register specified by Operand
1. All 8 bytes of the doubleword specified by Operand 2 must be in packed decimal format or a program check will
result.

label

CVB

R1,D2(X2,B2)
Operand 1
Destination
Register No.

Use
Format
Spec

R = Register #
or Symbolic Name
of Register

Operand 2*
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

* The effective address of Operand 2 must be on a double word boundary.

Machine code Instruction Length = Fullword
OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

4F

4FR1X2B2DDD2
The condition code is not affected by the CVB instruction.

Example:
PNUM
CVB

DS

R2,PNUM

Sign = C or F for Positive numbers, D for negative numbers

Before
(hex bytes)

After
(hex bytes)

R2
C 3 C 4 C 7 C 1
C

PNUM
0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 F

R2
0 0 0 0 3 0 3 9

PNUM
0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 F
3

(Packed Decimal Format)

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 40 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

CVD
Convert to Decimal
RX Type

Op code = 4E

Converts a binary number in the register specified by Operand 1 to a packed decimal number and places it in the
doubleword storage area specified by Operand 2.

label

CVD

R1,D2(X2,B2)
Operand 1
Destination
Register No.

Use
Format
Spec

R = Register #
or Symbolic Name
of Register

Operand 2*
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

* The effective address of Operand 2 should be on a double word boundary.

Machine code Instruction Length = Fullword
OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

4E

4ER1X2B2DDD2
The condition code is not affected by the CVD instruction.

Example:
PNUM
CVD
Before
(hex bytes)

After
(hex bytes)

DS

R2,PNUM
R2
0 0 0 0 3 0 3 9

PNUM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R2
0 0 0 0 3 0 3 9

PNUM
0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 C
(Packed Decimal Format) 3

Sign = C for Positive numbers, D for negative numbers

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 41 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

D
Divide
RX Type

Op code = 5D

Divides a 64 bit integer (dividend), contained in two registers starting with the register (even numbered) specified in
Operand 1., by a 32 bit integer (divisor) contained in fullword of storage. The quotient and the remainder replace the
dividend in the registers. The storage location remains unchanged. R1 must be an even numbered register and the
Operand 2 must be on a fullword boundary. Dividing by 0 will produce a dump.

label

R1,D2(X2,B2)

Use
Format
Spec

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

5D

5DR1X2B2DDD2
The condition code is not affected by the Divide instruction.
Example : (11 / 4 = 2, remainder 3)
R2 = X'00000000'
LABEL1
=
D
Before:
(hex bytes)

Before:
(hex bytes)

DC

R3 = X0000000B
X'00000004'

R2,LABEL1
Dividend
R2
R3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 B
Remainder
Quotient
R2
R3
0 0 0 0 0 0 0 3
0 0 0 0 0 0 0 2

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 42 ]

Divisor
LABEL1
0 0 0 0 0 0 0 4
LABEL1
0 0 0 0 0 0 0 4

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DC
Define Constant
(Assembler Directive)
The DC directive is used to allocate storage, establish values to that storage to be used as initial values or constants, and to
optionally assign a symbolic label to the address of that storage. Use DCs only in the Define Constants area of your
program. You must assign an initial value to the constants.

label

DC

dTlC

where:
label
d

=
=

(Optional) 1 to 8 Alpha-Numeric characters by which you refer to the constant

Duplication (Optional) (default=1) - Unsigned decimal value that expresses number of
times you want this storage to be repeated
Type (Required) - The type of constant that you want the assembler to define (See
Summary of Constants table below)
Length (Optional) - The character L plus a decimal value indicating how many bytes
you want this constant to be. If this value is omitted, the length will be implied by the
specified constant
Constant (Required) - The initial value for this area of storage
Summary of Constants

Type
C
X
B
F
H
D
P
Z
A
Y

Implied
Length
(bytes)
1
1
1
4
2
8
as necc.
as necc.
4
2

Max
Length
(bytes)
256
256
256
4
2
8
as necc.
as necc.
4
2

Boundary
Alignment
BYTE
BYTE
BYTE
WORD
HALFWORD
DOUBLEWORD
BYTE
BYTE
WORD
HALFWORD

Format
Characters
Hexadecimal Digits
Binary Digits
Signed Decimal
Signed Decimal
Signed Decimal
Packed Decimal
Zoned Decimal
Value of Address
Value of Address

Truncation
or
Padding
Right
Left
Left
Left
Left
Right
Left
Left
Left
Left

See examples on next page.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 43 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DC (cont.)
Define Constant
(Assembler Directive)
Examples:

( = space character - EBCDIC X40)

De fi ne Cons ta nt
S our ce S ta tem e nt
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

C1234567
4CG
CL101234567
CL31234567
XABCD
XL4ABCD
XL2ABCDEF
3XL2FOFOF1
B10010111
B10011
F21
F-1
H10
H-1
P123
P1234
PL312.3
PL21234
Z123
ZL312
ZL2123

As se mble d As

If Addr of LABEL1 = 00AE1234

1234567
GGGG
1234567
123
XABCD
X0000ABCD
XCDEF
XF0F1F0F1F0F1
B10010111
B00010011
X00000015
XFFFFFFFF
X000A
XFFFF
X123C
X01234C
X00123C
X234C
XF1F2C3
XF0F1F2
XF2F3
X00AE1238

If location counter = 00AE1234

X00AE1234

DC
DC

A(LABEL1+4)
A(*)

Re ma rk s

Implied length of 7 bytes

Duplication factor of 4
Pad right with spaces
Truncate on right
Implied length of 2 bytes
Pad left with zeros
Truncation on left
Duplication factor of 3, and truncation on left
Implied length of 1 byte
Padding on left to keep length a multiple of 8 bytes
Stores as Binary, Implied length of 4 bytes
Stores in twos compliment, Implied len. of 4 bytes
Stores as Binary, Implied length of 2 bytes
Stores in twos compliment, Implied len. of 2 bytes
Implied length of 2 bytes
Pad zero on left
Pad left with zeros; decimal point ignored
Truncation on left
Implied length, one byte per decimal digit
Pad EBCDIC zeros (F0) on left; dec. point ignored
Truncation on left
Length = 4 bytes (fullword)

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 44 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DR
Divide Registers
RR Type

Op code = 1D

Divides a 64 bit integer (dividend), contained in a register pair starting with the even numbered register specified in
Operand 1., by a 32 bit integer (divisor) contained in the register specified in Operand 2. The quotient and the remainder
replace the dividend in the Operand 1 register pair. The register specified in Operand 2 remains unchanged. R1 must be
an even numbered register. R2 must not be part of the R1 register pair. Dividing by 0 will produce a dump.

label

DR
Use
Format
Spec

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Operand 2
Source
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

1D

1DR1R2
The condition code is not affected by the Divide Register instruction.
Examples : (25 / 4 = 6, remainder 1)
R2 = X'00000000'
DR
Before:
(hex bytes)

After:
(hex bytes)

R3 = X00000019

R4 = X00000004

R2,R4
Dividend
R2
R3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 9
Remainder
Quotient
R2
R3
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 6

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 45 ]

Divisor
R4
0 0 0 0 0 0 0 4
R4
0 0 0 0 0 0 0 4

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DROP
Drop Base Register(s) Directive
This assembler directive cancels previous USINGs on one or more registers. Drop only affects those instructions that
physically follow it. An assembler error will occur if a DROP is specified for a register for which a USING was never in
effect. This directive is generally used to terminate the use a particular base register in preparation for establishing that
same register as a base register for another DSECT. If the operand is left blank, all registers will be dropped.

(No label)

DROP

R1[R2,...] or blank
(operand entries in brackets are optional)

Use
Format
Spec

Operand 1
Base Register
Register No.
R = Register # or
symbolic Reg name

Example:
If FLTREC and PSGDAT are symbolic labels for a DSECTs...
PGM400

PGM500

EQU
USING
GETCC
L

*
FLTREC,R7
D4,L2
R7,CE1CR1

Establishes R7 as base register for FLTREC DSECT

Get 1055 byte block on Level 4 for DSECT data storage
Load Data Level 1 base address in R7

EQU
DROP
USING
GETCC
L

*
R7
PGGDAT,R7
D5,L2
R7,CE1CR1

Cancel previous USING in effect for R7

Establishes R7 as base register for PSGDAT DSECT
Get 1055 byte block on Level 1 for DSECT data storage
Load Data Level 1 base address in R7

.
.
.

This example first establishes R7 as the base register for fields in the DSECT named FLTREC. When the program
reaches PGM500, register R7 is dropped so it can be re-used as a base register for the DSECT named PSGDAT.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 46 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DS
Define Storage
(Assembler Directive)
The DS directive is used to allocate storage without initializing the contents of the reserved bytes, and to optionally assign
a symbolic label to the address of that storage.

label

DS

dTl

where:
label

(Optional) 1 to 8 Alpha-Numeric characters by which you refer to the storage

Duplication (Optional) (default = 1) - Unsigned decimal value that expresses number

of times you want this storage to be repeated.
A value of 0 indicates that no storage will be reserved but the label will be referenced
to the current value of the location counter. If the duplication factor is 0 and the
constant type is D, F, or H, alignment to the indicated boundary occurs.
When the DS is used with a duplication factor of 0 in the programs Define Constant
area, it is usually followed by a number of DC directives whose length values total the
length value of the leading DS directive.

Type (Required) - The type of constant that you want the assembler to define for the
storage area (See Summary of Constants table below)

Length (Optional) - The character L plus a decimal value indicating how many bytes
you want this storage area to be. If this value is omitted, the length will be implied by
the specified constant
Summary of Constants

Type
C
X
B
F
H
D
P
Z
A
Y

Implied
Length
(bytes)
1
1
1
4
2
8
as necc.
as necc.
4
2

Max
Length
(bytes)
256
256
256
4
2
8
as necc.
as necc.
4
2

Boundary
Alignment
BYTE
BYTE
BYTE
WORD
HALFWORD
DOUBLEWORD
BYTE
BYTE
WORD
HALFWORD

Format
Characters
Hexadecimal Digits
Binary Digits
Signed Decimal
Signed Decimal
Signed Decimal
Packed Decimal
Zoned Decimal
Value of Address
Value of Address

See examples on next page.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 47 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DS (cont.)
Define Storage
(Assembler Directive)
Examples:
De fi ne Cons ta nt
Sourc e Sta te me nt
DS
DS
HOLD
B1
B2
DS
DS
DS
DS
DS
DS
DS
DS
DS
DS
DS
DS

CL10
4CL10
DS
DS
DS
XL8
100XL4
B
6B
D
0D
3F
0F
6H
0H
PL3
ZL2

0CL16
CL8
CL8

Rem ar ks

Reserves 10 consecutive bytes

Reserves 40 consecutive bytes
References label HOLD to current location count
and reserves storage for two 8-bytes storage areas
labeled B1 & B2
Reserves 8 consecutive bytes
Reserves 400 consecutive bytes
Reserves 1 byte
Reserves 6 consecutive bytes
Reserves a doubleword for numeric data
Forces doubleword alignment
Reserves 3 consecutive fullwords for numeric data
Forces fullword alignment
Reserves 6 consecutive halfwords for numeric data
Forces halfword alignment
Reserves 3 bytes for a packed decimal number
Reserves 3 bytes for a zoned decimal number

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 48 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

DSECT
Define Dummy Section
(Assembler Directive)
The DSECT directive initiates the definition of dummy section. A dummy section allows you to describe the layout of
data in a storage area without actually reserving any storage. Storage layout is defined using only the Define Storage (DS)
directive. To use the symbols defined in a dummy section, include in the mainline portion of the code a USING statement
that designates the label of the DSECT statement and a register to be used as the base register when referencing the
symbols.

label

DSECT

Example:

BEGIN NAME=PGM4,VER=T3
PRINT NOGEN
***********************************************************************
*
PROGRAM DESCRIPTION AREA
*
*
.
*
*
.
*
***********************************************************************
***********************************************************************
*
FLIGHT RECORD DSECT
*
***********************************************************************
FLTREC
DSECT
FFHDR
DS
CL18
HEADER INFO
ORG
FFHDR.
FFNUM
DS
CL5
FLIGHT NUMBER
FFAIRE
DS
CL3
AIRCRAFT EQUIPMENT
FAVLS
DS
H
AVAILABLE SEATS
FROUT
DS
CL6
CITY ROUTING (FROM/TO)
FNPIT
DS
H
NUMBER OF PSGR ITEMS
*---------------------------------------------------------------------*
PASSENGER INFORMATION FOR EACH PASSENGER ITEM
*
*---------------------------------------------------------------------FPITM
DS
XL140
10 PASSENGER ITEMS
*
(14 BYTES PER ITEM)
ORG
FPITM
*
FPMEALS DS
XL1
REQUESTED MEALS
*
X80 = SALT FREE
*
X40 = VEGITARIAN
*
X20 = CHILDS MEAL
*
X10 = KOSHER
FPCLASS DS
XL1
CLASS OF SERVICE
*
X80 = F
*
X40 = Y
*
X20 = M
*
X10 = (NOT USED)
FPNUM
DS
H
NUMBER IN PARTY
FPNAM
DS
CL9
PASSENGER NAME
FPSPA
DS
XL1
UNUSED BYTE (FUTURE)
.
FPLEN
EQU
*- FMEALS
LENGTH OF ONE ITEM
*
*---------------------------------------------------------------------PGM4
CSECT
***********************************************************************
*
BEGIN MAINLINE PORTION OF PROGRAM*
***********************************************************************
PGM40000 EQU
*
USING FLTREC,R7
.
.
.
.

This example shows the use of the DSECT directive used to define an area of storage called the Flight Record
(FLTREC). The Flight record consists of an 18 character header area and ten 14-byte passenger information
records. The passenger information area of the DSECT defines the typical layout for each of the 10 passenger
records to be stored, one after the other. The USING statement at PGM40000 directs the assembler to use R7 as
the base register whenever referring to any of the symbols in the FLTREC DSECT. Accessing a particular
passenger records data is done by bumping R7 through the records FPLEN at a time until you are at the desired
record, and then using the appropriate symbolic label such as FPNUM in your assembler statement(s).

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 49 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ED
Edit
SS Type

Op code = DE

The Edit instruction uses a pattern to convert a packed-decimal number into a printable field that can blank leading zeros
and include punctuation such as commas and decimal points. The packed-decimal field is edited one byte at a time, left to
right, and the result replaces the pattern. The pattern must be the same size or longer than the source packed-decimal
field. The length attribute of first operand must be the length of the pattern.

label

ED

D1(L,B1),D2(B2)

Operand 1
Operand 2
Destination and Pattern Packed-Decimal Source
Address
Address
Format
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.
Use

Machine code Instruction Length = One and a Half Words

OP CODE
L
B1
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

DE

DELLB1DDD1B2DDD2
Length value is 1 less than source statement length.

The condition code reflects the status of the last or only packed decimal field edited, and is set as follows:
Status of Last or Only Packed-Decimal Field
Cond code
ZERO
or
no Digit Selector or Significance Starter codes
encountered
NON-ZERO
and Significance Indicator is ON (Negative Number)
NON-ZERO
and Significance Indicator is OFF (Positive number)

0
1
2

Pattern Characters:
Name
Fill Character (FC)
Digit Selector (DS)
Significance Starter (SS)
Field Separator (FS)
Message Character (MC)

Hex code
X40
X20
X21
X22
Any EBCDIC character code

Notation

d
[
]
The Character

Pattern Example:
HEX
CHAR

40

20
d

20
d

6B
,

20
d

21
[

20
d

4B
.

20
d

20
d

First character of the pattern is the FILL character (FC),

in this case, the space character

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 50 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ED
Edit
(cont.)
Significance Indicator (SI):
The Significance Indicator indicates the significance of source digits or message characters and is turned off at the start of
the edit process. It is turned on after the edit process either encounters the first non-zero source digit or a significance
starter in the pattern. After the process encounters a plus sign code (XC) in the rightmost 4 bits of a byte, the
Significance Indicator is turned off, otherwise it is left on.
Digit Selector (DS) :
The Digit Selector causes the Edit instruction to process the next source digit. If the source digit is zero and the
Significance Indicator is off, the fill character replaces the Digit Selector in the pattern. If the source digit is non-zero or
the Significance Indicator is on, the source digit replaces the Digit Selector in the pattern.
Significance Starter (DS):
Use the Significance Starter to force leading zeros and message characters. When the Significance Starter is encountered,
it is replaced with the fill character if the Significance Indicator is off, or replaced with the next source digit if the
Significance Indicator is on. After the Significance Starter is encountered in the pattern, the Significance Indicator is
turned on. This will cause subsequent source digits to replace subsequent Digit Selectors in the pattern, and cause
subsequent message characters in the pattern to remain unchanged.
Field Separator (FS):
The Field Separator enables a single Edit instruction to process several packed-decimal fields that are defined in
contiguous storage bytes. The pattern consists of several sub-patterns--one per packed-decimal field--that are separated
by Field Separator codes. The Edit instruction always replaces the Field Separator with the fill character and then turns
the Significance Separator off. The fill character is the leftmost character of the pattern sequence and applies to all subpatterns.
Message Characters (MC):
You can insert characters such as dollar signs, commas, periods, and percent signs anywhere within the pattern to
punctuate or label the output field. The message character is left unchanged if the Significance Indicator is on, and
replaced with the fill character if the Significance Indicator is off.
Example 1: Edit the number X5DF (150310) which is in Register 2...

PATTERN

Before:

HEX
Char

After:

HEX
Char
.

CVD
R2,PNUM
ED
PATTERN,PNUM+5
X402020202020

DC

40


20
d

FC

DS

40


PATTERN
21 20 20
[
d
d
DS

DS

DS

20
d

00

PNUM (after CVD)

00 00 00 01

50

3C

00

00

00

PNUM
00 00

50

3C

DS

PATTERN (Output Field)

40 F1 F5 F0 F3

1
5
0
3

SI Off
SI On
Condition code = 2

00

01

SI Off

Note that the source operand PNUM+5 points to the sixth byte, so that the five digits 0,1,5,0,3 will be processed.
Also note that there are five digit selectors (X20) in the pattern, one for each of the digits to be processed.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 51 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ED
Edit
(cont.)
Example 2: Edit the number X5DF (150310) which is in Register 2 and insert commas where appropriate...

PATTERN

Before:

HEX
Char

After:

HEX
Char
.

CVD
R2,PNUM
ED
PATTERN,PNUM+5
X4020206B202020

DC

40


20
d

PATTERN
20 6B 20
d
,
d

FC

DS

DS

40


PATTERN (Output Field)

40 F1 6B F5 F0

1
,
5
0

MC

20
d

20
d

DS

DS

DS

SI Off
SI On
Condition code = 2

F3
3

00

00

PNUM (after CVD)

00 00 00 01

50

3C

00

00

00

PNUM
00 00

50

3C

01

SI Off

Note that the source operand PNUM+5 points to the sixth byte, so that the five digits 0,1,5,0,3 will be processed.
Also note that in addition to the comma message character (X6B), there are five digit selectors (X20) in the
pattern, one for each of the digits to be processed.
Example 3: Edit the number X3 (310) which is in Register 2 so that the result is 0.03...

PATTERN

Before:

HEX
Char

After:

HEX
Char
.

CVD
R2,PNUM
ED
PATTERN,PNUM+5
X402021204B2020

DC

40


20
d

PATTERN
21 20 4B
[
d
.

20
d

20
d

00

00

PNUM (after CVD)

00 00 00 00

00

3C

FC

SS

MC

40


PATTERN (Output Field)

40 40 F0 4B F0


0
.
0

F3
3

00

00

00

PNUM
00 00

00

3C

SI Off SI On
Condition code = 2

DS

DS

00

SI Off

Note that the source operand PNUM+5 points to the sixth byte, so that the five digits 0, 0, 0, 0, 3 will be
processed. Also note that there are four digit selectors (X20) and a significant starter (X21) in the pattern..
These five characters will each process one digit in PNUM. This type of pattern is used to produce leading zeros
in a number field.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 52 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ED
Edit
(cont.)
Example 4: The following shows the effect of a pattern on different packed decimal numbers. The pattern (PATTERN)
will produce numbers in a fixed place two decimal format and is capable of handling any positive packed decimal number
(PNUM) that resides in a doubleword of storage (up to 15 digits). Note that the significant starter also functions as a digit
selector. There are 14 digit selectors and 1 significant starter in PATTERN, each processing 1 of 15 digits in PNUM.
If

PATTERN = X40 20 6B 20 20 20 6B 20 20 20 6B 20 20 20 6B 20 21 20 4B 20 20 ,

the instruction ED
PATTERN,PNUM would produce the following results
(Note:  = space [blank])
Example 4a.
If PNUM = X00 00 00 00 00 00 00 3C, then...
PATTERN (after EDIT instruction) =
X40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 F0 4B F0 F3, and
PATTERN will print as... 0.03

(17 leading spaces)

Example 4b.
If PNUM = X00 00 00 00 00 02 01 4C, then...
PATTERN (after EDIT instruction) =
X40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 F2 F0 4B F1 F4, and
PATTERN will print as... 20.14

(16 leading spaces)

Example 4c.
If PNUM = X00 00 00 00 01 02 01 4C, then...
PATTERN (after EDIT instruction) =
X40 40 40 40 40 40 40 40 40 40 40 40 40 F1 6B F0 F2 F0 4B F1 F4, and
PATTERN will print as... 1,020.14

(13 leading spaces)

Example 4d.
If PNUM = X00 09 87 65 43 21 01 2C, then...
PATTERN (after EDIT instruction) =
X40 40 40 40 40 F9 6B F8 F7 F6 6B F5 F4 F3 6B F2 F1 F0 4B F1 F2, and
PATTERN will print as... 9,876,543,210.12

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 53 ]

(5 leading spaces)

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

EJECT
Skip to a New Page Directive
EJECT
The EJECT directive instructs the assembler to skip to a new page and print the next line at the top of the new page. The
EJECT directive must be coded beginning in column 10.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 54 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

END
END Source Module Directive
END
The END directive signals the end of a control section or program. END is normally coded as the last statement in your
source code beginning at column 10.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 55 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

EQU
Equate Directive
The Equate directive is used to define a symbol (label). Once defined with an Equate, the symbol is treated as an absolute
value equal to the value of expression. Equated symbols can represent quantities or addresses. Equated symbols do not
use storage and the Equate directive does not generate machine language. In other words, when the assembler
encounters an Equate directive, it is processed but the location counter is not altered. The symbol is assigned a length
attribute which is the length of the symbol itself, except when using * (location counter reference) as the expression. In
this case the length is 1. Any symbols used in the expression operand must have been previously defined.

label
where

EQU
label =
expression =

expression
1-31 character name by which the value of expression will be known
(required) An absolute expression or a relocatable expression

Example 1: (use of a relocatable expression)

001000

001062

001066

MVC
BASR
.
.
.
B

DEST(LSOURCE),SOURCE
R3,PGM10100

PGM10020
GET NEXT LINE.
*
**********************************************
* ROUTINE TO EDIT INPUT LINE
*
**********************************************
PGM10100
EQU
*
LA
R1,LSOURCE
LOAD LOOP COUNT
.
.
.

In this example, the symbol PGM10100 is equated to the value X001066. The * (location counter
reference) is a relocatable expression which represents the address of the next available byte. The location
counter is at X 001065 when the assembler reaches the equate statement and the address of the next
available byte is X001066. It is good practice to use the Equate statement in this manner to label
sections of your code, especially those that will be referenced elsewhere in the code, such as IN branch
instructions.
Example 2: (use of a relocatable expression)
001060
001270
001281

MSG
MSGLEN
TABLE

MVC
.
.
DC
EQU
DC

DEST(MSGLEN),MSG
CTHIS IS A MESSAGE
*-MSG
CC1C2C3C4C5C6

In this example, the symbol MSGLEN is equated to the value X11 (X010281 minus X001270). The *
(location counter reference) is a relocatable expression which represents the address of the next available
byte. The location counter is at X 001280 when the assembler reaches the equate statement and the
address of the next available byte is X001281. It is good practice to use the Equate statement in this
manner to avoid hard coding length values.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 56 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

EQU
Equate Directive
(cont.)
Example 3: (use of an absolute expression)
R5

EQU

In this example, the symbol R5 is equated to the value 5 and R5 now becomes an absolute symbol. This
Equate directive is actually performed in the BEGIN macro that is seen at the beginning of all code
segments. It allows you to use the symbol R5 when specifying Register 5 (represented by the number 5) in
instruction statements.
Example 4: (use of an absolute expression)
LABEL1

EQU

X0F

In this example, the symbol LABEL1 is equated to the value of the self-defining term X0F and LABEL1
now becomes an absolute symbol.

500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 57 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

EX
Execute
RX Type

Op code = 44

The Execute instruction allows you to alter bits 8-15 of another instruction at run time and then execute that instruction.
The rightmost byte of the source operand register is ORd with the second byte of the target instruction and then the target
instruction is executed. The next instruction is the one following the EX instruction unless the target instruction is a
branch instruction1. Typically, you would place the target instruction somewhere near the EX instruction and branch
around it. You can use the EX instruction to dynamically alter the length of the fields involved in SS type instructions
(eg., MVC), alter the immediate data portion (e.g., OI) or mask data portion (e.g., TM) of SI type instructions.

label

EX
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Target Instruction
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

44

44R1X2B2DDD2
The condition code is not affected by the Execute instruction.

Note: if the target instruction is a branch instruction, the four right most bits of the register (R1) must be zeros.
500-ASSEMBLER REFERENCE.DOC (6/7/2010) [ 500 - 58 ]
ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1995

Assembly Language Coding for TPF

Example 1: (using EX with SS type instructions)

0000CA D209 814B 8ID9 0014B 001D9

0000D0 D209 815F 8ID9 0015F 00ID9

31 ***********************************************************************
32 * BEGIN MAINLINE PORTION OF PROGRAM
*
33 ***********************************************************************
.
.
.
89 EXI1010 EQU
*
90 * MOVE LAST NAME AND FIRST NAME TO OUTPUT LINE
91
MVC
OUTPUT1,BLANKS10
BLANK OUT OUTPUT FIELD 1
92
MVC
OUTPUT2,BLANKS10
BLANK OUT OUTPUT FIELD 2

0000D6
0000DA
0000DE
0000E2

4110
4130
4120
4420

814B
81C5
0003
8138

0014B
001C5
00003
00138

94
95
96
97

LA
LA
LA
EX

R1l,OUTPUT1
R3,FNAME
R2,L'FNAME-1
R2,MOVE

ADDRESSABILITY TO OUTPUT AREA 1

ADDRESSABILITY TO FIRST NAME
LENGTH OF FIRST NAME (ADJUSTED)
MOVE FIRST NAME FOR EXACT LENGTH

0000E6
0000EP
0000EE
0000F2

4110
4130
4120
4420

815F
B1CD
0005
B138

0015F
001CD
00005
00138

99
l00
101
102

LA
LA
LA
EX

R1,OUTPUT2
R3,LNAME
R2,L'LNAME-1
R2,MOVE

ADDRESSABILITY
ADDRESSABILITY
LENGTH OF LAST
MOVE LAST NAME

104

XPRNT OUTPUT,L'OUTPUT

PRINT

EOU
*
BACKC

END OF PROGRAM
RETURN CONTROL TO CMS

000CA

0012A
000138 D200 1000 3000 00000 00000

000140
000140
000140
000141
00014B
000155
00015F
000169

FO
4040404040404040
4040404040404040
4040404040404040
4040404040404040
4040404040404040

0001C5
0001C9
0001CD
0001D3
0001D9 4040404040404040

500-ASSEMBLER REFERENCE.DOC (6/7/2010)

122
123
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148

EXI1900

TO OUTPUT AREA 1
TO LAST NAME
NAME (ADJUSTED)
FOR EXACT LENGTH

*
MOVE
MVC
0(0,R1),0(R3)
TARGET OF EXECUTE INSTRUCTION
*
***********************************************************************
* "WORKING STORAGE" DEFINITION BEGINS HERE
*
***********************************************************************
WORKAREA DS
0D
ALIGN ON DOUBLE WORD
*
OUTPUT
DS
0CL133
OUTPUT LINE
OUTCC
DC
CL10
CARRAGE CONTROL, DOUBLE SPACE
DC
CL10
INDENT 10
OUTPUT1 DC
CL10
OUTPUT FIELD1, 10 BYTES
DC
CL10
INDENT 10
OUTPUT2 DC
CL10
OUTPUT FIELD2, 10 BYTES
DC
CL(LOUTPUT-(*-OUTPUT))
REST OF OUTPUT RECORD
*
FNAME
DC
CJANE
HYPH1
DC
C----
LNAME
DC
CCODERS
HYPH2
DC
C------
BLANKS10 DC
CL10

[ 500 - 59 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

EX
Execute
(cont.)
This example uses one MVC instruction (statement 129) to move variable length fields to the output fields for printing.
Note that the MVC instruction is coded with a length of 0 and that the length values placed in Register 2 (statements 96
and 101) for the Execute instruction (statements 97 and 102) are one less than the actual length of the source fields. This
adjustment must be made since field length values in machine code must be one less that actual field length values.

FNAME
A N

LNAME
D E

OUTPUT2
R S

OUTPUT1
J

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[ 500 - 60 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Expressions
Expressions can be used to specify:

1
2
3
4
5

An address
An explicit length
A modifier
A duplication factor
A complete operand

For example:

EQU

X-Y+13-P/Q
1

MVC

TO+LTO-LFROM(LFROM),FROM

DS

(X-Y)XL(P/Q-10)
3

Expressions can be written with a simple term or as an arithmetic combination of terms.

Expressions are said to be either absolute or relocatable.
Absolute expressions are those whose values are independent of the actual starting address of the program. A selfdefining term is absolute. For example the value of the self-defining term is 3 regardless of where the program starts.
Absolute expressions typically represent quantities rather than addresses.
Relocatable expressions depend on the starting address of the program and typically represent an address value. For
example, in the statement...
PRTLINE

DS

CL133

the address of PRTLINE depends on the programs starting address.

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

FINIS
FINIS Macro
FINIS
The FINIS macro creates the work storage required for other commonly used macros. It also generates the register
equates R0 through R15. (See Register Usage). The FINIS is normally coded after the LTORG and before the END
statements at the end of your program beginning in column 10.

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[ 500 - 62 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

IC
Insert Character
RX Type

Op code = 43

Inserts a storage byte into a registers low-order byte. The registers high order byte and the source address data remain
unchanged.

label

IC
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

43

43R1X2B2DDD2
The condition code is not affected by the Insert Character instruction.
Examples:
R2 = X'0EF20010'
LABEL1
= DC
IC

XC1C2C3C4'

R2,LABEL1

Before:
(hex bytes)

R2
0 E F 2 0 0 1 0

LABEL1
C 1 C 2 C 3 C 4

R2
0 E F 2 0 0 C 1

LABEL1
C 1 C 2 C 3 C 4

After:
(hex bytes)

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[ 500 - 63 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ICM
Insert Characters Under Mask
RS Type

Op code = BF

Inserts the contents of the left most 1 to 4 bytes of a storage area into selected bytes of a register. The storage location is
unchanged. The bits of the mask correspond one-to-one with the bytes of the register.

label

ICM
Use
Format
Spec

R1,M,D3(B3)

Operand 1
Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Mask
Binary, Hex, or Decimal
Value
0-15
Binary, Hex, or Decimal
Value
0-15

Operand 3
Storage Area
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
M
B3
D3
0-7

8-11

12-15

16-19

20-31

BF

BFR1MB3DDD3
The condition code is set according to the results of the inserted bytes as follows:
Results of
Inserted Bytes
Only
ZERO
or
Mask = 0
Leftmost bit of
inserted bytes = 1
Not ZERO but
Leftmost bit of
inserted bytes = 0

Example 1:

Cond code
0
1
2

R2 = XC1C2C3C4
LABEL1
DC
XF1F2F3F4
ICM

R2,B'1010',LABEL1
R2 Byte #

MASK

(bits)

0
SELECTED R2 BYTES

R2

Byte #
(HEX)

LABEL1 (HEX)
CONDITION CODE = 1

In this example, the condition code would be set to 1 since the leftmost bit of the inserted bytes (F1 & F2) is 1.
ICM can be used in place of a LH when the storage area is not halfword aligned. For example...
SR
R2,R2
ICM
R2,B0011,LABEL1

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

L
Load
RX Type

Op code = 58

Copies fullword (4 bytes) from storage to a register. The storage location is unchanged.

label

R1,D2(X2,B2)

Use
Format
Spec

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

58

58R1X2B2DDD2
The condition code is not affected by the Load instruction.
Examples:
R2 = X'000F0B1E'
R8 = 010816
Addr 012816
= LABEL1
= DC
or

L
L

R2,32(R0,R8) or R2,32(,R8)
R2,LABEL1

Before:
(hex bytes)

R2
0 0 0 F 0 B 1 E

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

R2
0 0 0 0 0 0 0 C

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

After:
(hex bytes)

X'0000000C'

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[ 500 - 65 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

LA
Load Address
RX Type

Op code = 41

Places the effective address of the Operand 2 into the register specified Operand 1..The load address instruction also
provides a good way to load a register with a constant.

label

LA
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

41

41R1X2B2DDD2
The condition code is not affected by the Load instruction.
Example 1:
R2 = X'00000010'
Addr 012816
=
or

LA
LA

R8 = 010816
LABEL1
= DC

X'0000000C'

R2,32(R0,R8) or R2,32(,R8)
R2,LABEL1

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

R2
0 0 0 0 0 1 2 8

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

After:
(hex bytes)

Example 2: (Loads a Register 2 with a constant)

R2 = X'00000010'
LA
R2,5
Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

Example 3: (Bumps the value in Register 2 by 1)

R2 = X'00000010'
LA
R2,1(R2)
Before:
(hex bytes)

R2
0 0 0 0 0 0 0 5

(Note: The displacment value for operand 2 can be any value from 1 to 4096.)

R2
0 0 0 0 0 0 1 0

500-Assembler Reference.doc 6/7/2010

After:

[ 500 - 66 ]

After:

R2
0 0 0 0 0 0 1 1

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

LH
Load Halfword
RX Type

Op code = 48

Copies halfword (2 storage bytes) to the 2 low order bytes of a register. The high order bit of Operand 2 is propagated in
the 2 high order bytes of the register. The storage location is unchanged.

label

LH
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

48

48R1X2B2DDD2
The condition code is not affected by the Load Halfword instruction.
R2 = X'000F0B1E'
LABEL1
= DC

Example 1:

LH
Before:
(hex bytes)

After:
(hex bytes)

X'0ECD2A98'

R2,LABEL1+2
R2
0 0 0 F 0 B 1 E

LABEL1
0 E C D 2 A 9 8

R2
0 0 0 0 2 A 9 8

LABEL1
0 E C D 2 A 9 8

0010 1010 .....

high order bit of Opr2 is propagated in high order halfword

R2 = X'000E34B8
LABEL1
= DC

Example 2:

LH
Before:
(hex bytes)

After:
(hex bytes)

X'0EA3B490

R2,LABEL1+2
R2
0 0 0 E 3 4 B 8

LABEL1
0 E A 3 B 4 9 0

R2
F F F F B 4 9 0
0

LABEL1
0 E A 3 B 4 9 0

1011 0100 ....

high order bit of Opr2 is propagated in high order halfword

500-Assembler Reference.doc 6/7/2010

[ 500 - 67 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

LM
Load Multiple
RS Type

Op code = 98

Load several consecutively numbered registers from consecutive fullwords of storage. If the R1 value is greater than the
R2 value, the load operation will wrap around after reaching the count of 15 to the count of 0 and continue.

label

LM
Use
Format
Spec

R1,R2,D3(B3)

Operand 1
Beginning Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Ending Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 3
Source Address
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
R2
B3
D3
0-7

8-11

12-15

16-19

20-31

98

98R1R2B3DDD3
The condition code is not affected by the Load Multiple instruction.
Example 1:

DATA

LM
.
.
.
DC
DC
DC

R2,R4,DATA

F10
F-1
F194

In this example, Registers 2,3, and 4 are loaded with the contents of the fullwords at the addresses DATA, DATA
+ 4, and DATA + 8.
Example 2: (wraparound)
LM
.
.
.
DATA
DC
DC
DC
DC

R14,R1,DATA

F10
F-1
F194
F14

In this example, Registers 14, 15, 0, and 1 are loaded with the contents of the fullwords at the addresses DATA,
DATA + 4, DATA + 8, and DATA +12.

500-Assembler Reference.doc 6/7/2010

[ 500 - 68 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

LR
Load Register
RR Type

Op code = 18

Replace the contents of the register specified in operand 1with the contents of the register specified in operand 2.
Operand 2s contents remain unchanged.

label

LR
Use
Format
Spec

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Operand 2
Source
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

18

18R1R2
The condition code is not affected by the Load Register instruction.
Example:
R2 = X'00000010'
LR

R3 = X'00000023'

R2,R3

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

R3
0 0 0 0 0 0 2 3

R2
0 0 0 0 0 0 2 3

R3
0 0 0 0 0 0 2 3

After:
(hex bytes)

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[ 500 - 69 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

LTORG
Literal Origin Directive
The LTORG directive positions the literal pool, which was created since the beginning of the program or since the
last LTORG, at the next doubleword boundary after the occurrence of the LTORG in the program.
The LTORG is usually coded right before the FINIS and END statements in your source code, for example...

R3,=F5
.
.
.
LTORG
FINIS
END

The literal constant that is defined by =F5 is assembled and printed here on the listing

To avoid addressability problems, you should code a LTORG directive at the end of each control section (CSECT).

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[ 500 - 70 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

LTR
Load and Test Register
RR Type

Op code = 12

Load one register from a second register, test the result in the first register and set the condition code accordingly.

label

LTR

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Use
Format
Spec

Operand 2
Source
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

12

12R1R2
The condition code is set according to the results in Operand 1 as follows:
Results
if value in R1 is
Zero
Less than Zero
Greater than Zero

Cond code
0
1
2

Approp. Branch Ext.

Mnemonic
BZ, BNM, BNP
BM, BNZ
BP, BNZ

Example1 :
R2 = X'00C1C2C3'
LTR
BM
LA

R3 = XF0000002

R2,R3
LABEL1
R2,LABEL2

Before:
(hex bytes)

R2
0 0 C 1 C 2 C 3

R3
F 0 0 0 0 0 0 2

R2
F 0 0 0 0 0 0 2

R3
F 0 0 0 0 0 0 2

After:
(hex bytes)

Condition code=1

After execution, R2 contains a negative value which sets the condition code to 1. The branch on minus test in the
BM instruction will be successful and the branch to LABEL1 will be taken.
Example 2: (comparing a register with zero)
R5 = X'00000000'
LTR
BZ
LA

R5,R5
LABEL1
R2,LABEL2

500-Assembler Reference.doc 6/7/2010

This form is the preferred way of comparing the contents of a

register with zero. The LTR is an RR type instruction and is
shorter and faster than the Compare (C) instruction. The
branch to LABEL1 will be taken since R5 contains zero after
execution of the LTR instruction.

[ 500 - 71 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

M
Multiply
RX Type

Op code = 5C

Multiplies a 32 bit integer (multiplicand), contained in the odd numbered register of the pair beginning with the even
numbered register specified in Operand 1, by a 32 bit integer (multiplier) contained in the fullword of storage specified in
Operand 2. The product is a 64 bit integer which is placed in the register pair specified in Operand 1. Any value in the
even numbered register before the multiply operation is ignored and will be overwritten by the product after the multiply.
The storage area is unchanged.

label

M
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

5C

5CR1X2B2DDD2
The condition code is not affected by the Multiply Instruction.
Example : (5 * 2 = 10)
R2 = X'00C1C2C3'
R3 = X00000005
LABEL1
= DC
X'00000002'
M
Before:
(hex bytes)

After:
(hex bytes)

R2,LABEL1
Multiplicand
R2
R3
0 0 C 1 C 2 C 3
0 0 0 0 0 0 0 5
Product
R2
R3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 A

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[ 500 - 72 ]

Multiplier
LABEL1
0 0 0 0 0 0 0 2
LABEL1
0 0 0 0 0 0 0 2

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

MH
Multiply Halfword
RX Type

Op code = 4C

Multiplies a 32 bit integer (multiplicand), contained in the register specified in Operand 1, by a 16 bit integer (multiplier)
contained in the halfword of storage specified in Operand 2. The product is a 32 bit integer which is placed in the register
specified in Operand 1. The storage area remains unchanged.

label

MH

R1,D2(X2,B2)
Operand 1
Destination
Register No.

Use
Format
Spec

R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

4C

4CR1X2B2DDD2
The condition code is not affected by the Multiply Halfword instruction.
Example 1: (16* 2 =32)
R3 = X'00000010'
LABEL1
=
MH

DC

H2

R3,LABEL1
Multiplicand
R3
0 0 0 0 0 0 1 0
Multiplicand 6
R3
0 0 0 0 0 0 2 0

Before:
(hex bytes)

After:
(hex bytes)

Multiplier
LABEL1
0 0 0 2
Multiplier
LABEL1
0 0 0 2

Example 2: (8* 10 = 80)

R3 = X'00000008
MH
Before:
(hex bytes)

After:
(hex bytes)

R3,=H10
Multiplicand
R3
0 0 0 0 0 0 0 8
Multiplicand
R3
0 0 0 0 0 0 5 0

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Multiplier
0 0 0 A
Multiplier
0 0 0 A

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

MR
Multiply Registers
RR Type

Op code = 1C

Multiplies a 32 bit integer (multiplicand), contained in the odd numbered register of the pair beginning with the even
numbered register specified in Operand 1, by a 32 bit integer (multiplier) contained in the register specified in Operand 2.
The product is a 64 bit integer which is placed in the register pair specified in Operand 1. Any value in the even
numbered register before the multiply operation is ignored and will be overwritten by the product after the multiply. The
R2 register remains unchanged. The R2 register must not be part of the R1 register pair.

label

MR
Use
Format
Spec

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Operand 2
Source
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

1C

1CR1R2
The condition code is not affected by the Multiply Register Instruction.
Example : (5 * 2 = 10)
R2 = X'00C1C2C3'
MR
Before:
(hex bytes)

After:
(hex bytes)

R3 = X00000005

R4 = X00000002

R2,R4
Multiplicand
R2
R3
0 0 C 1 C 2 C 3
0 0 0 0 0 0 0 5
Product
R2
R3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 A

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Multiplier
R4
0 0 0 0 0 0 0 2
R4
0 0 0 0 0 0 0 2

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

MVC
Move Characters
SS Type

Op code = D2

Moves (duplicates) characters (one at a time) from the source address to the destination address.

label

MVC

D1(L,B1),D2(B2)

Operand 1
Operand 2
Destination Address
Source Address
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.
Use
Format

Machine code Instruction Length = One and a Half Words

OP CODE
L
B2
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

D2

D2LLB1DDD1B2DDD2
Actual length value is 1 less than source statement length.

The condition code is not affected by the MVC instruction.

Example 1:
R8 = 000A16
Addr 012816
MVC

DC

C'CODED'

256(4,R8),286(R8)

In this example, the characters, CODE, located at base/displacement 128 would be duplicated at the first four
bytes beginning at base/displacement 10A. Since the stated length of the move operation is 4 bytes, only the first
4 bytes of the first operand are moved. The source field remains unchanged.
Example 2:
LABEL1
LABEL2
MVC

=
=

DC
DC

C'1234
CDEAR

LABEL1,LABEL2

(MVC

LABEL1,=CDEAR

would produce the same results)

In this example, the characters, DEAR, located at the address equated to LABEL2 would be duplicated at the
first four bytes beginning at the address equated to LABEL1. Since there is no stated length, the length of the
move operation defaults to the length of the constant located at LABEL1, in this case 4 bytes. The source field
remains unchanged.
Example 3:
LABEL1
LABEL2
or

=
=

DC
DC

C'1234567'
C'HOUSEBOAT'

MVC

LABEL1(5),LABEL2

MVC

LABEL1(L'LABEL2-4),LABEL2

In this example, the characters HOUSE located at LABEL2 would be duplicated at the first five bytes beginning
at LABEL1. The length of the move operation is overridden by a length attribute which follows Operand 1, in
this case 5 bytes which is the length of LABEL2 minus 4. The source field remains unchanged.
Example 4: (Propogation Move) These two lines of code will clear the storage area named LABEL1 to spaces (X40).
MVI
MVC

LABEL1,X40
LABEL1+1(LLABEL1),LABEL1

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

MVI
Move Immediate
SI Type

Op code = 92

Moves (duplicates) the specified byte of data to the destination address.

label

MVI

Use
Format
Spec

D1(B1),I2
Operand 1
Destination Address
Base/Displacement
or label
D = Decimal value
B = Register # or
symbolic Reg name

Operand 2
Source Data
(Immediate)
Literal
Absolute expression
such as:
C.., X.., B.., or a
decimal value.

* Length is fixed at 1 byte.

Machine code Instruction Length = Fullword
I2
B1
D1

OP CODE
0-7

8-15

16-19

20-31

92

92II2B1DDD
The condition code is not affected by the MVI instruction.
Example 1:
R8 = 0000000A16
MVI

256(R8),C?

In this example, the character (one byte) ? would be duplicated at the storage byte whose address is
base/displacement 10A16.
Example 2:

MVI

LABEL1,X0F

In this example, hex 0F would be duplicated at the storage byte address equated to LABEL1.
Example 3:
or

MVI

PRINT,C

MVI

PRINT,X40

In this example, a space character would be duplicated at the storage byte address equated to PRINT.

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

N
AND
Op code = 54

RX Type

Turn one or more bits OFF in a register that are off in another fullword storage area according to the truth table shown
below.

label

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Use
Format
Spec

Operand 2
Mask
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

54

54R1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

Branch On Condition
Mask Value
8
4

Approp. Branch Ext.

Mnemonic
BZ
BNZ

LOGICAL 'AND' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
0
0
0
1
1

R2,LABEL1

Before:
R2
Hexadecimal
Binary Bits

C
1

4
0

LABEL1 (Mask)
Hexadecimal
Binary Bits

F
1

B
1

After:
R2
Hexadecimal
Binary Bits

C
1

0
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

NC
AND Characters
Op code = D4

SS Type

Turn one or more bits OFF in a storage area that are off in another storage area according to the truth table shown below.
The process proceeds left to right, one byte at a time.

label

NC

D1(L,B1),D2(B2)
Operand 1
Destination Address

Use
Format

Operand 2
Source Address
(Mask)
Base/Displacement
or label
D = Decimal value
B = Register # or
symbolic Reg name

Base/ILength/Displ
or label
Spec
D = Decimal value
L* = Decimal value
B = Register # or
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.

Machine code Instruction Length = One and a Half Words

OP CODE
L
B1
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

D4

D4LLB1DDD1B2DDD2
Length value is 1 less than source statement length.
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

NC

Branch On Condition
Mask Value
8
4

Approp. Branch Ext.

Mnemonic
BZ
BNZ

LOGICAL 'AND' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
0
0
0
1
1

LABEL1(1),LABEL2

Before:
LABEL1
Hexadecimal
Binary Bits

C
1

4
0

Immediate Data (Mask)

Hexadecimal
Binary Bits

F
1

B
1

After:
LABEL1
Hexadecimal
Binary Bits

C
1

0
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

NI
AND Immediate
Op code = 94

SI Type

Turn one or more bits OFF in a storage area that are off in the specified immediate data according to the truth table shown
below.

label

NI

D1(B1),I2
Operand 1
Destination
Base/Displacement
or Label
D = Decimal value
B = Register # or
symbolic Reg name

Use
Format
Spec

Operand 2
Mask Value
Immediate
Absolute expression
such as:
C.., X.., B.., or a
decimal value.

* Length is fixed at 1 byte.

Machine code Instruction Length = Fullword
OP CODE
I2
B1
D1
0-7

8-15

16-19

20-31

94

94II2B1DDD1
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

NI

Branch On
Condition
Mask Value
8
4

Appropriate
Branch Ext.
Mnemonic
BZ
BNZ

LOGICAL 'AND' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
0
0
0
1
1

LABEL1,X'7F'

Before:
LABEL1
Hexadecimal
Binary Bits

C
1

4
0

Immediate Data (Mask)

Hexadecimal
Binary Bits

7
0

F
1

After:
LABEL1
Hexadecimal
Binary Bits

4
0

4
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

NR
And Registers
Op code = 14

RR Type

Turn one or more bits OFF in a register that are off in another register according to the truth table shown below.

label

NR

R1,R2

Use
Format
Spec

Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Operand 2
Mask
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

14

14R1R2
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

NR

Branch On
Condition
Mask Value
8
4

Appropriate
Branch Ext.
Mnemonic
BZ
BNZ

LOGICAL 'AND' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
0
0
0
1
1

R2,R3

Before:
R2
Hexadecimal
Binary Bits

C
1

4
0

R3 (Mask)
Hexadecimal
Binary Bits

B
1

F
1

After:
R2
Hexadecimal
Binary Bits

8
1

4
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

O
OR
Op code = 56

RX Type

Turn one or more bits ON in a register that are on in another fullword storage area according to the truth table shown
below.

label

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Use
Format
Spec

Operand 2
Mask
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

56

56R1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Approp. Branch Ext.

Mnemonic
BZ
BNZ

LOGICAL 'OR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
1

Destination Bit
0
0
1
1

Example:

Branch On Condition
Mask Value
8
4

R2,LABEL1

Before:
R2
Hexadecimal
Binary Bits

C
1

4
0

LABEL1 (Mask)
Hexadecimal
Binary Bits

2
0

0
1

After:
R2
Hexadecimal
Binary Bits

E
1

4
1

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

OC
OR Characters
Op code = D6

SS Type

Turn one or more bits ON in a storage area that are on in another storage area according to the truth table shown below.
The process proceeds left to right, one byte at a time.

label

OC

D1(L,B1),D2(B2)
Operand 1
Destination Address

Use
Format

Operand 2
Source Address
(Mask)
Base/Displacement
or label
D = Decimal value
B = Register # or
symbolic Reg name

Base/ILength/Displ
or label
Spec
D = Decimal value
L* = Decimal value
B = Register # or
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.

Machine code Instruction Length = One and a Half Words

OP CODE
L
B1
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

D6

D6LLB1DDD1B2DDD2
Length value is 1 less than source statement length.
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

OC

Branch On Condition
Mask Value
8
4

Approp. Branch Ext.

Mnemonic
BZ
BNZ

LOGICAL 'OR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
1

LABEL1(1),LABEL2

Before:
LABEL1
Hexadecimal
Binary Bits

C
1

4
0

LABEL2 (Mask)
Hexadecimal
Binary Bits

0
0

1
0

After:
LABEL1
Hexadecimal
Binary Bits

C
1

5
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

OI
OR Immediate
Op code = 96

SI Type

Turn one or more bits ON in a storage area that are on in the specified immediate data according to the truth table shown
below.

label

OI

D1(B1),I2
Operand 1
Destination
Base/Displacement
or Label
D = Decimal value
B = Register # or
symbolic Reg name

Use
Format
Spec

Operand 2
Mask Value
Immediate
Absolute expression
such as:
C.., X.., B.., or a
decimal value.

* Length is fixed at 1 byte.

Machine code Instruction Length = Fullword
OP CODE
I2
B1
D1
0-7

8-15

16-19

20-31

96

96II2B1DDD1
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

OI

Branch On
Condition
Mask Value
8
4

Appropriate
Branch Ext.
Mnemonic
BZ
BNZ

LOGICAL 'OR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
1

LABEL1,X'08'

Before:
LABEL1
Hexadecimal
Binary Bits

C
1

4
0

Immediate Data
Hexadecimal
Binary Bits

0
0

8
0

After:
LABEL1
Hexadecimal
Binary Bits

C
1

C
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

OR
OR Registers
Op code = 16

RR Type

Turn one or more bits ON in a register that are on in another register according to the truth table shown below.

label

OR

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Use
Format
Spec

Operand 2
Mask
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

16

16R1R2
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

OR

Branch On
Condition
Mask Value
8
4

Appropriate
Branch Ext.
Mnemonic
BZ
BNZ

LOGICAL 'OR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
1

R2,R3

Before:
R2
Hexadecimal
Binary Bits

C
1

4
0

R3 (Mask)
Hexadecimal
Binary Bits

0
0

2
0

After:
R2
Hexadecimal
Binary Bits

C
1

6
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ORG
Origin Directive
The Origin directive instructs the assembler to change the value of the location counter to the address of LABEL1. If the
operand is left blank, the location counter is reset to the highest value obtained so far in the current control section..
LABEL1 must be defined before the ORG that specifies it and within the current control section of the code. Typically,
you use ORG to redefine areas of storage either in a DSECT or within the Constants Section (DCs) of the program.

label

ORG

Label1 or left blank

Example:
Hex
Loc
Cntr

Line
No.

0000
0000
0012
0000
0005
0008
000A
0010

0012
009E
0012

0013

0014
0016
001F

000
001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030

***********************************************************************
*
FLIGHT RECORD DSECT
*
***********************************************************************
FLTREC
DSECT
FFHDR
DS
CL18
RESERVE HEADER INFO STORAGE AREA
ORG
FFHDR
RESET LOC COUNTER TO HEADER AREA
FFNUM
DS
CL5
FLIGHT NUMBER
FFAIRE
DS
CL3
AIRCRAFT EQUIPMENT
FAVLS
DS
H
AVAILABLE SEATS
FROUT
DS
CL6
CITY ROUTING (FROM/TO)
FNPIT
DS
H
NUMBER OF PSGR ITEMS
*---------------------------------------------------------------------*
PASSENGER INFORMATION FOR EACH PASSENGER ITEM
*
*---------------------------------------------------------------------FPITM
DS
XL140
10 PSGR ITEMS,(14 BYTES PER ITEM)
ORG
FPITM
*
FPMEALS
DS
XL1
REQUESTED MEALS
*
X80 = SALT FREE
*
X40 = VEGITARIAN
*
X20 = CHILDS MEAL
*
X10 = KOSHER
FPCLASS
DS
XL1
CLASS OF SERVICE
*
X80 = F
*
X40 = Y
*
X20 = M
*
X10 = (NOT USED)
FPNUM
DS
H
NUMBER IN PARTY
FPNAM
DS
CL9
PASSENGER NAME
FPSPA
DS
XL1
UNUSED BYTE (FUTURE)
*
FPLEN
EQU
*- FMEALS
LENGTH OF ONE ITEM
*
*----------------------------------------------------------------------

In this example, an 18 byte storage area is reserved for the DSECT header area beginning at location 0000
(FFHDR). Then an ORG is done back to FFHDR which resets the location counter back to 0000. The 18 byte
area is defined or patterned in lines 3 through 7. Next, ten 14 byte storage areas (140 bytes) are reserved for
passenger information beginning at location 0012 (FPITM). Then an ORG is done back to FPITM which resets
the location counter back to 0012. The 14 byte pattern that will be used for each of the 10 passenger information
areas is defined in lines 14 through 26.

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

PACK
Pack
SS Type

Op code = F2

Convert the EBCDIC or Zoned number located at the storage area specified by Operand 2 to pack decimal format and
places it in the storage area specified by Operand 1.

label

PACK D1(L,B1),D2(L2,B2)
Operand 1**
Operand 2***
Destination Address
Source Address
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the operand. Maximum length of the operation is 16 bytes.
Use
Format

The minimum length of the receiving field in bytes is calculated by...

PACKED LENGTH = (ZONED LENGTH 2) + 1
(Disregard any remainder resulting from division portion of formula)
** The data stored at the address specified by Operand 2 must be in zoned or EBCDIC for mat.
Machine code Instruction Length = One and a Half Words
OP CODE L1
L2
B1
D1
B2
D2
0-7

8-11

12-15

16-19

20-31

32-35

36-48

F2

F2L1L2B1DDD1B2DDD2
Length values are 1 less than source statement lengths.

The condition code is not affected by the PACK instruction.

Example 1:
DWD
NOPTYHLD
PACK

DC
DC

D0
C'12345'

or
or

DC
DC

PL80
Z12345

DWD,NOPTYHLD(4)
Explicit length of 4

NOPTYHLD

DWD

(after PACK)

F1 F2 F3 F4 F5
00 00 00 00 00 01 23 4F
Zero fill unused portion
Sign = C or F for Positive numbers, D for negative numbers

This example packs the first four EBCDIC characters stored at NOPTYHLD into the double word DWD.

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

PACK
Pack
(cont.)

Performing Binary Arithmetic on EBCDIC or Zoned Numbers

INPUT
DATA

EBCDIC

PACK
PACKED
DECIMAL

UNPK
PACKED
DECIMAL
ARITHMETIC

CVB
BINARY
INTEGER

PACKED
DECIMAL

OI
w/ X'F0'
Zoned
Decimal

EBCDIC

OUTPUT

CVD
BINARY
ARITHMETIC

BINARY
INTEGER

A, S, M, D
AH, SH, MH

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

PRINT
Print Directive
PRINT

GEN or NOGEN

The PRINT directive instructs the assembler to either print or suppress the printing of macro expansions in the program
listing. Thus the PRINT directive (beginning at column 10) normally appears in the source code right before a macro call.

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

Register Usage
TPF
Equated
Label
R0*
R1*
R2*
R3*
R4*
R5*
R6*
R7*

Old PARS
Equated
Label
RAC
RG1
RGA
RGB
RGC
RGD
RGE
RGF

Register
No.
0
1
2
3
4
5
6
7

Use
Application Program Register
Application Program Register
Application Program Register
Application Program Register
Application Program Register
Application Program Register
Application Program Register
Application Program Register

R8
R9

RAP
REB

8
9

Active Program Base Register

Active ECB Base Register

R10

RLA

10

Application Program Register - Not saved through TPF macros

R11
R12

RLB
RLC

11
12

TPF System Base Register

TPF System Base Register

R13
R14
R15

RLD
RDA
RDB

13
14
15

Application Program Register - Not saved through TPF macros

Application Program Register - Not saved through TPF macros
Application Program Register - Not saved through TPF macros

The equated name shown for each register are defined by the FINIS macro that is normally coded between the
LTORG and END assembler directives.

R0 should not be used as a base register. Referencing R0 as an address pointer is

equivalent to the value of zero.
* These registers are saved across TPF macros

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

S
Subtract
RX Type

Op code = 5B

Subtracts contents of a fullword storage area from the contents of a register. The result in placed in the register. The
storage location is unchanged.

label

R1,D2(X2,B2)

Use
Format
Spec

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

5B

5BR1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results
ZERO
MINUS
PLUS
OVERFLOW

Cond code
0
1
2
3

Examples:
R2 = X'00000010'
Addr 012816
=
or

S
S

R8 = 010816
LABEL1
= DC

R2,32(R0,R8)
R2,LABEL1

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

R2
0 0 0 0 0 0 0 4

Addr 12816
LABEL1
0 0 0 0 0 0 0 C

After:
(hex bytes)

X'0000000C'

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SH
Subtract Halfword
RX Type

Op code = 4B

Subtract the contents of a 2-byte halfword storage area from the contents of a register. The results are placed in the
register. The storage location is unchanged.

label

SH

R1,D2(X2,B2)
Operand 1
Destination
Register No.

Use
Format
Spec

R = Register #
or Symbolic Name
of Register

Operand 2
Source
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

4B

4BR1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results
ZERO
MINUS
PLUS
OVERFLOW

Cond code
0
1
2
3

Example:
R2 = X'00000010'
Addr 012816
=
SH
or
SH
o r SH

R8 = X00000108
LABEL1
= DC H'12'

R2,32(R0,R8) or R2,32(R8) or R2,32(,R8)

R2,LABEL1
R2,=H'12'

Before:
(hex bytes)

R2
0 0 0 0 0 0 1 0

Addr 12816
LABEL1
0 0 0 C

R2
0 0 0 0 0 0 0 4

Addr 012816
LABEL1
0 0 0 C

After:
(hex bytes)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SLA
Shift Left Algebraic
RS Type

Op code = 89

Shifts the contents of the register specified in Operand 1 to the left by the number of bits specified in Operand 2.
The most significant bit (sign) remains unchanged to preserve the sign of the number and only the least
significant 31 bits are shifted. Although the effective address specified in Operand 2 is calculated, the resulting
value is not used as an address but as a count for the number of bit shifts to perform. The value used for this
count is actually the least significant 6 bits of the calculated effective address, and should never be higher then
3110 for a single register shift.

label

SLA

R1,D2(B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Use
Format
Spec

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

89

89R10B2DDD2
Bits 12-15 not used

The condition code is set according to the results in Operand 1 as follows:

Results
ZERO
NEGATIVE
POSITIVE
OVERFLOW*

Cond code
0
1
2
3

*An overflow condition will occur if a bit that differs from the sign bit is shifted out of the register.

Effect of Shift Left Algebraic (SLA)...

REGISTER

Sign Bit

0s
Bits shifted
out are lost

Examples:

SLA

R2,3

Before
(hex bytes)
(Binary)

Before
(hex bytes)
(Binary)

R2
8
1000

0
0000

0
0000

0
0000

0
0
0
1000
0000
0000
Condition code = 3 (Overflow)

1
0001

SIGN

500-Assembler Reference.doc 6/7/2010

2
0010

1
0001

4
0100

A
1010

0
0000

A
1010

5
0101

0
0000

R2

[ 500 - 92 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SLDA
Shift Left Double Algebraic
RS Type

Op code = 8F

Shifts the contents of the even/odd register pair specified in Operand 1 to the left by the number of bits specified
in Operand 2. The register pair are treated is if they made up one 64-bit register. The most significant bit (sign)
of the even register remains unchanged and the remaining 63bits are shifted. Although the effective address
specified in Operand 2 is calculated, the resulting value is not used as an address but as a count for the number of
bit shifts to perform. The value used for this count is actually the least significant 6 bits of the calculated
effective address, and should never be higher then 6310 for a double register shift.

label

SLDA
Use
Format
Spec

R1,D2(B2)

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

8F

8FR10B2DDD2
Bits 12-15 not used

The condition code is set according to the results in Operand 1 as follows:

Results
ZERO
NEGATIVE
POSITIVE
OVERFLOW*

Cond code
0
1
2
3

*An overflow condition will occur if a bit that differs from the sign bit is shifted out of the even register.

Effect of Shift Left Double Algebraic (SLDA)...

ODD REGISTER

EVEN REGISTER

0s

S
Bits shifted
out are lost

Examples:

SLDA

R2,3

Before

R2

R3

(hex bytes)
(Binary)

9
2
0
0
0
4
7
F
1001 0010 0000 0000 0000 0100 0111 1111

8
0
0
0
2
1
4
A
1000 0000 0000 0000 0010 0001 0100 1010

After
(hex bytes)
(Binary)

SIGN

R2

R3

9
0
0
0
2
3
F
C
1001 0000 0000 0000 0010 0011 1111 1100
Condition code = 3 (Overflow)

0
0
0
1
0
A
5
0
0000 0000 0000 0001 0000 1010 0101 0000

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

SLDL
Shift Left Double Logical
RS Type

Op code = 8D

Shifts the contents of the even/odd register pair specified in Operand 1 to the left by the number of bits specified
in Operand 2. The register pair are treated is if they made up one 64-bit register and all 64 bits are shifted.
Although the effective address specified in Operand 2 is calculated, the resulting value is not used as an address
but as a count for the number of bit shifts to perform. The value used for this count is actually the least
significant 6 bits of the calculated effective address, and should never be higher then 6310 for a double register
shift.

label

SLDL
Use
Format
Spec

R1,D2(B2)

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

8D

8DR10B2DDD2
Bits 12-15 not used

The condition code is not affected by the SLDL instruction.

Effect of Shift Left Double Logical (SLDL)...
ODD REGISTER

EVEN REGISTER

Bits shifted
out are lost

0s

Examples:
R2 = X'9200047F
SLDL
Before
(hex bytes)
(Binary)

After
(hex bytes)
(Binary)

R3 = X8000214A

R2,3

R2
9
2
0
0
0
4
7
F
1001 0010 0000 0000 0000 0100 0111 1111

R3
8
0
0
0
2
1
4
A
1000 0000 0000 0000 0010 0001 0100 1010

R2
9
0
0
0
2
3
F
C
1001 0000 0000 0000 0010 0011 1111 1100

R3
0
0
0
1
0
A
5
0
0000 0000 0000 0001 0000 1010 0101 0000

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SLL
Shift Left Logical
RS Type

Op code = 89

Shifts the contents of the register specified in Operand 1 to the left by the number of bits specified in Operand 2.
All 32 bits are shifted. Although the effective address specified in Operand 2 is calculated, the resulting value is
not used as an address but as a count for the number of bit shifts to perform. The value used for this count is
actually the least significant 6 bits of the calculated effective address, and should never be higher then 3110 for a
single register shift.

label

SLL
Use
Format
Spec

R1,D2(B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

89

89R10B2DDD2
Bits 12-15 not used

The condition code is not affected by the SLL instruction.

Effect of Shift Left Logical (SLL)...
REGISTER
Bits shifted
out are lost

0s

Examples:
R2 = X'8000214A'
SLL

R2,3

Before
(hex bytes)
(Binary)

R2
8
1000

0
0000

0
0000

0
0000

0
0000

0
0000

0
0000

1
0001

Before
(hex bytes)
(Binary)

2
0010

1
0001

4
0100

A
1010

0
0000

A
1010

5
0101

0
0000

R2

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SPACE
Insert Blank Lines Directive
SPACE [n]
(n is defaulted to 1 if omitted)

The SPACE directive instructs the assembler to insert n blank lines into the program listing. The SPACE directive must
be coded beginning in column 10.

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SR
Subtract Registers
RR Type

Op
code = 1B

Subtract the contents of a the register specified in Operand 2 from the contents of the register specified in Operand 1. The
result in placed in the register specified in operand 1. The register specified in operand 2 is unchanged.

label

SR
Use
Format
Spec

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Operand 2
Source
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

1B

1BR1R2
The condition code is set according to the results in Operand 1 as follows:
Results
ZERO
MINUS
PLUS
OVERFLOW

Cond code
0
1
2
3

Example 1:
R2 = X'00000033'
SR

R8 = X'00000023'

R2,R8

Before:
(hex bytes)

R2
0 0 0 0 0 0 3 3

R8
0 0 0 0 0 0 2 3

R2
0 0 0 0 0 0 1 0

R8
0 0 0 0 0 0 2 3

After:
(hex bytes)

Example 1: (Clearing a Register)

This line of code will clear Register 2
SR

R2,R2

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SRA
Shift Right Algebraic
RS Type

Op code = 8A

Shifts the contents of the register specified in Operand 1 to the right by the number of bits specified in Operand
2. Only the least significant 31 bits are shifted and copies of the most significant bit (sign) fills in the vacancies
that are introduced on the left. Although the effective address specified in Operand 2 is calculated, the resulting
value is not used as an address but as a count for the number of bit shifts to perform. The value used for this
count is actually the least significant 6 bits of the calculated effective address, and should never be higher then
3110 for a single register shift.

label

SRA
Use
Format
Spec

R1,D2(B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

89

8AR10B2DDD2
Bits 12-15 not used

The condition code is set according to the results in Operand 1 as follows:

Results
ZERO
NEGATIVE
POSITIVE
OVERFLOW*

Cond code
0
1
2
N/A

*An overflow condition is impossible with the SRA instruction.

Effect of Shift Right Algebraic (SRA)...

REGISTER

Sign Bit

Sign fills in vacancies

Examples:

SRA

Bits shifted
out are lost

R2,3

Before
(hex bytes)
(Binary)

Before
(hex bytes)
(Binary)

R2
8
1000

0
0000

0
0000

0
0000

SIGN

1
0001

4
0100

A
1010

0
0000

4
0100

2
0010

9
1001

R2

F
0
0
1111
0000
0000
Condition code = 1 (Negative)

500-Assembler Reference.doc 6/7/2010

2
0010

0
0000

[ 500 - 98 ]

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SRL
Shift Right Logical
RS Type

Op code = 88

Shifts the contents of the register specified in Operand 1 to the right by the number of bits specified in Operand
2. All 32 bits are shifted. Although the effective address specified in Operand 2 is calculated, the resulting value
is not used as an address but as a count for the number of bit shifts to perform. The value used for this count is
actually the least significant 6 bits of the calculated effective address, and should never be higher then 3110 for a
single register shift.

label

SRL
Use
Format
Spec

R1,D2(B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

88

88R10B2DDD2
Bits 12-15 not used

The condition code is not affected by the SRL instruction.

Effect of Shift Right Logical (SRL)...
REGISTER
Bits shifted
out are lost

0s

Examples:
R2 = X'8000214A'
SRL

R2,3

Before
(hex bytes)
(Binary)

R2
8
1000

0
0000

0
0000

0
0000

1
0001

0
0000

0
0000

0
0000

Before
(hex bytes)
(Binary)

2
0010

1
0001

4
0100

A
1010

0
0000

4
0100

2
0010

9
1001

R2

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SRDA
Shift Right Double Algebraic
RS Type

Op code = 8E

Shifts the contents of the even/odd register pair specified in Operand 1 to the right by the number of bits
specified in Operand 2. The register pair are treated is if they made up one 64-bit register. . The most significant
bit (sign) of the even register remains unchanged and the remaining 63bits are shifted. Although the effective
address specified in Operand 2 is calculated, the resulting value is not used as an address but as a count for the
number of bit shifts to perform. The value used for this count is actually the least significant 6 bits of the
calculated effective address, and should never be higher then 6310 for a double register shift.

label

SRDA R1,D2(B2)
Use
Format
Spec

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

8E

8ER10B2DDD2
Bits 12-15 not used

The condition code is set according to the results in Operand 1 as follows:

Results
ZERO
NEGATIVE
POSITIVE
OVERFLOW*

Cond code
0
1
2
N/A

*An overflow condition is impossible with the SRDA instruction.

Effect of Shift Right Double Algebraic (SRDA)...

EVEN REGISTER

ODD REGISTER

Bits shifted
out are lost

S
Sign fills in vacancies

Examples:
Before

SRDA

R2,3

(hex bytes)
(Binary)

R2
9
0
0
0
2
3
F
C
1001 0000 0000 0000 0010 0011 1111 1100

R3
0
0
0
1
0
A
5
0
0000 0000 0000 0001 0000 1010 0101 0000

After

R2

R3

(hex bytes)
(Binary)

F
2
0
0
0
4
7
F
1111 0010 0000 0000 0000 0100 0111 1111
Condition code = 1 (Negative)

8
0
0
0
2
1
4
A
1000 0000 0000 0000 0010 0001 0100 1010

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

SRDL
Shift Right Double Logical
RS Type

Op code = 8C

Shifts the contents of the even/odd register pair specified in Operand 1 to the right by the number of bits
specified in Operand 2. The register pair are treated is if they made up one 64-bit register and all 64 bits are
shifted. Although the effective address specified in Operand 2 is calculated, the resulting value is not used as an
address but as a count for the number of bit shifts to perform. The value used for this count is actually the least
significant 6 bits of the calculated effective address, and should never be higher then 6310 for a double register
shift.

label

SRDL
Use
Format
Spec

R1,D2(B2)

Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
No. of Bit Shifts
Base/Index/Displac
or label
or literal
D = Decimal value
or symbolic Reg
name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
0
B2
D2
0-7

8-11

12-15

16-19

20-31

8C

8CR10B2DDD2
Bits 12-15 not used

The condition code is not affected by the SRDL instruction.

Effect of Shift Right Double Logical (SRDL)...
EVEN REGISTER

ODD REGISTER

0s

Bits shifted
out are lost

Examples:
R2 = X'900023FC
SRDL
Before
(hex bytes)
(Binary)

After
(hex bytes)
(Binary)

R3 = X00010A50'

R2,3

R2
9
0
0
0
2
3
F
C
1001 0000 0000 0000 0010 0011 1111 1100

R3
0
0
0
1
0
A
5
0
0000 0000 0000 0001 0000 1010 0101 0000

R2
1
2
0
0
0
4
7
F
0001 0010 0000 0000 0000 0100 0111 1111

R3
8
0
0
0
2
1
4
A
1000 0000 0000 0000 0010 0001 0100 1010

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

ST
Store
RX Type

Op code = 50

Copies fullword (4 bytes) from a register to storage. The contents of the register are unchanged.

label

ST
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Source
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Destination
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

50

50R1X2B2DDD2
The condition code is not affected by the Store instruction.
Example:
R2 = X'000F0B1E
LABEL1
=
ST

DC

X'0000000C'

R2,LABEL1

Before:
(hex bytes)

R2
0 0 0 F 0 B 1 E

LABEL1
0 0 0 0 0 0 0 C

R2
0 0 0 F 0 B 1 E

LABEL1
0 0 0 F 0 B 1 E

After:
(hex bytes)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

STC
Store Character
RX Type

Op code = 42

Copys a registers low-order byte to a storage byte. The registers high order byte remains unchanged.

label

STC
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Source
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Destination
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

42

42R1X2B2DDD2
The condition code is not affected by the Store Character instruction.
Examples:
R2 = X'0EF20010'
LABEL1
= DC
STC

XC1C2C3C4'

R2,LABEL1

Before:
(hex bytes)

R2
0 E F 2 0 0 1 0

LABEL1
C 1 C 2 C 3 C 4

R2
0 E F 2 0 0 1 0

LABEL1
1 0 C 2 C 3 C 4

After:
(hex bytes)

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

STCM
Store Characters Under Mask
RS Type

Op code = BE

Stores the contents of selected bytes of a register into the left most 1 to 4 bytes of a storage area. The bits of the mask
correspond one-to-one with the bytes of the register.

label

STCM
Use
Format
Spec

R1,M,D3(B3)

Operand 1
Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Mask
Binary, Hex, or Decimal
Value
0-15
Binary, Hex, or Decimal
Value
0-15

Operand 3
Storage Area
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
M
B3
D3
0-7

8-11

12-15

16-19

20-31

BF

BFR1MB3DDD3
The condition code is not affected by the STCM instruction.
Example 1:

R2 = XC1C2C3C4
LABEL1
DC
XF1F2F3F4
STCM R2,B'1010',LABEL1
R2 Byte #

MASK

(bits)

0
SELECTED R2 BYTES

R2

Byte #
(HEX)

LABEL1

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

STH
Store Halfword
RX Type

Op code = 40

Copies a registers 2 low order bytes to a halfword storage area. The contents of the register remain unchanged.

label

STH
Use
Format
Spec

R1,D2(X2,B2)
Operand 1
Source
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Destination
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

40

40R1X2B2DDD2
The condition code is not affected by the Store Halfword instruction.
R2 = X'000F0B1E'
LABEL1
= DC

Example:

STH
Before:
(hex bytes)

After:
(hex bytes)

X'0ECD2A98'

R2,LABEL1
R2
0 0 0 F 0 B 1 E

LABEL1
0 E C D 2 A 9 8

R2
0 0 0 F 0 B 1 E
2

LABEL1
0 B 1 E 2 A 9 8

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

STM
Store Multiple
RS Type

Op code = 90

Copies the contents of consecutively numbered registers to consecutive fullwords of storage. If the R1 value is greater
than the R2 value, the store operation will wrap around after reaching the count of 15 to the count of 0 and continue.

label

STM
Use
Format
Spec

R1,R2,D3(B3)

Operand 1
Beginning Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 2
Ending Register
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Operand 3
Destination Address
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
R2
B3
D3
0-7

8-11

12-15

16-19

20-31

90

90R1R2B3DDD3
The condition code is not affected by the Store Multiple instruction.
Example 1:

STM
.
.
.
DC
DC
DC

R2,R4,DATA

F10
F-1
F194

In this example the contents of Registers 2, 3, and 4 are stored off the fullword addresses of DATA, DATA + 4,
and DATA + 8.
Example 2: (wraparound)
STM
.
.
.
DC
DC
DC
DC

R14,R1,DATA

F10
F-1
F194
F14

In this example, the contents of Registers 14, 15, 0, and 1 are stored at the fullword addresses of DATA, DATA
+ 4, DATA + 8 and DATA +12.

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

TM
Test Under Mask
Op code = 91

SI Type
Test one or more selected bits in a byte of storage for a ONE condition.

label

TM

D1(B1),I2
Operand 1
Storage Area

Use
Format

Base/Displacement
or Label
D = Decimal value
B = Register # or
symbolic Reg name

Spec

Operand 2
Mask
(Immediate)
Literal
Absolute expression
such as:
C.., X.., B.., or a
decimal value.

* Length is fixed at 1 byte.

Machine code Instruction Length = Fullword
OP CODE
I2
B1
D1
0-7

8-15

16-19

20-31

91

91II2B1DDD1
The condition code is set according to the results in Operand 1 as follows:
Results
of
Tested Bits
Ones [ All 1s ]
Mixed [ (1s) and (0s) ]
Zeros [ All 0s ]
Not Ones [ Not all 1s ]
Not Mixed [ (All 0s) or (All 1s) ]
Not Zeros [ (All 1s) or (All 1s and 0s)
]

Example:

TM

Cond code

3
1
0
1 or 0
0 or 3
1 or 3

Branch On
Condition
Mask Value
1
4
8
14 (X,E,)
11 (XB)
7

Single Bit
Test
1
N/A
0
0
0 or 1
1

Multi-Bit
Test
(e.g., 2 bits)
11
01 or 10
00
00 or 01 or 10
00 or 11
10 or 01 or 11

Approp. Branch Ext.

Mnemonic
BO (Branch Ones)
BM (Branch Mixed)
BZ (Branch Zeros)
BNO (Branch Not Ones)
BNM (Branch Not Mixed)
BNZ (Branch Not Zeros)

LABEL1,X05

Test:
LABEL1
Hexadecimal
Binary Bits

C
1

5
0

Test these bits for ONEs

Immediate Data (Mask)
Hexadecimal
Binary Bits

0
0

5
0

Results:
Tested Bits Were

ONE

ONE

CONDTION CODE = 3 (Ones)

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ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

TR
Translate
Op code = DC

SS Type

Replaces 8-bit quantities with other 8-bit quantities that are determined according to a translation table of your design.

label

TR

D1(L,B1),D2(B2)

Operand 1
Operand 2
Destination Address
Table Address
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand. Maximum length of the operation is 16 bytes.
Use
Format

Machine code Instruction Length = One and a Half Words

OP CODE
L
B2
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

DC

DCLLB1DDD1B2DDD2
Length value is 1 less than source statement length.

The condition code is not affected by the TR instruction.

Example:

ARG
TABLE

DC
DC

TR
ARG

(HEX

TABLE

ARG

ARG(7),TABLE
BYTES)

(HEX

(HEX

X010003040105060404
XC1C2C3C440D6E8C8'

01

C1

BYT ES)

BYTES)

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00

C2

03

C2

C1

04

C3

C4

[ 500 - 108 ]

01

C4

40

05

40

C2

06

D6

D6

04

E8

E8

04

C8

04

04

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

TRT
Translate and Test
Op code = DD

SS Type

Scans up to a 256 consecutive storage byte argument for a particular byte value. Translation proceeds from left to right in
the argument and stops when the first non-zero byte value is encountered in the translation table. The address of the
translated non-zero byte in the argument is stored in Register 1 and the corresponding byte found the translation table is
stored in the low-order byte of Register 2. The three high order bytes of Register 2 remain unchanged.

label

TRT

D1(L,B1),D2(B2)

Operand 1
Operand 2
Argument Address
Table Address
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand. Maximum length of the operation is 16 bytes.
Use
Format

Machine code Instruction Length = One and a Half Words

OP CODE
L
B2
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

DD

DDLLB1DDD1B2DDD2
Length value is 1 less than source statement length.

The condition code is set as follows:

Condition after Execution
All argument bytes considered and all table bytes referenced are zero
Non-zero table byte found and argument byte is not the last (rightmost) one
Non-zero table byte found and argument byte is the last (rightmost) one

Condition code
0*
1
2

For Condition code of 0, Registers 1 and 2 remained unchanged

Example:
Register 1 = X00000000 (before execution)
Register 2 = X00000000 (before execution)
Addr 00010400
ARG
DC X030006040105060404
TABLE
DC X00000000FF000000000000'
TRT
Addr 00010400
ARG (HEX

TABLE

(HEX

ARG(7),TABLE
03

BYTES)

BYT ES)
Table +

00

06

04

01

05

06

04

04

00

00

00

00

FF

00

00

00

00

Register 1 = X00010403 (after execution)

00
9

Register 2 = X000000FF (after execution)

This example shows how to scans the first 7 bytes of ARG and look for the hex value X04. It is scanning for
X04 because the byte at address TABLE + 4 is a non-zero value. When the scan encounters the fourth byte in
ARG, ( address 0001040316 ), the translated value for X04 ( TABLE + 04 ) is XFF and the operation stops
since it is a non-zero value. The address of the X04 in ARG is placed in Register 1 and the value found in the
translation table (XFF) is place in the low order byte of Register 2. The 3 high order bytes of Register 2 are
unchanged.

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

UNPK
Unpack
SS Type

Op code = F3

Converts the packed decimal number located at the doubleword specified by Operand 2 to zoned format and places it in
the storage area specified by Operand 1. If the destination storage area is longer than needed the instruction will pad left
with XF0s.

label

UNPK D1(L,B1),D2(L2,B2)
Operand 1**
Operand 2***
Destination Address
Source Address
Base/ILength/Displa
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand. Maximum length of the operation is 16 bytes.
Use
Format

The minimum length of the receiving field in bytes is calculated by...

CHARACTER LENGTH = (PACKED LENGTH x 2)

** The data stored by the instruction at the address specified by Operand 1will be in zoned EBCDIC for mat.
*** The effective address of Operand 2 should be on a double word boundary.

Machine code Instruction Length = One and a Half Words

OP CODE L1
L2
B1
D1
B2
D2
0-7

8-11

12-15

16-19

20-31

32-35

36-48

F3

F32L1L2B1DDD1B2DDD2
Length values are 1 less than source statement lengths.

The condition code is not affected by the UNPK instruction.

Example 1:
DWD
NOPTYHLD

DWD

DC
DC

X00 00 00 00 00 12 34 5C
CL70
or
DC ZL70

UNPK

NOPTYHLD,DWD

00 00 00 00 00 12 34 5C

NOPTYHLD

F0 F0 F1 F2 F3 F4 C5

Pad left with XF0s

Sign = C for Positive numbers, D for negative numbers

(See NOTE below)

This example unpacks the pack decimal number stored at DWD as a zoned number into the five bytes at
NOPTYHLD.
NOTE: To convert the zoned number at NOPTYHLD to EBCDIC, the sign (C or D) must be changed to F. This is done by ORing
the sign and its digit with the hex value F0 using the Or Immediate instruction as follows...

OI

NOPTYHOLD+6,XF0

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

USING
Declare Base Register Directive
Causes the assembler to assume that the specified register is a base register and that it contains the address of the symbolic
label specified in the first operand. At the time of assembly, R1 does not contain this address and the USING directive
does not load the base register; you must do that with a separate instruction such as a Load (L). This directive is typically
used to establish a base register for referencing symbolically named fields in a DSECT.

(No label)

USING
Use
Format
Spec

LABEL1,R1

Operand 1
Storage Address
Symbolic Label
Base address in
symbolic form

Operand 2
Base Register
Register No.
R = Register # or
symbolic Reg name

The instruction tells the assembler to use register R1.as the base register and to assume that the register will contain the
address of LABEL1 which is usually the name of a DSECT. The USING instruction does not generate machine language
instructions; it only provides information to the assembler. If R1 is already being used as a base register for another
DSECT due to a previous USING directive, the previous USING is canceled and R1 will be the base register for the newly
specified DSECT. To re-establish that register as a base for the first DSECT, a new USING directive must be used.
Example:
If FLTREC is the symbolic label for a DSECT...
PGM400

EQU
USING
GETCC
L

*
FLTREC,R7
D1,L2
R7,CE1CR1

Establishes R7 as base register for FLTREC DSECT

Get 1055 byte block on Level 1 for DSECT data storage
Load Data Level 1 base address in R7

This example establishes R7 as the base register to be used when referencing symbolic labels for fields in the
DSECT named FLTREC. The DSECTs data will be stored in the Level 1 data block whose address is stored at the
field labeled CE1CR1*. This address is loaded into R7. From this point on (or until another USING is coded for
FLTREC), the base displacement calculation for any of the fields in FLTREC will use the contents of R7 as a base
address.
* CE1CR1 is actually a symbolic label for the address of a fullword field in the ECB DSECT named EBOEB. The
contents of the fullword stored at CE1CR1 is the storage address of the data block obtained on level 1 when the
GETCC macro was executed.

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

X
Exclusive OR
Op code = 57

RX Type

Toggle bits in a register based on bits in a fullword storage area according to the truth table shown below.

label

R1,D2(X2,B2)
Operand 1
Destination
Register No.
or Symbolic Name of
Register
R = Register #
or Symbolic Name
of Register

Use
Format
Spec

Operand 2
Mask
Base/Index/Displac
or label
or literal
D = Decimal value
X = Register # or
symbolic Reg name
B = Register # or
symbolic Reg name

Machine code Instruction Length = Fullword

OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

57

57R1X2B2DDD2
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

Branch On Condition
Mask Value
8
4

Approp. Branch Ext.

Mnemonic
BZ
BNZ

LOGICAL 'XOR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
0

R2,LABEL1

Before:
R2
Hexadecimal
Binary Bits

C
1

4
0

LABEL1 (Mask)
Hexadecimal
Binary Bits

4
0

0
0

After:
R2
Hexadecimal
Binary Bits

8
1

4
0

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

XC
Exclusive OR Characters
Op code = D7

SS Type

Toggle bits in a storage area based on bits in another storage area according to the truth table shown below. . The process
proceeds left to right, one byte at a time.

label

XC

D1(L,B1),D2(B2)

Operand 1
Operand 2
Destination
Mask
Base/ILength/Displ
Base/Displacement
or label
or label
Spec
D = Decimal value
D = Decimal value
L* = Decimal value
B = Register # or
B = Register # or
symbolic Reg name
symbolic Reg name
* Length may also be specified by a length attribute (e.g. LABEL1(L'LABEL2)). If length is not specified, the length of the
operation defaults to the length of the first operand.
Use
Format

Machine code Instruction Length = One and a Half Words

OP CODE
L
B1
D1
B2
D2
0-7

8-15

16-19

20-31

32-35

36-48

D7

D7LLB1DDD1B2DDD2
Length value is 1 less than source statement length.
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example 1:

XC

Branch On Condition
Mask Value
8
4

Approp. Branch Ext.

Mnemonic
BZ
BNZ

LOGICAL 'XOR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
0

LABEL1(2),LABEL2

Before:
LABEL1
Hexadecimal
Binary Bits

C
1

4
0

Immediate Data (Mask)

Hexadecimal
Binary Bits

2
0

0
1

After:
LABEL1
Hexadecimal
Binary Bits

E
1

4
1

CONDTION CODE = 1 (Non-Zero Result)

Example 2: (Clearing a storage area to zeros)

This line of code will clear the storage area named LABEL1 to zeros.

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XC

LABEL1,LABEL1

ALC Reference for TPF Applications Programmers

Copyright Galileo International Partnership 1997

Assembly Language Coding for TPF

XI
Exclusive OR Immediate
Op code = 97

SI Type

Toggle bits in a storage area based on bits in the specified immediate data according to the truth table shown below.

label

XI

D1(B1),I2
Operand 1
Destination
Base/Displacement
or Label
D = Decimal value
B = Register # or
symbolic Reg name

Use
Format
Spec

Operand 2
Mask Value
Immediate
Absolute expression
such as:
C.., X.., B.., or a
decimal value.

* Length is fixed at 1 byte.

Machine code Instruction Length = Fullword
OP CODE R1
X2
B2
D2
0-7

8-11

12-15

16-19

20-31

97

97II2B1DDD1
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

XI

Branch On
Condition
Mask Value
8
4

Appropriate
Branch Ext.
Mnemonic
BZ
BNZ

LOGICAL 'XOR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
0

LABEL1,X'02'

Before:
LABEL1
Hexadecimal
Binary Bits

A
1

4
1

Immediate Data (Mask)

Hexadecimal
Binary Bits

0
0

2
0

After:
LABEL1
Hexadecimal
Binary Bits

A
1

6
1

CONDTION CODE = 1 (Non-Zero Result)

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ALC Reference for TPF Applications Programmers

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Assembly Language Coding for TPF

XR
Exclusive OR Registers
Op code = 17

RR Type

Turn one or more bits ON in a register that are on in another register according to the truth table shown below.

label

OR

R1,R2
Operand 1
Destination
Register No.
R = Register # or
symbolic Reg name

Use
Format
Spec

Operand 2
Mask
Register No.
R = Register # or
symbolic Reg name

Machine code Instruction

Length = Halfword
OP CODE R1
R2
0-7

8-11

12-15

17

17R1R2
The condition code is set according to the results in Operand 1 as follows:
Results

Cond code

Zero
Non-Zero

0
1

Destination Bit
0
0
1
1

Example:

XR

Branch On
Condition
Mask Value
8
4

Appropriate
Branch Ext.
Mnemonic
BZ
BNZ

LOGICAL 'XOR' TRUTH TABLE

Mask Bit
Resulting Destin. Bit
0
0
1
1
0
1
1
0

R2,R3

Before:
R2
Hexadecimal
Binary Bits

C
1

4
0

R3 (Mask)
Hexadecimal
Binary Bits

0
0

8
0

After:
R2
Hexadecimal
Binary Bits

C
1

C
0

CONDTION CODE = 1 (Non-Zero Result)

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