PIC12F508/509

Memory Programming Specification

This document includes the
programming specifications for the
following devices:

1.2

The Program/Verify mode for the PIC12F508/509

allows programming of user program memory, user ID
locations, backup OSCCAL location and the Configuration Word.

PIC12F508
PIC12F509

Pin Diagrams

PROGRAMMING THE
PIC12F508/509

PDIP, SOIC, MSOP

The PIC12F508/509 is programmed using a serial

method. The Serial mode will allow the PIC12F508/509
to be programmed while in the users system. This
allows for increased design flexibility. This
programming specification applies to PIC12F508/509
devices in all packages.

1.1

VDD

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

PIC12F508/509

1.0

Program/Verify Mode

VSS

GP0/ICSPDAT

GP1/ICSPCLK

GP2/T0CKI

Hardware Requirements

The PIC12F508/509 requires one power supply for

VDD (5.0V) and one for VPP (12V).

TABLE 1-1:
Pin Name

PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12F508/509

During Programming
Function

Pin Type

Pin Description

GP1

ICSPCLK

GP0

ICSPDAT

I/O

Data input/output Schmitt Trigger input

Programming Power

Clock input Schmitt Trigger input

Program/Verify mode

P(1)

VDD

VDD

Power Supply

VSS

VSS

Ground

MCLR/VPP

Legend: I = Input, O = Output, P = Power

Note 1: In the PIC12F508/509, the programming high voltage is internally generated. To activate the Program/
Verify mode, high voltage of IIHH current capability (see Table 6-1) needs to be applied to the MCLR input.

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 1

PIC12F508/509
MEMORY MAPPING

2.1

User Program Memory Map

FIGURE 2-1:

In the configuration memory space, 0x200-0x23F for

the PIC12F508 and 0x400-0x43F for the PIC12F509
are physically implemented. However, only locations
0x200-0x203 and 0x400-0x403 are available. Other
locations are reserved.

2.3

Configuration Word

The Configuration Word is physically located at 0x3FF

and 0x7FF, respectively. It is only available upon
Program mode entry. Once an Increment Address
command is issued, the Configuration Word is no
longer accessible, regardless of the address of the
program counter.
Note:

By convention, the Configuration Word is

stored at the logical address location of
0xFFF within the hex file generated for the
PIC12F508/509. This logical address
location may not reflect the actual physical
address for the part itself. It is the responsibility of the programming software to
retrieve the Configuration Word from the
logical address within the hex file and
granulate the address to the proper
physical location when programming.

DS41227E-page 2

0FFh
100h

Reset Vector

1FEh
1FFh

User ID Locations
Backup OSCCAL value

200h
203h
204h
205h

Reserved

Unimplemented
Configuration Word

FIGURE 2-2:
User Memory
Space

User ID Locations

A user may store identification information (ID) in four

user ID locations. The user ID locations are mapped in
[0x200:0x203] and [0x400:0x403], respectively. It is
recommended that the user use only the four Least
Significant bits (LSb) of each user ID location and
program the upper 8 bits as 1s. The user ID locations
read out normally, even after code protection is
enabled. It is recommended that user ID location is
written as 1111 1111 bbbb where bbbb is user
ID information.

On-chip User
Program Memory

23Fh
240h

On-chip User
Program
On-chip User
Program
Memory (Page 1)
User ID Locations
Backup OSCCAL value

000h
1FFh
200h
3FEh
3FFh
400h
403h
404h
405h

Reserved
43Fh
440h
Unimplemented
Configuration Word

2.4

3FEh
3FFh

PIC12F509 PROGRAM
MEMORY MAP

Reset Vector
Config Memory
Space

2.2

Config Memory
Space

The user memory space extends from (0x000-0x1FF)

on the PIC12F508 and (0x000-0x3FF) on the
PIC12F509. In Program/Verify mode, the program
memory space extends from (0x000-0x3FF) for the
PIC12F508 and (0x000-0x7FF) for the PIC12F509.
The first half, (0x000-0x1FF) and (0x000-0x3FF),
respectively, is user program memory. The second half,
(0x200-0x3FF) and (0x400-0x7FF), respectively, is
configuration memory. The PC will increment from
(0x000-0x1FF) and (0x000-0x3FF), respectively, then
to 0x200 and 0x400, respectively (not to 0x000).

PIC12F508 PROGRAM
MEMORY MAP
000h

User Memory
Space

2.0

7FEh
7FFh

Oscillator Calibration Bits

The oscillator Calibration bits are stored at the Reset

vector as the operand of a MOVLW instruction. Programming interfaces must allow users to program the
Calibration bits themselves for custom trimming of the
INTOSC. Capability for programming the Calibration
bits when programming the entire memory array must
also be maintained for backwards compatibility.

2.5

Backup OSCCAL Value

The backup OSCCAL value, 0x204/0x404, is a factory

location where the OSCCAL value is stored during testing of the INTOSC. This location is not erased during a
standard Bulk Erase, but is erased if the PC is moved
into configuration memory prior to invoking a Bulk
Erase. If this value is erased, it is the users responsibility to rewrite it back to this location for future use.

Preliminary

2007 Microchip Technology Inc.

PIC12F508/509
3.0

COMMANDS AND
ALGORITHMS

3.1

Program/Verify Mode

3.1.2

The ICSPCLK pin is used for clock input and the

ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (TSET1)
and hold (THLD1) times with respect to the falling edge
of the clock (see Table 6-1).

The Program/Verify mode is entered by holding pins

ICSPCLK and ICSPDAT low while raising VDD pin from
VIL to VDD. Then raise VPP from VIL to VIHH. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.

Commands that do not have data associated with them

are required to wait a minimum of TDLY2 measured
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait TDLY2
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.

The sequence that enters the device into the Programming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at VIL). This means
that all I/O are in the Reset state (high-impedance
inputs).

3.1.1

PROGRAMMING

The programming sequence loads a word, programs,

verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x3FF for the PIC12F508 and 0x7FF for the
PIC12F509. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.

FIGURE 3-1:

Note:

After every End Programming command,

a delay of TDIS is required.

The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a don't care during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.

ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
TPPDP

SERIAL PROGRAM/VERIFY
OPERATION

During Read commands, in which the data is output

from the PIC12F508/509, the ICSPDAT pin transitions
from the high-impedance input state to the low-impedance output state at the rising edge of the second data
clock (first clock edge after the Start cycle). The
ICSPDAT pin returns to the high-impedance state at
the rising edge of the 16th data clock (first edge of the
Stop cycle). See Figure 3-3.

THLD0

VPP
VDD

The commands that are available are described in

Table 3-1.

ICSPDAT
ICSPCLK

TABLE 3-1:

COMMAND MAPPING FOR PIC12F508/509

Command

Load Data for Program Memory

Mapping (MSb LSb)

x

Data
0

0, data (14), 0
0, data (14), 0

Read Data from Program Memory

Increment Address

Begin Programming

End Programming

Bulk Erase Program Memory

2007 Microchip Technology Inc.

Preliminary

Externally Timed
Internally Timed

DS41227E-page 3

PIC12F508/509
3.1.2.1

Load Data For Program Memory

After receiving this command, the chip will load in a

14-bit data word when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-1.

FIGURE 3-2:

LOAD DATA COMMAND (PROGRAM/VERIFY)

1

0
0
TSET1
THLD1

TDLY2

ICSPCLK

3.1.2.2

ICSPDAT

16

15

MSb stp_bit

LSb

strt_bit

TSET1
-+THLD1

TDLY1

Read Data From Program Memory

After receiving this command, the chip will transmit

data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as 0s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 Code Protection for details.

FIGURE 3-3:

READ DATA FROM PROGRAM MEMORY COMMAND

TDLY2
1

ICSPCLK
ICSPDAT

15

16

TDLY3
1 0

strt_bit
TDLY1

TSET1

MSb stp_bit
LSb

THLD1
input

DS41227E-page 4

output

Preliminary

input

2007 Microchip Technology Inc.

PIC12F508/509
3.1.2.3

Increment Address

The PC is incremented when this command is

received. A timing diagram of this command is shown
in Figure 3-4.
It is not possible to decrement the address counter. To
reset this counter, the user must either exit and re-enter
Program/Verify mode or increment the PC from 0x3FF
for the PIC12F508 or 0x7FF for the PIC12F509 to
0x000.

FIGURE 3-4:

INCREMENT ADDRESS COMMAND

TDLY2
1

Next Command
1

ICSPCLK

ICSPDAT

TSET1
THLD1

3.1.2.4

Begin Programming (Externally

Timed)

A Load command must be given before every Begin

Programming command. Programming will begin after
this command is received and decoded. Programming
requires (TPROG) time and is terminated using an End
Programming command. This command programs the
current location, no erase is performed.

FIGURE 3-5:

BEGIN PROGRAMMING (EXTERNALLY TIMED)

TPROG
1

End Programming Command

1

ICSPCLK

ICSPDAT

TSET1

2007 Microchip Technology Inc.

THLD1

Preliminary

DS41227E-page 5

PIC12F508/509
3.1.2.5

End Programming

The End Programming command terminates the

program process. A delay of TDIS (see Table 6-1) is
required before the next command to allow the internal
programming voltage to discharge (see Figure 3-6).

FIGURE 3-6:

END PROGRAMMING (EXTERNALLY TIMED)

TDIS
1

Next Command
1

ICSPCLK

ICSPDAT

TSET1

3.1.2.6

Bulk Erase Program Memory

After this command is performed, the entire program

memory and Configuration Word is erased.
Note 1: A fully erased part will read 1s in every
program memory location.
2: The oscillator Calibration bits are erased
if a Bulk Erase is invoked. They must be
read and saved prior to erasing the
device and restored during the programming operation. Oscillator Calibration bits
are stored at the Reset vector as the
operand of a MOVLW instruction.
To perform a Bulk Erase of the program memory and
configuration fuses, the following sequence must be
performed (see Figure 3-12).
1.

2.
3.
4.
5.

THLD1

To perform a full device Bulk Erase of the program

memory, configuration fuses, user IDs and backup
OSCCAL, the following sequence must be performed
(see Figure 3-13).
1.

2.
3.
4.
5.
6.
7.

Read and save 0x1FF/0x3FF oscillator Calibration bits and 0x204/0x404 backup OSCCAL bits
into computer/programmer temporary memory.
Enter Program/Verify mode.
Increment PC to 0x200/0x400 (first user ID
location).
Perform a Bulk Erase command.
Wait TERA to complete Bulk Erase.
Restore OSCCAL bits.
Restore backup OSCCAL bits.

Read and save 0x1FF/0x3FF oscillator

Calibration bits and 0x204/0x404 backup
OSCCAL bits into computer/programmer
temporary memory.
Enter Program/Verify mode. PC is set to
Configuration Word address.
Perform a Bulk Erase Program Memory
command.
Wait TERA to complete Bulk Erase.
Restore OSCCAL bits.

DS41227E-page 6

Preliminary

2007 Microchip Technology Inc.

PIC12F508/509
TABLE 3-2:

BULK ERASE RESULTS

Program Memory Space

PC =

Configuration Memory Space

Program Memory

Reset Vector

Configuration
Word

User ID

Backup
OSCCAL

Configuration Word or
Program Memory Space

First User ID Location

FIGURE 3-7:

BULK ERASE PROGRAM MEMORY COMMAND

TERA
1

Next Command
1

ICSPCLK

ICSPDAT

TSET1
THLD1

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 7

PIC12F508/509
FIGURE 3-8:

READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS

Start

Enter Programming
Mode

Increment
Address

No

PC =
0x1FF/0x3FF?
Yes
Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory

Increment
Address

No

PC =
0x204/0x404?

Yes

Read Backup OSCCAL

Calibration Bits
and Save in
Computer/Programmer
Temp. Memory

Exit Programming Mode

Done

DS41227E-page 8

Preliminary

2007 Microchip Technology Inc.

PIC12F508/509
FIGURE 3-9:

RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS

Start

Enter Programming
Mode

Increment
Address

No

PC =
0x1FF/0x3FF?
Yes
Read Calibration
Bits from
Computer/Programmer
Temp. Memory

Write Calibration Bits

back as the operand
of a MOVLW instruction
to 0x1FF/0x3FF

Increment
Address

No

PC =
0x204/0x404?

Yes
Read Backup OSCCAL
Calibration Bits from
Computer/Programmer
Temp. Memory

Write Backup OSCCAL

Bits back to 0x204/0x404

Exit Programming Mode

Done

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 9

PIC12F508/509
FIGURE 3-10:

PROGRAM FLOWCHART PIC12F508/509 PROGRAM MEMORY

Start

Read and save

OSCCAL bits
(Figure 3-8)

Enter Programming
Mode
PC = 0x3FF/0x7FF
(Config Word)

Increment
Address

Bulk Erase
Device

PROGRAM CYCLE
Load Data
for
Program Memory

One Word
Program Cycle
Begin
Programming
Command
(Externally timed)

Read Data
from
Program Memory

Data Correct?

No

Report
Programming
Failure

End
Programming

Yes
Increment
Address
Command

No

Wait TPROG

All Programming
Locations
Done?

Wait TDIS

Yes
Exit Programming
Mode

Restore 0SCCAL bits

(Figure 3-9)

Program
Configuration
Memory
(Figure 3-11)

Done

DS41227E-page 10

Preliminary

2007 Microchip Technology Inc.

PIC12F508/509
FIGURE 3-11:

PROGRAM FLOWCHART PIC12F508/509 CONFIGURATION MEMORY

Start
Enter Programming
Mode
PC = 0x3FF/0x7FF
(Config Word)

Load Data Command

Programs Configuration Word

One-Word
Programming
Cycle
(see Figure 3-10)

Read Data Command

Data
Correct?

No

Report
Programming
Failure

Yes
Increment Address
Command

No

Address =
0x200/0x400?
Yes
Load Data
Command

Programs User IDs

One-Word
Programming
Cycle
(see Figure 3-10)

Read Data Command

Data
Correct?

No

Report
Programming
Failure

Yes
Increment Address
Command

No

Address =
0x204/0x404?
Yes
Exit Programming Mode

Done

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 11

PIC12F508/509
FIGURE 3-12:

PROGRAM FLOWCHART ERASE PROGRAM MEMORY, CONFIGURATION

WORD
Start
Bulk Erase Device
Read and save
OSCCAL bits
(Figure 3-8)

Wait TERA

Restore OSCCAL bits

(Figure 3-9)

Enter
Program/Verify mode
PC = 0x3FF/0x7FF
(Config Word)

Exit Programming
Mode

Done

DS41227E-page 12

Preliminary

2007 Microchip Technology Inc.

PIC12F508/509
FIGURE 3-13:

PROGRAM FLOWCHART ERASE PROGRAM MEMORY, CONFIGURATION

WORD AND USER ID
Read and save
OSCCAL bits
(Figure 3-8)

Start

Enter
Program/Verify mode
PC = 0x3FF/0x7FF
(Config Word)

Increment
PC

No

PC = 0x200/0x400?
(First User ID)

Yes
Bulk Erase Device

Wait TERA

Restore OSCCAL bits

(Figure 3-9)

Exit Programming Mode

Done

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 13

PIC12F508/509
4.0

CONFIGURATION WORD

The PIC12F508/509 has several Configuration bits.

These bits can be programmed (reads 0) or left
unchanged (reads 1), to select various device
configurations.

REGISTER 4-1:

CONFIGURATION WORD PIC12F508/509

MCLRE

CP

WDTE

FOSC1 FOSC0

bit 11

bit 0

bit 11-5

Unimplemented: Read as 1

bit 4

MCLRE: Master Clear Enable bit

1 = GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD

bit 3

CP: Code Protection bit

1 = Code protection off
0 = Code protection on

bit 2

WDTE: Watchdog Timer Enable bit

1 = WDT enabled
0 = WDT disabled

bit 1-0

FOSC1:FOSC0: Oscillator Selection bits

00 = LP oscillator
01 = XT oscillator
10 = INTOSC
11 = EXTRC
Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

- n = Value at POR

1 = Bit is set

0 = Bit is cleared

DS41227E-page 14

Preliminary

x = Bit is unknown

2007 Microchip Technology Inc.

PIC12F508/509
5.0

CODE PROTECTION

5.3

For the PIC12F508/509, once code protection is

enabled, all program memory locations, 0x040-0x1FE
(F508) and 0x040-0x3FE (F509) inclusive, read all 0s.
Program memory locations 0x000-0x03F, 0x1FF
(F508) and 0x3FF (F509) are always unprotected. The
user ID locations, backup OSCCAL location and the
Configuration Word read out in an unprotected fashion.
It is possible to program the user ID locations, backup
OSCCAL location and the Configuration Word after
code-protect is enabled.

5.3.1

Checksum Computation
CHECKSUM

Checksum is calculated by reading the contents of the

PIC12F508/509 memory locations and adding up the
opcodes up to the maximum user addressable location
(e.g., 0x1FF for the PIC12F508). Any Carry bits
exceeding 16 bits are neglected. Finally, the Configuration Word (appropriately masked) is added to the
checksum. Checksum computation for the PIC12F508/
509 is shown in Table 5-1.
The checksum is calculated by summing the following:

5.1

Disabling Code Protection

It is recommended that the following procedure be

performed before any other programming is attempted.
It is also possible to turn code protection off (CP = 1)
using this procedure. However, all data within the
program memory will be erased when this
procedure is executed, and thus, the security of the
code is not compromised.
Enter Program mode
Execute Bulk Erase
command (001001)
Wait TERA

c)

5.2

Note:

The Least Significant 16 bits of this sum is the

checksum.
The following table describes how to calculate the
checksum for each device.
Note:

To disable code-protect:
a)
b)

The contents of all program memory locations

The Configuration Word, appropriately masked
Masked user ID locations (when applicable)

Program

Memory

The checksum calculation differs depending on the code-protect setting. The

Configuration Word and user ID locations
can always be read regardless of the
code-protect settings.

Embedding Configuration Word

and User ID Information in the
Hex File
To allow portability of code, the programmer is required to read the Configuration
Word and user ID locations from the hex
file when loading the hex file. If Configuration Word information was not present in
the hex file, then a simple warning
message may be issued. Similarly, while
saving a hex file, Configuration Word and
user ID information must be included. An
option to not include this information may
be provided.
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 15

PIC12F508/509
TABLE 5-1:
Device
PIC12F508

CHECKSUM COMPUTATIONS PIC12F508(1)

Code-Protect

Checksum*

Blank
Value

0x723 at 0
and Max
Address

OFF

SUM[0x000:0x1FE] + CFGW & 0x01F

0xEE20

0x0C68

ON

SUM[0x00:0x3F] + CFGW & 0x01F + SUM_ID

0xEDF7

0xD363

Legend: CFGW = Configuration Word

SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.

TABLE 5-2:
Device
PIC12F509

CHECKSUM COMPUTATIONS PIC12F509(1)

Code-Protect

Checksum*

Blank
Value

0x723 at 0
and Max
Address

OFF

SUM[0x000:0x3FE] + CFGW & 0x01F

0xEC20

0xDA68

ON

SUM[0x00:0x3F] + CFGW & 0x01F + SUM_ID

0xEBF7

0xD163

Legend: CFGW = Configuration Word

SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.

DS41227E-page 16

Preliminary

2007 Microchip Technology Inc.

PIC12F508/509
6.0

PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS

TABLE 6-1:

AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY

MODE
Standard Operating Conditions (unless otherwise stated)
Operating Temperature 10C TA 40C
Operating Voltage
4.5V VDD 5.5V

AC/DC CHARACTERISTICS

Sym.

Characteristics

Min.

Typ.

Max.

Units

VDDPROG VDD level for programming operations,

program memory

4.5

5.5

VDDERA

VDD level for Bulk Erase operations, program

memory

4.5

5.5

IDDPROG

IDD level for programming operations,

program memory

0.5

mA

IDDERA

IDD level for Bulk Erase operations, program

memory

0.5

mA

VPP

High voltage on MCLR for Program/Verify

mode entry

12.5

13.5

IPP

MCLR pin current during Program/Verify

mode

0.45

mA

TVHHR

MCLR rise time (VSS to VIHH) for Program/

Verify mode entry

1.0

0.8 VDD

Conditions/
Comments

General

TPPDP

Hold time after VPP

VIH1

(ICSPCLK, ICSPDAT) input high-level

VIL1

(ICSPCLK, ICSPDAT) input low-level

TSET0

ICSPCLK, ICSPDAT setup time before

MCLR (Program/Verify mode selection
pattern setup time)

THLD0

ICSPCLK, ICSPDAT hold time after MCLR

(Program/Verify mode selection pattern setup
time)

0.2 VDD

100

ns

Serial Program/Verify
TSET1

Data in setup time before clock

100

ns

THLD1

Data in hold time after clock

100

ns

TDLY1

Data input not driven to next clock input (delay

required between command/data or
command/command)

1.0

TDLY2

Delay between clock to clock of next

command or data

1.0

TDLY3

Clock to data out valid (during Read Data)

80

ns

(1)

TERA

Erase cycle time

10

TPROG

Programming cycle time (externally timed)

2(1)

ms

TDIS

Time delay for internal programming voltage

discharge

100

TRESET

Time between exiting Program mode with VDD

and VPP at GND and then re-entering Program
mode by applying VDD.

10

ms

Legend:
Note 1:

TBD = To Be Determined.
Minimum time to ensure that function completes successfully over voltage, temperature and device variations.

2007 Microchip Technology Inc.

Preliminary

ms

DS41227E-page 17

PIC12F508/509
NOTES:

DS41227E-page 18

Preliminary

2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

2007 Microchip Technology Inc.

Preliminary

DS41227E-page 19

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

ASIA/PACIFIC

EUROPE

Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com

Asia Pacific Office

Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431

India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632

Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829

India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513

France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79

Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122

Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44

Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509

Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104

Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302

China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521

Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934

China - Hong Kong SAR

Tel: 852-2401-1200
Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857
Fax: 60-3-6201-9859

China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470

Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068

China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205

Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069

China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066

Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850

China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526
Fax: 886-3-572-6459

China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760

Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803

China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571

Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102

China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118

Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350

Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820

China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256

10/05/07

DS41227E-page 20

Preliminary

2007 Microchip Technology Inc.