DESIGN OF LOW POWER CMOS THREE INPUT XOR/XNOR
Abstract: In this paper, we propose a new three-
input XOR/XNOR circuits to improve the speed and Compressors, Comparators, Parity Checkers, Code
power as these circuits is basic building blocks of converters, Error-detecting or Error-correcting codes,
many arithmetic circuits. This paper evaluates and and Phase detector circuit in PLL. We focus on
compares the performance of various XOR-XNOR
XORXNOR circuits as they are often used to obtain
circuits. We start with selecting a basic cell
including three independent inputs and two optimized performances for full adders. Balanced
complementary outputs. Next we combine this basic XORXNOR circuits along with multiplexers are
cell with various correction and optimization also the main components of compressors in parallel
techniques to build a perfect XOR-XNOR circuit multiplication circuits. Also these circuits play an
with full swing operation. The performance of the important role in comparator and parity checker
XOR-XNOR circuits based on 90 nm CMOS
blocks. Balanced XORXNOR circuits, which serve
technology process models at all range of the supply
voltage is evaluated by the comparison of the as critical components in balanced complimentary
simulation results obtained from MICRO WIND. outputs, eliminate power dissipated by the glitches. In
The simulation results demonstrate that the any type of logic design, the non full swing outputs
proposed circuits are superior in terms of speed, play a decisive role in cell weak drivability. Full
power consumption and power-delay product (PDP) swing outputs impact multi-stage structured
with respect to other designs.
arithmetic circuit performance. Therefore designers
consider achieving full swing output operations as an
Key words : Binary Decision Diagram, 3-input
important factor in arithmetic circuit basic block
XOR/XNOR circuits, CMOS.
design.
I.INTRODUCTION
While the growth of the electronics market has driven
the VLSI industry towards very high integration
density and system on chip designs and beyond few The performance of the complex logic circuits is
GHz operating frequencies, critical concerns have affected by the individual performance of the XOR-
been arising to the severe increase in power XNOR circuits that are included in them [1]-[6].
consumption and the need to further reduce it. Therefore, careful design and analysis is required for
Moreover, with the explosive growth th demand and XOR-XNOR circuits to obtained full output voltage
popularity of portable electronics is driving designers swing, lesser power consumption and delay in the
to strive for smaller silicon area, higher speeds, critical path. Additionally, the design should have a
longer battery life, and more reliability. Power is one lesser number of transistors to implement XOR-
of the premium resources a designer tries to save XNOR circuits and simultaneous generation of the
when designing a system. The XOR-XNOR circuits two non-skewed outputs. In this paper a PTL based
are basic building blocks in various circuit especially- XOR and XNOR circuits were considers. Despite the
Arithmetic circuits (Full adder, and multipliers), saving in transistor count, the output voltage level is
degraded at certain input combinations. The
reduction in voltage swing, on one hand, is beneficial
to power consumption. On the other hand, this may We consider the power-delay product (PDP) as the
lead to slow switching in the case of cascaded design target. This method has some advantages.
operation. We propose and compare new XOR- 1. It increases the driving capability and avoids
the degradation on the output voltage.
XNOR circuit designs which produce the XOR-
2. It uses only less number of transistors in the
XNOR outputs simultaneously with full output critical path which results in less delay and
voltage swing. The NMOS and PMOS transistors are power- delay product(PDP).
added to the basic circuits to alleviate the threshold 3. The dynamic consumption optimization
voltage loss problem commonly encountered in pass comes from the fact of well-balanced
transistor logic design. We see many published propagation delay.
4. Power-ground-free main structure leads to
papers that compete in designing better circuits [7]-
power reduction.
[12]. Such studies mostly rely on creative design 5. The methodology has high flexibility in
ideas but do not follow a systematic approach. As a target and systematically consider it in the
consequence, most of them suffer from some three design steps. This can lead to efficient
different disadvantages [8]. circuits in terms of performance , power,
PDP, EDP, area, or a combination of them.
1) They are implemented with logic styles
that have an incomplete voltage swing in
II.EXISTING WORK
some internal nodes, which leads to static
power dissipation. In this section, we will see the three-input
2) Most of them suffer from severe output XOR/XNOR circuits to examine their high-
performance[16].
signal degradation and cannot sustain low-
In complementary CMOS logic [16], the
voltage operation. pull-down and pull-up networks used in the circuit
3) They predominantly have dynamic power perform the function in a complementary way. It has
consumption for nonbalanced propagation high noise margin and no static power consumption.
delay inside and outside circuits, which In the CMOS with transmission gate ,[16]there is a
results in glitches at the outputs. advantage of using less number of transistors. In
complementary pass-transistor, it has a good output
Therefore, a well-organized design methodology can
driving capability and pass-transistor logics gain their
be regarded as a strong solution for the challenge.Cell
speed over the CMOS due to their high logic
design methodology (CDM) has been presented to
functionality.
design some limited functions, such as two-input
XOR/XNOR and carryinverse carry in the hybrid- The XNOR-XOR circuit by using
CMOS style [13][15]. The predominant results CMOS transistor and compare it with the
persuade us to improve CDM through two stages: 1) proposed design of XNOR-XOR circuit using
generating more complex functions and 2) rectifying transmission gate with CMOS inverter
some remaining flaws. The flaws in previously circuit. Figure-1[16] shows the XNOR-XOR
published CDM include containing some manual combine gate using CMOS transistor
steps in the design flow and generating a large circuit. There are total sixteen transistors
number of designs in which the predominant ones used in which 8 transistors are PMOS and
would be determined after the completion of rest are the NMOS transistors. The NMOS
simulations. CDM is matured as systematic CDM transistor can give the LOW signal
(SCDM) in designing the three-input XOR/XNORs completely, but it has very poor
for the first time. It systematically generates performance at HIGH signal. Similarly
elementary basic cell (EBC) using binary decision PMOS transistor can gives the HIGH
diagram (BDD), and wisely chooses circuit signal completely, but poor performance
components based on a specific target. Therefore, at LOW signal .
after the systematic generation, the SCDM considers The a concept of transmission
circuit optimization based on our target in three steps: gates and CMOS inverter[17]. The CMOS
1) wise selection of the basic cell; 2) wise selection inverter is driving the transmission gate to
of the amend mechanisms; and 3) transistor sizing. achieve the perfect output voltage swing.
P and Q are given as the input of
transmission gates through CMOS inverter.
Output
of transmission gates gives the XNOR feedback pull up-down, bootstrap-feedback , inverter-
output and using an inverter we get the feedback , and inverter-pull up-down].
XOR output. The transmission gate allows
to passes the signal through it, when the Introduction of Feedback Networks
enable signal of transmission gate is high.
The transmission gate has a n-channel All circuits with complementary outputs have the
device and a p-channel device, the n- ability to optionally determine the state of an output
channel MOS is situated on the bottom of or amplify it through the use of another output and a
the p-channel MOS. When zero signals
suitable transistor. Transistor or transistors which are
apply to the enable (i.e. en) pin the
transmission gate is off, and no signal is placed between the two outputs to influence the
transferred through it. When enable signal second output through activating the first one, are
is asserted high, the input signal appears called feedback networks. This feedback network is
to the output. placed between the two complementary out-puts and
causes the high impedance output states to be
III. PROPOSED WORK
eliminated and replaced by the desired levels. Also, it
1. INTRODUCTION OF CELLS is possible to ensure full swing operation at the
outputs. As different basic cell versions presented in
this work come with different short comings, the
In this section we introduce different basic cells
which are used as a basis for designing various required feedback net-work should be different.
circuits. To pro-vide better understanding we first
introduce the elementary structure, referred to as the
elementary basic cell. We use four different feed back networks and they
are: Fp, Fn, Fc and Fnp. Fp is a feedback network
2. The Elementary Basic Cell using two pMOS transistors. Fn is a feedback
network with two nMOS transistors. Fc is a
In order to generate the EBC of three-input complementary feedback network and Fnp includes
XOR/XNOR circuits, four steps are taken from . nMOS and pMOS transistors placed between the two
Initially, three-input XOR and its complement is complementary outputs Y and Y . Note that we
represented by one binary decision tree (BDT) [18] in improve the driving capability of feedback networks
order to share common sub circuits. as we use VDD and GND connections.
The step is followed by applying reduction rules to
simplify the BDT representation[19]. These include
elimination, merging, and coupling rules. The result
of applied reduction rules to the tree is shown
in Fig. 1(c). as the inputs into the first level are 0 s
and 1s of the functions truth table, the 0 and 1 can
be replaced by the Y and Y , respectively. Then the
simplified symbol can be divided into two distinct
symbols: 1) the plus sign with the x input control and
2) the minus sign with the x input control. The result
of applying steps 3 and 4 is shown in Fig. 1(d). The
EBC, which is extracted from the above procedure,
has been presented in Fig. 1(e).
MECHANISMS
Pull Up and Pull Down Networks
Different mechanisms are optimization mechanisms
to resolve non full swing [inverter and feedback ],
correction mechanisms to resolve high impedance
[pull up-down network and feedback ], or the
combinations of them [bootstrap-pull up-down,
The use of pull up and pull down networks as a
means of eliminating the critical states of a circuit is
common and has been used in several reports[20].
The high impedance states should be replaced by 0
or 1.One possible solution is to use pull up and pull
down networks. When facing output high impedance
states, it is possibleto use a pull up network to
connect Y or Y to the supply voltage.This results in
replacing the high impedance state by logic 1.T o
replace a high impedance state with logic 0, a pull
down network is used to connect the output to
ground.
Output Inverters
One way to ensure full swing operation at the outputs
is to use output inverters. Adding inverters to the
original circuit increases the number of transistors, Fig: Cmos Three-input XOR/XNOR circuit I.
power dissipation, area and the overall delay of the
circuit. Meantime using inverters results in signal
level restoration but enhances the circuit drive
according to transistor sizes. Using this mechanism
for the basic cells eliminates the non full swing
operation but cannot replace high impedance states.
Bootstrap Technique
By placing a boot transistor between the input and the
gate terminal of the transistor we shift the gate
voltage of the transistor.If the value of this shift is
greater than or equal to the threshold transistor
Fig: Cmos Three input XOR/XNOR circuit II.
voltage (VT ) the transistor can transfer data to the
outputs perfectly and there will be no voltage drop
due to transistors threshold voltages. Experimental
results and analysis of the circuit reveals that in order
to provide the capacitive property and for the boot
phenomenon to occur, boot transistors and main
transistors should be of the same type.
Fig: Cmos Three input XOR/XNOR circuit III.
IV.PERFORMANCE AND SIMULATION
Based on the performance of the proposed designs
the power , delay and PDP values are tabulated
The performance of our proposed designs of three- and compared with the existing circuits.
input XOR/XNOR are simulated below.
400
300
powe
200 r
dela
100 y
0
Cmos 90nm Cmos 65nm
Fig : output waveform of circuit I
Fig: power and delay of CMOS circuit I
3000
2500
2000
Powe
1500 r
Dela
1000 y
500
0
Cmos 90nm Cmos 65nm
Fig: power and delay of CMOS circuit II
Fig: output waveform of circuit II
500
400
300 Powe
r
200
Dela
y
100
0
Cmos 90nm Cmos 65nm
Fig: Power and Delay of CMOS circuit III
Fig: output waveform of circuit III
The performance results show that the feedback
networks are better to produce full output swing.
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