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Avc - M.tech. Sem II - Hw-I Feb. 2018

This document contains homework problems from the M.Tech. analog VLSI circuits course at Maulana Abul Kalam Azad University of Technology in West Bengal. The homework covers topics including: 1) Plotting MOSFET transconductance and deriving the transconductance equation accounting for channel length modulation. 2) Analyzing a two-MOSFET circuit and proving it can be viewed as a single transistor. 3) Deriving expressions for MOSFET cascode amplifier output resistance and voltage gain of a common-source stage. 4) Deriving conditions for MOSFET linear resistance and finding drain current in a circuit.

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Agnibha Dasgupta
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42 views

Avc - M.tech. Sem II - Hw-I Feb. 2018

This document contains homework problems from the M.Tech. analog VLSI circuits course at Maulana Abul Kalam Azad University of Technology in West Bengal. The homework covers topics including: 1) Plotting MOSFET transconductance and deriving the transconductance equation accounting for channel length modulation. 2) Analyzing a two-MOSFET circuit and proving it can be viewed as a single transistor. 3) Deriving expressions for MOSFET cascode amplifier output resistance and voltage gain of a common-source stage. 4) Deriving conditions for MOSFET linear resistance and finding drain current in a circuit.

Uploaded by

Agnibha Dasgupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Maulana Abul Kalam Azad University of Technology, PGMVD – 201

West Bengal
M.TECH. SEMESTER - II, FEBRUARY 2018
Home Work – I
PGMVD – 201: ANALOG VLSI CIRCUITS

1 a)

For the circuit shown above plot the transconductance against the drain-to-source voltage of
M1 .

b) Explain channel-length modulation in a MOSFET and derive the equation for the drain-
current in its presence.

c) Prove that the transconductance of a MOSFET in the presence of channel-length modulation


is
𝑊
µ𝑛 𝐶𝑂𝑋 𝐿 𝐼𝐷
𝑔𝑚 = √ where symbols carry their usual meaning in this context.
1 + 𝜆𝑉𝐷𝑆

2 a) For the circuit shown below calculate the drain-current as a function of VGS and VDS and
prove that it can be viewed as a single transistor with an aspect ratio of W/(2L). Assume that
neither body-effect nor channel-length modulation exists, i.e., λ = γ = 0.

MAKAUT, West Bengal, M.Tech. Semester–II, Home Work, February 2018 (Course # PGMVD – 201) Page 1 of 2
b)

Prove the following relationship that keeps the NMOS transistor M1 in saturation. Assume
that C1 acts as a AC short at the frequency of operation.
VGS3 + VTH1 ≥ VGS2 where VGS2(3) = Gate-to-source voltage of the transistor M2(3).

c) Calculate the intrinsic gain of an NMOS transistor operating in saturation with W/L = 50/0.5
and |ID| = 0.5 mA.

3 a) Draw the circuit diagram and its small-signal equivalent of a MOSFET cascode amplifier
and prove that its output resistance can be expressed as

where gm2 = transconductance of the MOSFET in the CG stage, ro2 = resistance due to
CLM of the MOSFET in the CG stage, ro1 = resistance due to CLM of the MOSFET in the
CS stage.

b) Draw the small-signal equivalent circuit of a CS stage with a load resistance RD in the
presence of channel-length modulation and hence derive the equation for its voltage-gain.
Hence find the voltage-gain if the load resistance is replaced with an ideal current-source.

4 a) Find the condition under which a MOSFET behave as a linear resistance and hence derive
the equation for this resistance in terms of gate-to-source voltage.

b) Find IX in the following circuit. Assume that there is no CLM and body effect.

MAKAUT, West Bengal, M.Tech. Semester–II, Home Work, February 2018 (Course # PGMVD – 201) Page 2 of 2

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