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Lec Arm PDF

- ARM is a British company that designs and licenses processor architectures and cores. It is known for its low-power ARM processors used in many portable devices. - The ARM architecture is 32-bit, load-store with 3-address instructions. It has conditional execution, shift and ALU operations in single cycles. - ARM processors use a Harvard architecture with separate instruction and data buses and caches. They employ pipeline techniques and have evolved from 3 to 5 stages.

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153 views

Lec Arm PDF

- ARM is a British company that designs and licenses processor architectures and cores. It is known for its low-power ARM processors used in many portable devices. - The ARM architecture is 32-bit, load-store with 3-address instructions. It has conditional execution, shift and ALU operations in single cycles. - ARM processors use a Harvard architecture with separate instruction and data buses and caches. They employ pipeline techniques and have evolved from 3 to 5 stages.

Uploaded by

spauls
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Spring 2010

Prof. Hyesoon Kim


• ARM is short for Advanced Risc Machines Ltd.
– Founded 1990, owned by Acorn, Apple and VLSI
• Known before becoming ARM as computer
manufacturer
• ARM is one of the most licensed company
• Used especially in portable devices due to low
power consumption and reasonable performance
(MIPS/watt)
• They do not fabricate silicon

http://tisu.it.jyu.fi/embedded/TIE345/luentokalvot/Embedded_3_ARM.pdf
• 32-bit wide (16-bit thumb compressed format)
• Load-store instruction set architecture
• 3-address data processing instructions
• Conditional execution of every instruction
• Powerful load and store multiple register instructions
• A general shift operation and a sequential ALU operations in a single
instruction that executes in a single clock cycle
• Open instruction set extension through the coprocessor instruction
set, including adding new registers and data types to the
programmer’s model
• Compressed 16-bit thumb architecture

Steve Furber, ARM system-on-chip architecture 2nd edition


• Data processing (ALU) operations write results only into
registers
• Memory operations are only copy (from memory to
registers, register to memory)
• ARM does not support memory-to-memory operations
• ARM instruction three categories
– 1. data processing instructions
– 2. Data transfer instructions
• memory-to/from-registers, exchange-memory-register (system only)
– 3. Control flow instructions
• Branch instructions, branch and link register (saving return
address), trap instructions (supervisor calls)

Steve Furber, ARM system-on-chip architecture 2nd edition


Usable
Current Visible Registers
in user mode
r0
Abort
SVC
Undef
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode
r1
r2
r3 Banked
Systemout
modes
Registers
only
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr
31 28 27 8 7 6 5 4 0

NZCV unused IF T mode

• N: Negative (the last ALU operation)


• Z: zero (the last ALU operation)
• C: carry (the last ALU or from shifter)
• V: overflow
CPSR[4:0] Mode Use Registers
10000 user Normal user code user
10001 FIQ Processing fast interrupts _fiq
10010 IRQ Processing standard interrupts _irq
10011 SVC Processing software interrupts (SWIs) _svc
10111 Abort Processing memory faults _abt
11011 Undef Handling undefined instruction traps _und
11111 System Running privileged operating system user
tasks

Software interrupt: supervisor calls


• A linear array of byte address
• Data format (8-bit bytes, 16-bit half-words, 32-bit words)
• Aligned address accesses
• Little endian
Bit 31 Bit 0
23 22 21 20
19 18 17 16
15 14 13 12
11 10 9 8
7 6 5 4

3 2 1 0
Byte 1 Byte 0

Steve Furber, ARM system-on-chip architecture 2nd edition


• Fetch/Decode/Execute
• Allow multi-cycle
execution
• Register, two read ports,
one write port,
– Additional register
read/write for r15 (program
counter)

Steve Furber, ARM system-on-chip architecture 2nd edition


• Fetch/Decode/Execut
e/Mem/write-back
• Introduce forwarding
path

Steve Furber, ARM system-on-chip architecture 2nd edition


• 2-Phase non-overlapping clock scheme

Steve Furber, ARM system-on-chip architecture 2nd edition


• SPSR (Saved Program Status Register)

Steve Furber, ARM system-on-chip architecture 2nd edition


• 16 bits long
• Similarity with ARM ISA
– The load-store architecture with data processing, data transfer,
and control-flow instructions
– Support Byte, half-word, word (aligned accesses)
– A 32-bit unsegmented memory
• Differences
– Most Thumb instructions are executed unconditionally
• All ARM instructions are executed conditionally
– Many thumb data processing instructions use a 2-address format
– Thumb instruction formats are less regular than ARM ISA.

Steve Furber, ARM system-on-chip architecture 2nd edition


• ARM7: 3 stage pipeline, 16 32-bit
Registers , 32-bit instruction set
• TMDI
– Thumb instruction set
– Debug-interface
– Multiplier (hardware)
– Interrupt (fast interrupt)
– The most commonly used one
• 32/16-bit RISC
• 32-bit ARM instruction
set
• 16-bit Thumb
instruction set
• 3-stage pipeline
• Very small die size
and low power
• Unified bus interface
(32-bit data bus carries
both instruction, data)
1st Phase 2nd Phase

The ARM9 Family-High Performance Microprocessors for Embedded Applications


• Instruction compression to save I-cache/memory
accesses
• Use only top 8 registers,
• 3 operands  2 operands
• Instructions are compiled either native
ARM code or Thumb code
– To utilize full 16bit opcode
– Use current processor status register (CPSR)
to set thumb/native instruction
• All instructions are conditional
• BX, branch and eXhange  branch and
exchange (Thumb)
• Link register (subroutine Link register)
– R14 receives the return address when a
Branch with Link (BL or BLX) instruction is
executed
• 5-stage pipeline
• I-cache and D-cache
• Floating point support
with the optional VFP9-S
coprocessor
• Enhanced 16 x 32-bit
multiplier capable of
single cycle MAC
operations
• The ARM946E-S
processor supports
ARM's real-time trace
technology
• ARM7 3stage->ARM9 5 stage
– Increase clock frequency

The ARM9 Family-High Performance Microprocessors for Embedded Applications


• ARM7: Thumb instruction decode: first ½
phase of decode stage
• ARM9: Parallel decoding
• ARM7: ALU (arithmetic, and logic units) is
active all the time
• ARM9: Two units are partitioned to save
power
• ARM9: Forwarding path

The ARM9 Family-High Performance Microprocessors for Embedded Applications

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