Fundamentals of
Signal and Power Integrity
1
Issues Associated with High Speed
Signals
Driver
Via
PCB
Power Plane
Ground Plane
DC Power Supply Receiver
3
Signal Integrity SI
Signal Transmission Issues:
Attenuation, Reflection, Dispersion, Interference, Crosstalk
4
Power Integrity
Power Delivery Issues:
Voltage Drop, Switching Noise, Crosstalk
6
Elctromagnatic Compatibilty EMC
Electromagnetic Compatibility Issues:
Near Field Coupling, Radiated Emissions
8
SI + PI + EMC = “Electrical Integrity“
10
(1)
Signal Integrity
13
Electrical Integrity of Digital Systems
14
Packaging of Digital Systems
Housing / Chassis
Daughtercard
Cable
IC (Transmitter)
IC (Receiver)
Package / Module
Socket
Connector
Connector
Backplane / Motherboard
15
Packaging of Digital Systems
Interconnect
(Link)
Connector
16
Effect of Interconnects
The ideal interconnect will simply delay the signal:
Tx Rx
Any real interconnect will additionally change timing and amplitude:
Rx
Tx
17
Effect of Interconnects
The deviations in timing and amplitude are in general called:
Timing jitter or simply: JITTER
Amplitude noise or simply: NOISE
18
Signal Bandwidth
1 0.3 .. 0.5
f max
s(t ) TR rise time
ŝ Maximum Frequency
ŝ / 2
TB
TR
t
1 0.5
f0
2TB bit period
Fundamental Frequency
19
Maintaining Signal Integrity
1. Match terminations
2. Manage discontinuities
3. Reduce Coupling
20
Effect of Terminations
Let‘s use the following interconnect (link) model:
Z0
ZS
ZL ??
Transmitter Interconnect Receiver
21
Effect of Terminations
Z0
ZS
ZL
input acceptance TL transfer function
source transmission load transmission
source reflection load reflection
28
Effect of Terminations
Z0
ZS
ZL
ZS Z L Z0
30
Effect of Terminations
Matched interconnect:
lossless transmisson line
Voltage
lossy transmisson line
Time
TD
Mismatched Interconnect: Voltage low source impedance
high source impedance
Time
2 TD
31
Matching Terminations
Check your interconnect length (3 TD
TR )
Check your interconnect impedance!
Match receiver input impedance!
Match transmitter output impedance!
33
Packaging of Digital Systems
Interconnect
(Link)
Connector
42
Effect of Coupling
Consider two transmission lines in close proximity:
(1) Input Aggressor Line (Active Line) (2) Output
(3) Near End Victim Line (Quiet Line) (4) Far End
43
Effect of Coupling
Consider two transmission lines in close proximity:
(1) Input (2) Output
IC
UL
(3) Near End (4) Far End
NEXT = FEXT =
Near End Crosstalk Far End Crosstalk
(sum of ind. and cap. crosstalk) (difference of ind. and cap. crosstalk)
44
Reducing Coupling (Crosstalk)
Increase line separation!
Decrease distance to ground!
Balance capacitive and inductive coupling!
Increase rise time!
Reduce coupling length!
Use differential signaling!
48
Differential Signaling
In a SINGLE-ENDED link
there is a common
(global) reference against
which the signal is
measured ("ground").
In a DIFFERENTIAL link
the reference is the
negative of the signal
itself (which has to be
transmitted as well).
49
(2)
Power Integrity
50
Electrical Integrity of Digital Systems
51
Effect of Common Power Delivery
IC #1 IC #2
ZPDN
U0
PDN = Power Delivery Network
52
Effect of Common Power Delivery
R L uIC
iGate1, iGate2, …
U0
Du
uIC = U0 - Du
Du (t ) R iGate1 (t ) iGate1 (t ) ... L iGate1 (t ) iGate1 (t ) ...
d
dt
"DC-drop or IR-drop" "DI-drop or DI-noise"
53
Maintaining Power Integrity
1. Decrease PDN impedance
2. Add decoupling
3. Add even more decoupling
4. Use several power supplies
5. Use on-chip VRMs
54
PDN Elements
IC incl.
High Power Discrete Power/Ground Grid Package incl.
DC Supply Decoupling & Integrated Decaps Power/Ground
Capacitors Planes
(various sizes)
Voltage
Regulator
Module
Printed Circuit Board incl.
Power/Ground Planes
55
Decreasing PDN Impedance
Use adequate copper cross sections!
Avoid big current loops!
Use power/ground planes!
Provide enough power/ground pins!
Decouple!
!
59
Decoupling
R L
U0 ~ ZIC ( f )
Z PDN R jwL
jwL (R = 0.7
m,
(for large w ) L = 40 nH)
60
Decoupling
… we ask what a so called "decoupling" or "bypass" capacitor does:
R L
U0 ~ C ZIC ( f )
R = 0.7 m
R jwL
Z PDN L = 40 nH
1 jwRC w 2 LC C = 1 mF
1
(for large w )
jwC
61
Decoupling
Heuristic explanation:
R L
U0 ~ C ZIC ( f )
Frequency domain: Beyond the resonance frequency the capacitor
decouples the part of the PDN that lies "left" of him, i.e. the IC sees
only the impedance of the capacitor.
Time domain: The capacitor stores charges close to the IC that can
become currents needed for fast switching. It is like a "small battery".
62
Decoupling
While being beneficial at higher
frequencies decoupling increases
the PDN impedance in the vicinity
of the resonance frequency:
Hence, increasing the "damping"
(by increasing R and/or reducing
L/C) can be helpful:
63
Real Word Decoupling Capacitors
Unfortunately, there is no ideal capacitor available in the real world!
Ideal world: … and real world:
C R L C
R is also is called the EQUIVALENT SERIES RESISTANCE
(ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL).
As a consequence any real world capacitor behaves approximately
like an inductor beyond its resonance frequency:
w0 1 / LC
64
More Decoupling
board-level package-level chip-level
65
Power/Ground Planes
Power/ground planes serve multiple purposes at the same time:
easy access to power and ground domains for mounted
components
a "natural" decoupling capacitor for PDN improvement
return current paths, i.e. they serve as reference conductors
shielding between different signal layers, i.e. they reduce
crosstalk
containment for internal EM fields, i.e. reduce EM emission
66
Adding Decoupling
Determine your target impedance!
Determine your operating frequency range!
Provide decoupling at all levels/frequencies!
Use parallel decoupling to reduce ESR/ESL!
Be wary of resonances!
69
(3)
Vias and Return Currents
70
The Problem With Vias
Signal Current
SignalVia
Load
Return Current
Ground Via
Load
This diagram shows two conductive traces on opposite sides of a
PCB. When a current starts to flow in the top trace, a return
current is immediately established in the bottom trace.
71
Best practices dictate the following: Always provide a ground return
path in the same layer or an adjacent layer for single-ended signals,
differential pairs, and power planes.
Usually signals that travel over the power planes before reaching the
ground layers share their electric fields with the power place and can
as a result create noise in the signal lines
Conclusion:
Utilize Ground Return Vias and Ground Return Paths
Careful and deliberate planning of a ground return path will keep
unwanted currents from forming in parts of your circuit where they
should not be. Provide deliberate ground return vias and ground return
paths for all of your signals—especially high-speed switching signals.
(4)
Wrapping Up
92
Electrical Integrity of Digital Systems
93
Electrical Integrity of Digital Systems
The basic goals of EMC, SI, and PI for an electrical system are
complementary to each other.
SIGNAL INTEGRITY: insure SNR
System
acceptable quality of signals within Target
Frequency
POWER INTEGRITY: insure PDN Target
acceptable quality of power Impedance System
delivery within
Frequency
Target
EMC: insure acceptable level of EMI
System
interference with the outside
Frequency
94
