Analog Integrated Circuits and Signal Processing 5, 19-30 (1994)

© 1994 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

A Simplified Synthesis of Transmission Lines with a Tree Structure

D. ZHOU, S. SU AND E TSUI

Department of Electrical Engineering, The University of North Carolina at Charlotte, Charlotte, NC 28223
D.S. GAO
Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CA 94043-1100
J.S. CONG
Department of Computer Science, The University of California at Los Angeles, Los Angeles, CA 90024

Received September 23, 1992; Revised May 3, 1993.

Abstract. The limiting factor for high-performance systems is being set by interconnection delay rather than tran-
sistor switching speed. The advances in circuits speed and density are placing increasing demands on the perform-
ance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extreme-
ly important and timely research area, we analyze in this paper the circuit property of a generic distributed RLC
tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform
and delay in an RLC tree. The result on the RLC tree is then extended to the case of a tree consisting of transmis-
sion lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form
solution. The approximation reveals the relationship between circuit performance and the design parameters which
is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.

1. Introduction A less complicated approach to evaluate intercon-

nection performance considers a 1-D problem, i.e.,
Interconnection design has been a major concern in the solves a 1-D telegraph equation [3]. Even though the
design of high-speed systems. The state-of-the-art IC dimension of the problem is reduced only the ideal case,
chips are designed to operate at multigigahertz clock an infinite long line or ideal termination, is analytic-
rate. In this speed range the traditional lumped RC ally solvable [4]. For a generic interconnection struc-
model can no longer provide sufficient modeling infor- ture, for instance, several lines connected into a tree,
mation about interconnections. Instead, the effect of in- an exact analytic solution is almost impossible to be
ductance must be considered, and, in general, a obtained because of the irregular boundary conditions
distributed or transmission line model need to be used. encountered in solving the telegraph equation.
Research on the evaluation of interconnection perform- The next level to attack the interconnection issue is
ance has been active in several different levels. The circuit simulation, which is a typical numerical ap-
most accurate and original method is to solve 3-D (or proach. Since circuit simulation is an indispensible step
2-19) time-variant Maxwell equations [1-2]. The effect in IC design the research along this line focuses on
of electrical and geometric parameters on the circuit developing an efficient interconnection model so that
performance can be investigated in great detail. For in- it can be easily incorporated into the existing circuit
stance, the scattering of waves at a wire bend (or a simulator, such as spice [5, 6]. Although a simulator
discontinuity) can be evaluated. However, due to the in principle can simulate any circuit it has the disad-
complexity of this approach only numerical method is vantage that a general understanding of physical mean-
feasible. A general relationship between the circuit per- ing behind the interconnection design is often shaded
formance and design parameters cannot be explicitly by the numerical calculation. For instance, a simulator
established. Furthermore, a practical design tool can- can easily evaluate the performances of the trees of dif-
not be developed based on this approach because of ferent topologies which implement the same net. It is
its formidable computation time. hard for the simulator to tell why one topology is
20 Zhou, Su, Tsui, Gao and Cong

better than the others. Even more importantly, it

is very difficult to construct a proper interconnection
topology using the information provided by the circuit
simulation.
A deep understanding of the intrinsic relationship
between interconnection performance and interconnec-
tion topology and parameters is the starting point for
optimal interconnection designs. Such a relationship
can only be thoroughly explored from an analytical ap-
proach. In this paper we first analyze a generic
distributed RLC-tree circuit. We shall solve this prob-
lem analytically, and then extend the result to the case
where the interconnection has a tree structure consisting
of transmission lines, which is called tree-of-trans-
mission-lines. Based on the analytic solution a lower-
order circuit approximation will be presented for devel-
oping a closed-form solution. The approximation re-
veals the interplay between circuit performance and the
design parameters which is essential to IC layout design
[7, 8]. A simplified formula is consequently derived
to guide VLSI performance driven layouts [9-11].
The article is organized as follows. In Section 2 the
necessary background and the circuit formulation of
interconnections in the high-speed system are intro-
duced. In Section 3 the defined problems, RLC tree and Fig. 1. An illustrationof the interconnectionlayoutin IC chips.
tree-of-transmission-lines, are analyzed analytically. In field, 2-D field effect is modeled by introducing extra
Section 4 the approximation technique is discussed and capacitance at the discontinuities of interconnections,
a closed-form solution is presented. In Section 5 some such as branching point and wire bend (figure 2). The
special issues regarding the tree-of-transmission-lines loading gates also introduce the capacitance or resis-
are discussed in detail. In Section 6 several design ex- tance at the nodes of the tree, depending on the tech-
amples are presented and the accuracy of the developed nology (MOS or bipolar device). Formally, we define
approximation is confirmed by the numerical simula-
tion. Finally, in Section 7 comments are made on the DEFINITION 1. The topology of the tree-of-transmission-
obtained results and on the further research. lines is a tree. Each edge of the tree is a transmission
line. At each node there is a capacitor connected to the
ground.
2. Preliminaries
In the following we shall first solve a distributed RLC
Let us consider a circuit layout as illustrated in figure tree circuit and then extend the result to the case of tree-
1 where gate Go drives six gates Gi, i = 1. . . . . 6 of-transmission-lines by taking appropriate limitations.
through a net N. The interconnection (net N) has a tree In order to do so we cut each edge of tree-of-trans-
structure. An accurate modeling of this interconnec- mission-lines into many small segments and model each
tion calls for the consideration of transmission line ef- segment by an RCL circuit as indicated in figure 2. The
fect when the circuit intends to operate at very high resulted circuit is a distributed RLC tree. Taking
frequency. That is, each wire segment needs to be Laplace transform on the RLC tree we can introduce
treated as a transmission line. Since a net is usually a more simple and general notation as illustrated in
laid out in a tree structure we hence have a tree in which figure 3, where Zi, i = . . . , represents impedance be-
edges are transmission lines. We call it tree-of- tween two nodes. Notice that the impedance here can
transmission-lines. Each transmission line in the tree represent a much more complicated circuit than just the
is described by a telegraph equation. Because the Laplace transform of a single resistance or capacitance.
telegraph equation considers only 1-D electromagnetical The analytical approach addressed in the following
 A Simplified Synthesis of Transmission Lines with a Tree Structure 21

G1

branching point

G2

G3

~4
Driver
::!!:::!~i:il

~ \.
¢::8 ~oTM

9 bipolar mos

Fig. 2. Tree-of-transmission-lines.

p(id) node j
1f 5 Z6 ~ 6 Z7 7

~ Zl Za9

| V 41-----t V V node inside Zlo

\ z~ ~zx~ .::~:.ii::i::iii.~,:,i=:.i.:iii::iii~4:.iii!::~
....
ii~: Z24
root z2 z3 3 .............
b r a n c h m g node ~ _ "....... =ii:~ii::i:
\ ["]z,, ~z,4/l /edge impedance ~ii:!~ii!i!i!!ii i
\ T T A I I z, / n~de impedance

L
on-path

Fig. 3. The distributed R C L tree to model the tree-of-transmission-lines.

22 Zhou, Su, Tsui, Gao and Cong

sections based on the circuit model shown in figure 3 kth column of A. Theoretically, Vk(S) can be calcu-
actually has a broader application than just the simple lated by using the following equation.
RLD tree.
Nk(s)
Let us consider the circuit voltage response Vk at an Vk -- D ( s ) ' k = 1, 2, . . . , m. (3)
arbitrary node k. Denote the path from the root to node
k by p(k). Denote the set of the nodes on p(k_) by Ap Since the computation of Nk(S) and D(s) is time con-
and the set of the rest nodes in the tree by Ap. The suming and, in general, only the numerical solutions
nodes in Ap and ,,ip are respectively called on-path and are feasible, Pillage and Rohrer [12] proposed an ap-
off-path nodes with respect to node k. Denote the path proximation method (AWE) to calculate them. In their
from node i to nodej by p(i, j). The impedance in an AWE method a high-order system is first approximated
edge of the tree is called edge impedance. Denote by by a desired lower-order system, and then poles are
Zp(i,j)(S ) the sum of the edge impedance of the edges calculated from the approximated lower-order system.
inp(i, j). Call Zp(i,j)(s) path impedance. From a node Notice that their method relies on the numerical tech-
j to ground there is a unique path without passing niques. The physical meaning of the solution is difficult
through the other nodes. The impedance of this unique to be explored explicitly. In the following we will ap-
path is denoted by Z,(j)(S) and called node im- proximate the calculation of system poles by exploiting
pedance. Denote by Zk,j(s) the path impedance of the the property of a linear system, and further develop an
common portion of the paths p (k) and p (j). Suppose analytical closed-form solution.
node i is the branching point between p(k) and p (j). Let s~, k = 1, . . . , m, be the roots o f D ( s ) = O.
From the definition, Zk,j(s ) = Zp(i)(s ). We illustrate From the linear algebra we can calculate the determin-
the above notations and definitions in figure 3 with k ant of A by expanding it along the kth row
= 11, j = 6 and i = 3. We have path impedance
Zll,6(s ) : Z 1 q- Z 2 -~- Z3, Zp(2,8)(s ) : Z 3 -t- Z8,
D(s) = det A = 2.a ak,j Ak,j, (4)
Zp~6)(s) = Z1 + Z2 + Z3 + Z4 + Z5 + Z6, and node
j=l
impedance Zno1)(s) = Z23.
where Ak,j = ( - - 1 ) k + j det Ak,j and det Ak,j is the deter-
minant of an (m - 1) by (m - 1) matrix obtained by
3. Analytical Theory
deleting the kth row andjth column. Ak,j is the cofac-
Let the input at the root be f ( t ) , and its Laplace tor of a~,j. We now present a theorem.
transform be F(s). Let Laplace transform of vk be
Vk(s ). Suppose there are total m nodes in the tree. For THEOREM 1. There exists at least one pole s k such that
an arbitrary node k the voltage difference between k ak, k(Sk) ~ O.
and the input is the summation of voltage drops along
the path p(k) [13]. Accordingly, we have Proof Since Ak,k(S) describes a subcircuit obtained by
m
deleting node k from the original circuit described by
F(s) - Vk(s) = ~ Zk,j(s) vAs) matrix A(s), there exists at least one pole s k which
Zn~j)(s), K 1. . . . . m. distinguishes the two circuits when both circuits have
j=l
a tree topology. []
(1)

This gives a set of linear equations with Vk(s), k = From Theorem 1 we can define
1. . . . , m, as unknowns. We write equation (1) into
the matrix form Ak,j(Sk) (5)
Ok,j- Ak, k(Sk)"
Equation (4) becomes
a2,I a2,2 "'" a2,m V2 = F2 (2)

am,1 am,2 . . . ak, k Vm FIn

where ak,j = Zk,j(s)/Zn~j)(s), k ~ j , aj,j =

Zjj(s)/Zn~j)(s) + 1, and Fi = F, i = 1. . . . . m.
Denote D(s) = det A and Nk(s) = det A k, where Ak = 1 + ~_~ Okj Z.(j~(s~) A~,k(s~) = 0 (61
is the matrix obtained by substituting vector ffinto the j=l
 A Simplified Synthesis of Transmission Lines with a Tree Structure 23

The fact that Ak, k(Sk) V~ 0 implies that s k must be the Notice that pole Sk is obtained by separating a fac-
solution of tor from det A(s) by expanding det A(s) along its kth

1 + Ok,j
zkj(s) -- 0 (7)
row. Since the kth row ofA (s) actually represents the
relationship between node k and all the other nodes,
j=l Zn(j)(s) we can "consider," for convenience, sk as a pole
associated with node k though we know that a pole is
There might be several s~s depending on the order of
related to a system instead to a node. From equation
equation (7). Considering the arbitrariness of the choice
(6) it is clear that the factor (1 + ~=10k,j Zk,j(sk)/
of row k and repeating the same operation to all rows
Znfj)(Sk) ) separated from det A(s) contains all the
of A (s) we obtain
information of the relationship between node k and the

D(s) = f i
I 1 + ~-]Ok,j~)
zkj(s) ] • (8)
rest of the circuit, since the other factor Ak,k(Sk) does
not contain any element connecting node k and the rest
k=l j=l of the circuit. Therefore, the poles sk calculated by set-
We, introduce a new parameter 3"k defined as 1 ring this factor equal to zero (equation (10)) can be used
as the poles of a lower-order approximation. Namely,
Zk,j(sk) j=~ zk,j(s~)
I
we use the poles sk calculated from
"/,~= j~= l Ok,iZ,,(j)(sD Zn(j)(Sk)1 Z~j(sk)
(9) j=l Zn(j)(sk) -- O. (12)
Equation (7) becomes
to approximate the response at node k. Suppose the
3"k+ ~ Z~,j(sk) _ above equation has an order d(k) with respect to s, and
j=l Zn(J)(Sk) O, k 1, . . . , m. (10) Sk(1), Sk(2), . . . , Sk(d(k)) are its roots. We have the
following approximation for the voltage at node k
All system poles are then calculated from equation (10).
d(k)
In the rest of this paper we assume that f ( t ) is a step
function, z Writing pole sj in the form sj = - 0 9 + il3j Vk(t) = Vo - ~ Res (Vk(Sk(j)))e~#. (13)
j=l
and taking the reverse Laplace transformation we obtain
equations (12) and (13) are the approximations of equa-
Vk(t) = Vo - ~ R e s (Vk(sj))e(-C~j+i{3J)t, tions (10) and (11), and specify a lower-order system
j=l which is an approximation of the original one.
It remains to calculate the poles from equation (12)
k = 1, . . . , m, (11)
and the corresponding residues. This requires 3' be
where Res (Vk(Sj)) is the residue of Vk(s ) at pole sj. calculated first? From the definition of 3/(equations
(9) and (5)) its value can be calculated if the poles are
known. We hence face a chicken-aM-egg problem here.
4. A Closed-Form Approximation The purpose of introducing 3, is to simplify the calcula-
tion of poles. Thus, we shall first calculate poles with
The primary goal of this paper is to find a causal rela- 3' as a parameter. We then determine 3" by considering
tionship between circuit response, such as the waveform some special cases where the solutions of poles are
at a node, and the circuit parameters. A closed form known. Namely, by comparing our solution of poles
solution is hence preferred since it reveals the physical with 3' as a parameter to the known poles we can deter-
meanings of the solution. Such a closed-form solution mine the value of 3'.
is also critical to the performance-driven layout in high- The special case we use to determine 3" is shown
speed IC design as demonstrated later in Section 6. In in figure 4a, where a uniform transmission line is con-
the previous section we have found a general solution nected to a driver at x = 0 and to a capacitor at x =
(equations (10) and (11)) to a distributed RLC tree cir- l. This is a general interconnection model for CMOS
cuit. Unfortunately, numeric calculation has to be used circuits. Zhou, Preparata, and Kang studied the analytic
to determine those poles and the corresponding residues solution of this problem and further suggested to use
for any nontrivial problems. This to a certain extent a two-pole system to approximate the original one [4].
shades the physical meaning of the solution. For the considered transmission line let the resistance,
 24 Zhou, Su, Tsui, Gao and Cong

driver l~m receiver

1000p.m x = l ~ i~iii
(a) A singletransmissionline.

driver
:~iiiiiiiiiili~i~ L receiver
i!!!!!!!~l L 2 3 L4 ~ ~ ; ::.
ii!i{ii ....... c ................... " ~#iii
i~i~~i~ ~ :~!i!~!~i~
i!{~ i ~ { ~ s e gv ~ ~s t ~e ! mg segment
e ~m~ 2!en Tni ntsement3
~ il~ i ! i ~ ..........
:::~:~:.::~
~:~:~ e RLC-model.

8.0
(volt) Two-pole approximation to the distributed RLC-tree

Spice simulation
6.0

4.0 "/ Distributed RC-tree model

t
2.0
/ RLC-lumped model

i
0.0e-10 0.5e-10 I .Oe-10
(see)
(c) Numericalcalculationof the waveformin a singletransmissionline.
Fig. 4. A single transmissionline.
inductance and capacitance of unit length by R, L, and
LCI2--~ +LlCg 1 s 2
C, respectively. The driver has output imedpance R 0.
The load has impedance 1/sCg. The poles of their two-
pole system are determined by the following equation + RoCl + T + (R° + Rl) Cg s + Ym = O.
with the assumption that Cl ,> Cg.4
(15)
CLl 2 s a + (2RoCl + R C l 2 + ) s + = 0 Using the same assumption that Cl ~> Cg and compar-
(14)
ing equations (15) and (14) we find 3'm = 1.23. The
response at the receiving end is expressed by
In order to make comparison we apply our result
equation (12) to the single transmission line case. We uni- 2 eSl t + - -Sl
S.__~_ eS2t
V(t) = V0 - V0 $2- sl s 1 - s2
formly cut the line into rn segments and later let m ~ co.
The nodes are labeled as shown in figure 4b. We calcu- (16)
late the pole associated with node m locating at x = l. where Sl and s2 are the solutions of equation (15).
Since the line is uniformly cut, Zn(jl(S) = 1/sCj = m~ We calculate numerically the waveform of the cir-
sCl, Zmj(S) = Rmj + sLmj = (IR/m + s l L / m ) j , Zo(S) = cuit shown in figure 4a, and the result is shown in figure
R0 and Zn(m)(s ) = 1/sCg, where Cg is the gate capaci- 4c. A fair match is seen comparing our result to the
tance. For the discussed circuit equation (12) becomes simulation one. It is also seen that the distributed R C
 A Simplified Synthesis of Transmission Lines with a Tree Structure 25

model [13] and lumped RLC model [8] cannot well off-path impedance. Denote them by Zon(kd) and
model the discussed problem at the concerned fre- Zoff(k,j), respectively.
Figure 5 illustrates the above
quency range. definitions. Equation (12) can be written as

Y~ + ~ Zk,j(s_____~)+ ~ Z~,j(s) _ 0 (17)

5. Tree of Transmission Lines jEAp Zn(j)(S) jEAp Zn(j)(S)

For a tree structure, the response differs from node to where Ap and ,4p are respectively the sets of on- and
node. The response at a particular node can be calcu- off-path nodes as defined in Section 2. If set ,4p is
lated based on the poles associated with this node as empty (no off-path nodes) the above equation describes
discussed in Section 4. When calculating the response a single transmission line which we have discussed in
at a given node k the main difference between the single Section 4. The effect of branching points and off-path
line and the tree-of-transmission-lines is the existence nodes is reflected by the last summation Ej~2p
of off-path nodes in the later case. In the following we Zk,j(s)/Zn ~j)(s). Notice that this summation originates
still use equations (12) and (13) as a genera solution from charging capacitors at off-path nodes. The follow-
form and properly introduce a scale factor to reflect ing observations are useful for the construction of the
the influence of the off-path nodes. scale factor (figure 5).
Let us consider the response at an arbitrary node 1. The off-path impedance is zero. The off-path capac-
k. Suppose nodej is an off-path node and the branching itors can be treated as the lumped capacitors at the
point between p(k) and p ( j ) is node i. The path im- corresponding branching node. This case can be
pedance Zp(j) consists of two portions: Zp(i) and Zp(i,j) , considered as a single transmission line. Equiva-
respectively. Call Zp (i) on-path impedance, and Zp(i,j) lently, the scale factor should be one unit in this case.

R3 L3 R4 L4 nodej

L2
Pc
R1 L1
node i
L5
R5 R6 L6 R7 L7 node k

off-path impedance = (R2+R3+R4) + (L2+L3+L4)s

off-path i m p e d a n ~ h impedance = oo

R1 LI R1 L1
node i
roo-'r¢ ,c2F node
oj r ~ node i

R5- L6 _ r. [1 R 5 R 6 L 6 R7 L7node k

Fig. 5, The effect of charging off-path node capacitors.

26 Zhou, Su, Tsui, Gao and Cong

2. The off-path impedance is of infinity. There is actu- is a distributed RLC tree, figure 6 compares the result
ally no need to consider charging the off-path node by the two-pole approximation with that by spice
capacitors. The summation term over the off-path simulation for the routing tree in figure 1. Tree edges
nodes should be scaled to zero. That is, the scale are cut into small wire segments of 10/zm long and
factor should be zero. each of them is then modeled by an RLC circuit as
3. Neither of the above two cases is true. That is, the described before. We calculate the voltage response at
off-path impedance has a finite value. The scale fac- node 11. It is seen that the two-pole approximation well
tor takes the value between 0 and 1. captures the main property of the distributed RLC cir-
cuit. Although the accuracy achieved by the two-pole
We introduce a scale factor 1/(1 + Zoff(k,j)) : j ~ iip.
approximation is inferior to the standard of circuit
We modify equation (17) by 5
simulation, it is sufficient to guide the performance-
1.23 + ~ Zk,j(s) driven layout. As has been shown in [9, 14] that an
jEA Zj(S) average up to 67 % reduction on the interconnection
delay can be obtained based on the presented two-pole
1 Zk,j(s) approximation, as compared to the traditional lumped
+ Z 1 + Zoff(k,j)(s ) Zj(s) - 0 (18) RC model.
j~,i
Therefore, the bigger the Zoff(k,j) the smaller the effect
6. Waveform, Delay, and Design Example
of charging off-path node j. The introduced scale fac-
tor satisfies the requirement at the two extreme situa- In this section we examine the waveform and delay of
tions: either the off-path impedance is zero or inifinite. an interconnection circuit, and then apply the obtained
Equation (18) and (13) are the approximations for the result to an IC design problem. The waveform is im-
tree-of-transmission-lines. Actually, we can conser- portant here because, different from the overdamping
vatively choose the scale factor to be one unit, which case, oscillations exist in the interconnection circuit as
leads to an upper bound on the delay estimation since demonstrated in figure 6. Therefore, to properly define
all off-path capacitors are to be charged regardless of the delay of interconnections is not a trivial problem.
the value of off-path impedance. Choosing the scale fac- Actually, it is a rather difficult problem.
tor as one unit we can merge equations (18) and (12) One of the traditional definitions of delay is defined
and, equivalently, we are no longer to distinguish the as the time period r in which the node voltage vk(t)
case of a single line from that of a tree-of-transmission- stably reaches a given value or high. One choice of this
lines. given value usually is 0.9 V0, where V0 is the final
To demonstrate the effectiveness of the two-pole value of Vk(OO).6 The stable here means vk(t) >- 0.9
approximation for the case where the original circuit V0 as t >_ r. This definition of delay is popular when

8.0
(volt)
Spicesimulation
6.0 f -po~approxi-_,
mation_
4.5 ......
4.0

2.0

0.0 7ps ' 28ps 5e-~11 le-10

(see)
Fig. 6. The effectiveness of two-pole approximation.
 A Simplified Synthesis of Transmission Lines with a Tree Structure 27

the response is over- or critically-damped. It is not clear mentation which provides the minimal delay under the
whether this definition is still a good one when there lumped RC model. However, using the distributed RLC
exists oscillation. In figure 6 we see r = 27 ps by this model and the two-pole approximation established in
definition. However, the loading gate at node k (= 11) the previous section we can construct an A-tree (tree2)
may have been permanently turned on at the time vk(t) which gives a shorter delay and smaller overshooting
first time reaches 0.9 V0 (t = 7 ps). Notice that dif- than that the minimum Steiner tree dose, as demon-
ferent gates may have different threshold voltage and strated in figure 8 [9]. In other words, tree2 provides
different circuits may have different gate turn-on and a better performance as compared with treel. The
turn-off design margin. It is clear that the definition reason that we are able to construct a better intercon-
of delay depends on the specific application and the nection topology is the availability of a closed-form
technology. solution equation 15 based on the second-order approx-
We now discuss a design example. We construct two imation [10, 11]. In contrast, a numercial simulator
different trees to implement the same net in figure 1. can usually provide the information for a proper choice
The constructed trees are shown in figure 7, where treel of interconnection parameters, such as wire size, but
is a minimum Steiner tree and tree2 is an A-tree [14]. hardly provide any information for the choice of the
Traditionally, treel is considered as the optimal imple- interconnection topology.

12,
- ~ Cgi
4
3
_.L. Cg2
driver
....~:~:~ilili~i~iiiili%~:ili!i!iiii:i#~~!i
,i ii~,~:
i
iJiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiNi
iNiiiiiii 1
treel

iiNg
8 -~- tSg4

9 e'-A._ Cg5
11__~--~ "~
T Cg6

12 ~ Cgl
4
5~Cg2
~'6--t- Cg3
8 7 ~- tree2
~ " Cg4

9 .A_
-~7 Cg5

cg6

Fig. 7. Two differenttrees to implementthe same net N in figure 1.

28 Zhou, Su, Tsui, Gao and Cong

r Two-pole approximation to tree2

6.0 - apic ~mximationto tree1

4.5
4.0

Difference in delay at V(t)=0.9Vo (Vo=5v)

2.0

i
0.0 5e-~11 le-10
(sec)

Fig. 8. Waveforms at node 11 of treel and tree2.

Note that treel is a minimum Steiner tree, but has . The definition of delay in a distributed RLC circuit
very long tree radius. Tree2 has a slightly longer total (or a tree-of-transmission-lines) is not clear, espe-
wire length, but much smaller tree radius. It was claimed cially when the transmission line is poorly termin-
in [15] tha.: a routing tree with small wire length and ated. As mentioned in the paper this issue is tech-
small rad! is the best in terms of circuit delay. Our nology dependent. However, a more objective mea-
work confirms their claim theoretically and experiment- sure on the signal delay needs to be addressed.
ally. An lent algorithm to construct a routing tree . Our result on the lower-order circuit approximation
with be tll radius and small wire length is given to a distributed RLC tree can be easily incorporated
in [15, urthermore, a minimal delay tree can be into VLSI layout tools since the result is in an analyt-
construc~ based on the analytical solution obtained ical closed form. The result not only provides a
in this p, [10, 11]. means for the performance evaluation of high-speed
interconnections, but also establishes the relationship
between the circuit response, such as delay, and the
7. Discus~ on and Conclusion interconnection topologies. Recent study has shown
that the interconnections constructed based on our
We have analyzed the distributed RCL tree circuit and two-pole approximation model preserve a highfidel-
extended the obtained results to the calculation of the ity to the optimal interconnection performance [11].
tree-of-transmission-lines. A lower order circuit approx-
imation has been established for developing the closed-
Acknowledgments
form solution. The numerical calculation has shown
the validity of the approximation. The obtained results
This research was supported in part by NSF under
have been applied to the design of IC layouts. We make
grants MIP-9110450 and MIP-9110511.
the following comments on the discussed problem for
the future research.
1. When studying the RLC system a one-pole circuit Notes
approximation will not be sufficient since it cannot
1. Notice that s k is the solution of equation (7).
model the wave phenomenon. The wave phenomenon 2. The case of an arbitrary driving functionf(t) can be discussed
is esser_dal in the transmission line analysis. Hence, similarly.
the approximation circuit should be at least of order 3. When context is clear we will omit the subscript of 3'.
2. Our lower order circuit approximation can be con- 4. This assumption can be satisfied in most practical interconnec-
tion design problems.
sidered as an extension of the result of Rubinstein
5. We suppose that 3, keeps the value determined from the single
et al. where they studied an RC tree [13]. In fact, line case.
by setting inductance equal to zero our result equa- 6. Recall that we have assumed that a step input is applied at the
tion (12) will reduce to their result. root of the tree.
 A S i m p l i f i e d S y n t h e s i s o f T r a n s m i s s i o n L i n e s w i t h a Tree S t r u c t u r e 29

References with the Applied Computation Theory Group at the Coordinated

Science Laboratory, the University of Illinois. He is currently an assis-
1. T.C. Edwards, Foundations for Microstrip Circuit Design, tant professor with the department of electrical engineering, University
Wiley: New York, 1984. of North Carolina at Charlotte. Dr. Zhou is a member of Tau Beta
2. B.J. Rubin, ' ~ n Electromagnetic Approach for Modeling High- Pi. He received the National Science Foundation Research Initia-
Performance Computer Package" IBM J. Res. Dev., Vol. 34, tion Award in 1991. He received the IEEE Circuit and System Society
pp. 585-599, 1990. 1993 Darlington Award. He served as a guest editor for International
3. L.V. Blake. Transmission Lines and Waveguides, Wiley: New Journal of Custom-Chip Design, Simulation and Testing.
York, 1969.
4. D. Zhou, EP. Preparata, and S.M. Kang, "Interconnection Delay
in Very High-Speed VLSI," IEEE Trans. Circuits Systems, Vol.
38, pp. 779-790, 1991.
5. L.W. Nagel, "Spice2, A Computer Program to Simulate Semicon-
ductor Circuits" Tech. Rep. ERL-M520, Univ. Calif. at Berkeley,
1975.
6. D.S. Gao, A.T. Yang, and S.M. Kang, "Modeling and Simulation
of Interconnection Delays and Crosstalks in High-Speed Integrated
Circuits" IEEE Trans. Circuits Systems, Vol. 37, pp. 1-10, 1990.
7. W.M. Dai, "Performance Driven Layout of Thin-Film Substrates
for Multichip Modules," in Proc. ISCAS'91, Vol. 4, pp. 2308-
2311, 1991.
8. H.B. Bakoglu, Circuits, Interconnections and Packagingfor FLSI,
Addison-Wesley, pp. 81-133, 1990. Shyang-lhi Su received his B.S. degree in electronics engineering
9. D. Zhou, E Tsui, D.S. Gao, and J.S. Cong, ' ~ Distributed-RLC from Tamkang University in 1982, his M.S. degree in electrical
Model for MCM Layout," Proc. IEEE Multichip Model Conf. engineering from the University of North Carolina at Charlotte in
pp. 191-197, 1993. 1989, and a Ph.D. in computer engineering from North Carolina
10. D. Zhou, E Tsui, and D.S. Gao, "High Performance Multichip State University in 1993. He is currently a research and teaching
Interconnection Design," Proc. 4th ACM/SIGDA VLSI Physical associate at the University of North Carolina at Charlotte. His research
Design Workshop, pp. 32-43, 1993. interests include design for testability, fault modeling, supply cur-
11. K.D. Boses, A.B. Kahng, M.A. McCoy, andG. Robins, "Toward rent testing, and VLSI CAD design.
Optimal Routing Trees," Proc. 4th ACM/SIGDA VLSI Physical
Design Workshop, pp. 44-51, 1993.
12. L.T. PillageandR.A. Rohrer, '~a.symptotieWaveformEvaluation
for Timing Analysis," IEEE Trans. CAD, Vol. 9, pp. 352-366,
1990.
13. J. Rubinstein, E Penfield, and N.A. Horowitz, "Signal Delay
in rc Tree Networks," IEEE Trans. CAD, Vol. CAD-2, No. 3,
pp. 202-211, 1983.
14. J.S. Cong, K.S. Leung, and D. Zhou, "Performance-Driven In-
terconnect Design Based on Distrihuted-RC Delay Model," Proc.
30th ACM/IEEE Design Automation Conf., 1993.
15. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, and C.K. Wang,
"Probably Good Performance-Driven Global Routing, IEEE Trans.
Computer-Aided Design, Vol. 11, No. 6, pp. 739-752, 1992.
16. K.D. Boses, J. Cong, K.S. Leung, and D. Zhou, "On High-Speed Fong Tsui received the B.S. degree in electronics engineering from
VLSI Interconnects: Analysis and Design," 1EEE Asia-Pacific Northwestern Polytechnical University, China, in 1987, and the M.S.
Conf. Circuits and Systems, 1993. degree in electrical engineering from the University of North Carofina
at Charlotte. She is currently employed by Cascade Design Automa-
tion Corporation, working on VLSI physical design. Her research
interests include VLSI design and CAD system and tools.

Dian Zhou received the B.S. degree in physics and the M.S. degree
in e!ectrical engineering from the Fudan University, Shanghai, China,
in 1982 and 1985, respectively, and the Ph.D. degree in electrical
and computer engineering from the University of Illinois at Urbana-
Champaign, Illinois in 1990. His research interests include VLSI David S. Gao received the B.S. degree from Rutgers University in
design, CAD systems and tools, circuit design and simulation, 1983, and the M.S. and Ph.D. degrees from University of Illinois
algorithms, and multichip model systems. He was a research assistant at Urbana-Champaign, in 1986 and 1990, all in electrical engineering.
30 Zhou, Su, Tsui, Gao and Cong

From 1983 to 1984, he was a design engineer at IBM, participated degrees in computer science from the University of Blinois at Urbana-
in logic design for mainframe computers. Currently, he is on the Champaign in 1987 and 1990, respectively. Currently, Dr. Cong is
technical staff at Sun Microsystem Inc., working on the CAD and an assistant professor in the Computer Science Departlnent of the
MCM design. His research interests include interconnection and University of California, Los Angeles. From 1986 to 1990, he was
packaging technology, device modeling and simulation, and optoelec- a research assistant in the Computer Science Department of the
tronic integrated circuits. David S. Gao is a member of IEEE, Tau University of Illinois. He worked at the Xerox Palo Alto Research
Beta Pi, and Eta Kappa Nu. Center in the summer of 1987. He worked at the National Semicon-
ductor Corporation in the summer of 1988. His research interests
include computer-aided design of VLSI circuits, fault-tolerant design
of VLSI systems, and design and analysis of efficient combinatorial
and goemetric algorithms. He has published over 40 research papers
in these fields. Dr. Cong received the Best Graduate Award from
Peking University in 1985. He was awarded a DEC Computer Science
Fellowship in 1988. He received the Ross J. Martin Award for Ex-
cellence in Research from the University of Illinois at Urbana-
Champaign in 1989. He received the National Science Foundation
Research Initiation Award in 1991, and the National Science Founda-
tion Young Investigator Award in 1993. Dr. Cong has served on the
program committees of several VLSI CAD conferences, including
Jason (Jingsheng) Cong received his B.S. degree in computer science ICCAD and MCMC. He was the chairman of the 4th ACM/SIGDA
from Peking University in 1985. He received his M.S. and Ph.D. Physical Design Workshop.