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5468.amba Axi Ahb Apb

This quick reference card summarizes key encoding details for the AMBA AXI, AHB, and APB bus protocols. It provides a side-by-side comparison of the transaction ID encoding, burst type encoding, cache attributes, response codes, and other signals for the different bus standards.

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Lohith Coreel
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0% found this document useful (0 votes)
195 views2 pages

5468.amba Axi Ahb Apb

This quick reference card summarizes key encoding details for the AMBA AXI, AHB, and APB bus protocols. It provides a side-by-side comparison of the transaction ID encoding, burst type encoding, cache attributes, response codes, and other signals for the different bus standards.

Uploaded by

Lohith Coreel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AMBA - AXI - Quick reference card by Matt Hutson ARCACHE[3:0] AWCACHE[3:0] Memory type

0000 0000 Device Non-bufferable

AMBA, AXI is ™ © of ARM® 0001 0001 Device Bufferable


0010 0010 Normal Non-cacheable Non-bufferable
0011 0011 Normal Non-cacheable Bufferable
1010 0110 Write-through No-allocate
xRESP[1:0] Response Encoding
1110 (0110) 0110 Write-through Read-allocate
0b00 OKAY
1010 1110 (1010) Write-through Write-allocate
0b01 EXOKAY
1110 1110 Write-through Read and Write-allocate
0b10 SLVERR
AxBURST[1:0] Burst type encoding 1011 0111 Write-back No-allocate
0b11 DECERR
0b00 FIXED 1111 (0111) 0111 Write-back Read-allocate
0b01 INCR 1011 1111 (1011) Write-back Write-allocate
0b10 WRAP 1111 1111 Write-back Read and Write-allocate
Transaction ID AXI3 AXI4 0b11 Reserved Memory type encoding - AXI3 legal in ()
Write streams AWID,WID,BID AWID,BID
Read streams ARID,RID ARID,RID AxSIZE[2:0] Bytes in beat
AxCACHE - Transaction attribute (0=Non|No)
0b000 1
AxPROT[2:0] Protection access type encoding Bit# AXI3 AXI4
0b001 2
Bit# 0 1 [0] Bufferable Bufferable
0b010 4
[0] Unprivileged Privileged [1] Cacheable Modifiable
0b011 8
[1] Secure Non-secure [2] Read-allocate W=Other Allocate R=Allocate
0b100 16
[2] Data Instruction [3] Write-allocate W=Allocate R=Other Allocate
0b101 32
Modifiable parameters:
AxLOCK AXI3 [1:0] AXI4 0b110 64 [AxADDR,AxREGION,AxSize,AxLEN,AxBURST,AxLOCK,AxPROT]
Normal 0b00 0b0 0b111 128
Burst size encoding (2^value) – AxCACHE Ordering requirements
Exclusive 0b01 0b1
Bytes in each beat of transfer
Locked 0b10 0b0 (AXI3 mapping to AXI4) Memory type Same ID Overlapping address Ordering required
Reserved 0b11 - AxLEN AXI3 AXI4 Yes X Yes
Access type encoding Burst_Length AxLEN[3:0] + 1 AxLEN[7:0] + 1 Yes Yes
Wrapping bursts, the burst length must be 2, 4, 8, or 16 Device No No No
AXI4 extras AxREGION,AxQOS,AxUSER A burst must not cross a 4KB address boundary Yes Yes
WUSER not supported by NoC AXI4 INCR burst is extended only, all others 1 to 16. Normal X No No
AMBA - AHB APB - Quick reference card by Matt Hutson
HTRANS[1:0] transfer type encoding
AHB
0b00 IDLE
AMBA, AHB, APB is ™ © of ARM® 0b01 BUSY
0b10 NONSEQ
0b11 SEQ
AXI4 lite
HBURST[2:0] Burst encoding
Unsupported signals 0b000 SINGLE Single transfer
Dec (d) Hex (x) Bin (b) Dec (d) Hex (x) Bin (b) 0b001 INCR Incrementing burst of unspecified length
AxLEN 0
0 0 0000 8 8 1000 0b010 WRAP4 4-beat Wrapping
1 1 0001 9 9 1001 AxSIZE access data width 32 or 64bit
0b011 INCR4 4-beat Incrementing
2 2 0010 10 A 1010 AxBURST no meaning as LEN is 0.
0b100 WRAP8 8-beat Wrapping
3 3 0011 11 B 1011 AxLOCK 0 Normal. 0b101 INCR8 8-beat Incrementing
4 4 0100 12 C 1100 AxCACHE 0b0000 Non-modifiable/bufferable. 0b110 WRAP16 16-beat Wrapping
5 5 0101 13 D 1101 0b111 INCR16 16-beat Incrementing
xLAST 1 LEN is 0.
6 6 0110 14 E 1110
xxID Optional support only HSIZE[2:0] bits Bytes Name
7 7 0111 15 F 1111
xRESP value EXOKAY unsupported only 0b000 8 1 Byte
0b001 16 2 Halfword
Value Log2 Hex mask Value Log2 Hex mask 0b010 32 4 Word
2 1 0001 128K 17 0001_FFFF 0b011 64 8-
4 2 0003 256K 18 0003_FFFF 0b100 128 16 4-word line
8 3 0007
APB 0b101 256 32 8-word line
512K 19 0007_FFFF
16 4 000F 1M 20 000F_FFFF Transfer control 0b110 512 64 -
32 5 001F 2M 21 001F_FFFF PSEL & PENABLE (& APB3 PREADY) 0b111 1024 128 -
64 6 003F 4M 22 003F_FFFF Transfer Size encoding
APB3 Extras
128 7 007F 8M 23 007F_FFFF
PREADY A ready signal to indicate completion of an APB transfer. HPROT[3:0]
256 8 00FF 16M 24 00FF_FFFF Bit# 0 1
PSLVERR An error signal to indicate the failure of a transfer.
512 9 01FF 32M 25 01FF_FFFF [0] Opcode fetch Data
1K 10 03FF 64M 26 03FF_FFFF APB4 Extras
[1] User access Privileged
2K 11 07FF 128M 27 07FF_FFFF PPROT[3:0] Protection encoding
[2] Not buffereable Bufferable
4K 12 0FFF 256M 28 0FFF_FFFF Bit# 0 1
[3] Not cacheable Cacheable
8K 13 1FFF 512M 29 1FFF_FFFF [0] Normal Privileged HRESP[1:0] Response Encoding
Protection encoding
[1] Secure Non-secure 0b00 OKAY
16K 14 3FFF 1G 30 3FFF_FFFF
0b01 ERROR
32K 15 7FFF 2G 31 7FFF_FFFF [2] Data Instruction
0b10 RETRY
64K 16 FFFF 4G 32 FFFF_FFFF PSTRB[n:0] Write strobe. Indicates which data byte is active. 0b11 SPLIT

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