Three Stages CMOS OpAmp: Design Methodology

Based on gm/ID
Heng Liu, Student Member, IEEE
Shanghai Jiao Tong University, Center of Analog/RF Integrated Circuit (CARFIC), Shanghai, China
E-mail: [email protected]

Abstract—This is the design report for a three-stage reversed 1:1

M6 M5 M8
nested Miller compensated OpAmp (RNMCFNR), using the I1 I2
M11 M12

gm/Id method. The amplifier is designed for 0.18µm technology.

The transfer function is derived from AICE tool, and the circuit Vin-
M1 M2
Vin+
Cc1
I3
Vout

is simulated using Cadence Virtuoso and Spectre design tools. In gm1

Cc2 CL

this design, high gain and low power consumption are priorities. Ibias
Rc

The result shows that the DC gain of the OpAmp is 109.8 dB, M3 M4 gm2 gm3 gmf

the GBW is 2.66 MHz, the phase margin is 79 degree, the slew M7
M9
M10

rate 2.4/-2.17 V /µs when driving a 500 pF load capacitance.

Furthermore, the input referred noise voltage is 2.43 f V 2 /Hz,
Fig. 2. Three-stage OpAmp circuit cell
the CMRR is 78.5 dB, the PSRR is 76 dB, and the total power
consumption is 147 µW . The reference paper is [1].
Keywords—Three-stage OpAmp, Reversed Nested Miller Com-
pensation, CMOS, gm/Id. that the Rc in compensation network should be selected as
a miller compensation resistor in AICE tool to generate the
I. I NTRODUCTION right result.
The specified circuit is shown in Figure 1 and Figure 2. The clean form transfer function is
Generally, it is called reversed nested Miller compensated Vout 1 + sb1 + s2 b2
OpAmp (RNMCFNR), which is different from the traditional = Ao , (1)
Vin (1 + ωsp1 )(1 + sa1 + s2 a2 )
NMC in that the inner compensation capacitance is not tied
to output stage, therefore, providing inherent high GBW and where
low power consumption. In this report the detailed analysis and gmf 1
b1 = (CC1 + CC2 )RC + ( − )CC2 , (2)
design procedure will be presented for the specs as follows: gm2 gm3 gm2
• DC gain Av ≥ 100 dB; (gmf + gm2 )RC − 1
• GBW ≥ 2.4 MHz;
b2 = CC1 CC2 , (3)
gm2 gm3
• Load capacitance CL = 500 pF ;
(gm2 + gmf − gm3 )CC1 + gm2 CL
• Phase margin ≥ 60 degree; a1 = CC2 , (4)
• Slew rate ≥ 1.8 V /µs;
gm2 gm3 CC1
• Power supply VDD = 1.8V ; CC2 CL
a2 = . (5)
gm2 gm3
To handle a high order transfer function, the most straight-
Cc1
forward idea is to eliminate some terms, or let some poles and
Cc2
zeros to be equal, so that to implement pole-zero cancellation.
Rc
In this circuit, let
-Gm1 -Gm2 +Gm3
1
Vin R1 R2 RC = , (6)
R3 CL Vmeter gm2 + gmf
and
gmf = gm3 (7)
-Gmf

to get the simplified transfer function as

Fig. 1. Three-stage OpAmp block
Vout 1 + s Cgm2
C1 +CC2
+gm3
= Ao . (8)
Vin (1 + s
ωp1 )(1 + s Cgm3
C1 +CL 2 CC2 CL
CC1 CC2 + s gm2 gm3 )
II. T RANSFER F UNCTION A NALYSIS From Equation 8, it’s easy to obtain that
In this section, the transfer function is derived using AICE (gm /ID )1 (gm /ID )7 (gm /ID )9
tool and verified by comparing with the referred paper. Notice Ao = − , (9)
λ1 + λ3 λ7 + λ8 λ9 + λ12
 1
ωp1 = , (10) IV. D ESIGN P ROCEDURE
ro1 gm2 ro2 gm3 ro3 CC1
gm1 In this section, the calculation procedure using gm /ID
ωGBW = . (11) lookup table are presented step by step for the parameter
CC1
determination.
Furthermore, the ButterWorth response which guarantees
the most flat response within bandwidth is preferred to manage A. Step 1: Channel length Selection
the two higher order poles. That is, First of all, the channel length is determined based on DC
1 gain
ξ=√ , (12)
2
√ (gm /ID )1 (gm /ID )7 (gm /ID )9
ωn = 2 2ωGBW . (13) Ao = − ≥ 100000. (25)
λ1 + λ3 λ7 + λ8 λ9 + λ12
Namely, It’s no need to deliberately set each stage has different gain,
a1 2 instead for the very beginning, assuming the gain of every
a2 = , (14)
2 stage is equal is preferred for the first shot.
ωp2 = 2ωGBW , (15)
(gm /ID )max 25
λP + λN ≤ √ = ≈ 0.54. (26)
ωp3 = 4ωGBW . (16) 3
100000 46.5
For simplicity, let gm2 = gm3 , then Based on Figure 3, the channel length is chosen to be 0.5µm
2
2gm3 CC1 CL 2
2CC1 for sake of redundance.
CC2 = ≈ , (17)
gm2 (CC1 + CL )2 CL
0.6
gm3 CC1 gm3 gm1
ωp2 = ≈ =2 , (18) 0.18um
0.35um
(CC1 + CL )CC2 2CC1 CC1 0.5 0.5um

gm2 (CC1 + CL ) gm2 gm1

ωp3 = ≈ =4 . (19) 0.4
CC1 CL CC1 CC1 lambda [1]

Finally, the transconductance of each stage is determined 0.3

gmf = gm2 = gm3 = 4gm1 . (20)

0.2

III. P HASE M ARGIN A NALYSIS

0.1
In this section, the phase margin is calculated based on the
condition listed above. 0
First of all, the phase shift of the system at the frequency 0 5 10 15
gm/Id [mS/mA]
20 25 30

of GBW is
1 + jωb1 + (jω)2 b2
Φ= |ω=GBW Fig. 3. λ vs gm /ID
(1 + ωsp1 )(1 + jωa1 + (jω)2 a2 )
b1 ωGBW a1 ωGBW
= arctan( ) − arctan( ) (21)
1 − b2 ωGBW
2 1 − a2 ωGBW
2 B. Step2: Design for GBW or SR
ωGBW
− arctan( ). As a consequence of the output stage being pesudo-class-
ωp1 AB, the slew rate is mainly restricted by the current flowing
Since ωp1 ≪ ωGBW , and through the first branch
1 I1
arctan x + arctan( ) = π, (22) SR = . (27)
x CC1 + CC2
x+y
arctan x + arctan y = arctan , (23) so the value of (gm /ID )1 is determined by the given specs
1 − xy
SR I1 /CC1 1
then ≈ = 2π × 2 × , (28)
P M =180o − Φ GBW gm1 /(2πCC1 ) (gm /ID )1
b1 ωGBW 1 − a2 ωGBW
2 GBW (M Hz) 2.4
= arctan( ) + arctan( ) (gm /ID )1 = 4π · = 4π × = 16.76, (29)
1 − b2 ωGBW 2 a1 ωGBW SR(V /µs) 1.8
2 ggm2 [( ggm2 )2 − 1)] which means the overdirve voltage of M1 is approximately
= arctan{ m1 gm2m12 } 120mV, and the circuit is restricted by speed.
3( gm1 ) + 2
12 In this design, the author choose (gm /ID )1 = 13 for all
= arctan( ) = 67o . transistors to enhance SR and speed of the circuit, which also
5
(24) takes matching into consideration.
 2 2
C. Step3: Current Distribution 2gm3 CC1 CL 2CC1 (4pF )2
CC2 = ≈ = 2 = 64f F.
gm2 (CC1 + CL )2 CL 500pF
The total static current is determined by power consumption. (34)
From the analysis above, And they are summarized in Table II.
gmf = gm2 = gm3 = 4gm1 , (30) TABLE II
PARAMETER S UMMARY
and the gm /ID is equal for all transistors, it’s obvious that
Comp. RC Cc1 Cc2
I2 = I3 = 2I1 (31)
Value 2KΩ 4pF 64fF
in Figure 2.
In this design, the author set I1 = 5µA to restrain the total F. Step6: Slew Rate Check
static current within 80µA.
Finally, the SR should be checked if all the requirements
D. Step4: Sizing met. Otherwise, the design need iteration.
I1 10uA
Based on the normalized current curve shown in Figure 4 SR = ≈ ≈ 2.5V /µS. (35)
with gm , with ID , the size of all transistor could be calculated CC1 + CC2 4pF
using Matlab with few lines of code. V. T ESTBENCH AND S IMULATION R ESULTS
A. Open Loop
150
Figure 5 shows the open loop test bench, where a LPF (R =
1T Ω, C = 1F ) is employed to define the output common
mode voltage, while the influence of high frequency is filtered.
100
Figure 6 illustrates that the DC gain equals 109.8 dB, GBW
is 2.66 MHz, and the phase margin is 79 degree to guarantee
Id/(W/L) [uA]

stability.

50

0
0 5 10 15 20 25 30
gm/Id [mS/mA]

Fig. 4. λ vs gm /ID

The parameters are summarized in Table I.

Fig. 5. Open Loop Test bench

TABLE I
PARAMETER S UMMARY

Transistor gm /ID [mS/mA] Size Current[µA] gm [µS]

M1/M2 13 5.3u/0.5u 5 65
M3/M4 13 1.4u/0.5u 5 65
M5/M6 13 10.6u/0.5u 10 130
M7 13 5.4u/0.5u 20 260
M8 13 21u/0.5u 20 260
M9/M10 13 5.4u/0.5u 20 260
M11/M12 13 21u/0.5u 20 260

E. Step5: Compensation Network Calculation

After determining the transconductance of all the transistors,
the compensation capacitors are easy to calculate.
1 1
RC = = ≈ 2KΩ, (32) Fig. 6. Open Loop Results
gm2 + gmf 260 + 260
gm1 65uS Figure 7 shows the static current, which accounts for the
Cc1 = = ≈ 4pF, (33) power consumption of 147 µW .
ωGBW 2.4M Hz × 2π
 Fig. 7. Power Consumption

Fig. 10. Settling Time

B. Slew Rate
It’s shown in Figure 8 that when measuring slew rate, a
large pulse should be imposed at the input, and Figure 9 What’s more, Figure 12 shows that the PSRR+ and PSRR-
demonstrates that the slew rate is 2.4/-2.17 V /µs. Settling are calculated individually when small signal is imposed at
time at 1% is 618 ns as illustrated in Figure 10. VDD or GND.

Fig. 8. Slew Rate Testbench

Fig. 11. CMRR Test bench

Fig. 9. Slew Rate

C. CMRR and PSRR

Figure 11 provides a method to in one test bench without
simulating ADM and ACM −DM separately. Fig. 12. PSRR Test bench

ACM vCM + Av [vCM − (vOU T − vCM )] = vOU T , (36)

vOU T ACM 1 Figure 13 and Figure 14 show that CMRR is 78.5 dB,
≈ = . (37) PSRR+ is 76.15 dB, and PSRR- equals 75.3 dB.
vCM Av CM RR
 TABLE III
P ERFORMANCE S UMMARY

[1] This Work

Technology 0.5 um 0.18 um
Power Supply 3V 1.8 V
Loading Capacitance 500 pF 500 pF
DC Gain 109 dB 109.8 dB
GBW 2.4 MHz 2.66 MHz
PM 58 degree 79 degree
SR 1.8/-1.8 V/us 2.4/-2.17 V/us
CMRR 79 dB 78.5 dB
PSRR 75 dB 76 dB
Settling Time @ 1% 740 ns 618 ns

Fig. 13. CMRR Result

ACKNOWLEDGMENT
The authors would like to thank Prof. Shi and all the
classmates in CARFIC.
R EFERENCES
[1] A. D. Grasso, G. Palumbo, and S. Pennisi, “Advances in reversed nested
miller compensation,” IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 54, no. 7, pp. 1459–1470, 2007.

Fig. 14. PSRR Result

D. Noise
Figure 15 shows that the IRN is 2.4 f V 2 /Hz@1M Hz.

Fig. 15. IRN Result

VI. C ONCLUSION
In this design, gm/Id method together with transfer function
analysis demonstrate them useful tools in analog design.
And the performance of the three-stage OpAmp is summa-
rized in Table. III.