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synthesis in pd design

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Synthesis Interview Questions. - Technology@Tdzire

synthesis in pd design

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srajece
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© © All Rights Reserved
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5/11/2020 Synthesis Interview Questions.

- Technology@Tdzire

Technology@Tdzire

SYNTHESIS, TECHNOLOGY

SYNTHESIS INTERVIEW
QUESTIONS.
MARCH 16, 2013 | GAYATHRI | 9 COMMENTS

Here I have enumerated Interview Questions for Synthesis. The answers


of most of these are there in my earlier Synthesis Technology posts.
Answers to some are given along with the questions itself. The
tool referenced here is Design Compiler.

1. What are the different steps in Synthesis ?


2. What are the inputs required to start synthesis ?

Ans : RTL les which has the source code, .libs for the hard macros, standard
cell libraries. Constraints are required to ne tune the synthesis.

tech.tdzire.com/synthesis-interview-questions/ 1/6
3. If you are given an RTL tag which is not getting linked properly, what
workarounds have you done ?

Ans : If designer is around, sit with him/her to get it corrected. If not, hack the
RTL, x the syntax mistakes, to get it linked. Even unsynthesisable code can
be present in the RTL, which gives Error in the Elaborate stage. Whatever
changes we make in the RTL should be informed and get it con rmed from the
Designer.

4) Can you keep proceeding if LINT Errors are present ?

Ans : LINT Errors needs attention and LINT with small numbers have higher
priority. It needs x from the designer. But for the time being, to keep going
with synthesis, to generate a netlist these can be suppressed.

5) How can you detect whether transparent latch is inferred while


elaboration ?

Ans : We can turn on the variable “hdlin_check_no_latch”, so that Design


Compiler issues a warning message, if transparent latches are inferred.

6) Which command do you use to get it compiled ?

Ans : compile_ultra

7) What are the requisites for compile stage ?

Ans : Fully elaborated database is the minimum requirement. Additional


information for compile are the constraints. Initial compile can be done
without constraints, if they are not ready. But this will take huge runtime.

8) What are constraints ?

9) What are the different constraints needed for Synthesis ?


Ans : Timing optimisation constraints — clock constraints which includes
create_clocks, create_generated_clocks, virtual_clocks, and exceptions which
includes multicycle_paths, case_analysis, false_paths. Input/Output
constraints like set_input_delay, set_output_delay are also required. If delay
constraints need to be speci ed, the set_max_delay, set_min_delay also should
be used. Optimisation constraints for area and power also should be speci ed
if needed.

Design Rule Constraints — This includes max_transition for the design,


input_transition and driving cell for the inputs, load/capacitance for
the outputs.

10) Which design rule constraint will be given the maximum priority by
Design Compiler ?

Ans : max_transition

11) What are the different steps to optimise a timing path ?

12) How is path groups used in Design Compiler ?

13) If you have a violating path after synthesis, how to optimise it ?

Ans : Group that path with -from -to option and give weightage value and do
an incremental compile.

14) Explain the steps for inserting clock gating in your design?

15) Once Compile is done with, what are the different reports which you
browse through ?

16) What are the information we get from check timing report ?
17) Which library will you generally use as target library, if your
standard cell library consists of multiple threshold voltage cells ?

Ans : We use normal threshold voltage cells as target library for Synthesis.

18) What corner will you use for Synthesis ?

Ans : Worst corner.

19) If you have multiple modes, where a single clock’s frequency differs,
how will you constrain it in Synthesis ?

Ans : We take the highest frequency for this clock while doing Synthesis
to optimise maximum.

20) What is a wire-load model, explain it’s contents and how will it help
your Synthesis?

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Blog Directory Constraints Exceptions Generally


Includes Incremental Informed Initial

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Name

hanu • 7 years ago


Also please let me know what Sequential
merging does?
△ ▽ • Reply • Share ›

tdzire > hanu • 7 years ago


Sequential merging is where
multiple flip flops or latches are
merged together based on the
logic. I will post the same as a topic
soon.
△ ▽ • Reply • Share ›

hanu • 7 years ago


Hi Gayatri,
Thanku for providing answer to my last
posted doubt.
I also wanted to know one more thing i.e,
i read in book that value of Uncertainity =
skew + Jitter + extra margin pessimissm.
What is that extra margin pessimissim?
△ ▽ • Reply • Share ›

tdzire > hanu • 7 years ago


Extra margin pessimism is which is
added to increase the pessimism.
The value can differ in different
stages like synthesis, timing
analysis etc. These values should
be ideally given from the foundry.
△ ▽ • Reply • Share ›

hanu > tdzire


• 7 years ago
but my doubt is why is that
pessimism required
actually?
△ ▽ • Reply • Share ›

tdzire > hanu


• 7 years ago
Extra pessimism is
more required in the
synthesis stage,
since we dont
have the physical
information at this
stage. This value will
get reduced
in the upcoming
stages, where the
physical information
of the design is

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