LTC4100

Smart Battery
Charger Controller
Features Description
n Single Chip Smart Battery Charger Controller The LTC®4100 Smart Battery Charger is a single chip
n 100% Compliant (Rev. 1.1) SMBus Support Allows charging solution that dramatically simplifies construction
for Operation with or without Host of an SBS compliant system. The LTC4100 implements
n SMBus Accelerator Improves SMBus Timing a Level 2 charger function whereby the charger can be
n Wide Output Voltage Range: 3.5V to 26V programmed by the battery or by the host. A SafetySignal
n Hardware Interrupt and SMBAlert Response on the battery being charged is monitored for temperature,
Eliminate Interrupt Polling connectivity and battery type information. The SMBus
n High Efficiency Synchronous Buck Charger interface remains alive when the AC power adapter is
n 0.5V Dropout Voltage; Maximum Duty Cycle > 98% removed and responds to all SMBus activity directed to
n AC Adapter Current Limit Maximizes Charge Rate it, including SafetySignal status (via the ChargerStatus
n ±0.8% Voltage Accuracy; ±4% Current Accuracy command). The charger also provides an interrupt to the
n Up to 4A Charging Current Capability host whenever a status change is detected (e.g., battery
n 10-Bit DAC for Charge Current Programming removal, AC adapter connection).
n 11-Bit DAC for Charger Voltage Programming
n User-Selectable Overvoltage and Overcurrent Limits
Charging current and voltage are restricted to chemistry-
n High Noise Immunity SafetySignal Sensor
specific limits for improved system safety and reliability.
n Available in a 24-Pin SSOP Package
Limits are programmable by two external resistors. Ad-
ditionally, the maximum average current from the AC
Applications adapter is programmable to avoid overloading the adapter
when simultaneously supplying load current and charging
n Portable Instruments and Computers current. When supplying system load current, charg-
n Data Storage Systems and Battery Backup Servers ing current is automatically reduced to prevent adapter
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
overload.
property of their respective owners. Protected by U.S. Patents including 6650174 and 5723970.

Typical Application
DCIN
13.7k 0.1µF VBAT PART
3V 1.21k < 5.5V LTC4101
TO 5.5V > 5.5V LTC4100
LTC4100 0.1µF 0.033Ω
17 5
VDD DCIN
11 4
DCDIV INFET 5k
6 24 SYSTEM LOAD
CHGEN CHGEN CLP
10 23
ACP ACP CLN 20µF SMART BATTERY
7 1 0.025Ω
SMBALERT TGATE
9 3 10µH
SCL BGATE
8 2
SDA PGND 20µF
15 21
THB CSP
16 22
THA BAT
13 18
ILIM VSET
1.13k 14 19 100Ω
VLIM ITH 0.01µF
20 12
10k IDC GND 6.04k
54.9k 0.0015µF
0.068µF 0.12µF 0.1µF

SMBALERT# SafetySignal
SMBCLK SMBCLK
SMBDAT SMBDAT 4100 TA01

Figure 1. 4A Smart Battery Charger

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LTC4100
Absolute Maximum Ratings Pin Configuration
(Note 1)
TOP VIEW
Voltage from VDD to GND.................................. 7V/–0.3V
Voltage from CHGEN, DCDIV, SDA, TGATE 1 24 CLP

SCL and SMBALERT to GND............................. 7V/–0.3V PGND 2 23 CLN

BGATE 3 22 BAT
Voltage from DCIN, CLP, CLN to GND............. 32V/–0.3V
INFET 4 21 CSP
Voltage from CLP to CLN........................................±0.3V
DCIN 5 20 IDC
PGND wrt. GND..................................................... ±0.3V CHGEN 6 19 ITH
CSP, BAT to GND................................................ 28V/–5V SMBALERT 7 18 VSET
Operating Ambient Temperature Range (Note 4) SDA 8 17 VDD
– 40°C to 85°C SCL 9 16 THA
Junction Temperature Range................. –40°C to 125°C ACP 10 15 THB
Storage Temperature Range................... –65°C to 150°C DCDIV 11 14 VLIM
Lead Temperature (Soldering, 10 sec).................... 300°C GND 12 13 ILIM

G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 90°C/W

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4100EG#PBF LTC4100EG#TRPBF LTC4100EG 24-Lead Plastic SSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4100EG LTC4100EG#TR LTC4100EG 24-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DCIN Operating Range ● 6 28 V
IDCIN DCIN Operating Current Charging, Sum of Currents on DCIN, 3 5 mA
CLP and CLN
VTOL Charge Voltage Accuracy (Note 2) –0.8 0.8 %
● –1 1 %
ITOL Charge Current Accuracy (Note 3) VCSP – VBAT Target = 102.3mV –4 4 %
IDAC = 0xFFFF ● –5 5 %
VDD VDD Operating Voltage 0V ≤ VDCIN ≤ 28V ● 3 5.5 V
Shutdown
Battery Leakage Current DCIN = 0V, VCLP = VCLN = VCSP = VBAT ● 15 35 µA
UVLO Undervoltage Lockout Threshold DCIN Rising, VBAT = 0V ● 4.2 4.7 5.5 V
VDD Power-Fail Part Held in Reset Until this VDD Present ● 3 V
DCIN Current in Shutdown VCHGEN = 0V 2 3 mA
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 LTC4100
Electrical
Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin 11.66 µA
CMSL CA1/I1 Input Common Mode Low ● 0 V
CMSH CA1/I1 Input Common Mode High VDCIN ≤ 28V ● VCLN –0.2 V
Current Comparators ICMP and IREV
ITMAX Maximum Current Sense Threshold (VCSP –VBAT) VITH = 2.5V ● 140 165 200 mV
ITREV Reverse Current Threshold (VCSP –VBAT) – 30 mV
Current Sense Amplifier, CA2
Transconductance 1 mmho
Source Current Measured at ITH, VITH = 1.4V –40 µA
Sink Current Measured at ITH, VITH = 1.4V 40 µA
Current Limit Amplifier
Transconductance 1.5 mmho
VCLP Current Limit Threshold ● 93 100 107 mV
ICLN CLN Input Bias Current 100 nA
Voltage Error Amplifier, EA
Transconductance 1 mmho
Sink Current Measured at ITH, VITH = 1.4V 36 µA
OVSD Overvoltage Shutdown Threshold as a Percent of ● 102 107 110 %
Programmed Charger Voltage
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (VDCIN –VCLP) DCIN Voltage Ramping Up from VCLP –0.05V ● 0 0.17 0.25 V
Forward Regulation Voltage (VDCIN –VCLP) ● 25 50 mV
Reverse Voltage Turn-Off Voltage (VDCIN –VCLP) ● –60 –25 mV
INFET ON Clamping Voltage (VDCIN –VINFET) IINFET = 1µA ● 5 5.8 6.5 V
INFET OFF Clamping Voltage (VDCIN –VINFET) IINFET = –25µA 0.25 V
Oscillator
fOSC Regulator Switching Frequency 255 300 345 kHz
fMIN Regulator Switching Frequency in Drop Out Duty Cycle ≥ 98% 20 25 kHz
DCMAX Regulator Maximum Duty Cycle VCSP = VBAT 98 99 %
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLP-VTGATE) ITGATE = –1mA 50 mV
VBGATE High CLOAD = 3000pF 4.5 5.6 10 V
VTGATE Low (VCLP-VTGATE) CLOAD = 3000pF 4.5 5.6 10 V
VBGATE Low IBGATE = 1mA 50 mV
TGATE Transition Time
TGTR TGATE Rise Time CLOAD = 3000pF, 10% to 90% 50 110 ns
TGTF TGATE Fall Time CLOAD = 3000pF, 10% to 90% 50 100 ns
BGATE Transition Time
BGTR BGATE Rise Time CLOAD = 3000pF, 10% to 90% 40 90 ns
BGTF BGATE Fall Time CLOAD = 3000pF, 10% to 90% 40 80 ns
VTGATE at Shutdown (VCLN-VTGATE) ITGATE = –1µA 100 mV
VBGATE at Shutdown ITGATE = 1µA 100 mV
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LTC4100
Electrical
Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Present Comparator
VACP DCDIV Threshold VDCDIV Rising from 1V to 1.4V ● 1.14 1.20 1.26 V
DCDIV Hysteresis 25 mV
DCDIV Input Bias Current VDCDIV = 1.2V –1 1 µA
ACP VOH IACP = –2mA 2 V
ACP VOL IACP = 1mA 0.5 V
DCDIV to ACP Delay VDCDIV = 1.3V 10 µs
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) ● 95 100 105 kΩ
RTHB = 54.9kΩ ±1%
SafetySignal Trip (RES_IDEAL/RES_COLD) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) ● 28.5 30 31.5 kΩ
RTHB = 54.9kΩ ±1%
SafetySignal Trip (RES_HOT/RES_IDEAL) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) ● 2.85 3 3.15 kΩ
RTHB = 54.9kΩ ±1%
SafetySignal Trip (RES_UR/RES_HOT) RTHA = 1130Ω ±1%, CTH = 1nF (Note 6) ● 425 500 575 Ω
RTHB = 54.9kΩ ±1%
Time Between SafetySignal Measurements DCDIV = 1.3V 32 ms
DCDIV = 1V 250 ms
DACs
Charging Current Resolution Guaranteed Monotonic Above IMAX/16 10 Bits
Charging Current Granularity RILIM = 0 1 mA
RILIM = 10k ±1% 2 mA
RILIM = 33k ±1% 4 mA
RILIM = Open (or Short to VDD) 4 mA
Wake-Up Charging Current (IWAKE-UP) All Values of RILIM 80 (Note 5) mA
All Values of RVLIM
Charging Current Limit RILIM = 0 (0-1A) 97.3 107.3 mV
CSP – BAT Charging Current = 0x03FF (0x0400 Note 7)
RILIM = 10k ±1% (0-2A) 97.3 107.3 mV
Charging Current = 0x07FE (0x0800 Note 7)
RILIM = 33k ±1% (0-3A) 72.3 82.3 mV
Charging Current = 0x0BFC (0x0C00 Note 7)
RILIM = 0pen (or Short to VDD) (0-4A) 97.3 107.3 mV
Charging Current = 0x0FFC (0x1000 Note 7)
Charging Voltage Resolution Guaranteed Monotonic (2.9V ≤ VBAT ≤ 28V) 11 Bits
Charging Voltage Granularity 16 mV
Charging Voltage Limit RVLIM = 0 8.730 8.800 8.870 V
Charging Voltage = 0x2260 (Note 7)
RVLIM = 10k ±1% 12.999 13.104 13.209 V
Charging Voltage = 0x3330 (Note 7)
RVLIM = 33k ±1% 17.269 17.408 17.547 V
Charging Voltage = 0x4400 (Note 7)
RVLIM = 100k ±1% 21.538 21.712 21.886 V
Charging Voltage = 0x5400 DCIN ≥ 22V
(Note 7)
RVLIM = 0pen (or Short to VDD) 27.781 28.006 28.231 V
Charging Voltage = 0x6D60 DCIN ≥ 29V
(Note 7)
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 LTC4100
Electrical
Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Logic Levels
VIL SCL/SDA Input Low Voltage VDD = 3V and VDD = 5.5V ● 0.8 V
VIH SCL/SDA Input High Voltage VDD = 3V and VDD = 5.5V ● 2.1 V
VOL SDA Output Low Voltage IPULL-UP = 350µA ● 0.4 V
IIL SCL/SDA Input Current VSDA, VSCL = VIL –1 1 µA
IIH SCL/SDA Input Current VSDA, VSCL = VIH –1 1 µA
VOL SMBALERT Output Low Voltage IPULL-UP = 500µA ● 0.4 V
SMBALERT Output Pull-Up Current VSMBALERT = VOL –17.5 –10 –3.5 µA
ILEAK SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV ● –2 2 µA
VOL CHGEN Output Low Voltage IOL = 100µA ● 0.5 V
CHGEN Output Pull-Up Current VCHGEN = VOL –17.5 –10 –3.5 µA
VIL CHGEN Input Low Voltage ● 0.9 V
VIH CHGEN Input High Voltage VDD = 3V ● 2.5 V
VDD = 5.5V 3.9 V
Power-On Reset Duration VDD Ramp from 0V to >3V in <5µs 100 µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH SCL Serial Clock High Period IPULL-UP = 350µA, CLOAD = 250pF, ● 4 µs
RPU = 9.31k, VDD = 3V and VDD = 5.5V
tLOW SCL Serial Clock Low Period IPULL-UP = 350µA, CLOAD = 250pF, ● 4.7 15000 µs
RPU = 9.31k, VDD = 3V and VDD = 5.5V
tR SDA/SCL Rise Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V and ● 1000 ns
VDD = 5.5V
tF SDA/SCL Fall Time CLOAD = 250pF, RPU = 9.31k, VDD = 3V and ● 300 ns
VDD = 5.5V
tSU:STA Start Condition Setup Time VDD = 3V and VDD = 5.5V ● 4.7 µs
tHD:STA Start Condition Hold Time VDD = 3V and VDD = 5.5V ● 4 µs
tHD:DAT SDA to SCL Falling-Edge Hold Time, Slave VDD = 3V and VDD = 5.5V ● 300 ns
Clocking in Data
tTIMEOUT Time Between Receiving Valid ChargingCurrent() VDD = 3V and VDD = 5.5V ● 140 175 210 sec
and ChargingVoltage() Commands

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Current accuracy dependent upon circuit compensation and sense
may cause permanent damage to the device. Exposure to any Absolute resistor.
Maximum Rating condition for extended periods may affect device Note 6: CTH is defined as the sum of capacitance on THA, THB and
reliability and lifetime. SafetySignal.
Note 2: See Test Circuit. Note 7: The corresponding overrange bit will be set when a HEX value
Note 3: Does not include tolerance of current sense resistor. greater than or equal to this value is used.
Note 4: The LTC4100E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

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 LTC4100
Typical Performance Characteristics
INFET Response Time to
Reverse Current VOUT vs IOUT PWM Frequency vs Duty Cycle
0 350
Vgs OF PFET (2V/DIV)
Vgs = 0 –0.5
300
–1.0

OUTPUT VOLTAGE ERROR (%)

PWM FREQUENCY (kHz)

–1.5 250

–2.0
Vs OF PFET (5V/DIV) 200
–2.5
150
–3.0
PROGRAMMED CURRENT = 10%
–3.5 100
Vs = 0V
–4.0
Id (REVERSE) OF 50 DCIN = 15V
PFET (5A/DIV) –4.5 DCIN = 20V DCIN = 20V
VBAT = 12.6V DCIN = 24V
Id = 0A –5.0 0
1.25µs/DIV 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TEST PERFORMED ON DEMOBOARD OUTPUT CURRENT (A) DUTY CYCLE (VOUT/VIN)
VIN = 15VDC VCHARGE = 12.6V 4100 G02 4100 G03
CHARGER = ON INFET = 1/2 Si4925DY
ICHARGE = <10mA 4100 G01

Disconnect/Reconnect Battery Battery Leakage Current

(Load Dump) vs Battery Voltage Efficiency at 19V VDCIN
40 100
VDCIN = 0V
3A STEP 35 16.8V
BATTERY LEAKAGE CURRENT (µA)

95
30 12.6V
1A STEP 1A STEP
VFLOAT
EFFICIENCY (%)
25 90
1V/(DIV)
20

15 85
3A STEP
LOAD 10
STATE DISCONNECT RECONNECT 80
5

0 75
LOAD CURRENT = 1A, 2A, 3A 0 5 10 15 20 25 30 0.50 1.00 1.50 2.00 2.50 3.00
DCIN = 20V BATTERY VOLTAGE (V) CHARGING CURRENT (A)
VFLOAT = 12.6V
4100 G05 4100 G06
4100 G04

Efficiency at 12.6V with 15V VDCIN SMBus Accelerator Operation Low Current Operation
100 0.5
VDD = 5V VDD = 5V
5V CBUS = 200pF TEMP = 27°C
TA = 25°C 0.4 DCIN = 15V
95
MEASURED CURRENT (A)

0.3
EFFICIENCY (%)

90 NO LOW
LTC4100
CURRENT
0.2 MODE PROGRAMMED
85 RPULLUP = 15k CURRENT
0.1 LOW
0V CURRENT
80 MODE
0

75 –0.1
0.50 1.00 1.50 2.00 2.50 3.00 0 0.1 0.2 0.3 0.4
CHARGING CURRENT (A) 1µs/DIV PROGRAMMED CURRENT (A)
4100 G07 4100 G08 4100 G09

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 LTC4100
Typical Performance Characteristics

Charging Current Error Charging Voltage Error

0.4 0.150
VDD = 5V VDD = 5V
TEMP = 27°C 0.125 TEMP = 27°C
0.3
VLOAD = 12V 0.100 ILOAD = 0.120A
OUTPUT CURRENT ERROR (A)

OUTPUT VOLTAGE ERROR (V)

0.2 0.075
0.050 DCIN = 20V
0.1
0.025 DCIN = 15V
0 0
–0.025
–0.1
–0.050
–0.2 DCIN = 15V, NoLowI –0.075
DCIN = 20V, NoLowI –0.100
–0.3 DCIN = 15V, LowI –0.125
DCIN = 20V, LowI
–0.4 –0.150
0 1 2 3 4 0 2 4 6 8 10 12 14 16 18 20 22
CHARGING CURRENT (A) CHARGING VOLTAGE (V)
4100 G10 4100 G11

Pin Functions
TGATE (Pin 1): Drives the Top External P-MOSFET of the change of status in the charger registers and that the host
Battery Charger Buck Converter. should read the LTC4100 status registers to determine if
PGND (Pin 2): High Current Ground Return for BGATE any action on its part is required. This signal can be con-
Driver. nected to the optional SMBALERT# line of the SMBus.
Open drain with weak current source pull-up to VDD (with
BGATE (Pin 3): Drives the Bottom External N-MOSFET of Schottky to allow it to be pulled to 5V externally).
the Battery Charger Buck Converter.
SDA (Pin 8): SMBus Data Signal from Main (host-
INFET (Pin 4): Drives the Gate of the External Input controlled) SMBus. External pull-up resistor is required.
P-MOSFET.
SCL (Pin 9): SMBus Clock Signal from Main (host-
DCIN (Pin 5): External DC Power Source Input. Bypass to controlled) SMBus. External pull-up resistor is required.
ground with a 0.1µF capacitor.
ACP (Pin 10): This Output Indicates the Value of the
CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger DCDIV Comparator. It can be used to indicate whether
Function. This pin is connected as a wired AND bus. AC is present or not.
The following events will cause the POWER_FAIL bit in DCDIV (Pin 11): Supply Divider Input. This is a high im-
the ChargerStatus register to become set: pedance comparator input with a 1.2V threshold (rising
1. An external device pulling the CHGEN signal to within edge) and hysteresis.
0.9V to GND; GND (Pin 12): Ground for Digital and Analog Circuitry.
2. The AC adapter voltage is not above the battery voltage. ILIM (Pin 13): An external resistor is connected between this
SMBALERT (Pin 7): Active Low Interrupt Output to Host pin and GND. The value of the external resistor programs
(referred to as the SMBALERT# signal in the SMBus Revi- the range and resolution of the programmed charger cur-
sion 1.1 specification). Signals host that there has been a rent. This is a digital, not an analog, function.
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LTC4100
Pin Functions
VLIM (Pin 14): An external resistor is connected between ITH (Pin 19): Control Signal of the Inner Loop of the Current
this pin and GND. The value of the external resistor pro- Mode PWM. Higher ITH corresponds to higher charging
grams the range and resolution of the charging voltage. current in normal operation. A 0.0015µF capacitor to GND
This is a digital, not an analog, function. filters out PWM ripple. Typical full-scale output current
THB (Pin 15): SafetySignal Force/Sense Pin to Smart is 40µA. Nominal voltage range for this pin is 0V to 3V.
Battery. See description of operation for more detail. The IDC (Pin 20): Bypass to GND with a 0.068µF Capacitor.
maximum allowed combined capacitance on THA, THB and CSP (Pin 21): Current Amplifier CA1 Input. This pin and
SafetySignal is 1nF (see Figure 4). A series resistor 54.9k the BAT pin measure the voltage across the sense resis-
needs to be connected between this pin and the battery’s tor, RSENSE, to provide the instantaneous current signals
SafetySignal for this circuit to work correctly. required for both peak and average current mode operation.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart BAT (Pin 22): Battery Sense Input and the Negative Refer-
Battery. See description of operation for more detail. The ence for the Current Sense Resistor. A bypass capacitor
maximum allowed combined capacitance on THA, THB of at least 10µF is required.
and SafetySignal is 1nF (see Figure 4). A series resistor
1130Ω needs to be connected between this pin and the CLN (Pin 23): Negative Input to the Input Current Limiting
battery’s SafetySignal for this circuit to work correctly. Circuit Block. If no current limit function is desired, connect
this pin to CLP. The threshold is set at 100mV below the
VDD (Pin 17): Power Supply Input for the LTC4100 Digital voltage at the CLP pin. When used to limit supply current,
Circuitry. Bypass this pin with 0.1µF. Typically between
a filter is needed to filter out the switching noise.
3.3V and 5VDC.
CLP (Pin 24): Positive Input to the Input Current Limiting
VSET (Pin 18): Tap Point of the Programmable Resistor
Circuit Block. This pin also serves as a power supply for
Divider, which Provides Battery Voltage Feedback to the
the IC.
Charger.

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 LTC4100
Block Diagram

C4 VBAT
R4 0.01µF
100Ω – 3k BAT
VSET 22
VBAT 18
+ 11.67µA
C5, 0.1µF 11-BIT RSENSE
VDAC
GND – 20µF
12 CA1 3k CSP
DCIN + 21
1.28V
0V
OSCILLATOR CSP
9k
WATCHDOG
DETECT tON gm = 1m
Ω BUFFERED
SYSTEM – ITH
LOAD 20µF EA ÷5
1.19V +
CLP +
–
L1 S
TGATE ICMP
CSP Q2 1 Q R

PWM IREV –
17mV
D1 BGATE LOGIC IDC
Q3 3 + 20
C8
R1 PGND – 0.068µF
2
100mV CA2
CLN gm = 1.5m
Ω
+ 1.19V
23 + gm = 1m
Ω
RCL C9 ITH
CLP CL1 19
24 –
10-BIT R5, 6.04k C7
DCIN
5 IDAC 0.0015µF
C6, 0.12µF
5.8V
INFET 10 ACP
Q1 4
CLP DCDIV
11 VIN
VIN CHGEN 6 R10
VDD 1.2V R11
C1, 0.1µF
10µA
SMBALERT 7 17 VDD TO SMBUS
POWER SUPPLY

TO HOST AND BATTERY SMBus

INTERFACE
SDA 8 AND CONTROL ILIM
13
SCL 9 LIMIT
1.13k DECODER VLIM
14
16
THA THERMISTER
15 INTERFACE RVLIM RILIM
54.9k THB

10k

Figure 2

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LTC4100
Test Circuit

LTC4100
1.19V +
– EA VBAT − VVDAC
– VTOL = • 100
+
VVDAC
VDAC FOR VVDAC = 17.57V(0x44A0)
21 22 18 19
CSP BAT VSET ITH DCIN = 21V
LT1055
+
CLN = CLP = 20V
0.6V
–

4100 TC01

Operation
Overview (Refer to Block Diagram) BATTERY_PRESENT, ALARM_INHIBITED, or VDD power-
fail. The host may query the charger, via the SMBus, to
The LTC4100 is composed of a battery charger section, a
obtain ChargerStatus() information. SMBALERT will be
charger controller, a 10-bit DAC to control charger current,
de-asserted upon a successful read of ChargerStatus()
an 11-bit DAC to control charger voltage, a SafetySignal
or a successful Alert Response Address (ARA) request.
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a Battery Charger Controller
RES_OR condition and charging is disabled by the charger
controller (CHGEN = Low). Charging will also be disabled if The LTC4100 charger controller uses a constant off-time,
DCDIV is low, or the SafetySignal is decoded as RES_HOT. current mode step-down architecture. During normal
If a battery is inserted and AC power is connected, the operation, the top MOSFET is turned on each cycle when
battery will be charged with an 80mA “wake-up” current. the oscillator sets the SR latch and turned off when
The wake-up current is discontinued after tTIMEOUT if the the main current comparator ICMP resets the SR latch.
SafetySignal is decoded as RES_UR or RES_C0LD, and While the top MOSFET is off, the bottom MOSFET is
the battery or host doesn’t transmit charging commands. turned on until either the inductor current trips the current
comparator IREV, or the beginning of the next cycle. The
The SMBus interface and control block receives Charg- oscillator uses the equation,
ingCurrent() and ChargingVoltage() commands via the
SMBus. If ChargingCurrent() and ChargingVoltage()
tOFF =
( VDCIN − VBAT )
command pairs are received within a tTIMEOUT interval, the
( VDCIN • f OSC )
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded to set the bottom MOSFET on-time. The result is quasi-
SafetySignal value will allow charging to commence. Charg- constant frequency operation: the converter frequency
ingCurrent() and ChargingVoltage() values are compared remains nearly constant over a wide range of output volt-
against limits programmed by the limit decoder block; if ages. This activity is diagrammed in Figure 3.
the commands exceed the programmed limits these limits
The peak inductor current, at which ICMP resets the SR
are substituted and overrange flags are set.
latch, is controlled by the voltage on ITH. ITH is in turn
The charger controller will assert SMBALERT whenever controlled by several loops, depending upon the situation
a status change is detected, namely: AC_PRESENT, at hand. The average current control loop converts the
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 LTC4100
Operation
voltage between CSP and BAT to a representative current. Charger Start-Up
Error amp CA2 compares this current against the desired When the charger is enabled, it will not begin switching
current programmed by the IDAC at the IDC pin and adjusts until the ITH voltage exceeds a threshold that assures initial
ITH for the desired voltage across RSENSE. current will be positive. This threshold is 5% to 15% of the
The voltage at BAT is divided down by an internal resis- maximum programmed current. After the charger begins
tor divider set by the VDAC and is used by error amp EA switching, the various loops will control the current at a
to decrease ITH if the divider voltage is above the 1.19V level that is higher or lower than the initial current. The
reference. duration of this transient condition depends upon the loop
compensation, but is typically less than 1ms.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/ SMBus Interface
RCL). At input current limit, CL1 will decrease the ITH volt-
All communications over the SMBus are interpreted by the
age to reduce charging current. SMBus interface block. The SMBus interface is a SMBus
An overvoltage comparator, OV, guards against transient slave device at address 0x12. All internal LTC4100 registers
overshoots (>7%). In this case, the top MOSFET is turned may be updated and accessed through the SMBus interface,
off until the overvoltage condition is cleared. This feature and charger controller as required. The SMBus protocol is
is useful for batteries that “load dump” themselves by a derivative of the I2C bus (Reference I 2C-Bus and How to
opening their protection switch to perform functions such Use It, V1.0 by Philips, and System Management Bus Speci-
as calibration or pulse mode charging. fication, Version 1.1, from the SBS Implementers Forum, for
a complete description of the bus protocol requirements).
PWM Watchdog Timer All data is clocked into the shift register on the rising
There is a watchdog timer that observes the activity on edge of SCL. All data is clocked out of the shift register
the TGATE pin. If TGATE stops switching for more than on the falling edge of SCL. Detection of an SMBus Stop
40µs, the watchdog activates and turns off the top MOSFET condition, or power-on reset via the VDD power-fail, will
for about 400ns. The watchdog engages to prevent very reset the SMBus interface to an initial state at any time.
low frequency operation in dropout—a potential source The LTC4100 command set is interpreted by the SMBus
of audible noise when using ceramic input and output interface and passed onto the charger controller block as
capacitors. control signals or updates to internal registers.

OFF
TGATE
ON

ON
BGATE tOFF
OFF

TRIP POINT SET

BY ITH VOLTAGE
INDUCTOR
CURRENT
4100 F03

Figure 3

*http://www.SBS-FORUM.org
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LTC4100
Operation
Description of Supported Battery Charger Functions The ENABLE_POLLING bit is not supported by the LTC4100.
The functions are described as follows (see Table 1 also): Values written to this bit are ignored.

FunctionName() ‘hnn (command code) The POR_RESET bit sets the LTC4100 to its power-on
default condition.
Description: A brief description of the function.
The RESET_TO_ZERO bit sets the ChargingCurrent()and
Purpose: The purpose of the function, and an example ChargingVoltage() values to zero. This function ALWAYS
where appropriate. clears the ChargingVoltage() and ChargingCurrent() values
• SMBus Protocol: Refer to Section 5 of the Smart to zero even if the INHIBIT_CHARGE bit is set.
Battery Charger specification for more details. ChargerStatus() (‘h13)
Input, Output or Input/Output: A description of the data Description: The SMBus Host uses this command to read
supplied to or returned by the function. the LTC4100’s status bits.
ChargerSpecInfo() (‘h11) Purpose: Allows the SMBus Host to determine the status
Description: The SMBus Host uses this command to read and level of the LTC4100.
the LTC4100’s extended status bits. • SMBus Protocol: Read Word.
Purpose: Allows the System Host to determine the Output: The CHARGE_INHIBITED bit reflects the status
specification revision the charger supports as well as of the LTC4100 set by the INHIBIT_CHARGE bit in the
other extended status information. ChargerMode() function.
• SMBus Protocol: Read Word. The POLLING_ENABLED, VOLTAGE_NOTREG, and
Output: The CHARGER_SPEC indicates that the LTC4100 CURRENT_NOTREG are not supported by the LTC4100.
supports Version 1.1 of the Smart Battery Charger The LTC4100 always reports itself as a Level 2 Smart
Specification. The SELECTOR_SUPPORT indicates that Battery Charger.
the LTC4100 does not support the optional Smart Battery
Selector Commands. CURRENT_OR bit is set only when ChargingCurrent()
is set to a value outside the current regulation range of
ChargerMode() (‘h12) the LTC4100. This bit may be used in conjunction with
Description: The SMBus Host uses this command to set the INHIBIT_CHARGE bit of the ChargerMode() and
the various charger modes. The default values are set to ChargingCurrent() to determine the current capability of
allow a Smart Battery and the LTC4100 to work in concert the LTC4100. When ChargingCurrent() is set to the ILIM
without requiring an SMBus Host. + 1, the CURRENT_OR bit will be set.
Purpose: Allows the SMBus Host to configure the charger VOLTAGE_OR bit is set only when ChargingVoltage()
and change the default modes. This is a write only function, is set to a value outside the voltage regulation range of
but the value of the “mode” bit, INHIBIT_CHARGE may be the LTC4100. This bit may be used in conjunction with
determined using the ChargerStatus() function. the INHIBIT_CHARGE bit of the ChargerMode() and
ChargingVoltage() to determine the voltage capability of
• SMBus Protocol: Write Word. the LTC4100. When ChargingVoltage() is set to the VLIM ,
Input: The INHIBIT_CHARGE bit allows charging to be the VOLTAGE_OR bit will be set.
inhibited without changing the ChargingCurrent() and The RES_OR bit is set only when the SafetySignal resis-
ChargingVoltage() values. The charging may be resumed tance value is greater than 95kΩ. This indicates that the
by clearing this bit. This bit is automatically cleared when SafetySignal is to be considered as an open circuit.
power is reapplied or when a battery is reinserted.
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 LTC4100
Operation
Table 1. Summary of Supported Charger Functions
SMBus Command Data
Function Access Address Code Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO

SELECTOR_SUPPORT
ChargerSpecInfo() 7'b0001_001 8'h11 Info
(0x12)

Reserved CHARGER_SPEC

Return
Read Values 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

ENABLE_POLLING

INHIBIT_CHARGE
RESET_TO_ZERO
ChargerMode() 7'b0001_001 8'h12 Control

POR_RESET
Reserved

Permitted
Write Values Ignored 1/0 1/0 Ign 1/0

ChargerStatus() 7'b0001_001 8'h13 Status

CHARGE_INHIBITED
POLLING_ENABLED
CURRENT_NOTREG
BATTERY_PRESENT

ALARM_INHIBITED

VOLTAGE_NOTREG
LEVEL:3/LEVEL:2
CURRENT_OR
AC_PRESENT

VOLTAGE_OR
POWER_FAIL

RES_COLD
RES_HOT
RES_UR

RES_OR
Return
Read Values 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1 0 0 0 1/0

ChargingCurrent() 7'b0001_001 8'h14 Value CHARGING_CURRENT[15:0]

Permitted
Unsigned integer representing current in mA
Write Values

ChargingVoltage() 7'b0001_001 8'h15 Value CHARGING_VOLTAGE[15:0]

Permitted Unsigned integer representing voltage in mV

Write Values
TERMINATE_DISCHARGE_ALARM

AlarmWarning() 7'b0001_001 8'h16 Control

REMAINING_CAPACITY_ALARM
TERMINATE_CHARGE_ALARM

REMAINING_TIME_ALARM
OVER_CHARGED_ALARM

OVER_TEMP_ALARM

FULLY DISCHARGED
RESERVED_ALARM

FULLY_CHARGED
DISCHARGING
INITIALIZED
Reserved

ERROR

Permitted
Write Values 1/0 1/0 1/0 1/0 Ignored
NO_LOWI

LTCO() 7'b0001_001 8'h3C Register

Reserved LTC4100's Version Identification

Permitted Ignored 1/0 Ignored

Write Values
Return
Read Values 0 0 0 1/0 0 0 1 0 0 0 0 0 0 0 1 0
Undefined

Alert Response 7'b0001_100 N/A Status LTC4100's Address

Address (0x18)
Not Supported
Read Return
Byte Values 0 0 0 1 0 0 1 X

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LTC4100
Operation
The RES_COLD bit is set only when the SafetySignal ChargingCurrent() (‘h14)
resistance value is greater than 28.5kΩ. The SafetySignal
Description: The Battery, System Host or other master
indicates a cold battery. The RES_COLD bit will be set
device sends the desired charging current (mA) to the
whenever the RES_OR bit is set.
LTC4100 .
The RES_HOT bit is set only when the SafetySignal
Purpose: The LTC4100 uses RILIM, the granularity of the
resistance is less than 3150Ω, which indicates a hot battery.
The RES_HOT bit will be set whenever the RES_UR bit is set. IDAC, and the value of the ChargingCurrent() function to
determine its charging current supplied to the battery. The
The RES_UR bit is set only when the SafetySignal resis- charging current will never exceed the maximum current
tance value is less than 575Ω. permitted by RILIM. The ChargingCurrent() value will be
ALARM_INHIBITED bit is set if a valid AlarmWarning() truncated to the granularity of the IDAC. The charging cur-
message has been received and charging is inhibited as rent will also be reduced if the battery voltage exceeds the
a result. This bit is cleared if both ChargingVoltage() and programmed charging voltage.
ChargingCurrent() are rewritten to the LTC4100, power • SMBus Protocol: Write Word.
is removed (DCDIV < VACP), or if a battery is removed.
The setting of the ALARM_INHIBITED will activate the Input: The CHARGING_CURRENT is an unsigned 16 bit
LTC4100 SMBALERT pull-down. integer specifying the requested charging current in mA.
The following table defines the maximum permissible
POWER_FAIL bit is set if the LTC4100 does not have suf- value of CHARGING_CURRENT that will not set the
ficient DCIN voltage to charge the battery or if an external CURRENT_OR in the ChargerStatus() function for a given
device is pulling the CHGEN input signal low. Charging value of the RILIM:
is disabled whenever this bit is set. The setting of this bit
does not clear the values in the ChargingVoltage() and RILIM ChargingCurrent() Current
ChargingCurrent() function values, nor does it necessarily Short to GND 0x0000 through 0x03FF 0mA through 1023mA
affect the charging modes of the LTC4100. 10kΩ ±1% 0x0000 through 0x07FF 0mA through 2047mA

BATTERY_PRESENT is set if a battery is present other- 33kΩ ±1% 0x0000 through 0x0BFF 0mA through 3071mA
wise it is cleared. The LTC4100 uses the SafetySignal Open (or Short to VDD) 0x0000 through 0x0FFF 0mA through 4095mA
in order to determine battery presence. If the LTC4100
detects a RES_OR condition, the BATTERY_PRESENT ChargingVoltage() (‘h15)
bit is cleared immediately. The LTC4100 will not set the
BATTERY_PRESENT bit until it successfully samples Description: The Battery, SMBus Host or other master
the SafetySignal twice and does not detect a RES_OR device sends the desired charging voltage (mV) to the
condition on either sampling. If AC is not present (e.g. LTC4100.
DCDIV < VACP), this bit may not be set for up to one-half Purpose: The LTC4100 uses RVLIM, the granularity of the
second after the battery is connected to the SafetySignal. VDAC, and the value of the ChargingVoltage() function to
The ChargingCurrent() and ChargingVoltage() function determine its charging voltage supplied to the battery. The
values are immediately cleared whenever this bit is cleared. charging voltage will never be forced beyond the voltage
Charging will never be allowed if this bit is cleared. A permitted by RVLIM. The ChargingVoltage() value will be
change in BATTERY_PRESENT will activate the LTC4100 truncated to the granularity of the VDAC. The charging
SMBALERT pull-down. voltage will also be reduced if the battery current exceeds
AC_PRESENT is set if the voltage on DCDIV is greater than the programmed charging current.
VACP. This does not necessarily indicate that the voltage
• SMBus Protocol: Write Word.
on DCIN is sufficient to charge the battery. A change
in AC_PRESENT will activate the LTC4100 SMBALERT Input: The CHARGING_VOLTAGE is an unsigned 16-bit
pull-down. integer specifying the requested charging voltage in mV.
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 LTC4100
Operation
The LTC4100 considers any value from 0x0001 through Purpose: This function allows the SMBus Host to deter-
0x049F the same as writing 0x0000. The following mine if the battery charger is an LTC4100. Identifying the
table defines the maximum permissible value of manufacturer and version of the Smart Battery Charger
CHARGING_VOLTAGE that will not set the VOLTAGE_OR permits software to perform tasks specific to a given
in the ChargerStatus() function for a given value of RVLIM: charger. The LTC4100 also provides a means of disabling
the LOWI current mode of the IDAC.
RVLIM Maximum ChargingVoltage()
Short to GND 0x225F (8796mV) • SMBus Protocol: Write Word.
10kΩ ±1% 0x332F (13100mV) Input: The NO_LOWI is the only bit recognized by this
33kΩ ±1% 0x43FF (17404mV) function. The default value of NO_LOWI is zero. The
100kΩ ±1% 0x54CF (21708mV) LTC4100 LOWI current mode provides a more accurate
Open (or Short to VDD) 0x6D5F (27996mV) average charge current when the charge current is less
than 1/16 of the full scale IDAC value. When the NO_LOWI
AlarmWarning() (‘h16) is set, a less accurate IDAC algorithm is used to generate
the charging current, but because the charger is not pulsed
Description: The Smart Battery, acting as a bus master on and off, it may be preferred.
device, sends the AlarmWarning() message to the LTC4100
to notify it that one or more alarm conditions exist. Alarm • SMBus Protocol: Read Word.
indications are encoded as bit fields in the Battery’s Sta- Output: The NO_LOWI indicates the IDAC mode of opera-
tus register, which is then sent to the LTC4100 by this tion. If clear, then the LOWI current mode will be used
function. when the charging current is less than 1/16 of the full-
scale IDAC value.
Purpose: The LTC4100 will use the information sent by
this function to properly charge the battery. The LTC4100 The LTC Version Identification will always be 0x202 for
will only respond to certain alarm bits. Writing to this the LTC4100.
function does not necessarily cause an alarm condition Alert Response Address (ARA)
that inhibits battery charging.
Description: The SMBus system host uses the Alert
• SMBus Protocol: Write Word. Response Address to quickly identify the generator of an
Input: Only the OVER_CHARGED_ALARM, TERMINATE SMBALERT# event.
_CHARGE_ALARM, reserved (0x2000), and OVER Purpose: The LTC4100 will respond to an ARA address
_TEMP_ALARM bits are supported by the LTC4100. 0x18 if the SMBALERT signal is actively pulling down the
Writing a one to any of these specified bits will inhibit SMBALERT# bus. The LTC4100 will follow the prioritiza-
the charging by the LTC4100 and will set the ALARM_ tion reporting as defined in the System Management Bus
INHIBITED bit in the ChargerStatus() function. The Specification, Version 1.1, from the SBS Implementers
TERMINATE_DISCHARGE_ALARM,  REMAINING_ Forum.
CAPACITY_ALARM, REMAINING_TIME_ALARM, and the • SMBus Protocol: A 7-bit Addressable Device Responds
ERROR bits are ignored by the LTC4100. to an ARA.
LTC0() (‘h3C) Output: The Device Address will be sent to the SMBus
Description: The SMBus Host uses this command to system host. The LTC4100 Device address is 0x12.
determine the version number of the LTC4100 and set The following events will cause the LTC4100 to pull-down
extended operation modes not defined by the Smart Bat- the SMBALERT# bus through the SMBALERT pin:
tery Charger Specification. • Change of AC_PRESENT in the ChargerStatus()
function.
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LTC4100
Operation
• Change of BATTERY_PRESENT in the ChargerStatus() ChargingVoltage() request functions and broadcast-
function. ing the charging commands to the LTC4100 over the
• Setting ALARM_INHIBITED in the ChargerStatus() SMBus.
function. 4. The LTC4100 will still respond to Smart Battery critical
• Internal power-on reset condition. warning messages without host intervention.

SMBus Accelerator Pull-Ups Wake-Up Charging Mode

Both SCL and SDA have SMBus accelerator circuits The following conditions must be met in order to allow
which reduce the rise time on systems with significant wake-up charging of the battery:
capacitance on the two SMBus signals. The dynamic pull-up 1. The SafetySignal must be RES_COLD, RES_IDEAL, or
circuitry detects a rising edge on SDA or SCL and applies RES_UR.
1mA to 10mA pull-up to VDD when VIN > 0.8V until VIN
< VDD – 0.8V (external pull-up resistors are still required 2. AC must be present. This is qualified by DCDIV > VACP.
to supply DC current). This action allows the bus to meet Wake-up charging initiates when a newly inserted battery
SMBus rise time requirements with as much as 250pF on does not send ChargingCurrent() and ChargingVoltage()
each SMBus signal. The improved rise time will benefit functions to the LTC4100.
all of the devices which use the SMBus, especially those
devices that use the I2C logic levels. Note that the dynamic The following conditions will terminate the wake-up
pull-up circuits only pull to VDD, so some SMBus devices charging mode.
that are not compliant to the SMBus specifications may still 1. A TTIMEOUT period is reached when the SafetySignal is
have rise time compliance problems if the SMBus pull-up RES_COLD or RES_UR.
resistors are terminated with voltages higher than VDD.
2. The SafetySignal is registering RES_OR.
The Control Block 3. The successful writing of the ChargingCurrent() AND
The LTC4100 charger operations are handled by the con- ChargingVoltage() function. The LTC4100 will proceed
trol block. This block is capable of charging the selected to the controlled charging mode after these two func-
battery autonomously or under SMBus Host control. tions are written.
The control block can request communications with the 4. The SafetySignal is registering RES_HOT.
system management host (SMBus Host) by asserting
SMBALERT = 0; this will cause the SMBus Host, if present, 5. The AC power is no longer present. (DCDIV < VACP)
to poll the LTC4100. 6. The ALARM_INHIBITED becomes set in the Charger-
The control block receives SMBus slave commands from Status() function.
the SMBus interface block. 7. The INHIBIT_CHARGE is set in the ChargerMode()
The control block allows the LTC4100 to meet the following function.
Smart Battery-controlled (Level 2) charger requirements: 8. The CHGEN pin is pulled low by an external device. The
1. Implements the Smart Battery’s critical warning mes- LTC4100 will resume wake-up charging, if the CHGEN
sages over the SMBus. pin is released by the external device. Toggling the
CHGEN pin will not reset the TTIMEOUT timer.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands 9. There is insufficient DCIN voltage to charge the battery.
and adjusts the charger output parameters accordingly. The LTC4100 will resume wake-up charging when there
is sufficient DCIN voltage to charge the battery. This
3. The host may control charging by disabling the Smart condition will not reset the TTIMEOUT timer.
Battery’s ability to transmit ChargingCurrent() and
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 LTC4100
Operation
Controlled Charging Algorithm Overview ChargingVoltage() AND ChargingCurrent() function
values.
The following conditions must be met in order to allow
controlled charging to start on the LTC4100: 7. RESET_TO_ZERO is set in the ChargerMode() function.
1. The ChargingVoltage() AND ChargingCurrent() function 8. CHGEN pin is pulled low by an external device. The
must be written to non-zero values. LTC4100 will resume charging using the previous
2. The SafetySignal must be RES_COLD, RES_IDEAL, or ChargingVoltage() AND ChargingCurrent() function
RES_UR. values, if the CHGEN pin is released by the external
device.
3. AC must be present. This is qualified by DCDIV > VACP.
9. Insufficient DCIN voltage to charge the battery. The
The following conditions will stop the controlled charging LTC4100 will resume charging using the previous
algorithm and will cause the battery charger controller to ChargingVoltage() AND ChargingCurrent() function
stop charging: values, when there is sufficient DCIN voltage to charge
1. The ChargingCurrent() AND ChargingVoltage() functions the battery.
have not been written for TTIMEOUT. 10. Writing a zero value to ChargingVoltage() function.
2. The SafetySignal is registering RES_OR. 11. Writing a zero value to ChargingCurrent() function.
3. The SafetySignal is registering RES_HOT.
The SafetySignal Decoder Block
4. The AC power is no longer present. (DCDIV < VACP)
This block measures the resistance of the SafetySignal and
5. ALARM_INHIBITED is set in the ChargerStatus() features high noise immunity at critical trip points. The low
function. power standby mode supports only battery presence SMB
6. INHIBIT_CHARGE is set in the ChargerMode() charger reporting requirements when AC is not present.
function. Clearing INHIBIT_CHARGE will cause the The SafetySignal decoder is shown in Figure 4. The value
LTC4100 to resume charging using the previous of RTHA is 1.13k and RTHB is 54.9k.

VDD VDD
THA_SELB
RTHA
1.13k AC_PRESENT
16 +
MUX TH_HI
THA –

+ 12.5k
HI_REF TH_LO +
REF –
VDD LO_REF 33k –
25k
THB_SELB SafetySignal + 4
RTHB CONTROL VLIM – VLIM [3:0]
54.9k 14 25k ENCODER
15 RES_OR +
THB RVLIM
CSS RSafetySignal 25k –
RES_COLD
+
LATCH
RES_H0T –
12.5k
RES_UR

4100 F04 4100 F05

Figure 4. SafetySignal Decoder Block Figure 5. Simplified VLIM Circuit Concept (ILIM is Similar)

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LTC4100
Operation
SafetySignal sensing is accomplished by a state machine The SafetySignal impedance is interpreted according to
that reconfigures the switches of Figure 4 using THA_SELB Table 4.
and THB_SELB, a selectable reference generator, and two
Table 4. SafetySignal State Ranges
comparators. This circuit has two modes of operation
SafetySignal CHARGE STATUS BITS DESCRIPTION
based upon whether AC is present. RESISTANCE
When AC is present, the LTC4100 samples the value of 0Ω to 500Ω RES_UR Underrange
RES_HOT
the SafetySignal and updates the ChargerStatus register BATTERY_PRESENT
approximately every 32ms. The state machine successively 500Ω to 3kΩ RES_HOT Hot
samples the SafetySignal value starting with the RES_OR BATTERY_PRESENT
≥ RES_COLD threshold, then RES_C0LD ≥ RES_IDEAL 3kΩ to 30kΩ BATTERY_PRESENT Ideal
threshold, RES_IDEAL ≥ RES_HOT threshold, and finally 30kΩ to 100kΩ RES_COLD Cold
the RES_HOT ≥ RES_UR threshold. Once the SafetySignal BATTERY_PRESENT
range is determined, the lower value thresholds are Above 100kΩ RES_OR RES_COLD Overrange
not sampled. The SafetySignal decoder block uses the Note: The underrange detection scheme is a very important feature of the
LTC4100. The RTHA/RSafetySignal divider trip point of 0.333 • VDD (1V) is
previously determined SafetySignal value to provide the
well above the 0.047 • VDD (140mV) threshold of a system using a 10k
appropriate adjustment in threshold to add hysteresis. pull-up. A system using a 10k pull-up would not be able to resolve the
The RTHB resistor value is used to measure the RES_OR important underrange to hot transition point with a modest 100mV of
≥ RES_COLD and RES_COLD ≥ RES_IDEAL thresholds by ground offset between battery and SafetySignal detection circuitry. Such
offsets are anticipated when charging at normal current levels.
connecting the THB pin to VDD and measuring the voltage
resultant on the THA pin. The RTHA resistor value is used The required values for RTHA and RTHB are shown in
to measure the RES_IDEAL ≥ RES_HOT and RES_HOT ≥ Table 5.
RES_UR thresholds by connecting the THA pin to VDD and
measuring the voltage resultant on the THB pin. Table 5. SafetySignal External Resistor Values
EXTERNAL RESISTOR VALUE (Ω)
The SafetySignal decoder block uses a voltage divider
RTHA 1130 ±1%
network between VDD and GND to determine SafetySig-
nal range thresholds. Since the THA and THB inputs are RTHB 54.9k ±1%

sequentially connected to VDD, this provides VDD noise

immunity during SafetySignal measurement. CSS represents the capacitance between the SafetySignal
and GND. CSS may be added to provide additional noise
When AC power is not available the SafetySignal block
immunity from transients in the application. CSS cannot
supports the following low power operating features:
exceed 1nF if the LTC4100 is to properly sense the value
1. The SafetySignal is sampled every 250ms or less, of RSafetySignal.
instead of 32ms.
2. A full SafetySignal status is sampled every 30s or less,
instead of every 32ms.

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 LTC4100
Operation
The ILIM Decoder Block The Voltage DAC Block
The value of an external resistor connected from this pin Note that the charger output voltage is offset by VREF.
to GND determines one of four current limits that are Therefore, the value of VREF is subtracted from the
used for maximum charging current value. These limits SMBus ChargingVoltage() value in order for the output
provide a measure of safety with a hardware restriction on voltage to be programmed properly (without offset). If the
charging current which cannot be overridden by software. ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 1.184V, the charger
Table 6. ILIM Trip Points and Ranges
output voltage is programmed to zero. In addition, if the
EXTERNAL CONTROLLED
RESISTOR CHARGING ChargingVoltage() value is above the limit set by the VLIM
(RILIM) ILIM VOLTAGE CURRENT RANGE GRANULARITY pin, then the charger output voltage is set to the value
Short to GND VILIM < 0.09VDD 0 < I < 1023mA 1mA determined by the VLIM resistor and the VOLTAGE_OR bit
10k ±1% 0.17VVDD < 0 < I < 2046mA 2mA is set. These limits are demonstrated in Figure 6.
VILIM < 0.34VVDD
33k ±1% 0.42VVDD < 0 < I < 3068mA 4mA
VILIM < 0.59V 25
RVLIM = 33k
Open (>250k, 0.66VVDD < 0 < I < 4092mA 4mA
or Short to VDD) VILIM 20

CHARGER VOUT (V)

15
The VLIM Decoder Block
The value of an external resistor connected from this pin 10

to GND determines one of five voltage limits that are ap-

plied to the charger output value. These limits provide a 5

measure of safety with a hardware restriction on charging

voltage which cannot be overridden by software. 0
0 5 10 15 20 25 30 35
PROGRAMMED VALUE (V)
Table 7. VLIM Trip Points and Ranges (See Figure 5) 4100 F06

EXTERNAL CONTROLLED NOTE: THE LTC4100 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.184V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
RESISTOR CHARGING VOLTAGE VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
(RVLIM) VLIM VOLTAGE (VOUT) RANGE GRANULARITY
Short to VVLIM < 0.09VVCCP 2900mV < VOUT 16mV Figure 6. Transfer Function of Charger
GND < 8800mV
10k ±1% 0.17VVDD < VVLIM 2900mV < VOUT 16mV
< 0.34VVDD < 13104mV
33k ±1% 0.42VVCCP < VVLIM 2900mV < VOUT 16mV
< 0.59VVDD < 17408mV
100k ±1% 0.66VVDD < VVLIM 2900mV < VOUT 16mV
< 0.84VVDD < 21712mV
Open or 0.91VVDD < VVLIM 2900mV < VOUT 16mV
Tied to VDD < 28000mV

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LTC4100
Operation
The Current DAC Block Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
The current DAC is a delta-sigma modulator which controls
the effective value of an external resistor, RSET, used to When wake-up is asserted to the current DAC block, the
set the current limit of the charger. Figure 7 is a simplified delta-sigma is then fixed at a value equal to 80mA, inde-
diagram of the DAC operation. The delta-sigma modulator pendent of the ILIM setting.
and switch convert the ChargingCurrent() value, received
via the SMBus, to a variable resistance equal to: Input FET
1.25RSET/[ChargingCurrent()/ILIM[x]] = RIDC The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
Therefore, programmed current is equal to: and provides an indication of this condition at both the
ICHARGE = (102.3mV/R­SENSE) (ChargingCurrent()/ CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
ILIM[x]), for ChargingCurrent() < ILIM[x]. register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
When a value less than 1/16th of the maximum current
reverse current flow through the input FET.
allowed by ILIM is applied to the current DAC input, the
current DAC enters a different mode of operation called If the input voltage is less than VCLP, it must go at least
LOWI. The current DAC output is pulse width modulated 130mV higher than VCLP to activate the charger. The CHGEN
with a high frequency clock having a duty cycle value of pin is forced low unless this condition is met. The gate
1/8. Therefore, the maximum output current provided by of the input FET is driven to a voltage sufficient to keep
the charger is IMAX/8. The delta-sigma output gates this a low forward voltage drop from drain to source. If the
low duty cycle signal on and off. The delta-sigma shift voltage between DCIN and CLP drops to less than 25mV,
registers are then clocked at a slower rate, about 45ms/ the input FET is turned off slowly. If the voltage between
bit, so that the charger has time to settle to the IMAX/8 DCIN and CLP is ever less than –25mV, then the input FET
value. The resulting average charging current is equal to is turned off quickly to prevent significant reverse current
that requested by the ChargingCurrent() value. from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
IPROG
(FROM CA1 AMP) The AC Present Block (AC_PRESENT)
IDC
– ITH
20
19
The DCDIV pin is used to determine AC presence. If the
+
RSET
VREF
DCDIV voltage is above the DCDIV comparator threshold
(VACP), then the ACP output pin will be switched to VDD and
∆-∑
MODULATOR
CHARGING_CURRENT
VALUE the AC_PRESENT bit in the ChargerStatus() function will be
set. If the DCDIV voltage is below the DCDIV comparator
4100 F07
threshold minus the DCDIV comparator hysteresis, then
the ACP output pin is switched to GND and the AC_PRES-
Figure 7. Current DAC Operation
ENT bit in the ChargerStatus() function is cleared. The
ACP output pin is designed to drive 2mA continuously.
AVERAGE CHARGER CURRENT
ILIMIT/8
0
~40ms 4100 F08

Figure 8. Charging Current Waveform in Low Current Mode

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 LTC4100
applications Information
Adapter Limiting
LTC4100
An important feature of the LTC4100 is the ability to auto- CLP
– 24 VIN
matically adjust charging current to a level which avoids C9
CL1 RCL*
overloading the wall adapter. This allows the product to CLN 0.1µF
+ 23
operate at the same time that batteries are being charged +
R1
100mV 4.99k
without complex load management algorithms. Addition- INFET TO LOAD
ally, batteries will automatically be charged at the maximum 4

possible rate of which the adapter is capable. *RCL =

100mV
ADAPTER CURRENT LIMIT 4100 F09

This feature is created by sensing total adapter output

current and adjusting charging current downward if a Figure 9. Adaptor Current Limiting
preset adapter current limit is exceeded. True analog
As is often the case, the wall adapter will usually have at
control is used, with closed loop feedback ensuring that
least a +10% current limit margin and many times one
adapter load current remains within limits. Amplifier CL1 in
can simply set the adapter current limit value to the actual
Figure 9 senses the voltage across RCL, connected be-
adapter rating (Figure 9).
tween the CLP and CLN pins. When this voltage exceeds
100mV, the amplifier will override programmed charging Charge Termination Issues
current to limit adapter current to 100mV/RCL. A lowpass
filter formed by 4.99k and 0.1µF is required to eliminate Batteries with constant current charging and voltage-
switching noise. If the current limit is not used, CLP should based charger termination might experience problems
be connected to CLN. with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
Setting Input Current Limit defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
To set the input current limit, you need to know the mini-
mum wall adapter current rating. Subtract 7% for the input Setting Output Current Limit (Refer to Figure 1)
current limit tolerance and use that current to determine
the resistor value. The LTC4100 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
RCL = 100mV/ILIM to do so will result in incorrect charge currents.
ILIM = Adapter Min Current
– (Adapter Min Current • 7%)

Table 8. Common RCL Resistor Values

ADAPTER RATING (A) –7% ADAPTER RATING (A) RCL VALUE* (Ω) 1% RCL LIMIT (A) RCL POWER DISSIPATION (W) RCL POWER RATING (W)
1.5 1.40 0.068 1.47 0.15 0.25
1.8 1.67 0.062 1.61 0.16 0.25
2.0 1.86 0.051 1.96 0.20 0.25
2.3 2.14 0.047 2.13 0.21 0.25
2.5 2.33 0.043 2.33 0.23 0.50
2.7 2.51 0.039 2.56 0.26 0.50
3.0 2.79 0.036 2.79 0.28 0.50
3.3 3.07 0.033 3.07 0.31 0.50
3.6 3.35 0.030 3.35 0.33 0.50
4.0 3.72 0.027 3.72 0.37 0.50
* Rounded to nearest 5% standard step value. Many nonstandard values are popular.
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LTC4100
Applications Information
IMAX is the full-scale charge current. Chose the lowest IMAX The transition to low current operation begins when the
value that is still above your expected battery charge cur- inductor current reaches zero while the bottom MOSFET
rent as requested over the SMBus. If you deviate from the is on. Lower inductor values (higher ∆IL) will cause this
resistance values shown in Table 9, it will lead to charge to occur at higher load currents, which can cause a dip in
current gain errors. The requested current and the actual efficiency in the upper range of low current operation. In
charge current applied to the battery will not be the same. practice 10µH is the lowest value recommended for use.
Table 9. Recommended Resistor Values Table 10. Recommended Inductor Values
IMAX (A) RSENSE (Ω) 1% RSENSE (W) RILIM (Ω) 1% Maximum Average Minimum Inductor Value
1.023 0.100 0.25 0 Current (A) Input Voltage (V) (µH)

2.046 0.05 0.25 10k 1 ≤20 40 ± 20%

3.068 0.025 0.5 33k 1 >20 56 ± 20%

4.092 0.025 0.5 Open 2 ≤20 20 ± 20%

2 >20 30 ± 20%
Warning 3 ≤20 15 ± 20%
DO NOT CHANGE THE VALUE OF RILIM DURING OPERA- 3 >20 20 ± 20%
TION. The value must remain fixed and track the RSENSE 4 ≤20 10 ± 20%
value at all times. Changing the current setting can result 4 >20 15 ± 20%
in currents that greatly exceed the requested value and Charger Switching Power MOSFET
potentially damage the battery or overload the wall adapter and Diode Selection
if no input current limiting is provided.
Two external power MOSFETs must be selected for use
Inductor Selection with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn-
Higher operating frequencies allow the use of smaller
chronous) switch.
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate The peak-to-peak gate drive levels are set internally. This
charge losses. In addition, the effect of inductor value voltage is typically 6V. Consequently, logic-level threshold
on ripple current and low current operation must also be MOSFETs must be used. Pay close attention to the BVDSS
considered. The inductor ripple current ∆IL decreases with specification for the MOSFETs as well; many of the logic
higher frequency and increases with higher VIN. level MOSFETs are limited to 30V or less.
1  V  Selection criteria for the power MOSFETs include the on-
∆IL = VOUT  1− OUT 
(f)(L)  VIN  resistance RDS(ON), total gate capacitance QG, reverse

transfer capacitance CRSS, input voltage and maximum
Accepting larger values of ∆IL allows the use of low output current. The charger is operating in continuous
inductances, but results in higher output voltage ripple mode so the duty cycles for the top and bottom MOSFETs
and greater core losses. A reasonable starting point for are given by:
setting ripple current is ∆IL = 0.4(IMAX). Remember the
Main Switch Duty Cycle = VOUT/VIN
maximum ∆IL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation. Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN

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 LTC4100
Applications Information
The MOSFET power dissipations at maximum output Calculating IC Power Dissipation
current are given by:
The power dissipation of the LTC4100 is dependent upon
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆T)RDS(ON) the gate charge of the top and bottom MOSFETs (Q2 &
+ k(VIN)2(IMAX)(CRSS)(fOSC) Q3 respectively) The gate charge (QG) is determined from
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆T)RDS(ON) the manufacturer’s data sheet and is dependent upon both
the gate voltage swing and the drain voltage swing of the
where δ∆T is the temperature dependency of RDS(ON) and MOSFET. Use 6V for the gate voltage swing and VDCIN for
k is a constant inversely related to the gate drive current. the drain voltage swing.
Both MOSFETs have I2R losses while the PMAIN equation
includes an additional term for transition losses, which PD = VDCIN • (fOSC (QGQ2 + QGQ3) + IDCIN) + VDD • IDD
are highest at high input voltages. For VIN < 20V the high Example: VDCIN = 19V, fOSC = 345kHz, QGQ2 = 25nC,
current efficiency generally improves with larger MOSFETs, QGQ3 = 15nC, IDCIN = 5mA, VDD = 5.5V,
while for VIN > 20V the transition losses rapidly increase to IDD = 1mA.
the point that the use of a higher RDS(ON) device with lower PD = 428mW
CRSS actually provides higher efficiency. The synchronous
MOSFET losses are greatest at high input voltage or during Calculating VDD Current
a short circuit when the duty cycle in this switch in nearly
100%. The term (1 + δ∆T) is generally given for a MOSFET The LTC4100 Vdd current, or Idd, consist of three parts:
in the form of a normalized RDS(ON) vs temperature curve, a. Irun = Current due to active clocking and bias inside
but δ = 0.005/°C can be used as an approximation for low the IC.
voltage MOSFETs. CRSS = QGD/∆VDS is usually specified
in the MOSFET characteristics. The constant k = 2 can be b. Ithrm = Current due to thermistor circuit activity.
used to estimate the contributions of the two terms in the c. Iaccel = Current due to SMBus acceleration activity.
main switch dissipation equation. Idd = Irun + Ithrm + Iaccel
If the charger is to operate in low dropout mode or with a) Irun current is basically independent of SCL clock rate.
a high duty cycle greater than 85%, then the topside Once the LTC4100 determines that there is activity on
P‑channel efficiency generally improves with a larger the SMBus, it turns on its internal HF oscillator. This
MOSFET. Using asymmetrical MOSFETs may achieve cost HF oscillator remains on until a stop event occurs or
savings or efficiency gains. SDA and SCL are at logic level 1 for the SMBus timeout
The Schottky diode D1, shown in the typical application period. Then it shuts off the HF oscillator. Thus, the
on the back page, conducts during the dead-time between length of the transmission and the rate of transmission
the conduction of the two power MOSFETs. This prevents bursts are more important in determining how much
the body diode of the bottom MOSFET from turning on current the LTC4100 burns, rather than the SCL rate.
and storing charge during the dead-time, which could cost In the equation below, IQ is the static current the IC
as much as 1% in efficiency. A 1A Schottky is generally consumes as a function of the Vdd voltage when not
a good size for 4A regulators due to the relatively small active. Since it is hard to quantify the actual messages
average current. Larger diodes can result in additional going down the SMBus, one must estimate the SMBus
transition losses due to their larger junction capacitance. activity level in term of bus utilization per second.
The diode may be omitted if the efficiency loss can be Irun = Message Duty Cycle • 950µA
tolerated. + (1 – Message Duty Cycle) • IQ
where IQ (typical) = Vdd /47.2k

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LTC4100
Applications Information
b) Ithrm current is due to SafetySignal (thermistor pin) Complete Examples
sampling that will vary with the presence of DC power 1) Battery thermistor = 400Ω, Vdd = 5.0V
being on or off. DCDIV is detected every 32ms. RTHX
is the value of the safety signal resistance, which will Battery mode (DC is off), SMBus activity is 10kHz
vary with temperature or battery configuration. and a 2% SMBus duty cycle, which represents a
suspended or sleep condition of a notebook.
b1) Ithrm(on) when DC is on:
Itotal = Irun + Ithrm(off) + Iaccel = 121.9µA
Ithrm(On)_OverRange = 1/16 • Vdd /(54.9k + RTHX) + 5.26µA + 2.44µA = 130µA
where RTHX > 100k
Battery mode and a 10% SMBus duty cycle, which
Ithrm(On)_Cold = 1/8 • Vdd /(54.9k + RTHX) where represents an active notebook at idle.
RTHX > 30k
Itotal = Irun + Ithrm(off) + Iaccel = 189.5µA
Ithrm(On)_normal = 1/8 • Vdd /(54.9k + RTHX) + 5.26µA + 12.2µA = 207µA
+ 1/16 • Vdd/(1.13k + RTHX)
DCIN = ON and a 20% SMBus duty cycle which
Ithrm(On)_hot* = 1/8 • Vdd /(54.9k + RTHX)
represents an active notebook charging.
+ 1/8 • Vdd /(1.13k + RTHX)
where RTHX < 3k Itotal = Irun + Ithrm(On) + Iaccel = 274µA
*= includes underrange + 215.6µA + 24.4µA = 514µA
b2) Ithrm(off) when DC is off, the thermistor monitoring 2) Battery thermistor = 10kΩ, Vdd = 5.0V
rate is reduced to every 250ms or less. Battery mode (DC is off), SMBus activity is 10kHz
Ithrm(Off)_OverRange = 1/50 • Vdd /(54.9k + RTHX) and a 2% SMBus duty cycle:
where RTHX > 100K Itotal = Irun + Ithrm(off) + Iaccel = 121.9µA
Ithrm(Off)_Cold = 1/50 • Vdd /(54.9k + RTHX) + 2.14µA + 2.44µA = 126µA
+ 1/1000 • Vdd /(54.9k + RTHX) Battery mode and a 10% SMBus duty cycle:
where RTHX > 30K
Itotal = Irun + Ithrm(off) + Iaccel = 189.5µA
Ithrm(Off)_normal = 1/50 • Vdd /(54.9k + RTHX) + + 2.14µA + 12.2µA = 204µA
1/500 • Vdd /(54.9k + RTHX) + 1/1000 • Vdd /(1.13k
+ RTHX) DCIN = ON and a 20% SMBus duty cycle:

Ithrm(Off)_hot* = 1/50 • Vdd /(54.9k + RTHX) + Itotal = Irun + Ithrm(off) + Iaccel = 274µA
1/500 • Vdd /(54.9k + RTHX) + 1/500 • Vdd /(1.13k + + 37.7µA + 24.4µA = 336µA
RTHX)
where RTHX < 3k
* includes underrange
c) Iaccel is the current used by the SMBus accelerators.
This directly depends on the SMBus frequency, duty
cycle of messages sent on the SMBus and how long
it takes to drive the SMBus to Vdd.
Iaccel = Ipull-up • 2 • SMBus Frequency •
Message Duty Cycle •Vdd /2.25V• Rise Time

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 LTC4100
Applications Information
Soft-Start and Undervoltage Lockout hot-plugged into the charger or when a battery is con-
The LTC4100 is soft-started by the 0.12µF capacitor on nected to the charger. Use only “surge robust” low ESR
the ITH pin. On start-up, ITH pin voltage will rise quickly tantalums. Regardless of which type of capacitor you
to 0.5V, then ramp up at a rate set by the internal 30µA use, after voltage selection, the most important thing
pull-up current and the external capacitor. Battery charging to meet is the ripple current requirements followed by
current starts ramping up when ITH voltage reaches 0.8V the capacitance value. By the time you solve the ripple
and full current is achieved with ITH at 2V. With a 0.12µF current requirements, the minimum capacitance value is
capacitor, time to reach full charge current is about 2ms often met by default. The following equation shows the
and it is assumed that input voltage to the charger will reach minimum COUT (±20% tolerance) capacitance values for
full value in less than 2ms. The capacitor can be increased stability when used with the compensation shown in the
up to 1µF if longer input start-up times are needed. typical application on the back page.
In any switching regulator, conventional timer-based COUT(MIN) = 200/L1
soft-starting can be defeated if the input voltage rises much The use of aluminum electrolytic for C1, located at the
slower than the time out period. This happens because AC adapter input terminal, is helpful in reducing ringing
the switching regulators in the battery charger and the during the hot-plug event. Refer to Application Note 88
computer power supply are typically supplying a fixed for more information.
amount of power to the load. If input voltage comes up
slowly compared to the soft-start time, the regulators will In the 4A lithium battery charger (typical application on
try to deliver full power to the load when the input voltage back page), the input capacitor (C2) is assumed to absorb
is still well below its final value. If the adapter is current all input switching ripple current in the converter, so it
limited, it cannot deliver full power at reduced output must have adequate ripple current rating. Worst-case RMS
voltages and the possibility exists for a quasi “latch” state ripple current will be equal to one half of output charging
where the adapter output stays in a current limited state at current. C2 is recommended to be equal to or greater than
reduced output voltage. For instance, if maximum charger C4 (output capacitor) in capacitance value.
plus computer load power is 30W, a 15V adapter might The output capacitor (C4) is also assumed to absorb
be current limited at 2.5A. If adapter voltage is less than output switching current ripple. The general formula for
(30W/2.5A = 12V) when full power is drawn, the adapter capacitor current is:
voltage will be pulled down by the constant 30W load
 V 
until it reaches a lower stable state where the switching 0.29(VBAT ) •  1− BAT 
regulators can no longer supply full load. This situation  VDCIN 
IRMS =
can be prevented by utilizing the DCDIV resistor divider, L1• f

set higher than the minimum adapter voltage where full
For example, VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
power can be achieved.
f = 300kHz, IRMS = 0.41A.
Input and Output Capacitors EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or induc-
We recommend the use of high capacity low ESR/ESL tors may be added to increase battery impedance at the
X5R type ceramic capacitors. Alternative capacitors 300kHz switching frequency. Switching ripple current splits
include OSCON or POSCAP type capacitors. Aluminum between the battery and the output capacitor depending
electrolytic capacitors are not recommended for poor on the ESR of the output capacitor and the battery imped-
ESR and ESL reasons. Solid tantalum low ESR capacitors ance. If the ESR of C3 is 0.2Ω and the battery impedance
are acceptable, but caution must be used when tantalum is raised to 4Ω with a bead or inductor, only 5% of the
capacitors are used for input or output bypass. High input current ripple will flow in the battery.
surge currents can be created when the power adapter is
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LTC4100
Applications Information
Protecting SMBus Inputs VDD

The SMBus inputs, SCL and SDA, are exposed to uncon-

trolled transient signals whenever a battery is connected CONNECTOR TO SYSTEM
to the system. If the battery contains a static charge, the TO BATTERY

SMBus inputs are subjected to transients which can cause

damage after repeated exposure. Also, if the battery’s posi- 4100 F10

tive terminal makes contact to the connector before the

Figure 10. Recommended SMBus Transient Protection
negative terminal, the SMBus inputs can be forced below
ground with the full battery potential, causing a potential
for latch-up in any of the devices connected to the SMBus
inputs. Therefore it is good design practice to protect the SWITCH NODE
L1
SMBus inputs as shown in Figure 10. VBAT

SafetySignal (Thermistor) Value HIGH

FREQUENCY
VIN C2 D1 C4 BAT
The SafetySignal (typical application on back page), is a CIRCULATING
PATH
multifunction signal the communicates three pieces of
information in order of importance:
1) Presence of the Smart Battery
4100 F11

Figure 11. High Speed Switching Path

2) The maximum time duration of the wake-up charge
allowed.
3) An optional and redundant temperature measurement
DIRECTION OF CHARGING CURRENT
system.
The value of the resistance to ground communicates all
this information. The resistance ranges and what it does RSENSE

is covered by the SBS Smart Battery Charger standard in

Section 6. Basically if you have a battery chemistry, such VIAS TO CSP AND BAT
as Li-ion, that cannot safely withstand an infinite duration
wake-up charge, the SafetySignal resistance value needs
4100 F12

to be less than 425Ω. The popular value to use is a fixed Figure 12. Kelvin Sensing of Charging Current
300Ω resistor. Otherwise the resistance value is 10k which
is normally expected to be done using a 10k NTC resistor.

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 LTC4100
Applications Information
PCB Layout Considerations 4. Place the output current sense resistor right next to
For maximum efficiency, the switch node rise and fall times the inductor output but oriented such that the IC’s
should be minimized. To prevent magnetic and electrical current sense feedback traces going to resistor are not
field radiation and high frequency resonant problems, long. The feedback traces need to be routed together
proper layout of the components connected to the IC is as a single pair on the same layer at any given time
essential. (See Figure 11.) Here is a PCB layout priority list with smallest trace spacing possible. Locate any filter
for proper layout. Layout the PCB using this specific order. component on these traces next to the IC and not at
the sense resistor location.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections. 5. Place output capacitors next to the sense resistor
Shortest copper trace connections possible. These output and ground.
parts must be on the same layer of copper. Vias must 6. Output capacitor ground connections need to feed
not be used to make this connection. into same copper that connects to the input capacitor
2. The control IC needs to be close to the switching FET’s ground before tying back into system ground.
gate terminals. Keep the gate drive signals short for
Interfacing with a Selector
a clean FET drive. This includes IC supply pins that
connect to the switching FET source pins. The IC can The LTC4100 is designed to be used with a true analog
be placed on the opposite side of the PCB relative to multiplexer for the SafetySignal sensing path. Some
above. selector ICs from various manufacturers may not imple-
ment this. Consult LTC applications department for more
3. Place inductor input as close as possible to switching information.
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount Electronic Loads
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in The LTC4100 is designed to work with a real battery.
parallel. Minimize capacitance from this node to any Electronic loads will create instability within the LTC4100
other trace or plane. preventing accurate programming currents and volt-
ages. Consult LTC applications department for more
information.

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LTC4100
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)

7.90 – 8.50*
1.25 ±0.12
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13

7.8 – 8.2 5.3 – 5.7

7.40 – 8.20
(.291 – .323)

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12
5.00 – 5.60** 2.0
(.197 – .221) (.079)
MAX

0° – 8°

0.65
0.09 – 0.25 0.55 – 0.95
(.0256)
(.0035 – .010) (.022 – .037)
BSC 0.05
0.22 – 0.38 (.002)
NOTE:
(.009 – .015) MIN
1. CONTROLLING DIMENSION: MILLIMETERS
TYP G24 SSOP 0204
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

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 LTC4100
Revision History (Revision history begins at Rev B)

REV DATE DESCRIPTION PAGE NUMBER

B 10/09 Add Table to Typical Application 1
Text Added to Pin Functions 8
Text Changes to Operation Section 11, 12, 15
Changes to Table 1 13
Added ‘Calculating VDD Current’ Section 23
Updated ‘Input and Output Capacitors’ Section 25
Added ‘SafetySignal (Thermistor) Value’ Section 26
Changes to Typical Application 29
C 02/14 SafetySignal Trip conditions: changed the value of RTHB from 54.9Ω to 54.9kΩ 4

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However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC4100
as described herein will not infringe on existing patent rights. 29
LTC4100
Typical Application
LTC4100 Li-Ion Battery Charger ILIM = 4A/VLIM = 17.4V, Adapter Rating = 2.7A
RCL
0.033Ω
DCIN
0.5W
Q1 1%
15V TO 20V
SYSTEM
DCIN
C9 LOAD
FROM WALL C1 R1
0.1µF
ADAPTER 0.1µF 4.9k DCIN D6
10V
100k
R10 4 24 23 Q4
13.7k
INFET CLP CLN
1% 5 1
DCIN TGATE Q2
C2, C3
11 10µF × 2
DCDIV
R11 25V
R5
1.21k 3 X5R
6.04k BGATE Q3 D1 OPTIONAL
1% 1% 19 DISCHARGE
2
ITH PGND PATH TO
C6, 0.12µF
L1 SYSTEM
10V, X7R
10µH LOAD
C7, 0.0015µF LTC4100
4A
10V, X7R 20 21
IDC CSP
C8, 0.068µF RSNS C4,C5
10V, X7R 12 0.025Ω 10µF × 2
GND 0.5W, 1% 25V
0.1µF 22
BAT X5R
10V 17
VDD
R6, RVLIM 33k 14 C4 4-CELL Li-Ion
VLIM 0.01µF SMART BATTERY
R4
25V
13 18 100Ω
ILIM VSET
C5
10 0.1µF RTHA 300Ω
ACP 1.13k SafetySignal
10V
3V TO 5.5V 6 16 1%
CHGEN THA
10k 10k D2 SDA
7 15
SDA SMBALERT THB SCL
RTHB
D3 8
SDA 54.9k
D4 1%
9 D1: MBRM140T3G
SCL SCL
D2-D5: SMALL SIGNAL SCHOTTKY
D5 4100 TA02
D6: 18V ZENER DIODE
Q1: 1/2 Si4925BDY
Q2: FDS6685
Q3: FDC645N
Q4: 1/2 Si4925

Related Parts
PART NUMBER DESCRIPTION COMMENTS
LTC1760 Smart Battery System Manager Autonomous Power Management and Battery Charging for Two Smart Batteries,
SMBus Rev 1.1 Compliant
LTC1960 Dual Battery Charger/Selector with SPI Interface Simultaneous Charge or Discharge of 2 Batteries, DAC Programmable Current
and Voltage, Input Current Limiting Maximizes Charge Current
LTC1980 Combination Battery Charger and DC/DC Converter Input Supply May be Above or Below Battery Voltage, up to 8.4V Float Voltage,
24-Pin SSOP Package
LTC4006 Small, High Efficiency, Fixed Voltage, Lithium-Ion Constant Current/Constant Voltage Switching Regulator with Termination Timer,
Battery Charger AC Adapter Current Limit and SafetySignal Sensor in a Small 16-Pin Package
LTC4007 High Efficiency, Programmable Voltage Battery Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit,
Charger with Termination SafetySignal Sensor and Indicator Outputs
LTC4008 High Efficiency, Programmable Voltage/Current Constant Current/Constant Voltage Switching Regulator; Resistor Voltage/
Battery Charger Current Programming, AC Adapter Current Limit and SafetySignal Sensor
LTC4101 Smart Battery Charger Controller For Smart Batteries with Voltages Below 5.5V
LTC4412 Low Loss PowerPath™ Controller Very Low Loss Replacement for Power Supply ORing Diodes Using Minimal
External Components

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