a

A Broadband Modem
Mixed-Signal Front End
AD9876
FEATURES FUNCTIONAL BLOCK DIAGRAM
Low Cost 3.3 V CMOS Mixed-Signal Front End (MxFE™)
Converter for Broadband Modems
PWR DN AD9876
10-/12-Bit D/A Converter (TxDAC+®)
Tx QUIET
64/32 MSPS Input Word Rate
GAIN 12 12 Tx+
2
/4
Interpolating LPF or BPF Transmit Filter Tx [5:0]
Tx Kx INTERPOLATION TxDAC+
MUX LPF/BPF Tx–
128 MSPS DAC Output Update Rate Tx SYNC

Wide (26 MHz) Transmit Bandwidth

Power-Down Mode
10-/12-Bit 50 MSPS A/D Converter PLL-A
VREF

L
Fourth Order Low-Pass Filter 12 MHz or 26 MHz CLK-A
GATE

with Bypass CLOCK GEN VRC FB

–6 dB to +36 dB Programmable Gain Amplifier CLK-B OSCIN

PLL-B
Internal Clock Multiplier (PLL)
M/N XTAL
Rx SYNC
Clock Outputs
Voltage Regulator Controller
Rx Rx+
48-Lead LQFP Package Rx [5:0]
MUX ADC PGA LPF PGA
12 Rx–
APPLICATIONS
Powerline Networking SPORT
3 REGISTER
CONTROL
Home Phone Networking
xDSL
Broadband Wireless
Home RF

PRODUCT DESCRIPTION path LPF cutoff frequency can be programmed to either 12 MHz
The AD9876 is a single-supply broadband modem mixed-signal or 26 MHz. The filter cutoff frequency can also be tuned or
front end (MxFE) IC. The device contains a transmit path bypassed where filter requirements differ. The 12-bit ADC uses
interpolation filter and DAC and a receive path PGA, LPF, and a multistage differential pipeline architecture to achieve excellent
ADC supporting a variety of broadband modem applications. dynamic performance with low power consumption.
Also on-chip is a PLL clock multiplier that provides all required The AD9876 provides a voltage regulator controller (VRC) that
clocks from a single crystal or clock input. The AD9876 provides can be used with an external power MOSFET transistor to form
12-bit converter performance on both the Tx and Rx path. a cost-effective 1.3 V linear regulator.
The TxDAC+ uses a selectable digital 2× or 4× interpolation The digital transmit and receive ports are each multiplexed to a
low-pass or band-pass filter to further oversample transmit data bus width of six bits and are clocked at a frequency of twice the
and reduce the complexity of analog reconstruction filtering. 12-bit word rate.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64 MSPS. The 12-bit DAC provides The AD9876 ADC and/or DAC can also be used at sampling
differential current outputs for optimum noise and distortion rates as high as 64 MSPS in a 6-bit resolution nonmulti-
performance. The DAC full-scale current can be adjusted from plexed mode.
2 to 20 mA by a single resistor, providing 20 dB of additional The AD9876 is pin compatible with the 10-bit AD9875. Both are
gain range. available in a space-saving 48-lead LQFP package. They are speci-
The receive path consists of a PGA, LPF, and ADC. The PGA has fied over the industrial (–40°C to +85°C) temperature range.
a gain range of –6 dB to +36 dB, programmable in 2 dB steps,
adding 42 dB of dynamic range to the receive path. The receive

MxFE is a trademark of Analog Devices, Inc.

TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. 2Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD9876–SPECIFICATIONS (V100=3.3DACV 10%, f = 32 MHz, f = 128 MHz, Gain = –6 dB, R
S OSCIN DAC
single-ended load, unless otherwise noted. )
SET = 4.02 k,

Test
Parameter Temp Level Min Typ Max Unit
OSCIN CHARACTERISTICS
Frequency Range Full II 10 64 MHz
Duty Cycle Full II 40 50 60 %
Input Capacitance 25°C III 3 pF
Input Impedance 25°C III 100 M⍀
CLOCK OUTPUT CHARACTERISTICS
CLK A Jitter (fCLKA Derived from PLL) 25°C III 14 ps rms
CLK A Duty Cycle 25°C III 50 ± 5 %
CLK B Jitter (fCLKB Derived from PLL) 25°C III 33 ps rms
CLK B Duty Cycle 25°C III 50 ± 5 %
Tx CHARACTERISTICS
Tx Path Latency, 4× Interpolation Full II 86 fDAC Cycles
Interpolation Filter Bandwidth (–0.1 dB)
4× Interpolation, LPF Full II 13 MHz
2× Interpolation, LPF Full II 26 MHz
TxDAC
Resolution Full II 12 Bits
Conversion Rate Full II 10 128 MHz
Full-Scale Output Current Full II 2 10 20 mA
Voltage Compliance Range Full II –0.5 +1.5 V
Gain Error Full II –5 ±2 +5 % FS
Output Offset (Single-Ended) Full II 0 2 5 µA
Differential Nonlinearity Full III ±1 LSB
Integral Nonlinearity 25°C III ±2 LSB
Output Capacitance 25°C III 5 pF
Phase Noise @ 1 kHz Offset, 10 MHz Signal 25°C III –100 dBc/Hz
Signal-to-Noise and Distortion (SINAD)
10 MHz Analog Out AD9876 (20 MHz BW) Full I 62.5 65 dB
Wideband SFDR (to Nyquist, 64 MHz Max) 25°C III
5 MHz Analog Out 25°C III 80 dBc
10 MHz Analog Out 25°C III 74 dBc
Narrow-Band SFDR (3 MHz Window):
10 MHz Analog Out 25°C III 88 dBc
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz) 25°C III –80 dBFS
Rx PATH CHARACTERISTICS
Resolution NA NA 12 Bits
Conversion Rate Full II 7.5 64 MHz
Pipeline Delay, ADC Clock Cycles NA NA 5.5 Cycles
DC Accuracy
Differential Nonlinearity Full II –1.0 ± 0.25 +1.0 LSB
Integral Nonlinearity Full II –4.5 ± 0.5 +3.5 LSB
Dynamic Performance (ADC Clocked Direct)
(AIN = –0.5 dBFS, f = 5 MHz)
@ fOSCIN = 32 MHz
Signal-to-Noise and Distortion Ratio (SINAD) Full I 60.8 63.2 dB
Effective Number of Bits (ENOB) Full I 9.8 10.2 Bits
Signal-to-Noise Ratio (SNR) 25°C III 64 dB
Total Harmonic Distortion (THD) 25°C III –70 dB
Spurious-Free Dynamic Range (SFDR) 25°C III 72 dB
Dynamic Performance (ADC Clocked, PLLB/2)
(AIN = –0.5 dBFS, f = 5 MHz)
@ FPLLB/2 = 50 MHz
Signal-to-Noise and Distortion Ratio (SINAD) 25°C III 56 dB
Effective Number of Bits (ENOB) 25°C III 9.3 Bits
Signal-to-Noise Ratio (SNR) 25°C III 59 dB
Total Harmonic Distortion (THD) 25°C III –63 dB
Spurious-Free Dynamic Range (SFDR) 25°C III 68 dB

–2– REV. A
 AD9876
Test
Parameter Temp Level Min Typ Max Unit
Rx PATH GAIN/OFFSET
Minimum Programmable Gain 25°C III –6 dB
Maximum Programmable Gain (12 MHz Filter) 25°C III 36 dB
Maximum Programmable Gain (26 MHz Filter) 25°C III 30 dB
Gain Step Size 25°C III 2 dB
Gain Step Accuracy 25°C III ± 0.4 dB
Gain Range Error 25°C III ± 1.0 dB
Offset Error, PGA Gain = 0 dB 25°C III ± 10 LSB
Absolute Gain Error 25°C III ± 0.8 dB
Rx PATH INPUT CHARACTERISTICS
Input Voltage Range Full III 4 Vppd
Input Capacitance 25°C III 4 pF
Differential Input Resistance 25°C III 270 Ω
Input Bandwidth (–3 dB) 25°C III 50 MHz
Input Referred Noise (at –36 dB Gain with Filter) 25°C III 16 µV rms
Input Referred Noise (at –6 dB Gain with Filter) 25°C III 684 µV rms
Common-Mode Rejection 25°C III 40 dB
Rx PATH LPF (Low Cutoff Frequency)
Cutoff Frequency 25°C III 12 MHz
Cutoff Frequency Variation 25°C III ±7 %
Attenuation @ 22 MHz 25°C III 20 dB
Pass-Band Ripple 25°C III ± 1.0 dB
Group Delay Variation 25°C III 30 ns
Settling Time
(to 1% FS, Min to Max Gain Change) 25°C III 150 ns
Total Harmonic Distortion at Max Gain (THD) 25°C III –68 dBc
Rx PATH LPF (High Cutoff Frequency)
Cutoff Frequency 25°C III 26 MHz
Cutoff Frequency Variation 25°C III ±7 %
Attenuation @ 44 MHz 25°C III 20 dB
Pass-Band Ripple 25°C III ± 1.2 dB
Group Delay Variation 25°C III 15 ns
Settling Time
(to 1% FS, Min to Max Gain Change) 25°C III 80 ns
Total Harmonic Distortion at Max Gain (THD) 25°C III –65 dBc
Rx PATH DIGITAL HPF
Latency (ADC Clock Source Cycles) Full II 1 Cycle
Roll-Off in Stop Band Full II 6 dB/Octave
–3 dB Frequency Full II fADC /400 Hz
Rx PATH DISTORTION PERFORMANCE
IMD: f1 = 6.5 MHz, f2 = 7.7 MHz
12 MHz Filter : 0 dB Gain 25°C III –65 dBc
: 30 dB Gain 25°C III –57 dBc
26 MHz Filter : 0 dB Gain 25°C III –65 dBc
: 30 dB Gain 25°C III –56 dBc
POWER-DOWN/DISABLE TIMING
DAC IOUT OFF after Tx QUIET Asserted Full II 200 ns
DAC IOUT ON after Tx QUIET De-Asserted Full II 1 µs
Power-Down Delay (Active to Power-Down)
DAC Full II 400 ns
Interpolator Full II 200 ns
Power-Up Delay (Power-Down to Active)
DAC Full II 40 µs
PLL Full II 10 µs
ADC Full II 1000 µs
PGA Full II 1 µs
LPF Full II 1 µs
Interpolator Full II 200 ns
VRC Full II 2 µs
Minimum RESET Pulsewidth Low (tRL) Full II 5 fOSCIN Cycles

REV. A –3–
AD9876
Test
Parameter Temp Level Min Typ Max Unit
Tx PATH INTERFACE
Maximum Input Nibble Rate, 2× Interpolation Full II 128 MHz
Tx Setup Time (tSU) Full II 3.0 ns
Tx Hold Time (tHD) Full II 0 ns
Rx PATH INTERFACE
Maximum Output Nibble Rate Full II 110 MHz
Rx Data Valid Time (tVT) Full II 3.0 ns
Rx Data Hold Time (tHT) Full II 1.5 ns
SERIAL CONTROL BUS
Maximum SCLK Frequency (fSCLK) Full II 25 MHz
Clock Pulsewidth High (tPWH) Full II 18 ns
Clock Pulsewidth Low (tPWL) Full II 18 ns
Clock Rise/Fall Time Full II 1 ms
Data/Chip-Select Setup Time (tDS) Full II 25 ns
Data Hold Time (tDH) Full II 0 ns
Data Valid Time (tDV) Full II 20 ns
CMOS LOGIC INPUTS
Logic “1” Voltage Full II VDRVDD – 0.7 V
Logic “0” Voltage Full II 0.4 V
Logic “1” Current Full II 12 µA
Logic “0” Current Full II 12 µA
Input Capacitance 25°C III 3 µF
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage Full II VDRVDD – 0.6 V
Logic “0” Voltage Full II 0.4 V
Digital Output Rise/Fall Time Full II 1.5 2.5 ns
POWER SUPPLY
All Blocks Powered Up
IS_TOTAL (Total Supply Current) Full I 262 288 mA
IS_TOTAL (Tx QUIET Pin Asserted) 25°C III 172 mA
Digital Supply Current (IDRVDD + IDVDD) 25°C III 77 mA
Analog Supply Current (IAVDD) 25°C III 185 mA
Power Consumption of Functional Blocks:
Rx LPF 25°C III 110 mA
ADC and SPGA 25°C III 55 mA
Rx Reference 25°C III 2 mA
Interpolator 25°C III 33 mA
DAC 25°C III 18 mA
PLL-B 25°C III 8 mA
PLL-A 25°C III 24 mA
Voltage Regulator Controller 25°C III 1 mA
All Blocks Powered Down
Supply Current IS, fOSCIN = 32 MHz Full II 19 22 mA
Supply Current IS, fOSCIN Idle Full II 10 12 mA
Power Supply Rejection
Tx Path (∆VS = ⫾10%) 25°C III 62 dB
Rx Path (∆VS = ⫾10%) 25°C III 54 dB
RECEIVE-TO-TRANSMIT ISOLATION
(10 MHz, Full-Scale Sine Wave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB 25°C III –75 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB 25°C III –70 dB
VOLTAGE REGULATOR CONTROLLER
Output Voltage (VFB with SI2301 Connected) Full I 1.25 1.30 1.35 V
Line Regulation (∆VFB%/∆VDVDD% × 100%) 25°C III 100 %
Load Regulation (∆VFB/∆ILOAD) 25°C III 60 mΩ
Maximum Load Current (ILOAD) Full II 250 mA
Specifications subject to change without notice.

–4– REV. A
 AD9876
ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS
Power Supply (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V I – Devices are 100% production tested at 25°C and guaran-
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA teed by design and characterization testing for industrial
Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V operating temperature range (–40°C to +85°C).
Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V II – Parameter is guaranteed by design and/or characteriza-
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C tion testing.
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C III – Parameter is a typical value only.
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C THERMAL CHARACTERISTICS
*Stresses greater than those listed under Absolute Maximum Ratings may cause Thermal Resistance
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the 48-Lead LQFP
operational section of this specification is not implied. Exposure to absolute ␪JA = 57°C/W
maximum rating conditions for extended periods may affect device reliability. ␪JC = 28°C/W

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9876BST –40°C to +85°C 48-Lead LQFP ST-48
AD9876-EB –40°C to +85°C Evaluation Board
AD9876BSTRL –40°C to +85°C BST Reel

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD9876 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

REV. A –5–
AD9876
PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 OSCIN Crystal Oscillator Inverter Input
2 SENABLE Serial Bus Enable Input
3 SCLK Serial Bus Clock Input
4 SDATA Serial Bus Data I/O
5, 38, 47 AVDD Analog 3.3 V Power Supply
6, 9, 39, 42, 43, 46 AVSS Analog Ground
7 Tx+ Transmit DAC+ Output
8 Tx– Transmit DAC– Output
10 FSADJ DAC Full-Scale Output Current Adjust with External Resistor
11 REFIO DAC Band Gap Decoupling Node
12 PWR DN Power-Down Input
13 DVSS Digital Ground
14 DVDD Digital 3.3 V Power Supply
15 FB Regulator Feedback Input
16 GATE Regulator Output to FET Gate
17 GAIN Transmit Data Port (Tx [5:0]) Mode Select Input
18 Tx QUIET Transmit Quiet Input
19–24 Tx [5:0] Transmit Data Input
25 Tx SYNC Transmit Synchronization Strobe Input
26 CLK-A L × fOSCIN Clock Output
27 CLK-B M/N × fOSCIN Clock Output
28 Rx SYNC Receive Data Synchronization Strobe Output
29–34 Rx[5:0] Receive Data Output
35 DRVDD Digital I/O 3.3 V Power Supply
36 DRVSS Digital I/O Ground
37 RESET Reset Input
40 REFB ADC Reference Decoupling Node
41 REFT ADC Reference Decoupling Node
44 Rx+ Receive Path + Input
45 Rx– Receive Path – Input
48 XTAL Crystal Oscillator Inverter Output

PIN CONFIGURATION
RESET
AVDD

AVDD
AVSS

AVSS
AVSS

REFB
AVSS
XTAL

REFT
Rx+
Rx–

48 47 46 45 44 43 42 41 40 39 38 37

OSCIN 1 36 DRVSS
PIN 1
SENABLE 2 IDENTIFIER 35 DRVDD
SCLK 3 34 Rx [0]
SDATA 4 33 Rx [1]
AVDD 5 32 Rx [2]
AVSS 6 AD9876 31 Rx [3]
Tx+ 7 TOP VIEW
(Not to Scale)
30 Rx [4]
Tx– 8 29 Rx [5]
AVSS 9 28 Rx SYNC
FSADJ 10 27 CLK-B
REFIO 11 26 CLK-A
PWR DN 12 25 Tx SYNC

13 14 15 16 17 18 19 20 21 22 23 24
DVSS
DVDD
FB
GATE
GAIN
Tx QUIET
Tx [5]
Tx [4]
Tx [3]
Tx [2]
Tx [1]
Tx [0]

–6– REV. A
 AD9876
DEFINITIONS OF SPECIFICATIONS OFFSET ERROR
CLOCK JITTER First transition should occur for an analog value 1/2 LSB above
The clock jitter is a measure of the intrinsic jitter of the PLL negative full scale. Offset error is defined as the deviation of the
generated clocks. It is a measure of the jitter from one rising actual transition from that point.
and of the clock with respect to another edge of the clock nine
cycles later. GAIN ERROR
The first code transition should occur at an analog value 1/2 LSB
DIFFERENTIAL NONLINEARITY ERROR above negative full scale. The last transition should occur for an
(DNL, NO MISSING CODES) analog value 1 1/2 LSB below the nominal full scale. Gain error
An ideal converter exhibits code transitions that are exactly 1 LSB is the deviation of the actual difference between the first and
apart. DNL is the deviation from this ideal value. Guaranteed last code transitions and the ideal difference between the first
no missing codes to 10-bit resolution indicates that all 1024 and last code transitions.
codes, respectively, must be present over all operating ranges.
INPUT REFERRED NOISE
INTEGRAL NONLINEARITY ERROR (INL) The rms output noise is measured using histogram techniques.
Linearity error refers to the deviation of each individual code The ADC output codes’ standard deviation is calculated in LSB
from a line drawn from “negative full scale” through “positive and converted to an equivalent voltage. This results in a noise
full scale.” The point used as negative full scale occurs 1/2 LSB figure that can be directly referred to the Rx input of the AD9876.
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
measured from the middle of each particular code to the true SINAD is the ratio of the rms value of the measured input signal to
straight line. the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
PHASE NOISE SINAD is expressed in decibels.
Single-sideband phase noise power density is specified relative to
the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the EFFECTIVE NUMBER OF BITS (ENOB)
carrier. Phase noise can be measured directly on a generated For a sine wave, SINAD can be expressed in terms of the num-
single tone with a spectrum analyzer that supports noise marker ber of bits. Using the following formula:
N = (SINAD – 1.76) dB 6.02
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It also it is possible to get a measure of performance expressed as N,
adds a correction factor that compensates for the implementation the effective number of bits.
of the resolution bandwidth, log display, and detector characteristic.
SIGNAL-TO-NOISE RATIO (SNR)
OUTPUT COMPLIANCE RANGE SNR is the ratio of the rms value of the measured input signal to
The range of allowable voltage at the output of a current-output the rms sum of all other spectral components below the Nyquist
DAC. Operation beyond the maximum compliance limits may frequency, excluding harmonics and dc. The value for SNR is
cause either output stage saturation, resulting in nonlinear per- expressed in decibels.
formance or breakdown.
TOTAL HARMONIC DISTORTION (THD)
SPURIOUS–FREE DYNAMIC RANGE (SFDR) THD is the ratio of the rms sum of the first six harmonic com-
The difference, in dB, between the rms amplitude of the DACs ponents to the rms value of the measured input signal and is
output signal (or ADCs input signal) and the peak spurious expressed as a percentage or in decibels.
signal over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted). POWER SUPPLY REJECTION
Power supply rejection specifies the converters maximum
PIPELINE DELAY (LATENCY) full-scale change when the supplies are varied from nominal to
The number of clock cycles between conversion initiation and minimum and maximum specified voltages.
the associated output data being made available.

REV. A –7–
AD9876 –Typical Tx Digital Filter Performance Characteristics
10 10

0 0

–10 INTERPOLATION –10

FILTER
–20 –20 INTERPOLATION
FILTER
MAGNITUDE – dB

MAGNITUDE – dB
–30 –30
INCLUDING SIN(X)/X
–40 INCLUDING SIN(X)/X –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED – fs NORMALIZED – fS

TPC 1. 4
Low-Pass Interpolation Filter TPC 4. 2
Band-Pass Interpolation Filter, fS /2 Modula-

tion, Adjacent Image Preserved

10 10
INTERPOLATION INTERPOLATION
0 0
FILTER FILTER
–10 –10

–20 MAGNITUDE – dB –20

MAGNITUDE – dB

–30 INCLUDING SIN(X)/X –30 INCLUDING SIN(X)/X

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED – fS NORMALIZED – fS

TPC 2. 2
Low-Pass Interpolation Filter TPC 5. 4
Band-Pass Interpolation Filter, fS /4 Modulation,

Lower Image Preserved

10 10
INTERPOLATION INTERPOLATION INCLUDING SIN(X)/X
0 0 FILTER
FILTER
–10 –10

–20 –20
MAGNITUDE – dB
MAGNITUDE – dB

–30 –30
INCLUDING SIN(X)/X
–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED – fS NORMALIZED – fS

TPC 3. 4
Band-Pass Interpolation Filter, fS /2 Modula- TPC 6. 4
Band-Pass Interpolation Filter, fS /4 Modulation,
tion, Adjacent Image Preserved Upper Image Preserved

–8– REV. A
 AD9876
Typical AC Characteristics Curves for TxDAC+( (R SET = 4.02 k, RDAC = 100 )
10 80

0
75
–10

–20
MAGNITUDE – dBc

70

MAGNITUDE – dBc
–30
fDATA = 50MSPS
–40 65

–50
60
–60

–70
55 fDATA = 32MSPS
–80

–90 50
0 13 26 38 51 64 77 90 102 115 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
FREQUENCY – MHz fOUT – MHz

TPC 7. Single-Tone Spectral Plot @ fDATA = 32 MSPS, TPC 10. Out-of-Band SFDR vs. fOUT @ fDATA = 32 MSPS
fOUT = 5 MHz, 4
LPF and 50 MSPS

10 90

0
85
–10

–20
MAGNITUDE – dBc

80
MAGNITUDE – dBc

–30
fDATA = 32MSPS
–40 75

–50
70
–60
fDATA = 50MSPS
–70
65
–80

–90 60
0 10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
FREQUENCY – MHz fOUT – MHz

TPC 8. Single-Tone Spectral Plot @ fDATA = 50 MSPS, TPC 11. In-Band SFDR vs. fOUT @ fDATA = 32 MSPS
fOUT = 11 MHz, 2
LPF and 50 MSPS

10 10

0 0

–10 –10

–20 –20
MAGNITUDE – dBc
MAGNITUDE – dBc

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5
FREQUENCY – MHz FREQUENCY – MHz

TPC 9. Dual-Tone Spectral Plot @ fDATA = 32 MSPS, TPC 12. Dual-Tone Spectral Plot @ fDATA = 50 MSPS,
fOUT = 6.9 MHz and 7.1 MHz, 4
LPF fOUT = 6.9 MHz and 7.1 MHz, 2
LPF

REV. A –9–
AD9876
Typical AC Characteristics Curves for TxDAC (R SET = 4.02 k, RDAC = 100 )
10 10

0
0
–10

–20 –10

MAGNITUDE – dBc
MAGNITUDE – dBc

–30 –20
–40
–30
–50

–60 –40

–70
–50
–80
–60
–90

–100 –70
–1 0 1 2 3 4 5 6 7 8 9 3 5 7 9 11 13 15 17 19 21 23
FREQUENCY OFFSET – kHz FREQUENCY – MHz

TPC 13. Phase Noise Plot @ fDATA = 32 MSPS, TPC 15. In-Band Multitone Spectral Plot
fOUT = 10 MHz, 4
LPF @ fDATA = 50 MSPS, fOUT = k
195 kHz, 2
LPF

10 10

0
0
–10
–10
–20
MAGNITUDE – dBc
MAGNITUDE – dBc

–30 –20
–40
–30
–50

–60 –40

–70
–50
–80
–60
–90

–100 –70
–1 0 1 2 3 4 5 6 7 8 9 3 11 21 31 41 51 61 71 81 91 101
FREQUENCY OFFSET – kHz FREQUENCY – MHz

TPC 14. Phase Noise Plot @ fDATA = 50 MSPS, TPC 16. Wideband Multitone Spectral Plot
fOUT = 10 MHz, 2
LPF @ fDATA = 50 MSPS, fOUT = k
195 kHz, 2
LPF

–10– REV. A
 AD9876
Typical Tx Digital Filter Performance Characteristics
40 18

38 17

36 16

34 15
FREQUENCY – MHz

FREQUENCY – MHz
32 14

30 13

28 12

26 11

24 10

22 9

20 8
64 80 96 112 128 144 160 176 192 48 64 80 96 112 128 144 160 176 192

TPC 17. Rx vs. Tuning Target, fADC = 32 MHz, TPC 19. fC vs. Tuning Target, fADC = 32 MHz,
LPF with Wideband Rx LPF = 1 LPF with Wideband Rx LPF = 0

0.60 2.5

2.4
0.40
2.3

0.20 2.2
MAGNITUDE – dB

MAGNITUDE – dB

2.1
0.00
2.0
–0.20
1.9

–0.40 1.8

1.7
–0.60
1.6

–0.80 1.5
–6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
VGA GAIN – dB VGA GAIN – dB

TPC 18. PGA Gain Error vs. Gain TPC 20. PGA Gain Step Size vs. Gain

REV. A –11–
AD9876
Typical AC Characterization Curves for Rx Path
LOG MAG 5dB/REF – 0dB –3.0dB DELAY 10ns/REF 0s 72.188ns

10.8MHz 9.0MHz
0
0

1MHz 10MHz 100MHz 1MHz 10MHz 100MHz

TPC 21. Rx LPF Frequency Response, Low fC TPC 24. Rx LPF Group Delay, Low fC Nominal
Nominal Tuning Targets Tuning Targets

LOG MAG 5dB/REF 0dB –3.0dB DELAY 5ns/REF 0s 34.431ns

26.5MHz 22.5MHz
0
0

1MHz 10MHz 100MHz 1MHz 10MHz 100MHz

TPC 22. Rx LPF Frequency Response, High fC TPC 25. Rx LPF Group Delay, High fC, Nominal
Nominal Tuning Targets Tuning Targets

LOG MAG 5dB/REF 0dB –3.0dB DELAY 10ns/REF 0s 51.244ns

14.5MHz 14.5MHz
0

1MHz 10MHz 100MHz 1MHz 10MHz 100MHz

TPC 23. Rx LPF Frequency Response, Low fC TPC 26. Rx LPF Group Delay, Low fC, 0
60 and
0
60 and 0
96 Turning Targets 0
96 Tuning Targets

–12– REV. A
 AD9876
Typical AC Characterization Curves for Rx Path (continued)
LOG DELAY 5dB/REF –2dB –5.1933dB LOG DELAY 5ns/REF 0s 29.97ns

33.5MHz 29.5MHz
0
COR
AVG
16 0

1MHz 10MHz 100MHz 1MHz 10MHz 100MHz

TPC 27. Rx LPF Frequency Response, High fC, TPC 30. Rx LPF Group Delay, High fC, 0
60 and
0
60 and 0
96 Tuning Targets 0
96 Tuning Targets

LOG MAG 5dB/REF 0dB –3.01dB

700
78.8MHz
0
COR 600
AVG FILTER ENABLED
16
500
ADC INPUT RMS NOISE – V

400

300

200
FILTER BYPASSED
100

0
10kHz 100kHz 1MHz –6 4 14 24 34
GAIN SETTING – dB

TPC 28. Rx HPF Frequency Response, fADC = 32 MHz TPC 31. Rx Input Referred Noise vs. Gain
@ fADC = 32 MSPS, fIN = 1 MHz

4000 4000

3800 3800
fADC = 50MHz
3600 3600
ADC OUTPUT CODE

fADC = 50MHz
ADC OUTPUT CODE

3400 3400

3200 3200

3000 3000
fADC = 32MHz fADC = 32MHz
2800 2800

2600 2600

2400 2400
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
ADC CLOCK CYCLES ADC CLOCK CYCLES

TPC 29. Rx Path Setting, 1/2 Scale Rising Step TPC 32. Rx Path Setting, 1/2 Scale Falling Step
with Gain Change with Gain Change

REV. A –13–
AD9876
Typical AC Characterization Curves for Rx Path (Gain = –6 dB, f IN = 5 MHz)
11.0 70 –50

10.5
fOSCIN 65 fOSCIN –55
10.0

MAGNITUDE – dB
MAGNITUDE – dB
60 –60
9.5
fPLLB/2 fOSCIN
ENOB

9.0 55 –65
fPLLB/2
8.5
50 –70 fPLLB/2
8.0
45 –75
7.5

7.0 40 –80
10 20 30 40 50 10 20 30 40 50 10 20 30 40 50
fS – MHz fS – MSPS fS – MSPS

TPC 33. Rx Path ENOB vs. fADC TPC 34. Rx Path SNR vs. fADC TPC 35. Rx Path THD vs. fADC

11.0 70 –50

10.5
fOSCIN 65 fOSCIN –55
10.0

MAGNITUDE – dB
MAGNITUDE – dB

60 –60 fPLLB/2
9.5
ENOB

9.0 55 –65
fPLLB/2 fPLLB/2
8.5
50 –70
8.0 fOSCIN
45 –75
7.5

7.0 40 –80
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
fIN – MHz fIN – MHz fIN – MHz

TPC 36. Rx Path ENOB vs. fIN TPX 37. Rx Path SNR vs. fIN TPC 38. Rx Path THD vs. fIN

11.0 70 –50

10.5

65 –55
fOSCIN fOSCIN
MAGNITUDE – dB
MAGNITUDE – dB

10.0
ENOB

9.5 60 –60
fPLLB/2

9.0 fPLLB/2
fPLLB/2
55 –65
8.5
fOSCIN

8.0 50 –70
–6 0 6 12 18 24 30 36 –6 0 6 12 18 24 30 36 –6 0 6 12 18 24 30 36
GAIN – dB GAIN – dB GAIN – dB

TPC 39. Rx Path ENOB vs. Gain TPC 40. Rx Path SNR vs. Gain TPC 41. Rx Path THD vs. Gain

–14– REV. A
 AD9876
TRANSMIT PATH The transmit path expects a new half-word of data at the rate
The AD9876 transmit path consists of a digital interface port, a of fCLK-A. When the Tx multiplexer is enabled, the frequency
programmable interpolation filter, and a transmit DAC. All of Tx Port is:
clock signals required by these blocks are generated from the fCLK − A = 2 × fDAC K = 2 × L × fOSCIN /K
fOSCIN signal by the PLL-A clock generator. The block diagram
below shows the interconnection between the major functional where K is the interpolation factor that can be programmed to be
components of the transmit path. 1, 2, or 4. When the Tx multiplexer is disabled, the frequency of
the Tx Port is:
Tx QUIET AD9876 fCLK − A = fDAC K = L × fOSCIN /K
GAIN 12 12 Tx+
Tx [5:0]
Tx Kx INTERPOLATION TxDAC+ Note, this will result in a 6-bit data path.
DEMUX LPF/BPF Tx–
Tx SYNC

fDAC = L ⴛ fOSCIN
INTERPOLATION FILTER
The interpolation filter can be programmed to run at 2× and 4×
PLL-A
ⴛL upsampling ratios in each of three different modes. The transfer
fCLK-A fOSCIN OSCIN
CLK-A functions of these six configurations are shown in TPCs 1–6.
CLOCK GEN XTAL The X-axis of each of these figures corresponds to the frequency
normalized to fDAC. These transfer functions show both the
discrete time transfer function of the interpolation filters alone
Figure 1. Transmit Path Block Diagram and with the SIN(x)/x transfer function of the DAC. The
interpolation filter can also be programmed into a pass-
DIGITAL INTERFACE PORT through mode if no interpolation filtering is desired.
The Transmit Digital Interface Port has several modes of opera- The contents of the interpolation filter are not cleared by
tion. In its default configuration, the Tx Port accepts six bit hardware or software resets. It is recommended to “flush” the
nibbles through the Tx [5:0] and Tx SYNC pins and demul- transmit path with zeros before transmitting data.
tiplexes the data into 12-bit words before passing it to the
interpolation filter. The input data is sampled on the rising edge The table below contains the following parameters as a function
of fCLK-A. of the mode that it is programmed.
Additional programming options for the Tx Port allow: sampling Latency – The number of clock cycles from the time a digital
the input data on the falling edge of fCLK-A, inversion or disabling impulse is written to the DAC until the peak value is output at
of fCLK-A, and reversing the order of the nibbles. Also, the Tx Port the T+ and T– pins.
interface can be controlled by the GAIN pin to provide direct Flush – The number of clock cycles from the time a digital
access to the Rx Path Gain Adjust Register. All of these modes impulse is written to the DAC until the output at the Tx+ and
are fully described in the Register Programming Definitions sec- Tx– pins settles to zero.
tion of this data sheet.
fLOWER (0.1 dB, 3 dB) – This indicates the lower 0.1 dB or 3 dB
The data format is twos complement, as shown below: cutoff frequency of the interpolation filter as a fraction of fDAC,
011 . . 11: Maximum the DAC sampling frequency.
000 . . 01: Midscale + 1 LSB fUPPER (0.1 dB, 3 dB) – This indicates the upper 0.1 dB or 3 dB
000 . . 00: Midscale cutoff frequency of the interpolation filter as a fraction of fDAC,
111 . . 11: Midscale – 1 LSB the DAC sampling frequency.
111 . . 10: Midscale – 2 LSB
Table I. Interpolation Filter Parameters vs. Mode
100 . . 00: Minimum
The data can be translated to a straight binary data format by Register 7 [7:4] 0 ⴛ 0 0ⴛ1 0ⴛ4 0ⴛ5 0ⴛ8 0ⴛC
simply inverting the most significant bit. Mode 4 × LPF 2 × LPF 4 × BPF 2 × BPF 4 × BPF 4 × BPF
The timing of the interface is fully described in the Transmit Adj. Adj. Lower Upper
Port Timing section of this data sheet. Latency, fDAC 86 30 86 3 86 86
Clock Cycles
PLL-A CLOCK DISTRIBUTION Flush, fDAC 128 48 128 48 148 142
Figure 1 shows the clock signals used in the transmit path. The Clock Cycles
DAC sampling clock, fDAC, is generated by PLL-A. fDAC has a fLOWER, 0.1 dB 0 0 0.398 0.276 0.148/ 0.274/
frequency equal to L × fOSCIN, where fOSCIN is the internal signal 0.774 0.648
generated either by the crystal oscillator when a crystal is con- fUPPER, 0.1 dB 0.102 0.204 0.602 0.724 0.226/ 0.352/
nected between the OSCIN and XTAL pins, or by the clock that 0.852 0.762
is fed into the OSCIN pin, and L is the multiplier programmed fLOWER, 3 dB 0 0 0.381 0.262 0.131/ 0.257/
through the serial port. L can have the values of 1, 2, 4, or 8. 0.757 0.631
fUPPER, 3 dB 0.119 0.238 0.619 0.738 0.243/ 0.369/
0.869 0.743

REV. A –15–
AD9876
D/A CONVERTER selected, or if the LPF is bypassed. If the wider (approximately
The AD9876 DAC provides differential output current on the 26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
Tx+ and Tx– pins. The value of the output currents are comple- +30 dB. The PGA is comprised of two sections, a continuous
mentary, meaning that they will always sum to IFS, the full-scale time PGA (CPGA) and a switched capacitor PGA (SPGA). The
current of the DAC. For example, when the current from Tx+ is CPGA has possible gain settings of 0, 6, 12, 18, 24, and 30. The
at full-scale, the current from Tx– is zero. The two currents will SPGA has possible gain settings of –6, –4, –2, 0, +2, +4, and +6
typically drive a resistive load that will convert the output dB. Table V shows how the gain is distributed for each pro-
currents to a voltage. The Tx+ and Tx– output currents are grammed gain setting.
inherently ground seeking and should each be connected to The CPGA input appears at the device Rx+ and Rx– input pins.
matching resistors, RL, that are tied directly to AGND. The input impedance of this stage is nominally 270 ⍀ differen-
The full-scale output current of the DAC is set by the value of tial and is not gain dependent. It is best to ac-couple the input
the resistor placed from the FSADJ pin to AGND. The relation- signal to this stage and let the inputs self bias. This will lower
ship between the resistor, RSET, and the full-scale output current the offset voltage of the input signal, which is important at higher
is governed by the following equation: gains, since any offset will lower the output compliance range of
the CPGA output. When the inputs are driven by direct coupling,
I FS = 39.4 RSET
the dc level should be AVDD/2. However, this could lead to
The full-scale current can be set from 2 to 20 mA. Generally, larger dc offsets and consequently reduce the dynamic range of the
there is a trade-off between DAC performance and power con- Rx path.
sumption. The best DAC performance will be realized at an IFS
of 20 mA. However, the value of IFS adds directly to the overall LOW-PASS FILTER
current consumption of the device. The low-pass filter (LPF) is a programmable, multistage, fourth
The single-ended voltage output appearing at the Tx+ and Tx– order filter comprised of two real poles and a complex pole pair.
nodes are: The first real pole is implemented within the CPGA. The second
filter stage implements a complex pair of poles. The last real
VTx + = I Tx + × R L pole is implemented in a buffer stage that drives the SPGA.
VTx − = I Tx − × R L There are two pass-band settings for the LPF. Within each pass
band the filters are tunable over about a ± 30% frequency range.
Note that the full-scale voltage of VTx+ and VTx– should not
The formula for the cutoff frequency is:
exceed the maximum output compliance range of 1.5 V to pre-
vent signal compression. To maintain optimum distortion and fCUTOFF LOW = f ADC × 64 (64 + Target )
fCUTOFF HIGH = f ADC × 158 (64 + Target )
linearity performance, the maximum voltages at VTx+ and VTx–
should not exceed 0.5 V.
The single-ended full-scale voltage at either output node will be: where Target is the decimal value programmed as the tuning
target in Register 5.
V FS = I FS × R L
This filter may also be bypassed by setting Bit 0 of Register 4.
The differential voltage, VDIFF, appearing across VTx+ and VTx– is: In this case, the bandwidth of the Rx path will decrease with
V DIFF = (TTx + − TTx − ) × R L increasing gain and will be approximately 50 MHz at the highest
gain settings.
and
V DIFF _ FS = I FS × R L ADC
The AD9876’s analog-to-digital converter implements a pipe-
For optimum performance, a differential output interface is rec- lined multistage architecture to achieve high sample rates while
ommended since any common-mode noise or distortion can be consuming low power. The ADC distributes the conversion over
suppressed. several smaller A/D subblocks, refining the conversion with
It should be noted that the differential output impedance of the progressively higher accuracy as it passes the results from stage
DAC is 2 × RL and any load connected across the two output to stage. As a consequence of the distributed conversion, ADCs
resistors will load down the output voltage accordingly. require a small fraction of the 2N comparators used in a tradi-
tional n-bit flash-type A/D. A sample-and-hold function within
RECEIVE PATH DESCRIPTION each of the stages permits the first stage to operate on a new
The receive path consists of a two-stage PGA, a continuous time, input sample while the remaining stages operate on preceding
4-pole LPF, an ADC, a digital HPF, and a digital data multiplexer. samples. Each stage of the pipeline, excluding the last, consists
Also working in conjunction with the receive path is an offset of a low resolution flash A/D connected to a switched capacitor
correction circuit and a digital phase-lock loop. Each of these DAC and interstage residue amplifier (MDAC). The residue
blocks will be discussed in detail in the following sections. amplifier amplifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe-
PROGRAMMABLE GAIN AMPLIFIER line. One bit of redundancy is used in each one of the stages to
The PGA has a programmable gain range from –6 dB to +36 dB facilitate digital correction of flash errors. The last stage simply
if the narrower (approximately 12 MHz) LPF bandwidth is consists of a flash A/D.

–16– REV. A
 AD9876
CLOCK AND OSCILLATOR CIRCUITRY
AINP The AD9876’s internal oscillator generates all sampling clocks
A/D
AINN
SHA GAIN SHA GAIN from a fundamental frequency quartz crystal. Figure 3a shows
how the quartz crystal is connected between OSCIN (Pin 1) and
A/D D/A A/D D/A XTAL (Pin 48) with parallel resonant load capacitors as speci-
fied by the crystal manufacturer. The internal oscillator circuitry
CORRECTION LOGIC can also be overdriven by a TTL-level clock applied to OSCIN
AD9876 with XTAL left unconnected.
The PLL has a frequency capture range between 10 MHz
Figure 2. ADC Theory of Operation and 64 MHz.
The digital data outputs of the ADC are represented in two’s
complement format. They saturate to full scale or zero when the AD9876
XTAL
input signal exceeds the input voltage range.
XTAL
The twos complement data format is shown below:
OSCIN
011 . . 11: Maximum Y1
C1 C2
000 . . 01: Midscale + 1 LSB
000 . . 00: Midscale
111 . . 11: Midscale – 1 LSB Figure 3a. Connections for a Fundamental Mode Crystal
111 . . 10: Midscale – 2 LSB
100 . . 00: Minimum VOLTAGE REGULATOR CONTROLLER
The maximum value will be output from the ADC when the The AD9876 contains an on-chip voltage regulator controller
Rx+ input is 1 V or more greater than the Rx– input. The mini- (VRC) for providing a linear 1.3 V supply for low voltage digital
mum value will be output from the ADC when the Rx– input is circuitry or other external use. The VRC consists of an op amp
1 V or more greater than the Rx+ input. This results in a full- and a resistive voltage divider. As shown in Figure 3b, the resis-
scale ADC voltage of 2 Vppd. tive divider establishes a voltage of 1.3 V at the inverting input
of the amplifier when DVDD is equal to its nominal voltage of
The data can be translated to straight binary data format by 3.3 V. The feedback loop around the op amp will adjust the gate
simply inverting the most significant bit. voltage such that the voltage at the FB pin, VFB, will be equal to
The best ADC performance will be achieved when the ADC the voltage at the inverting input of the op amp.
clock source is selected from fOSCIN and the OSCIN pin is driven
from a low jitter clock source. The amount of degradation from 3.3V

jitter on the ADC clock will depend on how quickly the input is
varying at the sampling instance. TPC 36 charts this effect in DVDD
the form of ENOB vs. input frequency for the two clocking AD9876
2R
scenarios.
S
The maximum sample rate of the ADC in Full-Precision Mode, GATE
G SI2301
that is outputting 12 bits, is 55 MSPS. TPC 33 shows the ADC 1.3R
D
VOUT
performance in ENOB versus fADC. The maximum sample rate VFB = 1.3V
FB
of the ADC in Half-Precision Mode, that is outputting five bits,
C
is 64 MSPS. The timing of the interface is fully described in the
Receive Port Timing section of this data sheet.

DIGITAL HPF
Figure 3b. Connections for 1.3 V Linear Regulator
Following the ADC, there is a bypassable digital HPF. The The maximum current output from the circuit is largely depen-
response is a single-pole IIR HPF. The transfer function is: dent on the MOSFET device. For the SI2301 shown, 250 mA
(
H (z ) = 1 – 0.99994Z –1 ) (1 – 98466Z ) –1 can be delivered. The regulated output voltage should have bulk
decoupling and high frequency decoupling capacitors to ground
where the sampling period is equal to the ADC clock period. as required by the load. The regulator circuit will be stable for
This results in a 3 dB frequency approximately 1/400th of the capacitive loads between 0.1 µF and 47 µF.
ADC sampling rate. The transfer functions are plotted for It should be noted that the regulated output voltage, VFB, is
32 MSPS and 50 MSPS in TPC 29 and TPC 32. proportional to DVDD. Therefore, the percentage variation in
The digital HPF introduces a 1 ADC clock cycle latency. If the DVDD will also be seen at the regulated output voltage. The
HPF function is not desired, the HPF can be bypassed and the load regulation is roughly equal to the ON resistance of the
latency will not be incurred. MOSFET device chosen. For the SI2301, this is about 60 mΩ.

REV. A –17–
AD9876
AGC TIMING CONSIDERATIONS Also, the Tx path can be used in a Reduced Resolution Mode
When implementing the AGC timing loop, it is important to by setting the Tx Port Multiplexer Bypass Bit (Register 7, Bit
consider the delay and settling time of the Rx path in response 0). In this mode, the Tx data-word becomes six bits and is read
to a change in gain. Figure 4 shows the delay the receive signal in a single cycle. The clocking modes are the same as described
experiences through the blocks of the Rx path. Whether the gain above, but the level of Tx SYNC is irrelevant.
is programmed through the serial port or over the Tx [5:0] pins,
If Tx SYNC is low for more than one clock cycle, the last trans-
the gain takes effect immediately with the delays shown below.
mit data will read continuously until Tx SYNC is brought high
When gain changes do not involve the CPGA, the new gain will
for the second nibble of a new transmit word. This feature can
be evident in samples after seven ADC clock cycles. When the
be used to “flush” the interpolator filters with zeros.
gain change does involve the CPGA, it takes an additional 45 ns
to 70 ns due to the propagation delays of the buffer, LPF and PGA Adjust Timing
PGA. Table V, details the PGA programming map. In addition to the serial port, the Tx [5:1] pins can be used to
write to the Rx Path Gain Adjust Bits (Register 6, Bits 4:0).
GAIN This provides a faster way to update the PGA gain. A high level
REGISTER
on the GAIN pin with Tx SYNC low programs the PGA setting
5ns
on either the rising edge or falling edge of CLK-A. The GAIN
DECODE pin must be held high, Tx SYNC must be held low, and GAIN
LOGIC
data must be stable for three clock cycles to successfully update
the PGA GAIN value. A low level on the GAIN pin enables data
to be fed to the interpolator and DAC.

DIGITAL ADC SHA BUFFER PGA tSU

LPF
HPF
1 CLK 5 CLK 1/2 CLK CLK-A
CYCLE CYCLE CYCLE 10ns 25ns or 50ns 10ns

tHD
Figure 4. AGC Timing Tx SYNC

Transmit Port Timing

Tx [5:0] GAIN
The AD9876 transmit port consists of a 6-bit databus Tx [5:0],
a clock, and a Tx SYNC signal. Two consecutive nibbles of the
Tx data are multiplexed together to form a 12-bit data-word. GAIN
The clock appearing on the CLK-A pin is a buffered version of
Figure 6. GAIN Programming
the internal Tx data sampling clock. Data from the Tx port is
read on the rising edge of this sampling clock. The Tx SYNC Receive Port Timing
signal is used to indicate to which word a nibble belongs. The The AD9876 receives port consists of a six bit databus Rx [5:0],
first nibble of every word is read while Tx SYNC is low, the a clock, and an Rx SYNC signal. Two consecutive nibbles of the
second nibble of that same word is read on the following Tx Rx data are multiplexed together to form a 10-/12-bit data-word.
SYNC high level. The timing is illustrated in the Figure 5. The Rx data is valid on the rising edge of CLK-A when the
ADC Clock Source PLL-B/2 Bit (Register 3, Bit 6) is set to 0.
tSU The Rx SYNC signal is used to indicate to which word a nibble
CLK-A
belongs. The first nibble of every word is transmitted while Rx
SYNC is low, the second nibble of that same word is transmit-
tHD
Tx SYNC
ted on the following Rx SYNC high level. When Rx SYNC is
low, the sampled nibble is read as the most significant nibble.
Tx [5:0] Tx 0 LSB Tx 1 MSB Tx 1 LSB Tx 2 MSB Tx 2 LSB Tx 3 MSB
When the Rx SYNC is high, the sampled nibble is read as the
least significant nibble. The timing is illustrated in Figure 7.
Figure 5. Transmit Timing Diagram AD9876
tHT
The Tx Port is highly configurable and offers the following options.
CLK-A/-B
Negative edge sampling can be chosen by two different methods;
tVT
either by setting the Tx Port Negative Edge Sampling Bit (Reg- Rx SYNC
ister 3, Bit 7) or the Invert CLK-A Bit (Register 8, Bit 6). The
main difference between the two methods is that setting Register Rx [5:0] Rx 0 LSB Rx 1 MSB Rx 1 LSB Rx 2 MSB Rx 2 LSB Rx 3 MSB
3, Bit 7 inverts the internal sampling clock and will affect only
the transmit path, even if CLK-A is used to clock the Rx Figure 7. Receive Timing Diagram
data. However, inverting CLK-A would affect both the Rx and The Rx Port is highly configurable and offers the following
Tx paths if they both use CLK-A. options.
The first nibble of each word can be read in as the least significant Negative edge sampling can be chosen by setting the Invert
nibble by setting the Tx LS Nibble First Bit (Register 7, Bit 2). CLK-A Bit (Register 8, Bit 6) or the Invert CLK-B Bit (Register
8, Bit 7), depending on the clock selected as the ADC sampling

–18– REV. A
 AD9876
source. Inverting CLK-A would affect the Tx sampling edge as Bits I4:I0 – A4:A0
well as the Rx sampling edge. These bits determine which register is accessed during the data
The first nibble of each word can be read in as the least significant transfer portion of the communications cycle. For multibyte
nibble by setting the Rx LS Nibble First Bit (Register 8, Bit 2). transfers, this address is the starting byte address. The remain-
ing register addresses are generated by the AD9876/AD9875.
Also, the Rx path can be used in a Reduced Resolution Mode
by setting the Rx Port Multiplexer Bypass Bit (Register 8, Bit Serial Interface Port Pin Description
0). In this mode, the Rx data-word becomes six bits and is read SCLK—Serial Clock
in a single cycle. The Clocking Modes are the same as described The serial clock pin is used to synchronize data transfers to and
above, but the level of Rx SYNC will stay low. from the AD9876 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
The Rx [5:0] pins can be put into a high impedance state by AD9876 is sampled on the rising edge of SCLK. All data read
setting the Three-State Rx Port Bit (Register 8, Bit 3). from the AD9876 is validated on the rising edge of SCLK and is
updated on the falling edge.
SERIAL INTERFACE FOR REGISTER CONTROL
The serial port is a 3-wire serial communications port consisting of SENABLE—Serial Interface Enable
a clock (SCLK), chip select (SENABLE), and a bidirectional The SENABLE pin is active low. It enables the serial communi-
data (SDATA) signal. The interface allows read/write access to cation to the device. SENABLE select should stay low during
all registers that configure the AD9876 internal parameters. Single the entire communication cycle. All input on the serial port is
or multiple byte transfers are supported as well as MSB first or ignored when SENABLE is inactive.
LSB first transfer formats. SDATA—Serial Data I/O
General Operation of the Serial Interface The signal on this line is sampled on the first eight rising edges
Serial communication over the serial interface can be from 1 to of SCLK after SENABLE goes active. Data is then read from or
5 bytes in length. The first byte is always the instruction byte. written to the AD9876 depending on what was read.
The instruction byte establishes whether the communication is Figures 8 and 9 show the timing relationships between the three
going to be a read or write access, the number of data bytes to SPI signals.
be transferred, and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
8th rising edge of SCLK after SENABLE is asserted. Likewise, SENABLE tDS tSCLK
the data registers change immediately upon writing to the 8th bit
of each data byte. tPWH tPWL
SCLK
Instruction Byte
The instruction byte contains the following information as
tDS tDH
shown below. SDATA
INSTRUCTION BIT 7 INSTRUCTION BIT 6

Table II. Instruction Byte Information

Figure 8. Timing Diagram Register Write to AD9876
MSB LSB

I7 I6 I5 I4 I3 I2 I1 I0 SENABLE

R/W N1 N0 A4 A3 A2 A1 A0
SCLK

tDV

Bit I7 – R/W SDATA DATA BIT n DATA BIT n–1

This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates read Figure 9. Timing Diagram Register Read from AD9876
operation; logic zero indicates a write operation.
MSB/LSB Transfers
Bits I6:I5 – N1:N0 The AD9876 serial port can support both most significant bit
These two bits determine the number of bytes to be transferred (MSB) first or least significant bit (LSB) first data formats. The
during the data transfer cycle. The bit decodes are shown in the bit order is controlled by the SPI LSB First Bit (Register 0, Bit
table below. 6). The default value is 0, MSB first. Multibyte data transfers in
Table III. Decode Bits MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
N1:N0 Description The AD9876 will automatically decrement the address for each
0:0 Transfer 1 Byte successive byte required for the multibyte communication cycle.
0:1 Transfer 2 Bytes When the SPI LSB First Bit (Register 0, Bit 6) is set high, the
1:0 Transfer 3 Bytes serial port interprets both instruction and data bytes LSB first.
1:1 Transfer 4 Bytes Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of

REV. A –19–
AD9876
the first address to be accessed. The AD9876 will automatically Notes on Serial Port Operation
increment the address for each successive byte required for the The serial port is disabled and all registers are set to their default
multibyte communication cycle. values during a hardware reset. During a software reset, all
Figures 10a and 10b show how the serial port words are built registers except Register 0 are set to their default values. Regis-
for each of these modes. ter 0 will remain at the last value sent, with the exception that
the Software Reset Bit will be set to 0.
The serial port is operated by an internal state machine and is
INSTRUCTION CYCLE DATA TRANSFER CYCLE
SENABLE dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a
SCLK byte is transferred over the SPI. During a multibyte write cycle,
SDATA R/W I6(N) I5(N) I4 I3 I2 I1 I0 D7N D6N D20 D10 D00 this means the registers of the AD9876 are not simultaneously
updated but occur sequentially. For this reason, it is recom-
Figure 10a. Serial Register Interface Timing MSB-First mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SENABLE

SCLK

SDATA I0 I1 I2 I3 I4 I5(N) I6(N) R/W D00 D10 D20 D6N D7N

Figure 10b. Serial Register Interface Timing LSB-First

Table IV. Register Layout

Address Default
(hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (hex) Comments
0 SPI Software 0 × 00 Read/Write
LSB First Reset
1 Power- Power- Power- Power- Power- Power- Power- Power- 0 × 00 Read/Write
Down Down Down Down Down Down Down Down PWR DN
Regulator PLL-B PLL-A DAC Interpolator Rx ADC and Rx LPF and Pin Low
Reference FPGA CPGA
2 Power- Power- Power- Power- Power- Power- Power- Power- 0 × 9F Read/Write
Down Down Down Down Down Down Down Down PWR DN
Regulator PLL-B PLL-A DAC Interpolator Rx ADC and Rx LPF and Pin High
Reference FPGA CPGA
3 Tx Port ADC Clock PLL-B PLL-B PLL-A 0 × 02 Read/Write
Negative Source (×M) Multiplier (N) Divider (×M) Multiplier
Edge PLL-B/2 <5:4> <3:3> <1:0>
Sampling
4 Rx Port Rx LPF Rx Path Rx Digital Fast ADC Wideband Enable Rx LPF 0 × 01 Read/Write
Negative Tuning DC Offset HPF Sampling Rx LPF 1-Pole Bypass
Edge In Progress Correction Bypass Rx LPF
Sampling (Read-Only)
5 Rx LPF fc Adjust <7:0> 0 × 80 Read/Write
6 PGA Rx Path Gain Adjust <4:0> 0 × 00 Read/Write
Gain Set
by Register
7 Interpolation Filter Select Power-Down Tx Port Tx Port 0 × 00 Read/Write
<3:0> Interpolator LS Nibble Demultiplexer
at First Bypass
Tx QUIET
Pin Low
8 Invert Invert Disable Disable Three-State Rx Port Rx Port 0 × 00 Read/Write
CLK-B CLK-A CLK-B CLK-A Rx Port LS Nibble Multiplexer
First Bypass
F Die Revision Number <3:0> Read- Only

–20– REV. A
 AD9876
REGISTER PROGRAMMING DEFINITIONS fCLKIN is selected as the ADC sampling clock source and should
REGISTER 0 – RESET/SPI CONFIGURATION be used as the ADC sampling clock whenever possible.
Bit 5: Software Reset Bit 1, 0: PLL-A Multiplier
Setting this bit high resets the chip. The PLLs will relock to the Bits 1 and 0 determine the multiplication factor (L) for PLL-A
input clock and all registers (except Register 0 × 0, Bit 6) revert to and the DAC sampling clock frequency, fDAC.
their default values. Upon completion of the reset, Bit 5 is reset to 0. fDAC = L × fCLKIN
The content of the interpolator stages are not cleared by software Bit 1, 0
or hardware resets. It is recommended to “flush” the transmit 0, 0: L = 1
path with zeros before transmitting data. 0, 1: L = 2
Bit 6: SPI LSB First 1, 0: L = 4
Setting this bit high causes the serial port to send and receive 1, 1: L = 8
data least significant bit (LSB) first. The default low state con- Bit 5 to 2: PLL-B Multiplier/Divider
figures the serial port to send and receive data most significant Bits 5 to 2 determine the multiplication factor (M) and division
bit (MSB) first. factor (N) for the PLL-B and the CLK-B frequency. For multi-
plexed 10-/12-bit data, fCLK-B = fCLKIN × M/N. For nonmultiplexed
REGISTERS 1 AND 2—POWER-DOWN 6-bit data, fCLK-B = (fCLKIN/2) × M/N. All nine combinations of M
The combination of the PWR DN pin and Registers 1 and 2 and N values are valid, yielding seven unique M/N ratios.
allow for the configuration of two separate pin selectable power
settings. The PWR DN pin selects between two sets of individually Bit 5,4 Bit 3,2
programmed operation modes. 0, 0: M = 3 0, 0: N = 2
0, 1: M = 4 0, 1: N = 4
When the PWR DN pin is low, the functional blocks corre- 1, 0: M = 6 1, 0: N = 1
sponding to the bits set in Register 1 will be powered down.
Bit 6: ADC Clock Source PLL-B/2
When the PWR DN pin is high, the functional blocks corre- Setting Bit 6 high selects PLL-B/2 as the ADC sampling clock
sponding to the bits set in Register 2 will be powered down. source. In this mode, the Rx data and CLK-B will run at a rate
Bit 0: Power-Down Receive Filter and CPGA of fCLK-B. Rx SYNC will run at fCLK-B/2.
Setting this bit high powers down and bypasses the Rx LPF and Setting Bit 6 low selects the fCLKIN signal as the ADC sampling
coarse programmable gain amplifier. clock source. This mode of operation yields the best ADC
Bit 1: Power-Down ADC and FPGA performance if an external crystal is used or a low jitter clock
Setting this bit high powers down the ADC and fine program- source drives the OSCIN pin.
mable gain amplifier (FPGA). Bit 7: Tx Port Negative Edge Sampling
Bit 2: Power-Down Rx Reference Setting Bit 7 high will cause the Tx Port to sample the Tx DATA
Setting this bit high powers down the ADC reference. This bit and Tx SYNC on the falling edge of CLK-A. By default, the Tx
should be set if an external reference is applied. Port sampling occurs on the rising edge of CLK-A. The timing
Bit 3: Power-Down Interpolators is shown in Figure 5.
Setting this bit high powers down the transmit digital interpolators.
It does not clear the content of the data path. REGISTER 4—RECEIVE FILTER SELECTION
The AD9876 receive path has a continuous time 4-pole LPF
Bit 4: Power-Down DAC and a 1-pole digital HPF. The 4-pole LPF has two selectable
Setting this bit high powers down the transmit DAC. cutoff frequencies. Additionally, the filter can be tuned around
Bit 5, Bit 6: Power-Down PLL-A, PLL-B those two cutoff frequencies. These filters can also be bypassed
Setting these bits high powers down the on-chip phase-lock to different degrees as described below.
loops that generated CLK-A and CLK-B, respectively. When The continuous time 4-pole low-pass filter is automatically
powered down, these clocks are high impedance. calibrated to one of two selectable cutoff frequencies.
Bit 7: Power-Down Regulator The cutoff frequency fCUTOFF is described as a function of the
Setting this bit high powers down the on-chip voltage control regulator. ADC sampling frequency fADC and can be influenced (± 30%) by
the Rx Filter Tuning Target word in Register 5.
REGISTER 3—CLOCK SOURCE CONFIGURATION
The AD9876 integrates two independently programmable PLLs fCUTOFF LOW = f ADC × 64 (64 + Target )
referred to as PLL-A and PLL-B. The outputs of the PLLs are fCUTOFF HIGH = f ADC × 158 (64 + Target )
used to generate all the chips internal and external clock signals
from the fCLKIN signal. All Tx path clock signals are derived Bit 0: Rx LPF Bypass
from PLL-A. If fCLKIN is programmed as the ADC sampling Setting this bit high bypasses the 4-pole LPF. The filter is auto-
clock source, then the Rx port clocks are also derived from matically powered down when this bit is set.
PLL-A. Otherwise, the ADC sampling clock is PLL-B/2 and the Bit 1: Enable 1-Pole Rx LPF
Rx path clocks are derived from PLL-B. The AD9876 can be configured with an additional 1-pole ~16 MHz
There is a restriction that the values of L and K both be equal to input filter for applications that require steeper filter roll-off or
4 when fCLKIN is selected as the ADC sampling clock source. want to use the 1-pole filter instead of the 4-pole receive low-
However, the best receive path performance is obtained when pass filter. The 1-pole filter is untrimmed and subject to cutoff
frequency variations of ⫾20%.

REV. A –21–
AD9876
Bit 2: Wideband Rx LPF Table V. PGA Programming Map
This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz. Rx Path Rx Path CPGA SPGA
When the wideband filter is selected, the Rx path gain is limited Gain [4:0] Gain Gain Gain
to 30 dB. 0 × 00 –6 –6 0
Bit 3: Fast ADC Sampling 0 × 01 –4 –6 2
Setting this bit increases the quiescent current in the SVGA 0 × 02 –2 –6 4
block. This may provide some performance improvement 0 × 03 0 –6 6
when the ADC sampling frequency is greater than 50 MSPS 0 × 04 2 –6 8
(in 6-Bit Mode). 0 × 05 4 –6 10
0 × 06 6 0 6
Bit 4: Rx Digital HPF Bypass 0 × 07 8 0 8
Setting this bit high bypasses the 1-pole digital HPF that follows 0 × 08 10 0 10
the ADC. The digital filter must be bypassed for ADC sampling 0 × 09 12 6 6
above 50 MSPS. 0 × 0A 14 6 8
Bit 5: Rx Path DC Offset Correction 0 × 0B 16 6 10
Writing a 1 to this bit triggers an immediate receive path offset 0 × 0C 18 12 6
correction and reads back zero after the completion of the offset 0 × 0D 20 12 8
correction. 0 × 0E 22 12 10
Bit 6: Rx LPF Tuning in Progress 0 × 0F 24 18 6
This bit indicates when the receive filter calibration is in progress. 0 × 10 26 18 8
The duration of a receive filter calibration is about 500 ms. 0 × 11 28 18 10
Writing to this bit has no effect. 0 × 12* 30/30 18/24 12/6
0 × 13* 30/32 18/24 12/8
Bit 7: Rx Port Negative Edge Sampling 0 × 14* 30/34 18/24 12/10
Setting this bit high disables the automatic background receive 0 × 15* 30/36 18/24 12/12
filter calibration. The AD9876 automatically calibrates the
*When the Wideband Rx Filter Bit is set high, the Rx Path Gain is limited to
receive filter on reset and every few (~2) seconds thereafter to
30 dB. The first of the two values in the chart refers to this mode. The second
compensate for process and temperature variation, power sup- number refers to the mode when the lower Rx LPF Cutoff Frequency is cho-
ply, and long term drift. Programming a 1 to this bit disables sen, or the Rx LPF Filter is bypassed.
this function. Programming a 0 triggers an immediate first cali-
bration and enables the periodic update. REGISTER 7—TRANSMIT PATH SETTINGS
The AD9876 transmit path has a programmable interpolation
REGISTER 5—RECEIVE FILTER TUNING TARGET filter that proceeds the transmit DAC. The interpolation filter
This register sets the filter tuning target as a function of fOSCIN. can be programmed to operate in seven different modes. Also,
See Register 4 description. the digital interface can be programmed to operate in several
different modes. These modes are described below.
REGISTER 6—Rx PATH GAIN ADJUST Bit 0: Transmit Port Demultiplexer Bypass
The AD9876 uses a combination of a continuous time PGA Setting Bit 0 high bypasses the input data demultiplexer. In this
(CPGA) and a switched capacitor PGA (SPGA) for a gain range mode, consecutive nibbles on the Tx [5:0] pins are treated as
of –6 dB to +36 dB with a resolution of 2 dB. The Rx path gain individual words to be sent through the Tx path. This creates a
can be programmed over the serial interface by writing to the six bit data path. The state of Tx SYNC is ignored in this mode.
Rx Path Gain Adjust Register or directly using the GAIN and
MSB aligned Tx [5:1] Bits. The register default value is 0 × 00 Bit 2: Transmit Port Least Significant Nibble First
for the lowest gain setting (–6 dB). The register always reads Setting Bit 2 high reconfigures the AD9876 for a Transmit
back the actual gain setting irrespective of which of the two Mode that expects least significant nibble before the most
programming modes were used. significant nibble.
Table V describes the gains and how they are achieved as a Bit 3: Power-Down Interpolator at Tx QUIET Pin Low
function of the Rx Path adjust bits. Setting Bit 3 high enables the Tx QUIET pin to shut off the
DAC output. If the bit is set to 1, then pulling the Tx QUIET
Bit 5: PGA Gain Set by Register pin low will power down the interpolator filters. In most appli-
Setting this bit high will result in the Rx Path Gain being set by cations, the interpolator filter will need to be flushed with 0s
writing to the PGA Gain Control Register. Default is zero which before or after being powered down.
selects writing the gain through the Tx [5:1] pins in conjunction
with the gain pin.

–22– REV. A
 AD9876
Bit 4 to Bit 7: Interpolation Filter Select circuits. Following the power, grounding and layout recommen-
Bits 4 to 7 define the interpolation filter characteristics and dations in this section will help you get the best performance
interpolation rate. from the MxFE.
Bits 7:4; Component Placement
0 × 2; Interpolation Bypass If the three following guidelines of component placement are
0 × 0; see TPC 1. 4× Interpolation, LPF followed, chances for getting the best performance from the
0 × 1; see TPC 2. 2× Interpolation, LPF MxFE are greatly increased. First, manage the path of return
0 × 4; see TPC 3. 4× Interpolation, BPF, Adjacent Image currents flowing in the ground plane so that high frequency
0 × 5; see TPC 4. 2× Interpolation, BPF, Adjacent Image switching currents from the digital circuits do not flow on the
0 × 8; see TPC 5. 4× Interpolation, BPF, Lower Image ground plane under the MxFE or analog circuits. Second, keep
0 × C; see TPC 6. 4× Interpolation, BPF, Upper Image noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and
The interpolation factor has a direct influence on the CLK-A analog (noise susceptible) circuits as far away from each other
output frequency. When the transmit input data multiplexer is as possible.
enabled (10-/12-Bit Mode):
In order to best manage the return currents, pure digital circuits
f CLK − A = 2 × f DAC K
that generate high switching currents should be closest to the
where K is the interpolation factor. When the transmit input data power supply entry. This will keep the highest frequency return
multiplexer is disabled (5-/6-Bit Mode): current paths short and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
f CLK− A = f DAC K
these circuits should be generously bypassed at each device
where K is the interpolation factor. which will further reduce the high frequency ground currents.
The MxFE should be placed adjacent to the digital circuits,
REGISTER 8—RECEIVER AND CLOCK OUTPUT such that the ground return currents from the digital sections
SETTINGS will not flow in the ground plane under the MxFE. The analog
circuits should be placed furthest from the power supply.
Bit 0: Rx Port Multiplexer Bypass
Setting this bit high bypasses the Rx Port output multiplexer. The AD9876 has several pins that are used to decouple sensitive
This will output only the 6 MSBs of the ADC word. This mode internal nodes. These pins are REFIO, REFB, and REFT. The
enables ADC sampling rates above 55 MSPS. decoupling capacitors connected to these points should have
low ESR and ESL. These capacitors should be placed as close
Bit 2: Rx Port LS Nibble First to the MxFE as possible and be connected directly to the analog
Reconfigures the AD9876 for a Receive Mode that expects less ground plane.
significant bits before the most significant bits.
The resistor connected to the FSADJ pin should also be placed close
Bit 3: Three-State Rx Port to the device and connected directly to the analog ground plane.
This bit sets the receive output Rx [5:0] into a high impedance
Three-State Mode. It allows for sharing the bus with other devices. Power Planes and Decoupling
The AD9876 evaluation board demonstrates a good power
Bit 4, Bit 5: Disable CLK-A, Disable CLK-B supply distribution and decoupling strategy. The board has four
Setting Bit 4 or Bit 5 stops CLK-A or CLK-B, respectively, layers: two signal layers, one ground plane, and one power plane.
from toggling. The output is held low. Setting Bit 4 or Bit 5 The power plane is split into a 3VDD section used for the 3 V
fixes CLK-A or CLK-B to a low output level, respectively. digital logic circuits, a DVDD section used to supply the digital
Bit 6: Invert CLK-A supply pins of the AD9876, an AVDD section used to supply
Setting Bit 6 high inverts the CLK-A output signal. the analog supply pins of the AD9876/AD9875, and a VANLG
section that supplies the higher voltage analog components on
Bit 7: Invert CLK-B
the board. The 3VDD section will typically have the highest
Setting this bit high inverts the CLK-B output signal. This effec-
frequency currents on the power plane and should be kept the
tively changes the timing of the Rx [5:0] and Rx SYNC signals
furthest from the MxFE and analog sections of the board. The
from rising edge triggered to falling edge triggered with respect
DVDD portion of the plane brings the current used to power
to the CLK-B signal.
the digital portion of the MxFE to the device. This should be
treated similarly to the 3VDD power plane and be kept from
REGISTER F, DIE REVISION
going underneath the MxFE or analog components. The MxFE
This register stores the die revision of the chip. It is a Read-
should largely sit on the AVDD portion of the power plane.
Only Register.
The AVDD and DVDD power planes may be fed from the same
low noise voltage source; however, they should be decoupled
PCB DESIGN CONSIDERATIONS
from each other to prevent the noise generated in the DVDD
Although the AD9876 is a mixed-signal device, the part should
portion of the MxFE from corrupting the AVDD supply. This
be treated as an analog component. The digital circuitry on-chip
can be done by using ferrite beads between the voltage source and
has been specially designed to minimize the impact that the
DVDD and between the source and the AVDD. Both DVDD
digital switching noise will have on the operation of the analog
and AVDD should have a low ESR, bulk decoupling capacitor

REV. A –23–
AD9876
on the MxFE side of the ferrite as well as a low ESR, ESL Signal Routing
decoupling capacitors on each supply pin (i.e., the AD9876 The digital Rx and Tx signal paths should be kept as short as
requires five power supply decoupling caps, one each on Pins 5, possible. Also, the impedance of these traces should have
38, 47, 14, and 35). The decoupling caps should be placed as close a controlled characteristic impedance of about 50 Ω. This will
to the MxFE supply pins as possible. An example of the proper prevent poor signal integrity and the high currents that can
decoupling is shown in the AD9876 evaluation board schematic. occur during undershoot or overshoot caused by ringing. If the
Ground Planes signal traces cannot be kept shorter than about 1.5 inches, series

C02599–0–10/02(A)
termination resistors (33 Ω to 47 Ω) should be placed close to
In general, if the component placing guidelines discussed earlier
all signal sources. It is a good idea to series-terminate all clock
can be implemented, it is best to have at least one continuous
signals at their source, regardless of trace length.
ground plane for the entire board. All ground connections should be
made as short as possible. This will result in the lowest impedance The receive Rx⫹ and Rx⫺ signals are the most sensitive
return paths and the quietest ground connections. signals on the entire board. Careful routing of these signals
is essential for good receive path performance. The Rx⫹ and
If the components cannot be placed in a manner that will keep the
Rx⫺ signals form a differential pair and should be routed
high frequency ground currents from traversing under the MxFE
together as a pair. By keeping the traces adjacent to each other,
and analog components, it may be necessary to put current steering
noise coupled onto the signals will appear as common mode and
channels into the ground plane to route the high frequency
will be largely rejected by the MxFE receive input. Keeping the
currents around these sensitive areas. These current steering
driving point impedance of the receive signal low and placing
channels should be made only when and where necessary.
any low-pass filtering of the signals close to the MxFE will
further reduce the possibility of noise corrupting these signals.

OUTLINE DIMENSIONS

48-Lead Plastic Quad Flatpack [LQFP]

1.4 mm Thick
(ST-48)
Dimensions shown in millimeters

1.60 MAX
PIN 1
0.75 INDICATOR
9.00 BSC
0.60
0.45 48 37
1 36

SEATING
1.45 PLANE
0.20 TOP VIEW 7.00
1.40
0.09 (PINS DOWN) BSC
1.35
7ⴗ VIEW A
3.5ⴗ
0.15 0ⴗ 12 25
0.05 SEATING 0.08 MAX 13 24
PLANE COPLANARITY
0.50 0.27
VIEW A BSC 0.22
ROTATED 90ⴗ CCW 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BBC

PRINTED IN U.S.A.

Revision History
Location Page
10/02—Data Sheet changed from REV. 0 to REV. A.
Changes to to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Changes to REGISTER 3—CLOCK SOURCE CONFIGURATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

–24– REV. A