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CSE 231 Final - Summer 2021

The document is a final exam for a digital logic design course. It consists of 4 questions worth a total of 50 marks. Question 1 (10 marks) involves sequential logic concepts like D and J-K flip-flops. Question 2 (10 marks) involves designing counters using flip-flops. Question 3 (20 marks) involves drawing circuit diagrams for MOD counters and determining maximum frequencies. Question 4 (10 marks) involves explaining the speed difference between SRAM and DRAM memory and performing calculations for a 12-bit DAC. The exam is 1 hour and 20 minutes long and students are instructed to answer all questions.

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Sifat Anwar
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410 views

CSE 231 Final - Summer 2021

The document is a final exam for a digital logic design course. It consists of 4 questions worth a total of 50 marks. Question 1 (10 marks) involves sequential logic concepts like D and J-K flip-flops. Question 2 (10 marks) involves designing counters using flip-flops. Question 3 (20 marks) involves drawing circuit diagrams for MOD counters and determining maximum frequencies. Question 4 (10 marks) involves explaining the speed difference between SRAM and DRAM memory and performing calculations for a 12-bit DAC. The exam is 1 hour and 20 minutes long and students are instructed to answer all questions.

Uploaded by

Sifat Anwar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Final Exam (Summer 2021)

CSE 231: Digital Logic Design


Instructor: Dr. Mainul Hossain (MHo1)
Department of Electrical and Computer Engineering
North South University

Total Marks = 50 Date:16/09/2021 Time = 1 hour 20 mins


ANSWER ALL QUESTIONS

Question 1: Sequential Logic (Flip Flops): 10 marks

(a) A D Flip-Flop is sometimes used to introduce a delay in a logic circuit, so that the output binary
waveform appears a certain amount of time after the input. For the following input and clock signals, draw
the output signal Q of the D FF, assuming that there is a delay of one clock period between the input and
the output, [3 marks]

(b) How can you obtain a delay of two clock periods between the input and the output? [2 marks]

(c) The following figures show two kinds of J-K FFs, one with active-high (H) inputs and another with
active-low inputs. The corresponding clock pulses are also shown. Complete the following table (the first
one is done for you). [5 marks]

J-K FFs Active-High Inputs J-K FFs Active-Low Inputs

Condition J K C J K C

SET 1 0

RESET

TOGGLE

1
Question 2: Sequential Logic (Counters): 10 marks

(a) A binary counter makes a total of 1024 counts, starting from 0.

(i) How many FFs do you need to design this counter? [1 mark]

(ii) Given that the input clock has a frequency of 2 MHz, determine the output frequency of the last FF
[2 marks]

(iii) Find the MOD number of the counter [1 mark]

(iv) After 2060 pulses, what is the state of the counter, assuming that the initial state was zero? [2 marks]

(b) Design a simple 2-bit asynchronous down counter with D FFs. Show the state level diagram. [4 marks]

Question 3: Sequential Logic (Counters): 20 marks

(a) Draw the circuit diagram of a MOD-32 synchronous counter using J-K FFs. [10 marks]

(b) For the counter in part (a), determine fmax for this counter if each FF has tpd = 20 ns and each gate has
tpd =10 ns. [5 marks]

(b) Construct a MOD-4 counter using D FFs [5 marks]

Question 4: Memory and ADC/DAC: 10 marks

(a) Explain why SRAM is faster than DRAM [5 marks]

(b) A 12-bit DAC has a full-scale output of 15.0 V. Determine the step size, the percentage resolution,
and the value of VOUT for an input code of 011010010101. [5 marks]

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