Design Project 3 (Digital CMOS)

Each group will undertake the task of capturing a schematic and designing a physical layout for a CMOS
digital logic gate. Groups may choose to make either a NAND or NOR gate. NAND gates and NOR gates
are called universal gates because any other digital logic function can be replicated with a network made
only of either gate. Additionally, they are among the smallest two-input gates that can be created with a
CMOS technology, typically having four transistors.
Groups will use Electric VLSI to perform the schematic and layout steps. On Moodle, there is a set of
instructions on how to use Electric. Electric is capable of connecting to LTSpice and performing
simulation of the gate designs. Instructions for configuring Electric to work with LTSpice are also on
Moodle.
In addition to turning in an Electric VLSI library file, each group should turn in a report. The report will
have three sections. For section 1, in about 500 words, describe a VLSI/CMOS technology topic. This can
be almost anything you want: an economic perspective of integrated circuits, a historical perspective of
integrated circuits, or a discussion of the chemical/electrical processing that creates the circuits (I’m
including with this document some details that I think you should know about VLSI that will help you
understand your project, so please make sure that your discussion isn’t simply a repeat of just the
information contained here). The second section should be a write-up of the steps you took to create
and verify your schematic and layout. Use screenshots where appropriate, and explain terms like DRC
and NCC/LVS when they come up. The third section will be devoted to answering specific questions that
I ask you about the project. The third section can be in a list format with the questions and answers,
instead of in paragraph form.

This is a 3D rendering of my original inverter that I created in ELEN 339 four years ago.
Section 3 Questions
1. What is meant by the term “CMOS process”?
2. CMOS processes are often labeled by their “process node” which is a characteristic length (eg.
130nm). What is the physical meaning of this length and what is the current state-of-the-art?
3. Why is the PMOS transistor larger than the NMOS transistor?
4. Why might parasitic extraction be an important step in the design of an integrated digital logic gate?
Very Large Scale Integration (VLSI)
VLSI is the name associated with a category of engineering design principles and tools used for creating
integrated circuits. Integrated circuits are electronic circuits where the different components are
integrated into a single package (almost always into the same piece of silicon). Extremely pure platter-
like samples of silicon, called wafers, are created to hold the many thousands of integrated devices.
Wafers are put through a series of chemical treatments collectively called a “process” that etch or
deposit the different features of the circuit into/onto the surface of the wafer. Many chips can be
fabricated on one wafer, which is then diced. The dice are then placed into familiar (usually black) plastic
packages and sold to consumers. The factory which processes wafers into integrated circuits is called a
foundry. Foundry engineers need to have an interdisciplinary knowledge of electrical, mechanical, and
chemical engineering to ensure the proper fabrication of integrated circuits.
Electronics engineers create a series of design files, in the form of layer masks, which control the
chemical processing steps. Layer masks specify locations on the wafer where metal will be deposited,
where oxide will be grown, where material will be etched, or where dopants will be added. The masks
are always used in a set order, defined by the process chosen. These design files are sent to a foundry,
where they are reviewed by foundry engineers. Foundry engineers check that the instructions contained
in the design files wont direct the automated machinery to create structures which are unreliable,
unrealizable, or which may damage the machinery. An example would be checking for wires which are
too close together, where the resolution of the metal deposition process cannot guarantee the wires
will not accidentally touch. This set of constraints, called the design rules, along with other details of the
chosen fabrication process are called a technology. Generally, electronic design automation (EDA)
software, such as Electric, is capable of performing most of the design rule checks at the press of a
button, which greatly reduces the amount of times a design must be rejected by the foundry, edited,
and resubmitted. Without EDA software, the integration of billions of transistors into one circuit would
be logistically impossible.
The layers that will be used in your project are the n-well, p-well, n-active, p-active, polysilicon, metal-1,
metal-2, and via layers (vias are vertical connections between layers). The technology chosen by default
in Electric is the MoCMOS technology. MoCMOS is a CMOS process, which means the process contains
steps which would be required to build both NMOS and PMOS structures. The MoCMOS process does
not contain layers and process steps which are required to build a bipolar transistor. The default unit of
spacing in electric for a MoCMOS layout is 200nm. A transistor with size 30 units by 5 units is 6 microns
by 1 micron when fabricated. The wafers used in the MoCMOS process are lightly doped p-type silicon,
and both p-wells and n-wells must be drawn to indicate the higher doped region that you would require
for the bulk of a MOSFET. On the surface of a silicon wafer, there is usually a layer of silicon oxide. To
connect to the silicon substrate with a metal via, an opening must be specified to be etched in the oxide.
These openings are specified by the n-active and p-active layer masks. The process of drawing the layer
masks is called “layout out” a circuit, and the drawing itself is called the “layout” because it is a top-
down view.
The EDA software is capable of performing two key design functions in addition to DRC: layout-vs-
schematic (LVS) comparison and parasitic extraction. A schematic contains information on only the
connectivity of devices, whereas the layout contains the physical geometric information. Typically a
design is first made as a schematic and then the schematic is used as a guide to create the layout. EDA
tools like Electric can perform a netlist extraction to determine the connectivity of devices from a layout,
and compare the extracted netlist to your schematic netlist to make sure they match. Electric calls the
LVS function Network Consistency Check (NCC). Electric can also perform a parasitic extraction which
infers extra devices, such as capacitors between wires which are too close, which help model real-world
unintentional coupling due to physical placement.

This is an example elevation or profile view of an integrated circuit. It shows the different coper (metal)
layers and locations of n- and p-wells. All EDA software requires input in the top-down layout view. So
this is an unusual perspective, but it might help you understand what your final design really looks like.