Morar Block Diagram 2005/05/28

A B C D E

Mobile CPU G792 Project Code:91.4E101.001 SYSTEM DC/DC

CLK GEN.
4
19
PCB:05210-SB TPS5130 35,36
4

IDT CV125 Dothan INPUTS OUTPUTS

3 4, 5 3D3V_S5
5V_S5

HOST BUS 400MHz

RGB CRT DCBATOUT
1D05V_S0
CONN 14 2D5V_S0(LDO)
DDR II 400MHz
LCD SYSTEM DC/DC
400 MHz Intel 910GML XGA/WXGA ISL6227 37
11,12 LVDS
13 INPUTS OUTPUTS
DDR II 400MHz DCBATOUT
5V_S5

400 MHz 6,7,8,9,10 3D3V_S3

11,12
TPS51100DGQ 37
DMI I/F 100MHz DDR_VREF
3 5V_S5 3
DDR_VREF_S3

Line In27 ACLINK ENE

Codec PCI BUS CB1410 PWR SW CHARGER
PCMCIA ISL6255
ALC655 CP2211 38
Int. 26 25
24,25
ONE SLOT
MIC In 27 25
INPUTS OUTPUTS

DCBATOUT
BT+
ICH6-M Mini-PCI 16.8V 3A
Line Out OP AMP 802.11 B/G 28
27
G1421B 27 LAN
10/100
RTL8110CL
TXFM RJ4523 CPU DC/DC
23 ISL6218CV-T
22, 23
2 34 2

INT.SPKR MODEM
27 INPUTS OUTPUTS
MDC Card
21 VCC_CORE
LPC BUS DCBATOUT
0.844~1.3V
27A
15,16,17,18
Xbus BIOS ROM
PATA

KBC 4M BITS
ENE KB3910 PM39LV040-70JCE

USB 29 31
4 PORT
HDD CD ROM 21
20 20
1 1

MINI USB 21 Touch INT_KB Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Blue-tooth Pad 30 30 Taipei Hsien 221, Taiwan, R.O.C.

Title
BLOCK DIAGRAM
Size Document Number Rev
Custom
MORAR SB
Date: Thursday, June 09, 2005 Sheet 1 of 40

A B C D E
 A B C D E
Alviso Strapping Signals ICH6-M Integrated Pull-up
and Configuration page 7 and Pull-down Resistors ICH6-M EDS 14308 0.8V1
Pin Name Strap Description Configuration
ACZ_BIT_CLK, DPRSLP#, EE_DIN,
CFG[2:0] FSB Frequency Select 000 = Reserved
001 = FSB533 EE_DOUT, GNT[5]#/GPO[17],
010 = FSB800 ICH6 internal 20K pull-ups
011-111 = Reversed GNT[6]#/GPO[16], LDRQ[1]/GPI[41],
4 CFG[3:4] Reversed LAD[3:0]#/FB[3:0]#, LDRQ[0],
4
CFG5 DMI x2 Select 0 = DMI x2 PME#, PWRBTN#, TP[3]
1 = DMI x4 (Default)
0 = DDR II
CFG6 DDR I / DDR II 1 = DDR I LAN_RXD[2:0] ICH6 internal 10K pull-ups
CFG7 CPU Strap 0 = Prescott
1 = Dothan (Default) ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs
CFG[8:11] Reversed ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
CFG[12:13] XOR/ALL Z test 00 = Reserved SPKR, EE_CS,
straps 01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation USB[7:0][P,N] ICH6 internal 15K pull-downs
(Default)
CFG[14:15] Reversed DD[7], SDDREQ ICH6 internal 11.5K pull-downs
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled LAN_CLK ICH6 internal 100K pull-downs
(Default)
CFG17 Reversed
CFG18 CPU core VCC 0 = 1.05V (Default)
Select 1 = 1.5V
3 CFG19 CPU VTT Select 0 = 1.05V (Default)
ICH6-M IDE Integrated Series 3
1 = 1.2V
CFG20 Reversed
PCI Routing Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ,
SDVOCRTL SDVO Present 0 = No SDVO device present IDSEL IRQ REQ/GNT approximately 33 ohm
_DATA (Default) DDACK#, IORDY, DA[2:0], DCS1#,
1= SDVO device present
7411 25 B.F.G 0 DCS3#, IDEIRQ
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
MiniPCI 21 F 1
LAN 23 E 2

2 2

1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Memo
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 2 of 40
 3D3V_S0 3D3V_S0 3D3V_S0
R191 R166 R155
1 2 3D3V_APWR_S0 1 2 3D3V_48MPWR_S0 1 2 3D3V_CLKGEN_S0
1 0R3-U

1
0R3-U 0R3-U
C201 C203 C215 C192 C191 C190 C200 C202 C214 C216 C217 C189 C193 C194 C188
SCD1U16V SC4D7U10V5ZY SCD1U16V SCD1U16V SC4D7U6D3V3KX SCD1U16V SCD1U16V SC10U10V5ZY-L SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
DREFSSCLK1 2 3 DREFSSCLK 7
DREFSSCLK#1 1 4 DREFSSCLK# 7

RN16
SRN33-2-U2

U13

R222 1 2 33R2 56 17
28 PCLK_MINI R175 33R2 PCI0 LVDS
22 PCLK_LAN 1 2 3 PCI1 LVDS# 18
R174 1 2 22R2 4
24 PCLK_PCM R173 33R2 PCI2
29 PCLK_KBC 1 2 5 PCI3 SRC1 19
H/L: 100/96MHz SRC1# 20
SS_SEL 9 22
R172 PCIF1/SEL100/96# SRC2
16 CLK_ICHPCI 1 2 33R2 ITP_EN 8 PCIF0/ITP_EN SRC2# 23
3D3V_S0
H/L : CPU_ITP/SRC7 SRC3 24
16 PM_STPPCI# 55 PCI_STOP# SRC3# 25
26 RN20 1 4 SRN33-2-U2 CLK_PCIE_ICH 16
SRC4
SRC4# 27 2 3 CLK_PCIE_ICH# 16
1

46 31 CLK_PCIE_ICH1
R151 11,18 SMBC_ICH SCL SRC5 CLK_PCIE_ICH#1 RN21
11,18 SMBD_ICH 47 SDA SRC5# 30 1 4 SRN33-2-U2 CLK_MCH_3GPLL 7
10KR2 33 CLK_MCH_3GPLL1 2 3
SRC6 CLK_MCH_3GPLL# 7
RN17 SRN33-2-U2 32 CLK_MCH_3GPLL#1
SRC6#
3 2 14
2

7 DREFCLK DOT96 CLK_XDP_CPU1 RN22

7 DREFCLK# 4 1 15 DOT96# CPU2_ITP/SRC7 36 1 4 SRN33-2-U2 CLK_XDP_CPU 4
Morar_SB VTT_PWRGD# 35 CLK_XDP_CPU#1 2 3 CLK_XDP_CPU# 4
CPU2_ITP#/SRC7#
C205 50 44 CLK_CPU_BCLK1 RN24 1 4 SRN33-2-U2 CLK_CPU_BCLK 4
XTAL_IN CPU0 CLK_CPU_BCLK#1
Q14 1 2 49 43 2 3 CLK_CPU_BCLK# 4
XTAL_OUT CPU0#
3 OUT 2 26 CLK_Audio
R218 1 2 33R2 CPU1 41 CLK_MCH_BCLK1
2 R1 SC33P50V2JN R217 1 2 33R2 40 CLK_MCH_BCLK#1 RN23 1 4 SRN33-2-U2
32,34 6218_PGOOD 16 CLK_ICH14 CPU1# CLK_MCH_BCLK 6
IN 1 GND 52 REF 2 3 CLK_MCH_BCLK# 6
R2 X1 R212 1 2 475R2F 39 54
IREF CPU_STOP# PM_STPCPU# 16,34
DTC124EKA C204 X-14D31818M-1 53 CPU_SEL0
1

FSC/TEST_SEL CPU_SEL1
1 2 FSB/TEST_MODE 16
VTT_PWRGD# 10 12 FS_A R163 2 1 22R2
SC33P50V2JN VTT_PWRGD#/PD USB48/FSA CLK48_ICH 16
CLK_ICH14 & CLK14_SIO
2 34 3D3V_CLKGEN_S0
3D3V_S0 need equal length 6
VSS_PCI VDD_SRC
21
VSS_PCI VDD_SRC
51 VSS_REF VDD_PCI 7
45 VSS_CPU VDD_PCI 1
1

38 VSSA
R167 R168 13 48
10KR2 10KR2 VSS48 VDD_REF
29 VSS_SRC VDD_CPU 42
IN EN OUT 37 3D3V_APWR_S0
VDDA 3D3V_48MPWR_S0
(3D3V_S0) (6218_PGOOD) (VTT_PWRGD#) 11
2

VDD48
VDD_SRC 28
H L H ITP_EN
SS_SEL
X H Hi - Z
1

IDTCV125PA
DY R169 R170 DY
10KR2 10KR2 EMI capacitor
2

CLK_ICH14 EC111 SC10P50V2JN-1

DY
3D3V_CLKGEN_S0 1D05V_S0

CLK_CPU_BCLK R216 1 2 49D9R2F

1

R159 R221 CLK_CPU_BCLK# R215 1 2 49D9R2F PCLK_PCM EC93 SC10P50V2JN-1

R162 DY
DUMMY-R2

DUMMY-R2

1KR2 CLK_PCIE_ICH R206 1 2 49D9R2F CLK_MCH_BCLK R214 1 2 49D9R2F PCLK_MINI EC113 SC10P50V2JN-1
DY
CLK_PCIE_ICH# R205 1 2 49D9R2F CLK_MCH_BCLK# R213 1 2 49D9R2F PCLK_KBC EC92 SC10P50V2JN-1
DY
2

FS_A DREFSSCLK# R156 1 2 49D9R2F CLK_ICHPCI EC91 SC10P50V2JN-1

CLK_MCH_3GPLL R209 1 2 49D9R2F DY
DREFSSCLK R157 1 2 49D9R2F CLK48_ICH EC90 SC10P50V2JN-1
CPU_SEL1 7
CLK_MCH_3GPLL# R207 1 2 49D9R2F DY
CPU_SEL0 4,7 DREFCLK R161 1 2 49D9R2F
CLK_XDP_CPU R211 1 2 49D9R2F
1

R165 R158 R220 DREFCLK# R160 1 2 49D9R2F

FS_C FS_B FS_A CPU CLK_XDP_CPU# R210 1 2 49D9R2F
DUMMY-R2

DUMMY-R2

DUMMY-R2

0 0 0 266M
0 0 1 133M
0 1 0 200M Wistron Corporation
2

0 1 1 166M 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1 0 0 333M Taipei Hsien 221, Taiwan, R.O.C.
1 0 1 100M
1 1 0 400M Title
1 1 1 Reserved
Clock Generator - IDT125
Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 3 of 40
 A B C D E

ADDR GROUP 0
U35A TP6
BGA479-SKT-2-U
TPAD28 1D05V_S0
4 H_A#3 P4 N2 4
6 H_A#[31..3] A3# ADS# H_ADS# 6
H_A#4 U4 L1
A4# BNR# H_BNR# 6
H_A#5 V3 J3 H_BPRI# 6
A5# BPRI#

1
H_A#6 R3
H_A#7 A6# R362
V2 A7# DEFER# L4 H_DEFER# 6
H_A#8 W1 H2 56R2J
A8# DRDY# H_DRDY# 6
H_A#9 T4 M2
A9# DBSY# H_DBSY# 6
H_A#10 W2

2
H_A#11 A10# Place testpoint on
Y4 A11# BR0# N4 H_BREQ#0 6
H_A#12 Y1 H_IERR# with a GND

CONTROL
H_A#13 A12# H_IERR# 0.1" away
U1 A13# IERR# A4
H_A#14 AA3 B5 H_INIT# 15
H_A#15 A14# INIT#
Y3 A15#
H_A#16 AA2 J2
A16# LOCK# H_LOCK# 6
6 H_ADSTB#0 U3 ADSTB#0 H_CPURST# 6
6 H_REQ#[4..0] RESET# B11 H_RS#[2..0] 6
H_REQ#0 R2 H1 H_RS#0
H_REQ#1 P3 REQ0# RS0# H_RS#1 U35B
REQ1# RS1# K1 H_D#[63..0] 6
H_REQ#2 T2 L2 H_RS#2 BGA479-SKT-2-U
H_REQ#3 P1 REQ2# RS2# H_D#0 H_D#32
REQ3# TRDY# M3 H_TRDY# 6 A19 D0# D32# Y26 H_DINV#[3..0] 6
H_REQ#4 T1 H_D#1 A25 AA24 H_D#33
REQ4# H_D#2 D1# D33# H_D#34
K3 H_HIT# 6 A22 T25 H_DSTBN#[3..0] 6

XTP/ITP SIGNALS
H_A#17 HIT# H_D#3 D2# D34# H_D#35
AF4 K4 B21 U23

DATA GRP 0
DATA GRP 2
A17# HITM# H_HITM# 6 D3# D35#
H_A#18 AC4 H_D#4 A24 V23 H_D#36
A18# D4# D36# H_DSTBP#[3..0] 6
H_A#19 AC7 C8 XDP_BPM#0 TPAD28 TP10 H_D#5 B26 R24 H_D#37
ADDR GROUP 1
H_A#20 A19# BPM#0 XDP_BPM#1 TPAD28 TP9 H_D#6 D5# D37# H_D#38
AC3 A20# BPM#1 B8 A21 D6# D38# R26
H_A#21 AD3 A9 XDP_BPM#2 TPAD28 TP11 H_D#7 B20 R23 H_D#39
H_A#22 A21# BPM#2 XDP_BPM#3 TPAD28 TP12 H_D#8 D7# D39# H_D#40
AE4 A22# BPM#3 C9 C20 D8# D40# AA23
H_A#23 AD2 A10 XDP_BPM#4 TPAD28 TP14 H_D#9 B24 U26 H_D#41
3 H_A#24 A23# PRDY# XDP_BPM#5 TPAD28 TP13 H_D#10 D9# D41# H_D#42 3
AB4 A24# PREQ# B10 D24 D10# D42# V24
H_A#25 AC6 A13 XDP_TCK TPAD28 TP72 H_D#11 E24 U25 H_D#43
H_A#26 A25# TCK XDP_TDI TPAD28 TP70 H_D#12 D11# D43# H_D#44
AD5 A26# TDI C12 C26 D12# D44# V26
H_A#27 AE2 A12 XDP_TDO TPAD28 TP71 H_D#13 B23 Y23 H_D#45
H_A#28 A27# TDO XDP_TMS TPAD28 TP69 H_D#14 D13# D45# H_D#46
AD6 A28# TMS C11 E23 D14# D46# AA26
H_A#29 AF3 B13 XDP_TRST# TPAD28 TP73 H_D#15 C25 Y25 H_D#47
H_A#30 A29# TRST# XDP_DBRESET# TPAD28 TP68 H_DSTBN#0 D15# D47# H_DSTBN#2
AE1 A30# DBR# A7 C23 DSTBN0# DSTBN2# W25
H_A#31 AF1 H_DSTBP#0 C22 W24 H_DSTBP#2
A31# CPU_PROCHOT# TPAD28 TP74 H_DINV#0 DSTBP0# DSTBP2# H_DINV#2
6 H_ADSTB#1 AE5 ADSTB#1 PROCHOT# B17 D25 DINV0# DINV2# T24
B18
HCLK THERM

THERMDA H_THERMDA 19
15 H_A20M# C2 A20M# THERMDC A18 H_THERMDC 19
D3 PM_THRMTRIP-A# 7 H_D#16 H23 AB25 H_D#48
15 H_FERR# FERR# H_D#17 D16# D48# H_D#49
15 H_IGNNE# A3 IGNNE# THERMTRIP# C17 G25 D17# D49# AC23
1 R377 2 0R0402-PAD PM_THRMTRIP-I# 15,19 H_D#18 L23 AB24 H_D#50
R360 2 H_STPCLK_R H_D#19 D18# D50# H_D#51
1 C6 A15 CLK_XDP_CPU# 3 M26 AC20

DATA GRP 1
DATA GRP 3
H_STPCLK# 0R0402-PAD STPCLK# ITP_CLK1 H_D#20 D19# D51# H_D#52
15 H_INTR D1 LINT0 ITP_CLK0 A16 CLK_XDP_CPU 3 H24 D20# D52# AC22
D4 B14 CLK_CPU_BCLK# 3 H_D#21 F25 AC25 H_D#53
15 H_NMI LINT1 BCLK1 H_D#22 D21# D53# H_D#54
15 H_SMI# B4 SMI# BCLK0 B15 CLK_CPU_BCLK 3 G24 D22# D54# AD23
H_D#23 J23 AE22 H_D#55
H_D#24 D23# D55# H_D#56
M23 D24# D56# AF23
connector PM_THRMTRIP# H_D#25 J25 AD24 H_D#57 Layout Note:
62.10053.061 should connect to H_D#26 D25# D57# H_D#58 Comp0, 2 connect with Zo=27.4 ohm, make
L26 D26# D58# AF20
ICH6 and Alviso H_D#27 N24 AE21 H_D#59 trace length shorter than 0.5" .
without T-ing H_D#28 D27# D59# H_D#60 Comp1, 3 connect with Zo=55 ohm, make
Morar_SA:62.10053.061 M25 D28# D60# AD21
( No stub) H_D#29 H26 AF25 H_D#61 trace length shorter than 0.5" .
H_D#30 D29# D61# H_D#62
Morar_SB:62.10053.061 N25 D30# D62# AF22
H_D#31 K25 AF26 H_D#63
H_DSTBN#1 K24 D31# D63# H_DSTBN#3
Morar_SB:62.10055.011(2nd) DSTBN1# DSTBN3# AE24
H_DSTBP#1 L24 AE25 H_DSTBP#3
2 H_DINV#1 DSTBP1# DSTBP3# H_DINV#3 2
J26 DINV1# DINV3# AD20
1D05V_S0
To V-CORE SWITCH TP7 E1 P25 COMP0 R35 1 2 27D4R2F
TPAD28 PSI# COMP0 COMP1 R36 54D9R2F
COMP1 P26 1 2

1
R374 1 2 0R3-U C16 AB2 COMP2 R24 1 2 27D4R2F
3,7 CPU_SEL0 BSEL0 COMP2 COMP3 R27 54D9R2F R41
C14 BSEL1 COMP3 AB1 1 2
TP15 TPAD28 200R2F
1D05V_S0
1D05V_S0 MISC G1 H_DPRSLP# 15

2
DPRSTP#
C3 RSVD2 DPSLP# B7 H_DPSLP# 15

1
TP8 TPAD28 AF7 C19 H_DPWR# 6
CPU_PROCHOT# R376 1 RSVD3 DPWR#
2 56R2F R320 TP67 TPAD28 AC1 RSVD4 PWRGOOD E4 H_PWRGD 15,19
1KR2F TP5 TPAD28 E26 A6 H_CPUSLP# 6,15
XDP_TDI R370 1 RSVD5 SLP#
2 150R2F TP16 TPAD28
GTLREF0 AD26 C5 TEST1
1 2

XDP_TMS R369 1 GTLREF0 TEST1

2 39D2R3F TEST2 F23 TEST2
Layout Note:
XDP_TDO R371 1 2 54D9R2F 0.5" max length.
R315 connector

1
H_CPURST# R366 1 2 54D9R2F 2KR2F 62.10053.061
R43 R359
2

1KR2 1KR2
3D3V_S0 BSEL[1:0] Freq.(MHz)
(A Stepping) DY DY

2
XDP_DBRESET# R365 1 2 150R2F LL 100
LH 133

1
XDP_TCK R372 1 2 27D4R2F BSEL[1:0] Freq.(MHz) 1
(B Stepping)
XDP_TRST# R373 1 2 680R3F LH 100
LL 133
All place within 2" to CPU Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (1 of 2)
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 4 of 40
A B C D E
 A B C D E

VCC_CORE_S0 U35D BGA479-SKT-2-U

A2 VSS0 VSS97 D13
VCC_CORE_S0 A5 D15
VSS1 VSS98
U35C A8 VSS2 VSS99 D17
A11 VSS3 VSS100 D19
BGA479-SKT-2-U A14 D21
VSS4 VSS101
AA11 VCC0 VCC59 G5 A17 VSS5 VSS102 D23
AA13 VCC1 VCC60 H22 A20 VSS6 VSS103 D26
AA15 VCC2 VCC61 H6 A23 VSS7 VSS104 E3
AA17 VCC3 VCC62 J21 A26 VSS8 VSS105 E6
AA19 VCC4 VCC63 J5 AA1 VSS9 VSS106 E8
AA21 VCC5 VCC64 K22 AA4 VSS10 VSS107 E10
AA5 VCC6 VCC65 U5 AA6 VSS11 VSS108 E12
4 AA7 V22 1D5V_VCCA_S0 AA8 E14 4
VCC7 VCC66 VSS12 VSS109
AA9 VCC8 VCC67 V6 AA10 VSS13 VSS110 E16
AB10 VCC9 VCC68 W21 AA12 VSS14 VSS111 E18

SC10U10V5ZY-L
AB12 VCC10 VCC69 W5 AA14 VSS15 VSS112 E20

1
SCD01U16V2KX
AB14 VCC11 VCC70 Y22 AA16 VSS16 VSS113 E22

C339
AB16 Y6 C338 AA18 E25
VCC12 VCC71 VSS17 VSS114
AB18 AA20 F1

2
VCC13 VSS18 VSS115
AB20 VCC14 VCCA0 F26 AA22 VSS19 VSS116 F4
AB22 VCC15 VCCA1 B1 Place these AA25 VSS20 VSS117 F5
AB6 VCC16 VCCA2 N1 PM_SLP_S3#_ICH 16 and dummy AB3 VSS21 VSS118 F7
AB8 AC26 1D05V_S0 AB5 F9
VCC17 VCCA3 1D5V_VCCA_S0 12K7R3F for VSS22 VSS119
AC11 VCC18 AB7 VSS23 VSS120 F11

1
D10 CPU_D10 R33 2

DUMMY-R2
AC13 VCC19 VCCP0 1 1D8V_VCCA_S0 AB9 VSS24 VSS121 F13
AC15 D12 0R0402-PAD AB11 F15
VCC20 VCCP1 VSS25 VSS122

R352
AC17 VCC21 VCCP2 D14 AB13 VSS26 VSS123 F17

1
AC19 VCC22 VCCP3 D16 AB15 VSS27 VSS124 F19

1
AC9 E11 I max = 120 mA R333 R334 AB17 F21
AD10
VCC23 VCCP4
E13 DY BC7 DY
22KR3F DY AB19
VSS28 VSS125
F24

2
VCC24 VCCP5 SC22P50V2JN-1 12K7R3F VSS29 VSS126
AD12 E15 U36 AB21 G2

2
VCC25 VCCP6 VSS30 VSS127
AD14 F10 AB23 G6

2
VCC26 VCCP7 VSS31 VSS128
AD16 VCC27 VCCP8 F12 3D3V_S0 1 SHDN# SET 5 AB26 VSS32 VSS129 G22
AD18 VCC28 VCCP9 F14 2 GND AC2 VSS33 VSS130 G23

1
AD8 VCC29 VCCP10 F16 3 IN OUT 4 AC5 VSS34 VSS131 G26
AE11 K6 R335 AC8 H3
AE13
VCC30
VCC31
VCCP11
VCCP12 L21 DY 49K9R2F AC10
VSS35
VSS36
VSS132
VSS133 H5

1
AE15 L5 G913C-U AC12 H21
VCC32 VCCP13 BC9 BC8 VSS37 VSS134
AE17 M22 AC14 H25
DY

2
VCC33 VCCP14 SC1U10V3ZY SC1U10V3ZY VSS38 VSS135
AE19 M6 AC16 J1

2
VCC34 VCCP15 VSS39 VSS136
AE9 N21 AC18 J4
3 AF10
VCC35
VCC36
VCCP16
VCCP17 N5 DY DY AC21
VSS40
VSS41
VSS137
VSS138 J6 3
AF12 VCC37 VCCP18 P22 AC24 VSS42 VSS139 J22
AF14 VCC38 VCCP19 P6 AD1 VSS43 VSS140 J24
AF16 VCC39 VCCP20 R21 AD4 VSS44 VSS141 K2
AF18 VCC40 VCCP21 R5 AD7 VSS45 VSS142 K5
AF8 VCC41 VCCP22 T22 AD9 VSS46 VSS143 K21
D18 VCC42 VCCP23 T6 AD11 VSS47 VSS144 K23
D20 U21 1D5V_S0 1D5V_VCCA_S0 AD13 K26
VCC43 VCCP24 VSS48 VSS145
D22 VCC44 AD15 VSS49 VSS146 L3
D6 VCC45 VCCQ0 P23 R332 AD17 VSS50 VSS147 L6
D8 VCC46 VCCQ1 W4 1 2 AD19 VSS51 VSS148 L22
E17 VCC47 AD22 VSS52 VSS149 L25
E19 E2 H_VID0 34 0R3-U AD25 M1
VCC48 VID0 VSS53 VSS150
E21 VCC49 VID1 F2 H_VID1 34 AE3 VSS54 VSS151 M4
E5 VCC50 VID2 F3 H_VID2 34 AE6 VSS55 VSS152 M5
E7 VCC51 VID3 G3 H_VID3 34 AE8 VSS56 VSS153 M21
E9 VCC52 VID4 G4 H_VID4 34 AE10 VSS57 VSS154 M24
F18 VCC53 VID5 H4 H_VID5 34 AE12 VSS58 VSS155 N3
F20 VCC54 AE14 VSS59 VSS156 N6
F22 1D05V_S0 AE16 N22
VCC55 TP_VCCSENSE VSS60 VSS157
F6 VCC56 VCCSENSE AE7 AE18 VSS61 VSS158 N23
F8 VCC57 AE20 VSS62 VSS159 N26

ST100U6D3VM-U
TP_VSSSENSE
SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V
G21 VCC58 VSSSENSE AF6 AE23 VSS63 VSS160 P2
AE26 VSS64 VSS161 P5
1

AF2 VSS65 VSS162 P21

1

1
connector AF5 P24
VSS66 VSS163

TC8
C44

C46

C51

C28

C27

C54

C43

C35

C34

C15
62.10053.061 R313 R314 AF9 R1
VSS67 VSS164
54D9R2F

54D9R2F

AF11 R4
2

2
VSS68 VSS165
AF13 R6
2

2 VSS69 VSS166 2
AF15 VSS70 VSS167 R22
AF17 R25
DY AF19
VSS71
VSS72
VSS168
VSS169 T3
AF21 VSS73 VSS170 T5
Layout Note:
VCCSENSE and VSSSENSE lines
DY DY VCC_CORE_S0 Morar_SB
AF24
B3
VSS74 VSS171 T21
T23
should be of equal length. VSS75 VSS172
B6 VSS76 VSS173 T26
B9 VSS77 VSS174 U2
SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX
B12 VSS78 VSS175 U6
1

1
C320

C321

C324

C336

C332

C333

C11

C18

C25

C23

C22

C20

C19

C16
Layout Note: B16 U22
Provide a test point (with VSS79 VSS176
B19 VSS80 VSS177 U24
no stub) to connect a B22 V1
2

2
differential probe VSS81 VSS178
B25 VSS82 VSS179 V4
between VCCSENSE and C1 V5
VSSSENSE at the location DY DY DY DY DY DY DY C4
VSS83
VSS84
VSS180
VSS181 V21
where the two 54.9ohm C7 V25
resistors terminate the VSS85 VSS182
C10 VSS86 VSS183 W3
55 ohm transmission line. VCC_CORE_S0 C13 W6
VSS87 VSS184
SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

C15 VSS88 VSS185 W22

C18 VSS89 VSS186 W23
SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX
C21 VSS90 VSS187 W26
1

1
C40

C17

C26

C325

C14
C24 VSS91 VSS188 Y2
C36

C52

C53

C37

C47

C38

C50

C55

C33

C45

D2 VSS92 VSS189 Y5
D5 Y21
2

2
VSS93 VSS190
D7 VSS94 VSS191 Y24
D9
DY D11
VSS95
VSS96 connector
62.10053.061
1
VCC_CORE_S0 <Core Design> 1

Wistron Corporation
SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX
1

1
C49

C42

C48

C39

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
2

Title

DY DY DY CPU (2 of 2)
Size Document Number Rev
A3
MORAR SB
Date: Thursday, May 26, 2005 Sheet 5 of 40
A B C D E
 A B C D E

H_XRCOMP

1
R356
24D9R2F
U45A
4 H_D#[63..0] H_A#[31..3] 4

2
H_D#0 E4 G9 H_A#3
H_D#1 HD0# HA3# H_A#4
4 E1 HD1# HA4# C9 4
H_D#2 F4 E9 H_A#5
H_D#3 HD2# HA5# H_A#6
H7 HD3# HA6# B7
H_D#4 E2 A10 H_A#7
1D05V_S0 H_D#5 HD4# HA7# H_A#8
F1 HD5# HA8# F9
H_D#6 E3 D8 H_A#9
H_D#7 HD6# HA9# H_A#10
D3 HD7# HA10# B10
H_D#8 K7 E10 H_A#11
HD8# HA11#

2
H_D#9 F2 G10 H_A#12
R355 H_D#10 HD9# HA12# H_A#13
J7 HD10# HA13# D9
54D9R2F H_D#11 J8 E11 H_A#14
H_D#12 HD11# HA14# H_A#15
H6 HD12# HA15# F10
H_D#13 F3 G11 H_A#16
1
H_D#14 HD13# HA16# H_A#17
K8 HD14# HA17# G13
H_XSCOMP H_D#15 H5 C10 H_A#18
H_D#16 HD15# HA18# H_A#19
H1 HD16# HA19# C11
H_D#17 H2 D11 H_A#20
H_D#18 HD17# HA20# H_A#21
K5 HD18# HA21# C12
1D05V_S0 H_D#19 K6 B13 H_A#22
H_D#20 HD19# HA22# H_A#23
J4 HD20# HA23# A12
H_D#21 G3 F12 H_A#24
HD21# HA24#
1

H_D#22 H3 G12 H_A#25

R358 H_D#23 HD22# HA25# H_A#26
J1 HD23# HA26# E12
221R2F-L H_D#24 L5 C13 H_A#27 1D05V_S0
H_D#25 HD24# HA27# H_A#28
K4 HD25# HA28# B11
H_D#26 J5 D13 H_A#29
2

HD26# HA29#

1
H_XSWING H_D#27 P7 A13 H_A#30
H_D#28 HD27# HA30# H_A#31 R73
L7 HD28# HA31# F13
1

H_D#29 J3 100R2F
HD29#
2

3 R357 H_D#30 P5 F8 3
100R2F HD30# HADS# H_ADS# 4
C343 H_D#31 L3 B9 H_ADSTB#0 4

2
SCD1U16V H_D#32 HD31# HADSTB#0
U7 E13 H_ADSTB#1 4
1

H_D#33 HD32# HADSTB#1 H_VREF

V6 J11
2

H_D#34 HD33# HVREF

R6 HD34# HBNR# A5 H_BNR# 4

1
H_D#35 R5 D5 H_BPRI# 4
HD35# HBPRI#

2
H_D#36 P3 E7 R72
HD36# HBREQ0# H_BREQ#0 4 200R2F
H_D#37 T8 H10 H_CPURST# 4 C105
H_D#38 HD37# HCPURST# SCD1U16V
R7

1
H_D#39 HD38#
R8

2
H_D#40 HD39#
U8

HOST
H_YRCOMP H_D#41 HD40#
R4 HD41# HCLKINN AB1 CLK_MCH_BCLK# 3
H_D#42 T4 AB2 CLK_MCH_BCLK 3
H_D#43 HD42# HCLKINP
T5 HD43#
1

H_D#44 R1 C6
HD44# HDBSY# H_DBSY# 4
R368 H_D#45 T3 E6 H_DEFER# 4
HD45# HDEFER# H_DINV#[3..0] 4
24D9R2F H_D#46 V8 H8 H_DINV#0
H_D#47 HD46# HDINV#0 H_DINV#1
U6 HD47# HDINV#1 K3
H_D#48 W6 T7 H_DINV#2
2

H_D#49 HD48# HDINV#2 H_DINV#3

U3 HD49# HDINV#3 U5
H_D#50 V5 G6 H_DPWR# 4
H_D#51 HD50# HDPWR#
W8 HD51# HDRDY# F7 H_DRDY# 4 H_DSTBN#[3..0] 4
H_D#52 W7 G4 H_DSTBN#0
H_D#53 HD52# HDSTBN#0 H_DSTBN#1
U2 HD53# HDSTBN#1 K1
1D05V_S0 H_D#54 U1 R3 H_DSTBN#2
H_D#55 HD54# HDSTBN#2 H_DSTBN#3
Y5 HD55# HDSTBN#3 V3 H_DSTBP#[3..0] 4
H_D#56 Y2 G5 H_DSTBP#0
H_D#57 HD56# HDSTBP#0 H_DSTBP#1
V4 HD57# HDSTBP#1 K2
2

H_D#58 Y7 R2 H_DSTBP#2
2 R363 H_D#59 HD58# HDSTBP#2 H_DSTBP#3 2
W1 HD59# HDSTBP#3 W4
54D9R2F H_D#60 W3 F6 TP_H_EDRDY# TPAD28 TP19
H_D#61 HD60# HEDRDY#
Y3 HD61# HHIT# D4 H_HIT# 4
H_D#62 Y6 D6 H_HITM# 4
1

H_D#63 HD62# HHITM#

W2 HD63# HLOCK# B3 H_LOCK# 4
H_YSCOMP A11 TP_H_PCREQ#
HPCREQ# H_REQ#[4..0] 4
H_XRCOMP C1 A7 H_REQ#0 TPAD28 TP75
H_XSCOMP HXRCOMP HREQ#0 H_REQ#1
C2 HXSCOMP HREQ#1 D7
H_XSWING D1 B8 H_REQ#2
1D05V_S0 H_YRCOMP HXSWING HREQ#2 H_REQ#3
T1 HYRCOMP HREQ#3 C7
H_YSCOMP L1 A8 H_REQ#4 H_RS#[2..0] 4
H_YSWING HYSCOMP HREQ#4 H_RS#0
P1 HYSWING HRS0# A4
1

C5 H_RS#1
R364 HRS1# H_RS#2
HRS2# B4
221R2F-L G8 H_CPUSLP#_1 R361 1 2 0R2-0
HCPUSLP# H_CPUSLP# 4,15
HTRDY# B5 H_TRDY# 4
DUMMY FOR DOTHAN A STEPPING
2

H_YSWING
1

71.0GMCH.08U
2

R367
100R2F C345
SCD1U16V
1
2

1 <Core Design> 1
Place them near to the chip
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (1 of 5)
Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 6 of 40
A B C D E
 A B C D E

1D05V_S0

1
R70
10KR2 CFG[2:0] Freq.(MHz)
U45B 101 400
001 533 Alviso will provide SDVO_CTRLCLK

2
DMI_TXN0 AA31 G16 CFG0 and CTRLDATA pulldowns on-die
16 DMI_TXN0 DMI_TXN1 DMIRXN0 CFG0 U45G
16 DMI_TXN1 AB35 DMIRXN1 CFG1 H13 CPU_SEL1 3
4 DMI_TXN2 4
16 DMI_TXN2 AC31 DMIRXN2 CFG2 G14 CPU_SEL0 3,4
DMI_TXN3 AD35 F16 CFG3 TP23 TPAD28 SDVOC_CTRLDATA H24 D36
16 DMI_TXN3 DMIRXN3 CFG3 CFG4 TP22 TPAD28 SDVOC_CTRLCLK H25 SDVOCTRL_DATA EXP_COMPI

MISC
CFG4 F15 SDVOCTRL_CLK EXP_ICOMPO D34
DMI_TXP0 Y31 G15 CFG5 AB29
16 DMI_TXP0 DMI_TXP1 DMIRXP0 CFG5 CFG6 3 CLK_MCH_3GPLL# GCLKN
16 DMI_TXP1 AA35 DMIRXP1 CFG6 E16 3 CLK_MCH_3GPLL AC29 GCLKP EXP_RXN0 E30
DMI_TXP2 AB31 D17 CFG7 F34
16 DMI_TXP2 DMI_TXP3 DMIRXP2 CFG7 CFG8 GMCH_TV_COMP EXP_RXN1
16 DMI_TXP3 AC35 DMIRXP3 CFG8 J16 A15 TVDAC_A EXP_RXN2 G30
D15 CFG9 GMCH_TV_LUMA C16 H34

DMI
CFG9 TVDAC_B EXP_RXN3

CFG/RSVD
DMI_RXN0 AA33 E15 CFG10 Morar_SB GMCH_TV_CRMA A17 J30
16 DMI_RXN0 DMI_RXN1 DMITXN0 CFG10 CFG11 TVDAC_C EXP_RXN4
16 DMI_RXN1 AB37 DMITXN1 CFG11 D14 1 2 J18 TV_REFSET EXP_RXN5 K34

TV
DMI_RXN2 AC33 E14 CFG12 R71 B15 L30
16 DMI_RXN2 DMI_RXN3 DMITXN2 CFG12 CFG13 R410 R412 R409 0R2-0 TV_IRTNA EXP_RXN6
16 DMI_RXN3 AD37 DMITXN3 CFG13 H12 B16 TV_IRTNB EXP_RXN7 M34
C14 CFG14 0R2-0 0R2-0 0R2-0 B17 N30
DMI_RXP0 CFG14 CFG15 TV_IRTNC EXP_RXN8
16 DMI_RXP0 Y33 DMITXP0 CFG15 H15 EXP_RXN9 P34
DMI_RXP1 AA37 J15 CFG16 R30

2
16 DMI_RXP1 DMI_RXP2 DMITXP1 CFG16 CFG17 EXP_RXN10
16 DMI_RXP2 AB33 DMITXP2 CFG17 H14 EXP_RXN11 T34
DMI_RXP3 AC37 G22 CFG18 U30
16 DMI_RXP3 DMITXP3 CFG18 CFG19 EXP_RXN12
CFG19 G23 EXP_RXN13 V34
D23 CFG20 W30
CFG20 EXP_RXN14
11 M_CLK_DDR0 AM33 SM_CK0 RSVD21 G25 14 GMCH_DDCCLK E24 DDCCLK EXP_RXN15 Y34
11 M_CLK_DDR1 AL1 SM_CK1 RSVD22 G24 14 GMCH_DDCDATA E23 DDCDATA
AE11 SM_CK2 RSVD23 J17 14 GMCH_BLUE E21 BLUE EXP_RXP0 D30
AJ34 A31 150R2F 1R411 2 D21 E34
11 M_CLK_DDR3 SM_CK3 RSVD24 BLUE# EXP_RXP1
AF6 A30 C20 F30

VGA
11 M_CLK_DDR4 SM_CK4 RSVD25 150R2F 1R408 14 GMCH_GREEN GREEN EXP_RXP2
AC10 SM_CK5 RSVD26 D26 2 B20 GREEN# EXP_RXP3 G34
RSVD27 D25 14 GMCH_RED A19 RED EXP_RXP4 H30
AN33 150R2F 1R407 2 B19 J34
11 M_CLK_DDR#0 SM_CK0# VSYNC RED# EXP_RXP5
11 M_CLK_DDR#1 AK1 SM_CK1# 14 GMCH_VSYNC 1 2 H21 VSYNC EXP_RXP6 K30
AE10 SM_CK2# 14 GMCH_HSYNC 1 R81 2 39R2J HSYNC G21 HSYNC EXP_RXP7 L34
AJ33 1 R80 2 39R2J CRTIREF J20 M30

PCI-EXPRESS GRAPHICS
11 M_CLK_DDR#3 SM_CK3# R107 REFSET EXP_RXP8
AF5 VGATE_PWRGD 2 1 R94 255R2F N34
11 M_CLK_DDR#4 SM_CK4# R92 EXP_RXP9
AD10 P30
3 SM_CK5# DY 10KR2 2 1
EXP_RXP10
EXP_RXP11 R34
3

AP21 0R2-0 T30

11,12 M_CKE0 SM_CKE0 EXP_RXP12
MUXING

11,12 M_CKE1 AM21 SM_CKE1 EXP_RXP13 U34

AH21 J23 PM_BMBUSY# 16 LBKLT_CRTL E25 V30
11,12 M_CKE2 SM_CKE2 BM_BUSY# LBKLT_CRTL EXP_RXP14
11,12 M_CKE3 AK21 SM_CKE3 EXT_TS0# J21 PM_EXTTS#0 29 BL_ON F25 LBKLT_EN EXP_RXP15 W34
EXT_TS1# H22 PM_EXTTS#1 LCTLA_CLK C23 LCTLA_CLK
AN16 F5 LCTLB_DATA C22 E32
PM

11,12 M_CS#0 SM_CS0# THRMTRIP# PM_THRMTRIP-A# 4 LCTLB_DATA EXP_TXN0

AM14 AD30 VGATE_PWRGD 16,32 CLK_DDC_EDID F23 F36
11,12 M_CS#1 SM_CS1# PWROK 13 CLK_DDC_EDID LDDC_CLK EXP_TXN1
DDR

Layout Note: AH15 AE29 1 2 DAT_DDC_EDID F22 G32

11,12 M_CS#2 SM_CS2# RSTIN# PLT_RST1# 16,18,29 13 DAT_DDC_EDID LDDC_DATA EXP_TXN2
Route as short AG16 R428 100R2 F26 H36
as possible 11,12 M_CS#3 SM_CS3# 13 GMCH_LCDVDD_ON LIBG LVDD_EN EXP_TXN3
DREF_CLKN A24 DREFCLK# 3 C33 LIBG EXP_TXN4 J32
M_OCDCOMP0 AF22 A23 TP25 TPAD28 L_LVBG C31 K36
CLK

SM_OCDCOMP0 DREF_CLKP DREFCLK 3 LVBG EXP_TXN5

M_OCDCOMP1 AF16 C37 DREFSSCLK# 3 TP26 TPAD28 L_VREFH F28 L32
SM_OCDCOMP1 DREF_SSCLKN LVREFH EXP_TXN6
1

D37 DREFSSCLK 3 TP27 TPAD28 L_VREFL F27 M36

R95 R74 DREF_SSCLKP LVREFL EXP_TXN7

LVDS
11,12 M_ODT0 AP14 SM_ODT0 EXP_TXN8 N32
40D2R2F 40D2R2F AL15 AP37 B30 P36
11,12 M_ODT1 SM_ODT1 NC1 13 GMCH_TXACLK- LACLKN EXP_TXN9
11,12 M_ODT2 AM11 SM_ODT2 NC2 AN37 13 GMCH_TXACLK+ B29 LACLKP EXP_TXN10 R32
AN10 AP36 13 GMCH_TXBCLK- C25 T36
2

11,12 M_ODT3 SM_ODT3 NC3 LBCLKN EXP_TXN11

NC4 AP2 13 GMCH_TXBCLK+ C24 LBCLKP EXP_TXN12 U32
M_RCOMPN AK10 AP1 V36
DDR_VREF_S3 M_RCOMPP SMRCOMPN NC5 EXP_TXN13
AK11 SMRCOMPP NC6 AN1 13 GMCH_TXAOUT0- B34 LADATAN0 EXP_TXN14 W32
AF37 B1 When High 1K Ohm B33 Y36
NC

SMVREF0 NC7 13 GMCH_TXAOUT1- LADATAN1 EXP_TXN15

2D5V_S0
SC2D2U6D3V3MX-1

AD1 SMVREF1 NC8 A2 13 GMCH_TXAOUT2- B32 LADATAN2

SMXSLEW
SC2D2U6D3V3MX-1

AE27 SMXSLEWIN NC9 B37 EXP_TXP0 D32

AE28 A36 R106 1 2 DUMMY-R2 CFG18 E36
SMYSLEW SMXSLEWOUT NC10 EXP_TXP1
AF9 SMYSLEWIN NC11 A37 13 GMCH_TXAOUT0+ A34 LADATAP0 EXP_TXP2 F32
1

R101 1 2 DUMMY-R2 CFG19

SCD1U16V

SCD1U16V

AF10 SMYSLEWOUT 13 GMCH_TXAOUT1+ A33 LADATAP1 EXP_TXP3 G36

13 GMCH_TXAOUT2+ B31 LADATAP2 EXP_TXP4 H32
R105 1 2 DUMMY-R2 CFG20 J36
2

EXP_TXP5
13 GMCH_TXBOUT0- C29 LBDATAN0 EXP_TXP6 K32
R65 1 2 DUMMY-R2 CFG3 D28 L36
71.0GMCH.08U 13 GMCH_TXBOUT1- LBDATAN1 EXP_TXP7
2 C433 BC3 C349 BC6 C27 M32 2
13 GMCH_TXBOUT2- LBDATAN2 EXP_TXP8
R83 1 2 DUMMY-R2 CFG4 N36
EXP_TXP9
13 GMCH_TXBOUT0+ C28 LBDATAP0 EXP_TXP10 P32
2D5V_S0 R66 1 2 DUMMY-R2 CFG5 D27 R36
13 GMCH_TXBOUT1+ LBDATAP1 EXP_TXP11
13 GMCH_TXBOUT2+ C26 LBDATAP2 EXP_TXP12 T32
1 R103 2 PM_EXTTS#0 R86 1 2 2K2R2 CFG6
EXP_TXP13 U36
10KR2 V32
R82 2D5V_S0 EXP_TXP14
1 2 DUMMY-R2 CFG7
EXP_TXP15 W36

1 R102 2 PM_EXTTS#1 R85 1 2 DUMMY-R2 CFG8 LCTLA_CLK 1 R104 2 2K2R2

10KR2 DY
R69 1 2 DUMMY-R2 CFG9 LCTLB_DATA 1 R90 2K2R2
1D8V_S3 DY2 71.0GMCH.08U
R84 1 2 DUMMY-R2 CFG10 CLK_DDC_EDID 1 R87 2 2K2R2
1

R75 R64 1 2 DUMMY-R2 CFG11 DAT_DDC_EDID 1 R88 2 2K2R2

80D6R2F
R63 1 2 DUMMY-R2 CFG12
M_RCOMPN
2

R51 1 2 DUMMY-R2 CFG13 BL_ON 1 R98 2 100KR2

M_RCOMPP R61 1 2 DUMMY-R2 CFG14 LBKLT_CRTL 1 R97 2 100KR2

1

R68 1 2 DUMMY-R2 CFG15 LIBG 1 R427 2 1K5R2F

R76
80D6R2F R67 1 2 DUMMY-R2 CFG16
2

R62 1 2 DUMMY-R2 CFG17

When Low choice

lower than 3.5K
1 Ohm 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (2 of 5)
Size Document Number Rev
Custom
MORAR SB
Date: Saturday, May 28, 2005 Sheet 7 of 40
A B C D E
 A B C D E

4 4

U45C U45D

11 M_A_DQ[63..0] 11 M_B_DQ[63..0]
M_A_DQ0 AG35 AK15 M_A_BS#0 11,12 M_B_DQ0 AE31 AJ15 M_B_BS#0 11,12
M_A_DQ1 SADQ0 SA_BS0# M_B_DQ1 SBDQ0 SB_BS0#
AH35 SADQ1 SA_BS1# AK16 M_A_BS#1 11,12 AE32 SBDQ1 SB_BS1# AG17 M_B_BS#1 11,12
M_A_DQ2 AL35 AL21 M_A_BS#2 11,12 M_B_DQ2 AG32 AG21 M_B_BS#2 11,12
M_A_DQ3 SADQ2 SA_BS2# M_B_DQ3 SBDQ2 SB_BS2#
AL37 SADQ3 M_A_DM[7..0] 11 AG36 SBDQ3 M_B_DM[7..0] 11
M_A_DQ4 AH36 AJ37 M_A_DM0 M_B_DQ4 AE34 AF32 M_B_DM0
M_A_DQ5 SADQ4 SA_DM0 M_A_DM1 M_B_DQ5 SBDQ4 SB_DM0 M_B_DM1
AJ35 SADQ5 SA_DM1 AP35 AE33 SBDQ5 SB_DM1 AK34
M_A_DQ6 AK37 AL29 M_A_DM2 M_B_DQ6 AF31 AK27 M_B_DM2
M_A_DQ7 SADQ6 SA_DM2 M_A_DM3 M_B_DQ7 SBDQ6 SB_DM2 M_B_DM3
AL34 SADQ7 SA_DM3 AP24 AF30 SBDQ7 SB_DM3 AK24
M_A_DQ8 AM36 AP9 M_A_DM4 M_B_DQ8 AH33 AJ10 M_B_DM4
M_A_DQ9 SADQ8 SA_DM4 M_A_DM5 M_B_DQ9 SBDQ8 SB_DM4 M_B_DM5
AN35 SADQ9 SA_DM5 AP4 AH32 SBDQ9 SB_DM5 AK5
M_A_DQ10 AP32 AJ2 M_A_DM6 M_B_DQ10 AK31 AE7 M_B_DM6
M_A_DQ11 SADQ10 SA_DM6 M_A_DM7 M_B_DQ11 SBDQ10 SB_DM6 M_B_DM7
AM31 SADQ11 SA_DM7 AD3 AG30 SBDQ11 SB_DM7 AB7
M_A_DQ12 AM34 M_B_DQ12 AG34
SADQ12 M_A_DQS[7..0] 11 SBDQ12 M_B_DQS[7..0] 11
M_A_DQ13 AM35 AK36 M_A_DQS0 M_B_DQ13 AG33 AF34 M_B_DQS0
M_A_DQ14 SADQ13 SA_DQS0 M_A_DQS1 M_B_DQ14 SBDQ13 SB_DQS0 M_B_DQS1
AL32 SADQ14 SA_DQS1 AP33 AH31 SBDQ14 SB_DQS1 AK32
M_A_DQ15 AM32 AN29 M_A_DQS2 M_B_DQ15 AJ31 AJ28 M_B_DQS2
M_A_DQ16 SADQ15 SA_DQS2 M_A_DQS3 M_B_DQ16 SBDQ15 SB_DQS2 M_B_DQS3
AN31 SADQ16 SA_DQS3 AP23 AK30 SBDQ16 SB_DQS3 AK23
M_A_DQ17 AP31 AM8 M_A_DQS4 M_B_DQ17 AJ30 AM10 M_B_DQS4
M_A_DQ18 SADQ17 SA_DQS4 M_A_DQS5 M_B_DQ18 SBDQ17 SB_DQS4 M_B_DQS5
AN28 SADQ18 SA_DQS5 AM4 AH29 SBDQ18 SB_DQS5 AH6
M_A_DQ19 AP28 AJ1 M_A_DQS6 M_B_DQ19 AH28 AF8 M_B_DQS6
M_A_DQ20 SADQ19 SA_DQS6 M_A_DQS7 M_B_DQ20 SBDQ19 SB_DQS6 M_B_DQS7
AL30 SADQ20 SA_DQS7 AE5 AK29 SBDQ20 SB_DQS7 AB4
M_A_DQ21 AM30 M_B_DQ21 AH30
SADQ21 M_A_DQS#[7..0] 11 SBDQ21 M_B_DQS#[7..0] 11
M_A_DQ22 AM28 AK35 M_A_DQS#0 M_B_DQ22 AH27 AF35 M_B_DQS#0
3 M_A_DQ23 SADQ22 SA_DQS0# M_A_DQS#1 M_B_DQ23 SBDQ22 SB_DQS0# M_B_DQS#1 3
AL28 SADQ23 SA_DQS1# AP34 AG28 SBDQ23 SB_DQS1# AK33
DDR SYSTEM MEMORY A

M_A_DQ24 AP27 AN30 M_A_DQS#2 M_B_DQ24 AF24 AK28 M_B_DQS#2

M_A_DQ25 SADQ24 SA_DQS2# M_A_DQS#3 M_B_DQ25 SBDQ24 SB_DQS2# M_B_DQS#3
AM27 AN23 AG23 AJ23

DDR SYSTEM MEMORY B

M_A_DQ26 SADQ25 SA_DQS3# M_A_DQS#4 M_B_DQ26 SBDQ25 SB_DQS3# M_B_DQS#4
AM23 SADQ26 SA_DQS4# AN8 AJ22 SBDQ26 SB_DQS4# AL10
M_A_DQ27 AM22 AM5 M_A_DQS#5 M_B_DQ27 AK22 AH7 M_B_DQS#5
M_A_DQ28 SADQ27 SA_DQS5# M_A_DQS#6 M_B_DQ28 SBDQ27 SB_DQS5# M_B_DQS#6
AL23 SADQ28 SA_DQS6# AH1 AH24 SBDQ28 SB_DQS6# AF7
M_A_DQ29 AM24 AE4 M_A_DQS#7 M_B_DQ29 AH23 AB5 M_B_DQS#7
M_A_DQ30 SADQ29 SA_DQS7# M_B_DQ30 SBDQ29 SB_DQS7#
AN22 SADQ30 M_A_A[13..0] 11,12 AG22 SBDQ30 M_B_A[13..0] 11,12
M_A_DQ31 AP22 AL17 M_A_A0 M_B_DQ31 AJ21 AH17 M_B_A0
M_A_DQ32 SADQ31 SA_MA0 M_A_A1 M_B_DQ32 SBDQ31 SB_MA0 M_B_A1
AM9 SADQ32 SA_MA1 AP17 AG10 SBDQ32 SB_MA1 AK17
M_A_DQ33 AL9 AP18 M_A_A2 M_B_DQ33 AG9 AH18 M_B_A2
M_A_DQ34 SADQ33 SA_MA2 M_A_A3 M_B_DQ34 SBDQ33 SB_MA2 M_B_A3
AL6 SADQ34 SA_MA3 AM17 AG8 SBDQ34 SB_MA3 AJ18
M_A_DQ35 AP7 AN18 M_A_A4 M_B_DQ35 AH8 AK18 M_B_A4
M_A_DQ36 SADQ35 SA_MA4 M_A_A5 M_B_DQ36 SBDQ35 SB_MA4 M_B_A5
AP11 SADQ36 SA_MA5 AM18 AH11 SBDQ36 SB_MA5 AJ19
M_A_DQ37 AP10 AL19 M_A_A6 M_B_DQ37 AH10 AK19 M_B_A6
M_A_DQ38 SADQ37 SA_MA6 M_A_A7 M_B_DQ38 SBDQ37 SB_MA6 M_B_A7
AL7 SADQ38 SA_MA7 AP20 AJ9 SBDQ38 SB_MA7 AH19
M_A_DQ39 AM7 AM19 M_A_A8 M_B_DQ39 AK9 AJ20 M_B_A8
M_A_DQ40 SADQ39 SA_MA8 M_A_A9 M_B_DQ40 SBDQ39 SB_MA8 M_B_A9
AN5 SADQ40 SA_MA9 AL20 AJ7 SBDQ40 SB_MA9 AH20
M_A_DQ41 AN6 AM16 M_A_A10 M_B_DQ41 AK6 AJ16 M_B_A10
M_A_DQ42 SADQ41 SA_MA10 M_A_A11 M_B_DQ42 SBDQ41 SB_MA10 M_B_A11
AN3 SADQ42 SA_MA11 AN20 AJ4 SBDQ42 SB_MA11 AG18
M_A_DQ43 AP3 AM20 M_A_A12 M_B_DQ43 AH5 AG20 M_B_A12
M_A_DQ44 SADQ43 SA_MA12 M_A_A13 M_B_DQ44 SBDQ43 SB_MA12 M_B_A13
AP6 SADQ44 SA_MA13 AM15 AK8 SBDQ44 SB_MA13 AG15
M_A_DQ45 AM6 M_B_DQ45 AJ8
M_A_DQ46 SADQ45 M_B_DQ46 SBDQ45
AL4 SADQ46 SA_CAS# AN15 M_A_CAS# 11,12 AJ5 SBDQ46
M_A_DQ47 AM3 AP16 M_A_RAS# 11,12 M_B_DQ47 AK4 AH14 M_B_CAS# 11,12
M_A_DQ48 SADQ47 SA_RAS# SA_RCVENIN# TP24 TPAD28 M_B_DQ48 SBDQ47 SB_CAS#
AK2 SADQ48 SA_RCVENIN# AF29 AG5 SBDQ48 SB_RAS# AK14 M_B_RAS# 11,12
M_A_DQ49 AK3 AF28 SA_RCVENOUT# TP28 TPAD28 M_B_DQ49 AG4 AF15 SB_RCVENIN# TP20 TPAD28
M_A_DQ50 SADQ49 SA_RCVENOUT# M_B_DQ50 SBDQ49 SB_RCVENIN# SB_RCVENOUT# TP21 TPAD28
AG2 SADQ50 SA_WE# AP15 M_A_WE# 11,12 AD8 SBDQ50 SB_RCVENOUT# AF14
M_A_DQ51 AG1 M_B_DQ51 AD9 AH16 M_B_WE# 11,12
2 M_A_DQ52 SADQ51 M_B_DQ52 SBDQ51 SB_WE# 2
AL3 SADQ52 AH4 SBDQ52
M_A_DQ53 AM2 Place Test PAD Near to Chip M_B_DQ53 AG6
M_A_DQ54 SADQ53 M_B_DQ54 SBDQ53
AH3 SADQ54 as could as possible AE8 SBDQ54 Place Test PAD Near to Chip
M_A_DQ55 AG3 M_B_DQ55 AD7
M_A_DQ56 SADQ55 M_B_DQ56 SBDQ55 ascould as possible
AF3 SADQ56 AC5 SBDQ56
M_A_DQ57 AE3 M_B_DQ57 AB8
M_A_DQ58 SADQ57 M_B_DQ58 SBDQ57
AD6 SADQ58 AB6 SBDQ58
M_A_DQ59 AC4 M_B_DQ59 AA8
M_A_DQ60 SADQ59 M_B_DQ60 SBDQ59
AF2 SADQ60 AC8 SBDQ60
M_A_DQ61 AF1 M_B_DQ61 AC7
M_A_DQ62 SADQ61 M_B_DQ62 SBDQ61
AD4 SADQ62 AA4 SBDQ62
M_A_DQ63 AD5 M_B_DQ63 AA5
SADQ63 SBDQ63

71.0GMCH.08U 71.0GMCH.08U

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GMCH (3 of 5)
Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 8 of 40
A B C D E
 1
2
3
4
2 1

C126

3D3V_S0
SC4D7U6D3V3KX

2 1
2 1
C140

1D05V_S0
1
1
1
1

3D3V_S0
SC4D7U6D3V3KX

C85
R60
R58

DY
DY
DY

0R3-U
0R3-U

R59
R57

10R3
R423

2 1

DY
0R3-U
DY 2
2
2
DY1KR22

C128

use 1D05V_S0
SC4D7U6D3V3KX

SC10U10V5ZY-L

A
A

2 1 2 1 2 1 2 1
2 1

then connect to the gnd plane

decoupling cap groung lead and
C125

Route ASSATVBG gnd from GMCH to

C103
C120
C118
C104
1

0R2-0
0R2-0
0R2-0
0R2-0

SC4D7U6D3V3KX
D39

high speed clock.default

2 1 2 1

graphic clock.1D5V_S0 for

VCC 1D05_S0 for low speed
2

C127
SCD1U16V

C122
DYSSM5818SL
3D3V_TVDACA_S0

3D3V_TVDACB_S0

3D3V_TVDACC_S0

T29 VCC0 VCCA_TVDACA0 F17

When GML replace to PM

2 1 R29 VCC1 VCCA_TVDACA1 E17
N29 D18
1D5V_S0

3D3V_ATVBG_S0
C108 VCC2 VCCA_TVDACB0
M29 C18

DYSCD022U16V2KX
SCD1U16V VCC3 VCCA_TVDACB1
K29 VCC4 VCCA_TVDACC0 F18
J29 VCC5 VCCA_TVDACC1 E18
V28 VCC6
2 1 U28 VCC7 VCCA_TVBG H18
T28 VCC8 VSSA_TVBG G18
C129 R28
SCD1U16V VCC9
P28 VCC10 VCCD_TVDAC D19

1D5V_S0
N28 VCC11 VCCDQ_TVDAC H17
M28

2
VCC12
2 1 L28 VCC13 VCCD_LVDS0 B26
K28 VCC14 VCCD_LVDS1 B25
C141

R375
J28 VCC15 VCCD_LVDS2 A25

0R5J-1
SCD1U16V H28 VCC16
G28 A35

1
VCC17 VCCA_LVDS 2D5V_ALVDS_S0
V27 VCC18
U27 B22
1D5V_DLVDS_S0

VCC19 VCCHV0
T27 B21

B
B

VCC20 VCCHV1
R27 A21

1
1
1
1
VCC21 VCCHV2
P27 VCC22
N27 AM37 V1.8_DDR_CAP1 2 1

L11
L10
L19
L18
1D5V_TVDAC_S0

VCC23 VCCSM0
M27 AH37 V1.8_DDR_CAP2 2 1
1D5V_QTVDAC_S0

VCC24 VCCSM1
L27 VCC25 VCCSM2 AP29 V1.8_DDR_CAP5 2 1 2 1
K27 AD28

IND-D1UH
IND-D1UH
IND-D1UH
IND-D1UH
VCC26 VCCSM3
C415

J27 AD27

2
2
2
2
VCC27 VCCSM4
C432
C124
C119

H27 AC27
0R2-0
0R2-0

VCC28 VCCSM5
2 1 2 1 2 1 2 1 K26 AP26
1
SCD1U16V

VCC29 VCCSM6
H26 AN26
SCD1U16V

VCC30 VCCSM7
C416

K25 VCC31 VCCSM8 AM26

C348
C347
C425
C402
J25 AL26
2

SCD1U16V
SCD1U16V

VCC32 VCCSM9
C404

K24 VCC33 VCCSM10 AK26

K23 VCC34 VCCSM11 AJ26 2 1
internally

K22 VCC35 VCCSM12 AH26

pins shorted

K21 VCC36 VCCSM13 AG26

SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
W20 AF26
Note: All VCCSM

VCC37 VCCSM14
2D5V_TVDAC_S0

U20 VCC38 VCCSM15 AE26

2 1 2 1 2 1 2 1 T20 AP25
1
1

VCC39 VCCSM16
R99

K20 AN25
0R3-U

VCC40 VCCSM17
V19 VCC41 VCCSM18 AM25 2 1

C87
C86
C428
C403
U19 VCC42 VCCSM19 AL25
K19 AK25
DY
DY
R100 0R3-U

VCC43 VCCSM20
C390

W18 AJ25
2
2

POWER

SCD1U16V
SCD1U16V
SCD1U16V
SCD1U16V
VCC44 VCCSM21
V18 VCC45 VCCSM22 AH25
Morar_SB

T18 VCC46 VCCSM23 AG25

R406

K18 VCC47 VCCSM24 AF25

K17 AE25
1D5V_S0

0R3-U

VCC48 VCCSM25

1D5V_HPLL_S0

1D5V_MPLL_S0
SC10U10V5ZY-L

AE24
2

1D5V_DPLLB_S0
1D5V_DPLLA_S0
1D5V_HMPLL_S0
VCCSM26
AC2 VCCH_MPLL1 VCCSM27 AE23
AC1 VCCH_MPLL0 VCCSM28 AE22 2 1
B23 VCCA_DPLLA VCCSM29 AE21
C405

C
C

C35 AE20
2D5V_S0

VCCA_DPLLB VCCSM30 SC10U10V5ZY-L

AA1 VCCA_HPLL VCCSM31 AE19
AA2 VCCA_MPLL VCCSM32 AE18
VCCSM33 AE17
F19 VCCA_CRTDAC0 VCCSM34 AE16 2 1
E19 VCCA_CRTDAC1 VCCSM35 AE15
G19 AE14 C406
1
2D5V_S0
1
2D5V_S0
1
1D5V_S0

VSSA_CRTDAC VCCSM36 SC10U10V5ZY-L

VCCSM37 AP13
VCCSM38 AN13
GMCH_VCC_SYNC
R424
R426
R425

H20 VCC_SYNC VCCSM39 AM13

AL13 2 1
0R3-U
0R3-U
0R3-U

VCCSM40
K13 AK13
2
2
2

VTT0 VCCSM41 C391

J13 AJ13
1
SCD1U16V
SCD1U16V
SCD1U16V

VTT1 VCCSM42
1D8V_S3

SC10U10V5ZY-L
C414
C426
C413

K12 VTT2 VCCSM43 AH13

W11 VTT3 VCCSM44 AG13 2 1 2 1 2 1
R93

V11 AF13
0R2-0

VTT4 VCCSM45
U11 VTT5 VCCSM46 AE13
T11 AP12
2

VTT6 VCCSM47
2D5V_CRTDAC_S0

C545

R11 AN12 2 1 2 1 2 1
SC4D7U6D3V3KX

VTT7 VCCSM48
2 1 P11 AM12
DY

VTT8 VCCSM49
N11 VTT9 VCCSM50 AL12
C412

M11 AK12
of Alviso. Route FB
VTT10 VCCSM51
Morar_SB

within 3" of Alviso.

2D5V_ALVDS_S0

C411
C427

2 1 2 1 L11 AJ12
2D5V_TXLVDS_S0

VTT11 VCCSM52
K11 AH12
1

VTT12 VCCSM53
Route caps within 250mil

W10 AG12
Layout Notes: VSSA_CRTDAC
1D5V_DLVDS_S0

VTT13 VCCSM54
C121

V10 AF12
1

VTT14 VCCSM55
R91
SC10U10V5ZY-L

C123

U10 AE12
DY
0R3-U

VTT15 VCCSM56
R89
SC4D7U10V5ZY
SCD01U16V2KX

T10 AD11
0R3-U

SCD1U16V
SCD1U16V

VTT16 VCCSM57
C375

R10 AC11
2
2

SCD1U16V

VTT17 VCCSM58
internally

P10 AB11
2

VTT18 VCCSM59
pins shorted

N10 VTT19 VCCSM60 AB10

M10 AB9
Note: All VCCSM

VTT20 VCCSM61
K10 VTT21 VCCSM62 AP8 V1.8_DDR_CAP6
D
D

J10 AM1 V1.8_DDR_CAP4 2 1

1
2D5V_S0

VTT22 VCCSM63 V1.8_DDR_CAP3

Y9 VTT23 VCCSM64 AE1 2 1
1D05V_S0

W9 VTT24
R422
C351

U9 B28
1KR2

VTT25 VCCTX_LVDS0
C350

R9 VTT26 VCCTX_LVDS1 A28

P9 A27
connect to the gnd plane.
2
SCD1U16V

VTT27 VCCTX_LVDS2
N9
SCD1U16V

VTT28
M9 AF20
1

VTT29 VCCA_SM0
L9 VTT30 VCCA_SM1 AP19
2D5V_TXLVDS_S0

J9 AF19
Route VSSA_CRTDAC gnd from GMCH to

VTT31 VCCA_SM2
D38

decoupling cap ground lead and then

N8 VTT32 VCCA_SM3 AF18

M8 VTT33
SSM5818SL

A3

N7 AE37
2
SCD1U16V

VTT34 VCC3G0
Title

Size

M7 VTT35 VCC3G1 W37

N6 VTT36 VCC3G2 U37
SCD47U10V3ZY
C374
C132

M6 VTT37 VCC3G3 R37 2 1

2 1 VCCP_GMCH_CAP1 A6 N37 2 1
VTT38 VCC3G4
1D05V_S0

N5 L37 C431
VTT39 VCC3G5
Morar_SB

M5 J37 2 1 SC10U10V5ZY-L
VTT40 VCC3G6
N4 VTT41
M4 Y29 C142 2 1
1D5V_DDRDLL_S0

SCD47U10V3ZY VTT42 VCCA_3GPLL0 SCD1U16V

C106
C342

N3 VTT43 VCCA_3GPLL1 Y28 2 1

SC4D7U10V5ZY
1D05V_S0

2 1 M3 Y27
Document Number

VTT44 VCCA_3GPLL2 C441

2 1 N2
Date: Saturday, May 28, 2005

VTT45 SC10U10V5ZY-L
C393

1D5V_PCIE_S0

M2 VTT46 VCCA_3GBG F37 2 1

SCD22U16V3ZY VCCP_GMCH_CAP2
C346

B2 G37
1

VCCP_GMCH_CAP3 VTT47 VSSA_3GBG C417

2 1 V1 VTT48
SC2D2U6D3V3MX-1 N1 SC10U10V5ZY-L 2 1
VTT49
1D5V_3GPLL_S0
R420

2 1 M1 VTT50
VCCP_GMCH_CAP4 C430
ST100U6D3VM-U

2 1 G1 2 1
0R3-U

VTT51 SC10U10V5ZY-L
2

SCD22U16V3ZY
C107

MORAR
C344
1
1

E
E

2D5V_3GBG_S0

SCD1U16V
C429

Sheet
R112

2 1
U45E
1

SCD1U16V
R446

9
1D5V_S0

GMCH (4 of 5)
0R3-U
0R3-U

C109
R429

2
2

71.0GMCH.08U
0R3-U
2

of
Taipei Hsien 221, Taiwan, R.O.C.
1D5V_S0

2D5V_S0
1D5V_S0

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

40
Rev
then connect to the gnd plane

Wistron Corporation
decoupling cap groung lead and
Route ASSA3GBG gnd from GMCH to

SB
1
2
3
4
 1
2
3
4
U45F

B36 VSSALVDS
AL24

71.0GMCH.08U
VSS267

A
A

AN24

U45H
VSS266
Y1 VSS271 VSS265 A26
D2 VSS270 VSS264 E26
G2 G26

71.0GMCH.08U
VSS269 VSS263
VCCSM_NCTF31 AB12 J2 VSS268 VSS262 J26
VCCSM_NCTF30 AC12 L2 VSS260 VSS261 B27
VCCSM_NCTF29 AD12 P2 VSS259 VSS129 E27

1D8V_S3
VCCSM_NCTF28 AB13 T2 VSS258 VSS128 G27
AC13 SC10U10V5ZY-L V2 W27
VCCSM_NCTF27 VSS257 VSS127
VCCSM_NCTF26 AD13 2 1 AD2 VSS256 VSS126 AA27
VCCSM_NCTF25 AC14 AE2 VSS255 VSS125 AB27

C392
VCCSM_NCTF24 AD14 AH2 VSS254 VSS124 AF27
VCCSM_NCTF23 AC15 AL2 VSS253 VSS123 AG27
VCCSM_NCTF22 AD15 AN2 VSS252 VSS122 AJ27
AC16 SCD1U16V A3 AL27
VCCSM_NCTF21 VSS251 VSS121
VCCSM_NCTF20 AD16 2 1 C3 VSS250 VSS120 AN27
VCCSM_NCTF19 AC17 AA3 VSS249 VSS119 E28

C110
VCCSM_NCTF18 AD17 AB3 VSS248 VSS118 W28
VCCSM_NCTF17 AC18 AC3 VSS247 VSS117 AA28
VCCSM_NCTF16 AD18 AJ3 VSS246 VSS116 AB28
AC19 SCD1U16V C4 AC28
VCCSM_NCTF15 VSS245 VSS115

1D05V_S0
VCCSM_NCTF14 AD19 2 1 H4 VSS244 VSS114 A29
VCCSM_NCTF13 AC20 C130 L4 VSS243 VSS113 D29
VCCSM_NCTF12 AD20 P4 VSS242 VSS112 E29
L12 VTT_NCTF17 VCCSM_NCTF11 AC21 U4 VSS241 VSS111 F29
M12 VTT_NCTF16 VCCSM_NCTF10 AD21 Y4 VSS240 VSS110 G29
N12 AC22 SCD1U16V AF4 H29
VTT_NCTF15 VCCSM_NCTF9 VSS239 VSS109
P12 VTT_NCTF14 VCCSM_NCTF8 AD22 2 1 AN4 VSS238 VSS108 L29
R12 VTT_NCTF13 VCCSM_NCTF7 AC23 E5 VSS237 VSS107 P29
C135

T12 VTT_NCTF12 VCCSM_NCTF6 AD23 W5 VSS236 VSS106 U29

U12 VTT_NCTF11 VCCSM_NCTF5 AC24 AL5 VSS235 VSS105 V29
V12 VTT_NCTF10 VCCSM_NCTF4 AD24 AP5 VSS234 VSS104 W29
W12 AC25 SCD1U16V B6 AA29

B
B

VTT_NCTF9 VCCSM_NCTF3 VSS233 VSS103

L13 VTT_NCTF8 VCCSM_NCTF2 AD25 2 1 J6 VSS232 VSS102 AD29
M13 VTT_NCTF7 VCCSM_NCTF1 AC26 L6 VSS231 VSS101 AG29
C134

N13 VTT_NCTF6 VCCSM_NCTF0 AD26 P6 VSS230 VSS100 AJ29

P13 VTT_NCTF5 T6 VSS229 VSS99 AM29
R13 VTT_NCTF4 VCC_NCTF78 L17 AA6 VSS228 VSS98 C30
T13 M17 SCD1U16V AC6 Y30
VTT_NCTF3 VCC_NCTF77 VSS227 VSS97
U13 VTT_NCTF2 VCC_NCTF76 N17 2 1 AE6 VSS226 VSS96 AA30
V13 VTT_NCTF1 VCC_NCTF75 P17 AJ6 VSS225 VSS95 AB30
C111

W13 T17 G7 AC30

DY

VTT_NCTF0 VCC_NCTF74 VSS224 VSS94

VCC_NCTF73 U17 V7 VSS223 VSS93 AE30
VCC_NCTF72 V17 AA7 VSS222 VSS92 AP30
W17 SCD1U16V AG7 D31
VCC_NCTF71 VSS221 VSS91
VCC_NCTF70 L18 2 1 AK7 VSS220 VSS90 E31
VCC_NTTF69 M18 AN7 VSS219 VSS89 F31
C112

Y12 VSS_NCTF68 VCC_NCTF68 N18 C8 VSS218 VSS88 G31

AA12 VSS_NCTF67 VCC_NCTF67 P18 E8 VSS217 VSS87 H31
Y13 VSS_NCTF66 VCC_NCTF66 R18 L8 VSS216 VSS86 J31
AA13 Y18 SCD1U16V P8 K31
VSS_NCTF65 VCC_NCTF65 VSS215 VSS85
L14 VSS_NCTF64 VCC_NCTF64 L19 2 1 Y8 VSS214 VSS84 L31
M14 VSS_NCTF63 VCC_NCTF63 M19 AL8 VSS213 VSS83 M31
C133

N14 VSS_NCTF62 VCC_NCTF62 N19 A9 VSS212 VSS82 N31

P14 VSS_NCTF61 VCC_NCTF61 P19 H9 VSS211 VSS81 P31
R14 VSS_NCTF60 VCC_NCTF60 R19 K9 VSS210 VSS80 R31
T14 Y19 SCD1U16V T9 T31
Place these Hi-Freq decoupling caps near GMCH

VSS_NCTF59 VCC_NCTF59 VSS209 VSS79

U14 VSS_NCTF58 VCC_NCTF58 L20 2 1 V9 VSS208 VSS78 U31
V14 VSS_NCTF57 VCC_NCTF57 M20 AA9 VSS207 VSS77 V31
C143

W14 VSS_NCTF56 VCC_NCTF56 N20 AC9 VSS206 VSS76 W31

Y14 VSS_NCTF55 VCC_NCTF55 P20 AE9 VSS205 VSS75 AD31
AA14 VSS_NCTF54 VCC_NCTF54 R20 AH9 VSS204 VSS74 AG31
AB14 Y20 SCD1U16V AN9 AL31
NCTF

VSS_NCTF53 VCC_NCTF53 VSS203 VSS73

L15 L21 2 1 D10 A32
VSS

VSS_NCTF52 VCC_NCTF52 VSS202 VSS72

M15 VSS_NCTF51 VCC_NCTF51 M21 L10 VSS201 VSS71 C32
C131

C
C

N15 VSS_NCTF50 VCC_NCTF50 N21 Y10 VSS200 VSS70 Y32

P15 VSS_NCTF49 VCC_NCTF49 P21 AA10 VSS199 VSS69 AA32
R15 VSS_NCTF48 VCC_NCTF48 T21 F11 VSS198 VSS68 AB32
T15 VSS_NCTF47 VCC_NCTF47 U21 H11 VSS197 VSS67 AC32
U15 VSS_NCTF46 VCC_NCTF46 V21 Y11 VSS196 VSS66 AD32
V15 VSS_NCTF45 VCC_NCTF45 W21 AA11 VSS195 VSS65 AJ32
W15 VSS_NCTF44 VCC_NCTF44 L22 AF11 VSS194 VSS64 AN32
Y15 VSS_NCTF43 VCC_NCTF43 M22 AG11 VSS193 VSS63 D33
AA15 VSS_NCTF42 VCC_NCTF42 N22 AJ11 VSS192 VSS62 E33
AB15 VSS_NCTF41 VCC_NCTF41 P22 AL11 VSS191 VSS61 F33
L16 VSS_NCTF40 VCC_NCTF40 R22 AN11 VSS190 VSS60 G33
M16 VSS_NCTF39 VCC_NCTF39 T22 B12 VSS189 VSS59 H33
N16 VSS_NCTF38 VCC_NCTF38 U22 D12 VSS188 VSS58 J33
P16 VSS_NCTF37 VCC_NCTF37 V22 J12 VSS187 VSS57 K33
R16 VSS_NCTF36 VCC_NCTF36 W22 A14 VSS186 VSS56 L33
T16 VSS_NCTF35 VCC_NCTF35 L23 B14 VSS185 VSS55 M33
U16 VSS_NCTF34 VCC_NCTF34 M23 F14 VSS184 VSS54 N33
V16 VSS_NCTF33 VCC_NCTF33 N23 J14 VSS183 VSS53 P33
W16 VSS_NCTF32 VCC_NCTF32 P23 K14 VSS182 VSS52 R33
Y16 VSS_NCTF31 VCC_NCTF31 R23 AG14 VSS181 VSS51 T33
AA16 VSS_NCTF30 VCC_NCTF30 T23 AJ14 VSS180 VSS50 U33
AB16 VSS_NCTF29 VCC_NCTF29 U23 AL14 VSS179 VSS49 V33
R17 VSS_NCTF28 VCC_NCTF28 V23 AN14 VSS178 VSS48 W33
Y17 VSS_NCTF27 VCC_NCTF27 W23 C15 VSS177 VSS47 AD33
AA17 VSS_NCTF26 VCC_NCTF26 L24 K15 VSS176 VSS46 AF33
AB17 VSS_NCTF25 VCC_NCTF25 M24 A16 VSS175 VSS45 AL33
AA18 VSS_NCTF24 VCC_NCTF24 N24 D16 VSS174 VSS44 C34
AB18 VSS_NCTF23 VCC_NCTF23 P24 H16 VSS173 VSS43 AA34
AA19 VSS_NCTF22 VCC_NCTF22 R24 K16 VSS172 VSS42 AB34
AB19 VSS_NCTF21 VCC_NCTF21 T24 AL16 VSS171 VSS41 AC34
AA20 VSS_NCTF20 VCC_NCTF20 U24 C17 VSS170 VSS40 AD34
AB20 VSS_NCTF19 VCC_NCTF19 V24 G17 VSS169 VSS39 AH34
R21 VSS_NCTF18 VCC_NCTF18 W24 AF17 VSS168 VSS38 AN34
D
D

Y21 VSS_NCTF17 VCC_NCTF17 L25 AJ17 VSS167 VSS37 B35

AA21 VSS_NCTF16 VCC_NCTF16 M25 AN17 VSS166 VSS36 D35
AB21 VSS_NCTF15 VCC_NCTF15 N25 A18 VSS165 VSS35 E35
Y22 VSS_NCTF14 VCC_NCTF14 P25 B18 VSS164 VSS34 F35
AA22 VSS_NCTF13 VCC_NCTF13 R25 U18 VSS163 VSS33 G35
AB22 VSS_NCTF12 VCC_NCTF12 T25 AL18 VSS162 VSS32 H35
Y23 VSS_NCTF11 VCC_NCTF11 U25 C19 VSS161 VSS31 J35
AA23 VSS_NCTF10 VCC_NCTF10 V25 H19 VSS160 VSS30 K35
AB23 VSS_NCTF9 VCC_NCTF9 W25 J19 VSS159 VSS29 L35
Y24 VSS_NCTF8 VCC_NCTF8 L26 T19 VSS158 VSS28 M35
AA24 VSS_NCTF7 VCC_NCTF7 M26 W19 VSS157 VSS27 N35
AB24 VSS_NCTF6 VCC_NCTF6 N26 AG19 VSS156 VSS26 P35
A3

Y25 VSS_NCTF5 VCC_NCTF5 P26 AN19 VSS155 VSS25 R35

Title

Size

AA25 VSS_NCTF4 VCC_NCTF4 R26 A20 VSS154 VSS24 T35

AB25 VSS_NCTF3 VCC_NCTF3 T26 D20 VSS153 VSS23 U35
Y26 VSS_NCTF2 VCC_NCTF2 U26 E20 VSS152 VSS22 V35
AA26 VSS_NCTF1 VCC_NCTF1 V26 F20 VSS151 VSS21 W35
AB26 VSS_NCTF0 VCC_NCTF0 W26 G20 VSS150 VSS20 Y35
V20 VSS149 VSS19 AE35
1D05V_S0

AK20 VSS148 VSS18 C36

C21 VSS147 VSS17 AA36
F21 VSS146 VSS16 AB36
AF21 AC36
Document Number

VSS145 VSS15
Date: Friday, June 24, 2005

AN21 VSS144 VSS14 AD36

A22 VSS143 VSS13 AE36
D22 VSS142 VSS12 AF36
E22 VSS141 VSS11 AJ36
J22 VSS140 VSS10 AL36
AH22 VSS139 VSS9 AN36
AL22 VSS138 VSS8 E37
H23 VSS137 VSS7 H37
MORAR

AF23 VSS136 VSS6 K37

B24 M37
E
E

VSS135 VSS5
D24 P37
Sheet

VSS134 VSS4
F24 VSS133 VSS3 T37
J24 VSS132 VSS2 V37
10

AG24 Y37
GMCH (5 of 5)

VSS131 VSS1
AJ24 VSS130 VSS0 AG37
of
Taipei Hsien 221, Taiwan, R.O.C.
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

40
Rev
Wistron Corporation

SB
1
2
3
4
 A B C D E

8,12 M_A_A[13..0] DM2

DM1 M_A_A0 102 108 M_A_RAS# 8,12
8,12 M_B_A[13..0] A0 /RAS
M_B_A0 102 108 M_B_RAS# 8,12 M_A_A1 101 109 M_A_WE# 8,12
M_B_A1 A0 /RAS M_A_A2 A1 /WE
101 A1 /WE 109 M_B_WE# 8,12 100 A2 /CAS 113 M_A_CAS# 8,12
M_B_A2 100 113 M_B_CAS# 8,12 M_A_A3 99
M_B_A3 A2 /CAS M_A_A4 A3
99 A3 98 A4 /CS0 110 M_CS#0 7,12
M_B_A4 98 110 M_CS#2 7,12 M_A_A5 97 115 M_CS#1 7,12
M_B_A5 A4 /CS0 M_A_A6 A5 /CS1
97 A5 /CS1 115 M_CS#3 7,12 94 A6
M_B_A6 94 M_A_A7 92 79 M_CKE0 7,12
M_B_A7 A6 M_A_A8 A7 CKE0
92 A7 CKE0 79 M_CKE2 7,12 93 A8 CKE1 80 M_CKE1 7,12
M_B_A8 93 80 M_CKE3 7,12 M_A_A9 91
4
M_B_A9 A8 CKE1 M_A_A10 A9 4
91 A9 105 A10/AP CK0 30 M_CLK_DDR0 7
M_B_A10 105 30 M_CLK_DDR3 7 M_A_A11 90 32 M_CLK_DDR#0 7
M_B_A11 A10/AP CK0 M_A_A12 A11 /CK0
90 A11 /CK0 32 M_CLK_DDR#3 7 89 A12
M_B_A12 89 M_A_A13 116 164 M_CLK_DDR1 7
M_B_A13 A12 A13 CK1
116 A13 CK1 164 M_CLK_DDR4 7 86 A14 /CK1 166 M_CLK_DDR#1 7
86 A14 /CK1 166 M_CLK_DDR#4 7 84 A15 M_A_DM[7..0] 8
84 8,12 M_A_BS#2 85 10 M_A_DM0
A15 M_B_DM[7..0] 8 A16/BA2 DM0
8,12 M_B_BS#2 85 10 M_B_DM0 26 M_A_DM1
A16/BA2 DM0 M_B_DM1 DM1 M_A_DM2
DM1 26 8,12 M_A_BS#0 107 BA0 DM2 52
8,12 M_B_BS#0 107 52 M_B_DM2 8,12 M_A_BS#1 106 67 M_A_DM3
BA0 DM2 M_B_DM3 BA1 DM3 M_A_DM4
8,12 M_B_BS#1 106 BA1 DM3 67 DM4 130
130 M_B_DM4 M_A_DQ0 5 147 M_A_DM5
M_B_DQ0 DM4 M_B_DM5 M_A_DQ1 DQ0 DM5 M_A_DM6
5 DQ0 DM5 147 8 M_A_DQ[63..0] 7 DQ1 DM6 170
M_B_DQ1 7 170 M_B_DM6 M_A_DQ2 17 185 M_A_DM7
8 M_B_DQ[63..0] DQ1 DM6 DQ2 DM7
M_B_DQ2 17 185 M_B_DM7 M_A_DQ3 19
M_B_DQ3 DQ2 DM7 M_A_DQ4 DQ3 SMBD_ICH
19 DQ3 4 DQ4 SDA 195
M_B_DQ4 4 195 SMBD_ICH 3,18 M_A_DQ5 6 197 SMBC_ICH
M_B_DQ5 DQ4 SDA M_A_DQ6 DQ5 SCL
6 DQ5 SCL 197 SMBC_ICH 3,18 14 DQ6
M_B_DQ6 14 M_A_DQ7 16 199
DQ6 DQ7 VDDSPD 3D3V_S0
M_B_DQ7 16 199 M_A_DQ8 23
DQ7 VDDSPD 3D3V_S0 DQ8

1
M_B_DQ8 23 M_A_DQ9 25 198 BC2 C32
DQ8 DQ9 SA0

1
M_B_DQ9 25 198 C31 M_A_DQ10 35 200 SCD1U16V SC2D2U6D3V3MX-1
M_B_DQ10 DQ9 SA0 M_A_DQ11 DQ10 SA1
35 200 1 2 3D3V_S0 DY 37
DY DY

2
M_B_DQ11 DQ10 SA1 R32 M_A_DQ12 DQ11

SC2D2U6D3V3MX-1
37 20 50

2
M_B_DQ12 DQ11 BC1 M_A_DQ13 DQ12 NC#50
20 DQ12 NC#50 50 22 DQ13 NC#69 69
M_B_DQ13 22 69 10KR2 M_A_DQ14 36 83
M_B_DQ14 DQ13 NC#69 M_A_DQ15 DQ14 NC#83

SCD1U16V
36 DQ14 NC#83 83 38 DQ15 NC#120 120
M_B_DQ15 38 120 M_A_DQ16 43 163
M_B_DQ16 DQ15 NC#120 M_A_DQ17 DQ16 NC#163/TEST
43 DQ16 NC#163/TEST 163 45 DQ17
M_B_DQ17 45 M_A_DQ18 55
M_B_DQ18 DQ17 M_A_DQ19 DQ18
55 DQ18 57 DQ19 VDD 81
3 M_B_DQ19 57 81 Morar_SB M_A_DQ20 44 82 3
M_B_DQ20 DQ19 VDD M_A_DQ21 DQ20 VDD
44 82 46 87
REVISED TYPE
M_B_DQ21 DQ20 VDD M_A_DQ22 DQ21 VDD
46 87 56 88

REVISED TYPE
M_B_DQ22 DQ21 VDD M_A_DQ23 DQ22 VDD
56 DQ22 VDD 88 58 DQ23 VDD 95
M_B_DQ23 58 95 M_A_DQ24 61 96
M_B_DQ24 DQ23 VDD M_A_DQ25 DQ24 VDD
61 DQ24 VDD 96 63 DQ25 VDD 103
M_B_DQ25 63 103 M_A_DQ26 73 104
M_B_DQ26 DQ25 VDD M_A_DQ27 DQ26 VDD
73 DQ26 VDD 104 75 DQ27 VDD 111
M_B_DQ27 75 111 M_A_DQ28 62 112
M_B_DQ28 DQ27 VDD M_A_DQ29 DQ28 VDD
62 DQ28 VDD 112 64 DQ29 VDD 117
M_B_DQ29 64 117 M_A_DQ30 74 118
DQ29 VDD DQ30 VDD 1D8V_S3
M_B_DQ30 74 118 M_A_DQ31 76
DQ30 VDD 1D8V_S3 DQ31
M_B_DQ31 76 M_A_DQ32 123 3
M_B_DQ32 DQ31 M_A_DQ33 DQ32 VSS
123 DQ32 VSS 3 125 DQ33 VSS 8
M_B_DQ33 125 8 M_A_DQ34 135 9
M_B_DQ34 DQ33 VSS M_A_DQ35 DQ34 VSS
135 DQ34 VSS 9 137 DQ35 VSS 12
M_B_DQ35 137 12 M_A_DQ36 124 15 Place near DM2
M_B_DQ36 DQ35 VSS M_A_DQ37 DQ36 VSS
124 DQ36 VSS 15 126 DQ37 VSS 18
M_B_DQ37 126 18 M_A_DQ38 134 21
M_B_DQ38 DQ37 VSS M_A_DQ39 DQ38 VSS M_CLK_DDR0
M_B_DQ39
134 DQ38 VSS 21 Place near DM1 M_A_DQ40
136 DQ39 VSS 24
136 DQ39 VSS 24 141 DQ40 VSS 27

1
M_B_DQ40 141 27 M_A_DQ41 143 28
M_B_DQ41 DQ40 VSS M_CLK_DDR4 M_A_DQ42 DQ41 VSS C139 SC10P50V2JN-1
143 DQ41 VSS 28 151 DQ42 VSS 33
M_B_DQ42 151 33 M_A_DQ43 153 34
DY

2
DQ42 VSS DQ43 VSS
1

M_B_DQ43 153 34 M_A_DQ44 140 39 M_CLK_DDR#0

M_B_DQ44 DQ43 VSS C56 SC10P50V2JN-1 M_A_DQ45 DQ44 VSS
140 DQ44 VSS 39 142 DQ45 VSS 40
M_B_DQ45 142 40 M_A_DQ46 152 41 M_CLK_DDR1
DY
2

M_B_DQ46 DQ45 VSS M_CLK_DDR#4 M_A_DQ47 DQ46 VSS

152 DQ46 VSS 41 154 DQ47 VSS 42

1
M_B_DQ47 154 42 M_A_DQ48 157 47
M_B_DQ48 DQ47 VSS M_CLK_DDR3 M_A_DQ49 DQ48 VSS C57 SC10P50V2JN-1
157 DQ48 VSS 47 159 DQ49 VSS 48
M_B_DQ49 159 48 M_A_DQ50 173 53
DY

2
DQ49 VSS DQ50 VSS
1

M_B_DQ50 173 53 M_A_DQ51 175 54 M_CLK_DDR#1

2
M_B_DQ51 DQ50 VSS C136 SC10P50V2JN-1 M_A_DQ52 DQ51 VSS 2
175 DQ51 VSS 54 158 DQ52 VSS 59
M_B_DQ52 158 59 M_A_DQ53 160 60
DY
2

M_B_DQ53 DQ52 VSS M_CLK_DDR#3 M_A_DQ54 DQ53 VSS

160 DQ53 VSS 60 174 DQ54 VSS 65
M_B_DQ54 174 65 M_A_DQ55 176 66
M_B_DQ55 DQ54 VSS M_A_DQ56 DQ55 VSS
176 DQ55 VSS 66 179 DQ56 VSS 71
M_B_DQ56 179 71 M_A_DQ57 181 72
M_B_DQ57 DQ56 VSS M_A_DQ58 DQ57 VSS
181 DQ57 VSS 72 189 DQ58 VSS 77
M_B_DQ58 189 77 M_A_DQ59 191 78
M_B_DQ59 DQ58 VSS M_A_DQ60 DQ59 VSS
191 DQ59 VSS 78 180 DQ60 VSS 121
M_B_DQ60 180 121 M_A_DQ61 182 122
M_B_DQ61 DQ60 VSS M_A_DQ62 DQ61 VSS
182 DQ61 VSS 122 192 DQ62 VSS 127
M_B_DQ62 192 127 M_A_DQ63 194 128
M_B_DQ63 DQ62 VSS DQ63 VSS
194 DQ63 VSS 128 VSS 132
132 M_A_DQS#0 11 133
M_B_DQS#0 VSS M_A_DQS#1 /DQS0 VSS
11 /DQS0 VSS 133 8 M_A_DQS[7..0] 29 /DQS1 VSS 138
M_B_DQS#1 29 138 M_A_DQS#2 49 139
8 M_B_DQS#[7..0] /DQS1 VSS /DQS2 VSS
M_B_DQS#2 49 139 M_A_DQS#3 68 144
M_B_DQS#3 /DQS2 VSS M_A_DQS#4 /DQS3 VSS
68 /DQS3 VSS 144 129 /DQS4 VSS 145
M_B_DQS#4 129 145 M_A_DQS#5 146 149
M_B_DQS#5 /DQS4 VSS M_A_DQS#6 /DQS5 VSS
146 /DQS5 VSS 149 167 /DQS6 VSS 150
M_B_DQS#6 167 150 M_A_DQS#7 186 155
M_B_DQS#7 /DQS6 VSS /DQS7 VSS
186 /DQS7 VSS 155 VSS 156
156 M_A_DQS0 13 161
M_B_DQS0 VSS M_A_DQS1 DQS0 VSS
13 DQS0 VSS 161 8 M_A_DQS#[7..0] 31 DQS1 VSS 162
M_B_DQS1 31 162 M_A_DQS2 51 165
8 M_B_DQS[7..0] DQS1 VSS DQS2 VSS
M_B_DQS2 51 165 M_A_DQS3 70 168
M_B_DQS3 DQS2 VSS M_A_DQS4 DQS3 VSS
70 DQS3 VSS 168 131 DQS4 VSS 171
M_B_DQS4 131 171 M_A_DQS5 148 172
M_B_DQS5 DQS4 VSS M_A_DQS6 DQS5 VSS
148 DQS5 VSS 172 169 DQS6 VSS 177
M_B_DQS6 169 177 M_A_DQS7 188 178
M_B_DQS7 DQS6 VSS DQS7 VSS
188 DQS7 VSS 178 VSS 183
1 183 114 184 1
VSS 7,12 M_ODT0 ODT0 VSS
7,12 M_ODT2 114 ODT0 VSS 184 7,12 M_ODT1 119 ODT1 VSS 187
7,12 M_ODT3 119 ODT1 VSS 187 VSS 190
190 1 193
DDR_VREF_S3 1 VREF
VSS
VSS 193
DDR_VREF_S3
2
VREF
VSS
VSS
VSS 196 Wistron Corporation
1

2 196 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

VSS VSS
1

C137 BC5 202 201 Taipei Hsien 221, Taiwan, R.O.C.

C138 BC4 SC4D7U6D3V3KX SCD1U16V GND GND
202 201
2

SC4D7U6D3V3KX SCD1U16V GND GND Title

9.2mm
2

DDR2-200P-2 5.2mm connector

connector 62.10017.751 DDR Socket
62.10017.741 Morar_SA:62.10017.751 Size Document Number Rev
Morar_SA:62.10017.741 Custom
Morar_SB:62.10017.991 MORAR SB
Morar_SB:62.10017.691 Date: Saturday, May 28, 2005 Sheet 11 of 40

A B C D E
 A B C D E

PARALLEL TERMINATION Decoupling Capacitor

Put decap near power(0.9V) and pull-up resistor
Put decap near power(0.9V)
DDR_VREF
and pull-up resistor
4 M_A_A[13..0] 8,11 4
DDR_VREF
DY DY DY DY DY DY

1
M_B_A[13..0] 8,11
C93 C65 C78 C377 C355 C376 C69 C354 C378 C64 C352 C353 C66
R395 1 2 56R2J SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
R379 56R2J M_CKE2 7,11
1 2 M_ODT3 7,11
R381 1 2 56R2J
R391 56R2J M_B_WE# 8,11
1 2 M_B_BS#2 8,11
R48 1 2 56R2J
R380 56R2J M_ODT1 7,11
1 2 M_CS#3 7,11
DY DY

1
R52 1 56R2J 2
R396 56R2J M_B_A3 M_CKE0 7,11 C379 C357 C358 C356 C380 C67 C68 C90 C76 C91 C79 C92 C77
1 2
R397 1 56R2J 2 M_B_A8 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
R392 1 56R2J 2 M_B_A9
R393 1 56R2J 2 M_B_A12
R378 1 56R2J 2 M_B_A10

RN6
8 1 M_B_RAS# 8,11
7 2 M_CS#2 7,11
6 3 M_ODT2 7,11
5 4 M_B_A13
1D8V_S3
SRN56-1
Place these Caps near DM1
RN5
8 1 M_B_A4

1
7 2 M_B_A2
3 6 3 M_B_A0 C88 C83 C82 C75 C89 3
5 4 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1

2
M_B_BS#1 8,11
SRN56-1

RN9
8 1 M_CKE3 7,11
7 2 M_B_A11
DY DY DY DY

1
6 3 M_B_A7
5 4 M_B_A6 EC39 EC44 EC40 EC38
SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
SRN56-1

R394 1 56R2J 2 M_B_A5

R383 1 56R2J 2 M_B_A1
R384 1 56R2J 2
R382 56R2J M_B_BS#0 8,11
1 2 M_B_CAS# 8,11
1D8V_S3
Place these Caps near DM2
RN29
8 1 M_A_RAS# 8,11
7 2 M_CS#0 7,11

1
6 3 M_ODT0 7,11
5 4 M_A_A13 C96 C97 C84 C80 C81
SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1

2
SRN56-1
2 2
RN30
8 1 M_A_A4
7 2 M_A_A2
6 3 M_A_A0 1
DY DY DY DY

1
5 4 M_A_BS#1 8,11 EC43 EC42 EC41 EC47
SRN56-1 SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
RN8
8 1 M_CS#1 7,11
7 2 M_A_CAS# 8,11
6 3 M_A_WE# 8,11
5 4 M_A_BS#0 8,11
SRN56-1

RN10
8 1 M_A_A8
7 2 M_A_A9
6 3 M_A_A12
5 4 M_A_BS#2 8,11
SRN56-1

RN31
8 1 M_CKE1 7,11
7 2 M_A_A11
6 3 M_A_A7
1 5 4 M_A_A6 1

SRN56-1
Wistron Corporation
RN7 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
8 1 M_A_A10 Taipei Hsien 221, Taiwan, R.O.C.
7 2 M_A_A1
6 3 M_A_A3 Title
5 4 M_A_A5
DDR2 Termination Resistor
SRN56-1 Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 12 of 40

A B C D E
 NEED FOLLOW BOLSENA
NUM_LED# EC18 1DY 2 SC100P50V2JN-U
LED 29 NUM_LED#
NUM_LED# 1
R14
2
100R2
1
D4
2
LED-G-31
5V_S0

on KB Cover
CAP_LED# EC17 1DY 2 SC100P50V2JN-U D3 LED-G-31
CAP_LED# 1 2 1 2 on KB Cover
1DY 2
MAIL_LED# EC11 SC100P50V2JN-U 29 CAP_LED# R13 100R2
D2 LED-G-31
IDE_LED# EC19 1DY 2 SC100P50V2JN-U
29 MAIL_LED#
MAIL_LED# 1 2 1 2 on KB Cover,UP
R12 100R2
D7 LED-G-31
Near Mail MAIL_LED# 1 2 1 2 on KB Cover,DOWN
FRONT_PWRLED#EC144 DY 2 SC100P50V2JN-U R21
1
Button DY100R2 DY
STDBY_LED# EC143 1DY 2 SC100P50V2JN-U D5 LED-G-31
IDE_LED# 1 2 1 2 on KB Cover
1DY 2
DC_BATFULL# EC141 SC100P50V2JN-U 20 IDE_LED# R15 100R2
D44 LED-Y-22
CHARGE_LED# EC139 1DY 2 SC100P50V2JN-U 5V_S0
28 WLAN_LED#
WLAN_LED# 1 2 1 2 on Front Panel
R551 100R2
BAV99LT1 D1 LED-G-31
2
Near Power 1
R9
2
100R2
1 2 on KB Cover,UP
WLAN_LED# 3 D45 D6 LED-G-31
BLT_LED# DY 2
1 DY Button 1 2 1 2 on KB Cover,DOWN
EC140 SC100P50V2JN-U 1 R20 100R2

WLAN_LED# 1DY 2
EC142 SC100P50V2JN-U FRONT_PWRLED#1 2 1 2 on Front Panel
BAV99LT1 29 FRONT_PWRLED# R297 100R2 D49 LED-G-31
2

BLT_LED# 3 D19 5V_S5

DY D47 LED-G-31
1 DC_BATFULL# 1 2 1 2 on Front Panel
29 DC_BATFULL# R295 100R2

Morar_SB 5V_S0
D43 DY LED-B-27-U-GP
29 BLT_LED#
BLT_LED# 1 DY 2 2 1 on Front Panel
R548 470R2
3D3V_S0
5V_S5
D48 LED-Y-22
STDBY_LED# 1 2 1 2 on Front Panel
29 STDBY_LED# R296 100R2
D46 LED-Y-22
1
2

2D5V_S0 CHARGE_LED#
29 CHARGE_LED# 1
R294
2
100R2
1 2 on Front Panel
Morar_SB SRN2K2J
RN28
Q26 on KB cover
4
3
1

FDN337N-U
G

LED V V V V V
2 3 EDID_CLK Button V V V V V
7 CLK_DDC_EDID
1
D
S

POWER1 E-MAIL INTERNET e-BTN PROGRAM CAPS NUM HDD

2 3 EDID_DAT
7 DAT_DDC_EDID
Front panel
D
S

Q27
FDN337N-U
LCDVDD
LED V V V V Charger: Power2:
Layout 40 mil 3D3V_S0 Button V V Green : DC only or Battery full with DC Green : S0
U3 Orange : Charging Orange : S3
BlutTooth Wireless Charger Power2 Orange Blink : Battery low Orange Blinking : Enter S4
1 OUT IN 6
R19 2 5
GMCH_LCDVDD_ON LCDVDD_ON_1 GND GND
1 2 3 4
7 GMCH_LCDVDD_ON ON/OFF# IN (Please See M.E. drawing LED position)
LCD CONN
1

1KR2
SC1U10V3ZY

C9 C10 C8
SCD1U16V AAT4280IGU-3-T1 SC1U10V3ZY LCDVDD
2

SC10U10V5ZY-L
LCD1

1
42 C5 C6 EC22
2 1 SCD1U16V SCD1U16V
DY
DY

2
4 3
6 5
8 7
10 9 GMCH_TXBCLK+ 7
3D3V_S0 12 11 GMCH_TXBCLK- 7
14 13 GMCH_TXBOUT2+ 7
EDID_CLK 16 15
EDID_DAT GMCH_TXBOUT2- 7
18 17 GMCH_TXBOUT1+ 7
20 19 GMCH_TXBOUT1- 7
22 21 GMCH_TXBOUT0+ 7
24 23 GMCH_TXBOUT0- 7
29 BRIGHTNESS 26 25 GMCH_TXACLK+ 7
29 FPBACK 28 27 GMCH_TXACLK- 7
DCBATOUT 30 29 GMCH_TXAOUT2+ 7
32 31 GMCH_TXAOUT2- 7
EC155 34 33 GMCH_TXAOUT1+ 7
2

EC154 C298 EC156 36 35 GMCH_TXAOUT1- 7 Wistron Corporation

1
1
SCD1U50V3ZY
SC100P50V2JN-U

SC100P50V2JN-U

SC10U35V0ZY-L

38 37 GMCH_TXAOUT0+ 7
40 39 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY DY
1

GMCH_TXAOUT0- 7 Taipei Hsien 221, Taiwan, R.O.C.

41
DY
2
2

JST-CONN40A-2 Morar_SA:20.F0687.040 Title

connector
20.F0439.040 Morar_SB:20.F0687.040
LCD CONN & LED
Size Document Number Rev
Morar_SB:20.F0737.040(2nd) A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 13 of 40
 CRT CONNECTOR
Ferrite bead impedance: 75ohm@100MHz
L6
GMCH_RED 50 Ohm Impedance 1 2
75 Ohm Impedance CRT_R
7 GMCH_RED
BLM11B750S

L7
GMCH_GREEN 1 2 CRT_G
7 GMCH_GREEN
BLM11B750S

L8
GMCH_BLUE 1 2 CRT_B
7 GMCH_BLUE
1

1
BLM11B750S
R300 R301 R302 EC157 EC159 EC160 EC145 EC146 EC147
150R2F 150R2F 150R2F SC3P50V2CN SC3P50V2CN SC3P50V2CN SC6D8P50V2DC SC6D8P50V2DC SC6D8P50V2DC

2
DY DY DY
2

Hsync & Vsync level shift

5V_S0 1

C7

SCD1U16V
2

U26D
14

13

TSAHCT125

GMCH_HSYNC 12 11 CRT_HSYNC1
7 GMCH_HSYNC

DAT_DDC1_5
14

7
1

GMCH_VSYNC 2 3 CRT_VSYNC1 CRT_HSYNC1

7 GMCH_VSYNC

U26A CRT_VSYNC1
7

TSAHCT125
1

CLK_DDC1_5
C300 C299
SC33P50V2JN SC33P50V2JN ESD Protection Diode
2

1
EC1 EC2 EC148 EC149

SC10P50V2JN-1

SC10P50V2JN-1
5V_S0
SC100P50V2JN-U

SC100P50V2JN-U
2

2
BAV99PT-GP-U
2

CRT_R 3
D28
1
DDC_CLK & DATA level shift

5V_S0 BAV99PT-GP-U
D31 RB751V-40-U 2

1 2 5V_CRT_S0 CRT_G 3
D29
DY
1

1
EC161
2D5V_S0 SCD01U16V2KX
2

BAV99PT-GP-U
2

CRT_B 3
D30
5V_CRT_S0 1
1

CRT1
1

R1 R5 17
2K2R2 2K2R2
R2 R4 6
2

2K2R2 2K2R2 CRT_R 1 11

2

2
1

Q1
G

7
FDN337N-U CRT_G 2 12 DAT_DDC1_5
2 3 DAT_DDC1_5 8
7 GMCH_DDCDATA
CRT_B 3 13 CRT_HSYNC1
D
S

5V_CRT_S0 9
4 14 CRT_VSYNC1
Q2 10
1

FDN337N-U CLK_DDC1_5
G

5 15
Wistron Corporation
2 3 CLK_DDC1_5 16 Morar_SA:20.20378.015 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
7 GMCH_DDCCLK
Taipei Hsien 221, Taiwan, R.O.C.
D
S

Morar_SB:20.20378.015
20.20378.015 Title
Morar_SB CRT Connector
VIDEO-15-42
connector Size Document Number Rev
Custom
MORAR SB
Date: Saturday, May 28, 2005 Sheet 14 of 40
 A B C D E

1D05V_S0
C448 XTAL-32D768K-4P 3D3V_S0
1 2 NO_STUFF

1
SC3D9P16V3JN R454
X4 DY 56R2J LPC_LDRQ1 1 R474 2

1
3D3V_AUX_S5 RTC_AUX_S5 R451 10KR2

2
D42 H_DPSLP#
1 2 KBRCIN#_1 1 R563 2

1
10MR3
4 CH751H-40-U C469 10KR2 4

2
SC1U10V3ZY U49A

2
C543 KA20GATE_1 1 R564
RTC circuitry 1 2
LPC_LAD[0..3] 29 2

RCT_X1 Y1 P2 LPC_LAD0 Morar_SB 10KR2

SC3D9P16V3JN RCT_X2 Y2 RTCX1 LAD[0]/FWH[0] LPC_LAD1
RTCX2 LAD[1]/FWH[1] N3
LPC_LAD2

LPC
N5

RTC
D41 LAD[2]/FWH[2]
BAT_D
1 2 R479 1 2 20KR2F RCT_RST# AA2 N4 LPC_LAD3
RTCRST# LAD[3]/FWH[3]
1

R204 CH751H-40-U R480 1 2 1MR2 INTRUDER# AA3 N6 LPC_LDRQ#0

1KR2 INTVRMEN INTRUDER# LDRQ[0]# LPC_LDRQ1 TP107 TPAD28
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4

1
C463 TP39 TPAD28
SCD1U16V P3 LPC_LFRAME# 29
2

19 INTRUDER# LFRAME#/FWH[4]
D12

2
EE_CS Open R453 for Dothan A step 1D05V_S0
B12 EE_SHCLK
D11 AF22 Shunt for Dothan B step
EE_DOUT A20GATE KA20GATE_1 29
F13 AF23 & all Yonah
EE_DIN A20M# H_A20M# 4

1
LAN
F12 AE27 H_CPUSLP#1 R453 1 2 0R2-0 H_CPUSLP# 4,6 R443
LAN_CLK CPUSLP# 56R2J
BAT

R485
1 2 B11 AE24 H_DPRSLP#1 R445 1 2 0R2-0 H_DPRSLP# 4
LAN_RSTSYNC DPRSLP#
AD27 H_DPSLP# 4

2
DPSLP#
5

1
2
3

10KR2 E12

CPU
LANRXD[0] H_FERR_R R444
Morar_SA:21.D0010.103 E11 LANRXD[1] FERR# AF24 1 2 56R2J H_FERR# 4
C13 LANRXD[2]
Morar_SB:20.F0735.003 CPUPWRGD/GPO[49] AG25 H_PWRGD 4,19
C12 LANTXD[0]
21.D0010.103 C11 AG26 H_IGNNE# 4
RTC1 connector LANTXD[1] IGNNE# FWH_INIT# TP36
E13 LANTXD[2] INIT3_3V# AE22
3 AF27 3
INIT# H_INIT# 4
R187 1 2 0R3-U C10 AG24 H_INTR 4
26 ACZ_BITCLK ACZ_BIT_CLK INTR

1
R483 1 2 39R2J ACZ_SYNC_R B9 1D05V_S0
DY

AC-97/AZALIA
21,26 ACZ_SYNC ACZ_SYNC C440
RCIN# AD23 KBRCIN#_1 29 IDE_PDA1 20
R484 1 2 39R2J ACZ_RST#_R A10 SC4700P50V2KX

2
21,26 ACZ_RST# ACZ_RST#

1
NMI AF25 H_NMI 4
F11 AG27 H_SMI# 4 R442
BAT EC108 1 26 ACZ_SDATAIN0 ACZ_SDIN[0] SMI# 75R2F
2 SCD01U16V2KX 21 ACZ_SDATAIN1 F10 ACZ_SDIN[1]
B10 ACZ_SDIN[2] STPCLK# AE26 H_STPCLK# 4
TP93 TPAD28
DY R441

2
R186 1 2 39R2J ACZ_SDATAOUT_R C9 AE23 H_THERMTRIP_R 1 2 PM_THRMTRIP-I# 4,19
21,26 ACZ_SDATAOUT ACZ_SDO THRMTRIP#

SATA_LED# Layout Note: R632 needs to placed

AC19 SATALED# DA[0] AC16 IDE_PDA0 2056R2J
TP34 TPAD28 AB17 within 2" of ICH6, R634 must be placed
DA[1] within 2" of R632 w/o stub.
AE3 SATA[0]RXN DA[2] AC17 IDE_PDA2 20
AD3 SATA[0]RXP
SATA_TXN0_C AG2 AD16 IDE_PDCS1# 20
TP77 TPAD28 SATA_TXP0_C SATA[0]TXN DCS1#
AF2 SATA[0]TXP DCS3# AE17 IDE_PDCS3# 20
TP76 TPAD28
AD7 SATA[2]RXN DD[0] AD14 IDE_PDD0 20
AC7 AF15

SATA
SATA[2]RXP DD[1] IDE_PDD1 20
SATA_TXN1_C AF6 AF14
SATA[2]TXN DD[2] IDE_PDD2 20
TP80 TPAD28 SATA_TXP1_C

IDE
AG6 SATA[2]TXP DD[3] AD12 IDE_PDD3 20
TP81 TPAD28 AE14
DD[4] IDE_PDD4 20
RTC_AUX_S5 AC2 AC11
SATA_CLKN DD[5] IDE_PDD5 20
AC1 SATA_CLKP DD[6] AD11 IDE_PDD6 20
DD[7] AB11 IDE_PDD7 20
1

AG11 SATARBIAS# DD[8] AE13 IDE_PDD8 20

2 R126 2
AF11 SATARBIAS DD[9] AF13 IDE_PDD9 20
100KR2 AB12
DY P.H. for internal VCCSUS1_5 DD[10]
DD[11] AB13
IDE_PDD10
IDE_PDD11
20
20
AC13 IDE_PDD12 20
2

DD[12]
20 IDE_PDIORDY AF16 IORDY DD[13] AE15 IDE_PDD13 20
INTVRMEN AB16 AG15
20 INT_IRQ14 IDEIRQ DD[14] IDE_PDD14 20
20 IDE_PDDACK# AB15 DDACK# DD[15] AD13 IDE_PDD15 20
20 IDE_PDIOW# AC14 DIOW#
1

20 IDE_PDIOR# AE16 DIOR# DDREQ AB14 IDE_PDDREQ 20

R125
0R2-0
2

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH6-M (1 of 4)
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 15 of 40
A B C D E
 A B C D E

U49C Layout Note:

PCIE AC coupling caps
U49B 3D3V_S0 need to be within 250 mils of the driver.
2,24,28 PCI_AD[31..0]
PM_RI# T2 H25 TPAD28 TP52
PCI_AD0 PCI_REQ#0 RI# PERn[1] TPAD28 TP51
E2 AD[0] REQ[0]# L5 PCI_REQ#0 24 PERp[1] H24
PCI_AD1 E5 PCI C1 PCI_GNT#0 PCI_GNT#0 24 1 R432 2 10KR2 SATA0_R0 AF17 G27 TPAD28 TP85
PCI_AD2 AD[1] GNT[0]# PCI_REQ#1 R433 10KR2 SATA0_R1 SATA[0]GP/GPI[26] PETn[1] TPAD28 TP89
C2 AD[2] REQ[1]# B5 PCI_REQ#1 28 1 2 AE18 SATA[1]GP/GPI[29] PETp[1] G26
PCI_AD3 F5 B6 PCI_GNT#1 28 1 R435 2 10KR2 SATA0_R2 AF18
PCI_AD4 AD[3] GNT[1]# PCI_REQ#2 R434 10KR2 SATA0_R3 SATA[2]GP/GPI[30] TPAD28 TP50
F3 AD[4] REQ[2]# M5 PCI_REQ#2 22 1 2 AG18 SATA[3]GP/GPI[31] PERn[2] K25
PCI_AD5 TPAD28 TP49

PCI-EXPRESS
E9 AD[5] GNT[2]# F1 PCI_GNT#2 22 PERp[2] K24
PCI_AD6 F2 B8 PCI_REQ#3 Y4 J27 TPAD28 TP92
AD[6] REQ[3]# 18 SMB_CLK SMBCLK PETn[2]
PCI_AD7 D6 C8 TP46 TPAD28 W5 J26 TPAD28 TP86
AD[7] GNT[3]# 18 SMB_DATA SMBDATA PETp[2]
PCI_AD8 E6 F7 BOOT_BLOCK# TP48 TPAD28 SMB_LINK_ALERT# Y5
PCI_AD9 AD[8] REQ[4]#/GPI[40] TP47 TPAD28 SMLINK0 LINKALERT# TPAD28 TP44
D3 E7 W4 M25

GPIO
4 4
PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQ#5 SMLINK1 SMLINK[0] PERn[3] TPAD28 TP43
A2 AD[10] REQ[5]#/GPI[1] E8 U6 SMLINK[1] PERp[3] M24
PCI_AD11 D2 F6 PCI_GNT#5 MCH_SYNC# AG21 L27 TPAD28 TP91
PCI_AD12 AD[11] GNT[5]#/GPO[17] PCI_REQ#6 MCH_SYNC# PETn[3] TPAD28 TP88
D5 AD[12] REQ[6]#/GPI[0] B7 26 ACZ_SPKR F8 SPKR PETp[3] L26
PCI_AD13 H3 D8 PCI_GNT#6
PCI_AD14 AD[13] GNT[6]#/GPO[16] TPAD28 TP42
B4 AD[14] 29 PM_SUS_STAT# W3 SUS_STAT#/LPCPD# PERn[4] P24
PCI_AD15 J5 J6 P23 TPAD28 TP41
AD[15] C/BE[0]# PCI_C/BE#0 22,24,28 PERp[4]
PCI_AD16 K2 H6 DBRESET# U2 N27 TPAD28 TP90
AD[16] C/BE[1]# PCI_C/BE#1 22,24,28 SYS_RESET# PETn[4]
PCI_AD17 K5 G4 N26 TPAD28 TP87
AD[17] C/BE[2]# PCI_C/BE#2 22,24,28 PETp[4]
PCI_AD18 D4 G2 AD19
AD[18] C/BE[3]# PCI_C/BE#3 22,24,28 7 PM_BMBUSY# BMBUSY#
PCI_AD19 L6 T25 DMI_RXN0 7
PCI_AD20 AD[19] DMI[0]RXN
G3 AD[20] IRDY# A3 PCI_IRDY# 22,24,28 29 ECSCI#_1 AE19 GPI[7] DMI[0]RXP T24 DMI_RXP0 7
PCI_AD21 H4 E1 R1 R27 Layout Note:

Direct Media Interface

AD[21] PAR PCI_PAR 22,24,28 29 ECSMI# GPI[8] DMI[0]TXN DMI_TXN0 7
PCI_AD22 H2 R2 R472 1 2 47R2 R26 PCIE AC coupling caps
AD[22] PCIRST# PCIRST1# 22,24,28 DMI[0]TXP DMI_TXP0 7
PCI_AD23 H5 C3 SMB_ALERT# W6 need to be within 250 mils of the driver.
AD[23] DEVSEL# PCI_DEVSEL# 22,24,28 SMBALERT#/GPI[11]
PCI_AD24 B3 E3 V25 DMI_RXN1 7
AD[24] PERR# PCI_PERR# 22,24,28 DMI[1]RXN
PCI_AD25 M6 C5 PCI_LOCK# TP45 TPAD28 ICH_GPI12 M2 V24 DMI_RXP1 7
PCI_AD26 AD[25] PLOCK# GPI[12] DMI[1]RXP
B2 AD[26] SERR# G5 PCI_SERR# 22,24,28 29 ECSWI# R6 GPI[13] DMI[1]TXN U27 DMI_TXN1 7
PCI_AD27 K6 J1 U26 DMI_TXP1 7
AD[27] STOP# PCI_STOP# 22,24,28 DMI[1]TXP
PCI_AD28 K3 J2 AC21
AD[28] TRDY# PCI_TRDY# 22,24,28 3 PM_STPPCI# STP_PCI#
PCI_AD29 A5 Y25 DMI_RXN2 7
PCI_AD30 AD[29] TP37 TPAD28 ICH_GPO19 DMI[2]RXN
L1 AD[30] AB21 GPO[19] DMI[2]RXP Y24 DMI_RXP2 7
PCI_AD31 K4 R5 PLT_RST1#_1 1 R142 2 47R2 PLT_RST1# 7,18,29 W27 DMI_TXN2 7
AD[31] PLTRST# DMI[2]TXN
PCICLK G6 CLK_ICHPCI 3 3,34 PM_STPCPU# AD22 STP_CPU# DMI[2]TXP W26 DMI_TXP2 7
2,24,28 PCI_FRAME# J3 FRAME# PME# P6 ICH_PME# 22,29 Int. PH
TP35 TPAD28 ICH_GPO21 AD20 AB24 DMI_RXN3 7
KBC_SLP_WAKE AD21 GPO[21] DMI[3]RXN 1D5V_S0
Interrupt I/F 29 KBC_SLP_WAKE GPO[23] DMI[3]RXP AB23 DMI_RXP3 7
INT_PIRQA# N2 D9 INT_PIRQE# INT_PIRQE# 22 AA27 DMI_TXN3 7
INT_PIRQB# PIRQ[A]# PIRQ[E]#/GPI[2] INT_PIRQF# DMI[3]TXN Place within 500 mils of ICH
24 INT_PIRQB# L2 PIRQ[B]# PIRQ[F]#/GPI[3] C7 INT_PIRQF# 28 31 PCB_VER1 V3 GPIO[24] DMI[3]TXP AA26 DMI_TXP3 7

1
3 INT_PIRQC# M1 C6 INT_PIRQG# INT_PIRQG# 24
3
INT_PIRQD# PIRQ[C]# PIRQ[G]#/GPI[4] INT_PIRQH# R154
L3 PIRQ[D]# PIRQ[H]#/GPI[5] M3 31 PCB_VER2 P5 GPIO[25] DMI_CLKN AD25 CLK_PCIE_ICH# 3
R3 AC25 24D9R2F
31 PCB_VER0 GPIO[27] DMI_CLKP CLK_PCIE_ICH 3
RESERVED CHK_PW# T3
TP29 TPAD28 TPAD28 TP32 31 CHK_PW# GPIO[28]
AC5 AD9 22,24,28,29 PM_CLKRUN# AF19 F24

2
TP30 TPAD28 RSVD[1] RSVD[6] TPAD28 TP82 TP84 TPAD28 ICH_GPIO33 CLKRUN# DMI_ZCOMP
AD5 RSVD[2] RSVD[7] AF8 AF20 GPIO[33]
TP78 TPAD28 AF4 AG8 TPAD28 TP83 TP33 TPAD28 ICH_GPIO34 AC18 F23 DMI_IRCOMP_R RP4
RSVD[3] RSVD[8] GPIO[34] DMI_IRCOMP 3D3V_S5
TP79 TPAD28 AG4 U3 TPAD28 TP38 USB_OC#2 1 10
TP31 TPAD28 RSVD[4] TP[3] ICH6_WAKE# USB_OC#4
AC9 RSVD[5] U5 WAKE# OC[4]#/GPI[9] C23 USB_OC#4 21USB_OC#1 2 9 USB_OC#7
D23 USB_OC#5 USB_OC#3 3 8 USB_OC#6
OC[5]#/GPI[10] USB_OC#6 USB_OC#0 USB_OC#5
24,28,29 INT_SERIRQ AB20 SERIRQ OC[6]#/GPI[14] C25 4 7
C24 USB_OC#7 5 6 USB_OC#4
3D3V_S0 OC[7]#/GPI[15] 3D3V_S5
3D3V_S5 THRM# AC20
ICH6 Pullups
PM_RI# R473
19 THRM# THRM#
OC[0]# C27 USB_OC#0 USB_OC#0 21 SRP10K
1 2 10KR2 PCI_REQ#6 R481 1 2 10KR2 7,32 VGATE_PWRGD AF21 VRMPWRGD OC[1]# B27 USB_OC#1
RP1 B26 USB_OC#2 USB_OC#2 21
3D3V_S0 OC[2]#
INT_PIRQD# 1 10 SMB_ALERT# R468 1 2 10KR2 PCI_REQ#1 R184 1 2 10KR2 E10 C26 USB_OC#3

CLOCKS
PCI_REQ#5 PCI_FRAME# 3 CLK_ICH14 CLK14 OC[3]#
2 9
PCI_SERR# 3 8 PCI_STOP# SMB_LINK_ALERT# R464 1 2 10KR2 BOOT_BLOCK# R153 1 2 10KR2 A27 C21
INT_PIRQF# 4 7 PCI_TRDY# 3 CLK48_ICH CLK48 USBP[0]N
USBP[0]P D21
USBPN2
USBPP2
21
21
3D3V_S0 DY
5 6 PCI_PERR# SMLINK0 R124 1 2 10KR2 ECSCI#_1 R436 1 2 100KR2 V6 A20 USBPN1 R152 1KR2 R7F9
3D3V_S0 18 PM_SUS_CLK SUSCLK USBP[1]N
B20 USBPP1 TPAD28 TP98 1 2 ACZ_SPKR
SMLINK1 R465 1 USBP[1]P
SRP10K 2 10KR2 5 PM_SLP_S3#_ICH T4 SLP_S3# USBP[2]N D19 TPAD28 TP99
USBPN4 21
RP3 3D3V_S0 T5 C19 USBPP4 21
PCI_LOCK# ICH6_WAKE# R469 1 29,37 PM_SLP_S4# SLP_S4# USBP[2]P
1 10 2 1KR2 PM_SLP_S5# T6 SLP_S5# USBP[3]N A18 USBPN3
INT_PIRQG# 2 9 PCI_REQ#3 TP40 TPAD28 B18 USBPP3 TPAD28 TP97 R7F8
PCI_DEVSEL# INT_PIRQE# PM_BATLOW#_R R471 1 Need to check what power we will use USBP[3]P
3 8 2 8K2R2 AA1 E17 TPAD28 TP96
USBPN0 21
R482 1KR2

POWER MGT
PCI_IRDY# PM_CLKRUN# 19 PWROK PWROK USBP[4]N PCI_GNT#6
4 7 D17 1 2
3D3V_S0 5 6 PCI_REQ#2 DBRESET# R475 1 2 10KR2
34 PM_DPRSLPVR
R439 1 2 100R2 PM_DPRSLPVR_RAE20 DPRSLPVR
USBP[4]P
USBP[5]N B16 USBPN5
USBPP0 21 DY
2 2

USB
ECSMI# R470 1 2 100KR2 A16 USBPP5 TPAD28 TP95
SRP10K ECSWI# R467 1 DY 2 100KR2 PM_BATLOW#_R V2
USBP[5]P
C15 USBPN6 TPAD28 TP94 R477 1KR2 R7F7
RP2 CHK_PW# R466 1 DY 2 10KR2 BATLOW# USBP[6]N
D15 USBPP6
USBPN6 21
1 2 PCI_GNT#5
PCI_REQ#0 1 10
3D3V_S0
29 PM_PWRBTN#
PM_PWRBTN# U1 PWRBTN#
USBP[6]P
USBP[7]N A14 USBPN7
USBPP6 21
USBPN7 21
DY
R452
INT_PIRQA# 2 9 INT_SERIRQ B14 USBPP7 100KR2
USBP[7]P USBPP7 21
INT_PIRQC# 3 8 THRM# LAN_RST# V5 1 2 PWROK
INT_PIRQH# MCH_SYNC# PM_SLP_S3#_ICH R463 2 LAN_RST# R189
4 7 1 PM_SLP_S3# 18,29,32,37 USBRBIAS# A22
5 6 INT_PIRQB# 0R0402-PAD Y3 B22 USB_RBIAS_PN 1 2
3D3V_S0 29,32 RSMRST#_KBC RSMRST# USBRBIAS
2

1
SRP10K R460 22D6R2F
PM_DPRSLPVR_R R146 R476 Place within 500 mils of ICH
DY 100KR2
10KR2
2

100KR2
1

R437

2
DY 100KR2
ICH6-M Strapping Options
1

REF FUNCTION DEFAULT OPTIONAL OVERRIDE

R7F9 No Reboot NO_STUFF STUFF

A16 Swap
R7F8 Override NO_STUFF STUFF

R7F7 Boot BIOS NO_STUFF STUFF

1 <Core Design> 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH6-M (2 of 4)
Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 16 of 40
A B C D E
 A B C D E

1D5V_S0

Layout Note:
Place above caps within

1
100 mils of ICH near F27, P27, AB27 C171
U49E C169 C178 C159 C150 Layout Note:
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V Place near pin AA19

2
1D5V_S0

AA22 VCC1_5_B VCC1_5_A F9

AA23 VCC1_5_B VCC1_5_A U17

1
AA24 VCC1_5_B VCC1_5_A U16

1
4 TC18 C456 C186 C185 AA25 U14 4
ST220U2D5VBM SCD1U16V SCD1U16V SCD1U16V VCC1_5_B VCC1_5_A C167 EC82 EC195 EC78 EC89
AB25 U12

2
VCC1_5_B VCC1_5_A SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
AB26 U11

2
VCC1_5_B VCC1_5_A
AB27 VCC1_5_B VCC1_5_A T17
F25 VCC1_5_B VCC1_5_A T11
F26 P17

CORE
VCC1_5_B VCC1_5_A
F27 VCC1_5_B VCC1_5_A P11
G22 VCC1_5_B VCC1_5_A M17
G23 VCC1_5_B VCC1_5_A M11
G24 VCC1_5_B VCC1_5_A L17
Layout Note: G25 L16
IDE decoupling VCC1_5_B VCC1_5_A
H21 VCC1_5_B VCC1_5_A L14
3D3V_S0 H22 L12
VCC1_5_B VCC1_5_A
J21 VCC1_5_B VCC1_5_A L11 ALL NO_STUFF Caps do
1

1
J22 VCC1_5_B VCC1_5_A AA21 not have layout
C153 C447 C464 C166 K21 AA20 Place within 100 requirements but if
1D5V_S0 VCC1_5_B VCC1_5_A mils of ICH pin 3D3V_S0
SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V
K22 AA19 layout allows then place
2

2
VCC1_5_B VCC1_5_A AG13, AG16
L21 VCC1_5_B
next to ICH6

1
L22 AA10
DY

PCIE
VCC1_5_B VCC3_3

1
EC83 M21 AG19
DY SCD1U16V M22
VCC1_5_B VCC3_3
AG16 C423 C165 *Within a given well, 5VREF needs to be up before the

2
VCC1_5_B VCC3_3 SCD1U16V SCD1U16V
N21 AG13 corresponding 3.3V rail

2
VCC1_5_B VCC3_3
N22 VCC1_5_B VCC3_3 AD17
Layout Note: N23 AC15

IDE
PCI decoupling VCC1_5_B VCC3_3
N24 VCC1_5_B VCC3_3 AA17
N25 VCC1_5_B VCC3_3 AA15
P21 AA14 Layout Note: 3D3V_S0 3D3V_S0 5V_S0
VCC1_5_B VCC3_3 Distribute in PCI section
P25 VCC1_5_B VCC3_3 AA12
P26 near pin A2-A6 near D1-H1
VCC1_5_B

2
3 P27 P1 3
VCC1_5_B VCC3_3

1
R21 M7 D17 R185
VCC1_5_B VCC3_3 C465 C175 C455
R22 VCC1_5_B VCC3_3 L7 CH751H-40-U 10R2
T21 L4 SCD1U16V SCD1U16V SCD1U16V

2
VCC1_5_B VCC3_3 83.R0304.08F
T22 J7

1
VCC1_5_B VCC3_3

PCI
U21 H7 1D5V_ICH_S5 V5REF_S0
VCC1_5_B VCC3_3 1D5V_INT_S5 R149
U22 VCC1_5_B VCC3_3 H1

1
V21 VCC1_5_B VCC3_3 E4 1 0R3-U 2

1
V22 B1 C196 C197
VCC1_5_B VCC3_3 C162 C163 SCD1U16V SC1U10V3ZY
W21 A6

2
VCC1_5_B VCC3_3 SCD1U16V SCD1U16V
W22

2
1D5V_S0 VCC1_5_B
Y21 VCC1_5_B VCCSUS1_5 U7
Y22 VCC1_5_B VCCSUS1_5 R7
1D5V_INT_S5 3D3V_S5 5V_S5
AA6 VCC1_5_A

USB
AB4 VCC1_5_A VCCSUS1_5 G19
1

2
Place within 100 C170 C151 C176 AB5 1D5V_S0
DY VCC1_5_A

1
mils of ICH Layout Note: D18 R486
SCD1U16V

SCD1U16V

SCD1U16V

AB6 VCC1_5_A VCC1_5_A G20

1
near pin AG5 AC4 F20 C183 Place near ICH6
2

VCC1_5_A VCC1_5_A C168 C184 SCD1U16V CH751H-40-U 10R2

AD4 E24

2
VCC1_5_A VCC1_5_A SCD1U16V SCD1U16V 83.R0304.08F
AE4 E23

USB CORE

1
VCC1_5_A VCC1_5_A V5REF_S5
AE5 VCC1_5_A VCC1_5_A E22
AF5 E21 Place both
VCC1_5_A VCC1_5_A

1
1D5V_S0 AG5 E20 within 100 mils
SATA

VCC1_5_A VCC1_5_A of ICH near D27 C467 C466

VCC1_5_A D27
Place within 100 AA7 D26 SCD1U16V SC1U10V3ZY

2
mils of ICH VCC1_5_A VCC1_5_A
AA8 VCC1_5_A VCC1_5_A D25
1

near pin AG9 C154 C172 C164 AA9 D24

1D5V_GPLL_ICH_S0 VCC1_5_A VCC1_5_A
SCD1U16V

SCD1U16V

SCD1U16V

AB8 VCC1_5_A
2 1D5V_S0 V2D5S_PCI_IDE 2D5V_S0 2
AC8 G8
2

R128 VCC1_5_A VCC1_5_A

AD8 VCC1_5_A R127
1 0R3-U 2 AE8 AB18 1 2
PCI/IDE

VCC1_5_A VCC2_5

1
AE9 P7 1D5V_ICH_S0
VCC1_5_A VCC2_5
1

Place within 100 C450 AF9 C160 0R3-U

VCC1_5_A
REF

mils of ICH C451 SCD01U16V2KX AG9 SCD1U16V Layout Note: 3D3V_S5

2
SC10U10V5ZY-L VCC1_5_A Place near AB18 Place within 100 1D5V_ICH_S5
AA18
2

V5REF

1
AC27 A8 mils of ICH U51
3D3V_S0 VCCDMIPLL V5REF V5REF_S0 C199
E26 VCC3_3
F21 V5REF_S5 3D3V_ICH_S5 SCD01U16V2KX 2

2
V5REF_SUS VOUT
AE1 VCCSATAPLL 3 VIN
1

SCD1U16V 1D5V_S0 R190 1D5V_ICH_S0 AG10 A25 1

VCC3_3 VCCUSBPLL GND

1
Place within 100 C187 1 2 A24
VCCSUS3_3

1
mils of ICH A13 Place within 100 C446 C454
2

VCCLAN3_3/VCCSUS3_3
1

1
near E26, E27 0R3-U F14 AB3 mils of ICH SC1U10V3ZY APL5308-15AC-GP SC2D2U6D3V3MX-1

2
C149 VCCLAN3_3/VCCSUS3_3 VCCRTC C182
G13

2
Place within 100 SCD1U16V VCCLAN3_3/VCCSUS3_3 1D5V_INT_S5 SCD1U16V
G14
2

2
mils of ICH VCCLAN3_3/VCCSUS3_3
VCCLAN1_5/VCCSUS1_5 G11
1

3D3V_S0 pin AE1 A11 G10

VCCSUS3_3 VCCLAN1_5/VCCSUS1_5 C177 Place within 100 RTC_AUX_S5
U4 VCCSUS3_3
V1 AG23 SCD1U16V mils of ICH
2

VCCSUS3_3 V_CPU_IO
1

Place within 100 V7 AD26 pin G10 Layout Note:

mils of ICH C152 VCCSUS3_3 V_CPU_IO Place near AB3
W2 VCCSUS3_3 V_CPU_IO AB22

1
pin AG10 SCD1U16V Y7 1D05V_S0
2

3D3V_S5 VCCSUS3_3 C148 C439

VCCSUS3_3 G16
1

A17 G15 SCD1U16V SCD1U16V

2
VCCSUS3_3 VCCSUS3_3 C424
B17 VCCSUS3_3 VCCSUS3_3 F16
C17 F15 SCD1U16V
2

VCCSUS3_3 VCCSUS3_3
1

C198 C179 F18 E16 Layout Note:

1 VCCSUS3_3 VCCSUS3_3 1
1D5V_S0 G17 D16 Place near AG23
Place within 100 SCD1U16V SCD1U16V VCCSUS3_3 VCCSUS3_3
G18 C16
Wistron Corporation
2

mils of ICH VCCSUS3_3 VCCSUS3_3

EC190 EC79 C449 C422 pin A13 3D3V_ICH_S5 3D3V_S5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

R188 Taipei Hsien 221, Taiwan, R.O.C.

SCD1U16V

SCD1U16V

SCD1U16V

SC10U10V5ZY-L

3D3V_S5 V3D3A_VCCPSUS 1 0R3-U 2

1 0R3-U 2 Title
2

1
R150
DY ICH6-M (3 of 4)
1

Place within 100 C180 C468 C181

DY C161 mils of ICH SCD1U16V SCD1U16V SCD1U16V Place within 100 Size Document Number Rev
2

SCD1U16V pin V7 mils of ICH A3

MORAR SB
2

pin A17
Date: Friday, June 24, 2005 Sheet 17 of 40

A B C D E
 A B C D E

U49D

E27 VSS VSS F4

Y6 VSS VSS F22
32K suspend clock output 3D3V_S5 Y27 F19
VSS VSS
Y26 VSS VSS F17
Y23 VSS VSS E25
U48 W7 E19
VSS VSS
16,29,32,37 PM_SLP_S3# 1 OE VCC 5 W25 VSS VSS E18
16 PM_SUS_CLK 2 A R461 W24 VSS VSS E15
3 4 32KHZ 1 2 G791_32K 19 W23 E14
GND Y VSS VSS
4 W1 VSS VSS D7 4
NC7SZ126-1 10R2 V4 D22
VSS VSS
V27 VSS VSS D20
V26 VSS VSS D18

1
V23 VSS VSS D14
R462 U25 D13
240KR3 VSS VSS
U24 VSS VSS D10
63.24434.151 U23 VSS VSS D1
U15 C4

2
VSS VSS
U13 VSS VSS C22
T7 VSS VSS C20
T27 VSS VSS C18
T26 VSS VSS C14
T23 VSS VSS B25
T16 VSS VSS B24
T15 VSS VSS B23
T14 VSS VSS B21
T13 VSS VSS B19
T12 VSS VSS B15
T1 VSS VSS B13
R4 VSS VSS AG7
R25 VSS VSS AG3
R24 VSS VSS AG22
5V_S0 R23 AG20
U26C VSS VSS
R17 VSS VSS AG17

14

10
R16 VSS VSS AG14
R15 VSS VSS AG12
R304 R14 AG1
VSS VSS
7,16,29 PLT_RST1# 9 8 1 2 RSTDRV#_5 20 R13 VSS VSS AF7
3 R12 AF3 3
VSS VSS

1
33R2 R11 AF26
VSS VSS

VSS
TSAHCT125 P22 AF12

7
R303 VSS VSS
P16 VSS VSS AF10
10KR2 P15 AF1
VSS VSS
P14 AE7

2
VSS VSS
P13 VSS VSS AE6
P12 VSS VSS AE25
N7 VSS VSS AE21
PCIRST# 3V to 5V level shift for HDD & CDROM N17 VSS VSS AE2
N16 VSS VSS AE12
N15 VSS VSS AE11
N14 VSS VSS AE10
N13 VSS VSS AD6
N12 VSS VSS AD24
N11 VSS VSS AD2
N1 VSS VSS AD18
M4 VSS VSS AD15
M27 VSS VSS AD10
M26 VSS VSS AD1
M23 VSS VSS AC6
M16 VSS VSS AC3
M15 VSS VSS AC26
M14 VSS VSS AC24
M13 VSS VSS AC23
M12 VSS VSS AC22
L25 VSS VSS AC12
L24 VSS VSS AC10
L23 VSS VSS AB9
2 2
L15 VSS VSS AB7
L13 VSS VSS AB2
K7 VSS VSS AB19
K27 AB10
SMBUS K26
VSS
VSS
VSS
VSS AB1
K23 VSS VSS AA4
K1 VSS VSS AA16
3D3V_S5 J4 AA13
5V_S0 3D3V_S0 VSS VSS
J25 VSS VSS AA11
J24 VSS VSS A9
J23 VSS VSS A7
H27 VSS VSS A4
1
1

H26 VSS VSS A26

3
4

R123 R122 H23 A23

VSS VSS
G9 VSS VSS A21
SRN10KJ RN12 4K7R2 4K7R2 G7 A19
VSS VSS
G21 A15
2
2

VSS VSS
G12 VSS VSS A12
Q12 G1 A1
2
1

VSS VSS
1

2N7002
G

16 SMB_CLK 3 2 SMBC_ICH 3,11

1
G
D

16 SMB_DATA 3 2 SMBD_ICH 3,11

Q94 & Q95 connect SMLINK and
D

Q11
SMBUS in S) for SMBus 2.0
1
compliance 2N7002 <Core Design> 1
84.27002.031

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ICH6-M (4 of 4)
Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 18 of 40
A B C D E
 FAN1_VCC

*Layout* 15 mil

1
C61 C73 D9 C72
SCD1U16V SC10U10V5ZY-L BAT54-1 SC2200P50V2KX 5V_S0
2

1
Morar_SB

2
R44
10KR2

FAN1

2
5
3
2
FAN1_VCC
1
4

1
C70 *Layout* 15 mil

SC100P50V2JN-U
connector

2
20.D0122.103
Morar_SA:20.D0122.103
5V_S0 Morar_SB:20.F0736.003
5V_S0 U5
*Layout* 30 mil
R38 200R2F
1 2 5V_G791_S0 6 1
VCC FAN1
20 DVCC FG1 4

1
CLK 14 G791_32K 18

1
C60 C63 C71 C74 16
SDA SMBD_G792 29
SCD1U16V R37 SCD1U16V SCD1U16V

SC4D7U10V5ZY
7 18 SMBC_G792 29
2
4K99R2F DXP1 SCL
9 19 Morar_SB

2
DXP2 NC H_THERMDA
11 DXP3 G792_DXP3 SC470P50V2KX

SC2200P50V2KX

SC2200P50V2KX
5 G792_DXP2 SC470P50V2KX
DGND

3
TP17 ALERT# 15 17 Q31
ALERT# DGND

3
G792_THERM# 13 Q40 C389 1
THERM#

C58

C322
Setting T8 as TPAD28 V_DEGREE 3 8 H_THERMDC C544 1
THERM_SET SGND1 G792_DXN2 PMBS3904-1-GP
2 10

2
RESET# SGND2
1
100 Degree 12 PMBS3904-1-GP

2
R39 SGND3 G792_DXN3
49K9R2F G7

2
GAP-CLOSE

GAP-CLOSE
V_DEGREE G792SFX
=(((Degree-72)*0.02)+0.34)*VCC System Sensor
2

G6
3D3V_S0
R40 System接第二組,VGA接第三組

1
75KR2F
1

16 PWROK 1 2 G792_RESET#
R46 DXP1:108 Degree H_THERMDA 4
1

1
10KR2
C62 R42 DXP2:H/W Setting Place near chip as close C59
SC2200P50V2KX 100KR2F DXP3:88 Degree as possible SC2200P50V2KX H_THERMDC 4
2

2
ALERT# 1 R47 2
0R0402-PAD
THRM# 16
DY
2

DY
2 1 INTRUDER# 15
0R2-0 R251
Morar_SB Morar_SB
5V_AUX_S5
3D3V_AUX_S5 MAX6326UR29-T-U R591
RESET# 2 1 2 RSMRST# 29
1

3 VCC
R28 1 0R2-0
GND
150R2F 3
5V_AUX_S5 DY
DY DY
1

HW thermal shut down tempature U61

2

R250 D23
setting 95 degree . Put Near CPU . 10KR2 3D3V_AUX_S5
DY
1

C21 R29 U19

2

U4 SCD1U16V 0R2-0 BAT54-1 1 5

2

R34 A VCC
DY18KR2F2 DY
1

1 CPU_THSET 1 5 Morar_SB 2
29 S5_ENABLE
DY
2

SET VCC C244 B

2 GND

1
T8_HW_SHUT# 3 4 CPU_TH_HYST SCD1U16V 3 4 S5PWR_ENABLE 35
2

OUT# HYST GND Y

1

R565
DY D24 100KR2F NC7S08-U
1

G709T1U RB751V-40-U
DY R30
DY DY

2
0R2-0 (dummy, KBC already delay) R562
2

1 2
2

0R2-0

Morar_SB
T8_HW_SHUT#

Morar_SB
3

R208
1 2 1 Q17
4,15 H_PWRGD CHT2222A Wistron Corporation
330R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
1

Taipei Hsien 221, Taiwan, R.O.C.

C213 PM_THRMTRIP-I# 4,15
SCD1U16V Title
2

Thermal/Fan Controllor
Size Document Number Rev
Custom
MORAR SB
Date: Saturday, May 28, 2005 Sheet 19 of 40
 CD-ROM Connector
HDD Connector 3D3V_S0
Morar_SA:20.80251.050
Morar_SB:20.80251.050
Morar_SA:20.80592.044 Morar_SB:20.80633.050(2nd) G13 1 2 GAP-CLOSE
HDD1
Morar_SB:20.80592.044

1
46 ODD1 CD_AGND

1
43 44 RSTDRV#_5 RSTDRV#_5 18 R132 R131 R130 51
5 IDE_PDD8 IDE_PDD8 41 42 IDE_PDD7 4K7R2 4K7R2 4K7R2 2 1 CS_CDL 26
IDE_PDD7 15 26 CS_CDR
5 IDE_PDD9 IDE_PDD9 39 40 IDE_PDD6
IDE_PDD6 15
5 IDE_PDD10 IDE_PDD10 37 38 IDE_PDD5 4 3 CD_AGND
IDE_PDD5 15

2
5 IDE_PDD11 IDE_PDD11 35 36 IDE_PDD4 IDE_PDD8 6 5 RSTDRV#_5
IDE_PDD4 15

2
5 IDE_PDD12 IDE_PDD12 33 34 IDE_PDD3 IDE_PDD9 8 7 IDE_PDD7
IDE_PDD3 15
5 IDE_PDD13 IDE_PDD13 31 32 IDE_PDD2 IDE_PDIORDY IDE_PDD10 10 9 IDE_PDD6
IDE_PDD2 15
5 IDE_PDD14 IDE_PDD14 29 30 IDE_PDD1 IDE_PDDACK# IDE_PDD11 12 11 IDE_PDD5
IDE_PDD1 15
5 IDE_PDD15 IDE_PDD15 27 28 IDE_PDD0 INT_IRQ14 IDE_PDD12 14 13 IDE_PDD4
IDE_PDD0 15
25 26 IDE_PDD13 16 15 IDE_PDD3
23 24 IDE_PDDREQ IDE_PDD14 18 17 IDE_PDD2
IDE_PDDREQ 15
21 22 IDE_PDIOW# IDE_PDD15 20 19 IDE_PDD1
IDE_PDIOW# 15
19 20 IDE_PDIOR# IDE_PDDREQ 22 21 IDE_PDD0
IDE_PDIOR# 15
R129 1 2 470R2 HDDCSEL 17 18 IDE_PDIORDY IDE_PDIOR# 24 23
IDE_PDIORDY 15
15 16 IDE_PDDACK# 26 25 IDE_PDIOW#
IDE_PDDACK# 15
13 14 INT_IRQ14 IDE_PDDACK# 28 27 IDE_PDIORDY
INT_IRQ14 15
PDIAG 11 12 IDE_PDA1 30 29 INT_IRQ14
IDE_PDA1 15
IDE_PDA2 9 10 IDE_PDA0 5V_S0 R430 1 2 10KR2 PDIAG 32 31 IDE_PDA1
15 IDE_PDA2 IDE_PDA0 15
IDE_PDCS3# 7 8 IDE_PDCS1# IDE_PDA2 34 33 IDE_PDA0
15 IDE_PDCS3# IDE_PDCS1# 15
5 6 IDE_LED# R115 1 2 4K7R2 5V_S0 IDE_PDCS3# 36 35 IDE_PDCS1#
3 4 38 37 IDE_LED#
DY 40 39 Morar_SB
1 2 IDE_LED# 13 5V_S0 42 41 5V_S0
45 44 43
5V_S0 46 45
SPD-CONN44D-7-U1 48 47 CSEL 1 R584 2

1
20.80175.044 50 49
connector C419 C421 C420 52 10KR2

SCD1U16V

SCD1U16V
SC10U10V5ZY-L

2
DY
1

1
STC-CONN50-4R
1

1
SC10U10V5ZY-L

TC14 C146 C155 C418 20.80251.050 R96

DY 0R2-0
ST100U6D3VDM-5

SCD1U16V SCD1U16V D40 connector

2

SSM22LL-U
2

PIN 49,50 DON'T USE

DY

2
2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
HDD and CDROM
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 20 of 40
 100 mil
5V_USB0_S0
5V_USB0_S0 5V_USB1_S0
USB PORT 5V_USB0_S0

USB_0-
5V_S5 U46 16 USBPN7 USB2
R431 6
1 DY DY

1
1 8 1 1KR2 2 1
GND OC1# USB_OC#0 16

2
TC15 EC187 EC183 2 7 TR4
IN OUT1

SC1000P50V
SE150U10VM 3 6 R450 USB_0- 2
2

2
EN1/EN1# OUT2

SCD1U16V
4 5 1 1KR2 2 USB_0+ 3
29 USB_PWR_EN# EN2/EN2# OC2# USB_OC#2 16 DY 4
DY DY

1
5
G546B2P1UF-GP EC189 EC184

SCD1U16V
SCD1U16V
100 mil L-63UH 68.03216.20B SKT-USB-97-U

3
G5258B2 Active Low 1.5A connector
5V_USB1_S0
16 USBPP7
USB_0+ 22.10218.H01
Morar_SB Morar_SA:22.10218.H01
DY DY
1

RN11 Morar_SB:22.10218.H01
TC17 EC193 EC192 3 2
SE100U10VM

SC1000P50V
4 1 5V_USB0_S0
2

2
SCD1U16V

SRN0-2-U
5V_S5 U1 5V_USB2_S0

1 8 USB_1- USB3
GND OUT 16 USBPN6
2 IN OUT 7 6
3 IN OUT 6 1
USB_PWR_EN# 4 5 R6 1 1KR2 2
EN#/EN FLG USB_OC#4 16

2
100 mil TR5 USB_1- 2
USB_1+ 3
DY

1
5V_USB2_S0 G528P1U 4
EC4 5
G528P1U Active Low SCD1U16V DY

2
SKT-USB-97-U
DY DY
1

L-63UH 68.03216.20B

3
TC4 EC152 EC153 connector
SE100U10VM

SC1000P50V

22.10218.H01
2

2
SCD1U16V

USB_1+
16 USBPP6
Morar_SA:22.10218.H01
RN14 Morar_SB:22.10218.H01
3 2
4 1

SRN0-2-U 5V_USB1_S0

USB_2-
16 USBPN0 USB4
6
1
BLUETOOTH MODULE

2
TR6
USB_2- 2
3D3V_S0 USB_2+ 3
Morar_SB U2 4
3D3V_BT_S0 DY 5
2 GND IN 5 R18
3 L-63UH 68.03216.20B SKT-USB-97-U

3
NC 3D3V_BT_S0_R 3D3V_BT_S0
4 ON/OFF# OUT 1 1 2
29 BLUETOOTH_EN
0R3-U
16 USBPP0
USB_2+ 22.10218.H01
1

AAT4250-U EC21
DY
connector
SCD1U16V

RN15
2

BLUE1 3 2 Morar_SA:22.10218.H01
10 4 1
SRN0-2-U Morar_SB:22.10218.H01
8 BT_AUX TP3 TPAD28
7 BT_GPIO2 TP4 TPAD28 USB_3-
16 USBPN2 5V_USB2_S0
6 BT_GPIO1
5 BT_LINK_LED TP1 TPAD28
4 TP2 TPAD28
USBPN4 16

2
3 USBPP4 16 TR1
connector 2 USB1
20.D0012.108 1 3D3V_BT_S0 Morar_SA:20.D0012.108 6
1
9 Morar_SB:20.F0714.008 DY
USB_3- 2
Morar_SB:20.D0196.108(2nd) L-63UH 68.03216.20B USB_3+ 3

3
4
5
USB_3+
16 USBPP2
SKT-USB-97-U
MDC 1.5 CONNECTOR 3
RN1
2 22.10218.H01
4 1
MDC1
SRN0-2-U connector
13 15
Morar_SB MH1 14
1 2 TP66 TPAD28 Morar_SA:22.10218.H01
0R2-0 R590
15,26 ACZ_SDATAOUT ACZ_SDATAOUT
2 1
3 4 TP65 TPAD28 Morar_SB:22.10218.H01
5 6 3D3V_LAN_S5
15,26 ACZ_SYNC ACZ_SYNC 7 8
15 ACZ_SDATAIN1 1 0R2-0 2 ACSDATAIN1_A 9 10
R23 ACZ_RST# 11 12
15,26 ACZ_RST# ACZ_BTCLK_MDC 26
MH2 17
1

Morar_SB 16 18 C312
Wistron Corporation
1

C13
1

SC22P50V2JN-1 AMP-CONN12A-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SC4D7U10V5ZY
2

connector R22 C12 Taipei Hsien 221, Taiwan, R.O.C.

2

100KR2 DUMMY-C2
20.F0582.012
Title
Morar_SB DY DY
R588 Morar_SA:20.F0582.012 USB / MDC / BLUETOOTH
2

C565
2 1 2 1 Morar_SB:20.F0582.012 Size Document Number Rev
A3
SCD47U10V3ZY 10R2 Morar_SB:20.F0604.012(2nd) MORAR SB
Date: Saturday, May 28, 2005 Sheet 21 of 40
 A B C D E

TGP0 TGP1 CLOSE TO 16,24,28 PCI_C/BE#[3..0]

Morar_SB
TGN0 TGN1 LAN CHIP
16,24,28 PCI_AD[31..0]

1
R260 R259 R262 R261
49D9R2F 49D9R2F 49D9R2F 49D9R2F

LAN_X2 1 2

2
C249

2
MID0X MID1X X3 SC12P50V2JN
4 4

1
X-25MHZ-11-U
C266 C268

1
SCD01U50V3KX SCD01U50V3KX LAN_X1 1 2

2
C248
SC12P50V2JN

3D3V_LAN_S5
U17
LAVDDH
DY LAN_EECS_3 1 8
CS VCC

1
LAN_X1 1 R252 2 10KR2 LAN_EESK 2 7
3D3V_LAN_S5 SK DC
1 R246 2 3K6R3D LAN_EEDI 3 6 C246
3D3V_LAN_S5 DI ORG SCD1U16V
LAN_X2 LAN_EEDO 4 5

2
DO GND

ACT_LED# EEPROM LED OPTION USE '01' AT93C46-10SU-1GP

ACT_LED# 23
LDVDD_A LDVDD
RTL_LED1# (DEFINED IN SPEC) 2nd
RTL_LED1# 23
=> LED0 : ACT Morar_SB
LAN_EESK => LED1 : LINK
LDVDD (BOTH 10/100 AND GIGA CHIP)
LAN_EEDI 45 Ohm,
LAN_EEDO
3D3V_LAN_S5 3D3V_LAN_S5 600mA LAVDDH
3D3V_LAN_S5
1 R258 2 LAN_EECS_3
5K6R3F L4
PCI_AD0 1 2
3 RSET PCI_AD1 3
0R3-U DY

1
128
127

126

125

124

123

122

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
U20 C253 C237 C235 C234 C278
Morar_SB C252 C271 C250

2
SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V
DY DY DY
VSS

VSS

VSS

EESK

EEDI

EECS
LANWAKE
RSET

VSSPST
AVDD18

CTRL18

XTAL2

XTAL1

LED0
VDD18
LED1
LED2
LED3

VDD18

EEDO
VDD33

PCIAD0
PCIAD1
AVDDH

GND

GND

SCD1U16V

SCD1U16V

SCD1U16V
TGP0 1 102 PCI_AD2 3D3V_LAN_S5
23 TGP0 MDI0+ PCIAD2
23 TGN0 TGN0 2 101 Morar_SB
LAVDDL MDI0- VSSPST
3 AVDDL GND 100

3
4 99 LDVDD
TGP1 VSS VDD18 PCI_AD3 CTRL25 Q22
23 TGP1 5 MDI1+ PCIAD3 98 1
TGN1 6 97 PCI_AD4 BCP69T1-U
23 TGN1 MDI1- PCIAD4
LAVDDL 7 96 PCI_AD5 45 Ohm,

2
CTRL25 AVDDL PCIAD5 PCI_AD6
8 95
9
CTRL25 PCIAD6
94 LDVDD 600mA
LAVDDH VSS VDD33 PCI_AD7 LDVDD_A
10 AVDDH PCIAD7 93
11 92 PCI_C/BE#0 L5
LDVDD HSDAC+ CBEB0
12 91 1 2
13
HSDAC-
VSS
VSSPST
PCIAD8 90 PCI_AD8 DY
14 89 PCI_AD9 0R3-U
MDI2+ PCIAD9

1
15 MDI2- M66EN 88
LAVDDL 16 87 PCI_AD10 Morar_SB
AVDDL PCIAD10 PCI_AD11 C277 C255 C254 C233 C238 C247 C275 C236 C272 C251
17 86

2
VSS PCIAD11 PCI_AD12
18 85
2 3D3V_S0 MDI3+ PCIAD12 DY 2

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V

SCD1U16V
SC10U10V5ZY-L
19 MDI3- VDD33 84
1 LAVDDL 20 83 PCI_AD13
R265 2 1KR2 AVDDL PCIAD13 PCI_AD14
3 1 21 VSSPST PCIAD14 82
2 D25 BAT54-1 22 GND VSSPST 81
1 R264 2 ISOLATE# 23 80
15KR2F LDVDD ISOLATE# GND PCI_AD15
24 VDD18 PCIAD15 79
16 INT_PIRQE# 25 78 LDVDD
INTA# VDD18 PCI_C/BE#1
3D3V_LAN_S5 26 VDD33 CBEB1 77 Morar_SB
16,24,28 PCIRST1# 27 76 PCI_PAR
PCIRST# PAR PCI_PAR 16,24,28 3D3V_LAN_S5
3 PCLK_LAN 28 75 PCI_SERR#
PCICLK SERR# PCI_SERR# 16,24,28
16 PCI_GNT#2 PCI_GNT#2 29 74
PCI_REQ#2 GNT# NC
16 PCI_REQ#2 30 REQ# GND 73
16,29 ICH_PME# 31 PME# NC 72

1
LDVDD 32 71
PCI_AD31 VDD18 VDD33 PCI_PERR# R263
33 PCIAD31 PERR# 70 PCI_PERR# 16,24,28
PCI_AD30 34 69 PCI_STOP# 0R3-U
PCIAD30 STOP# PCI_DEVSEL# PCI_STOP# 16,24,28
35 GND DEVSEL# 68 PCI_DEVSEL# 16,24,28
PCI_AD29 36 67 PCI_TRDY# LAVDDL
PCI_TRDY# 16,24,28

2
PCI_AD28 PCIAD29 TRDY#
37 PCIAD28 VSSPST 66
38 65 PM_CLKRUN#
VSSPST CLKRUN# PM_CLKRUN# 16,24,28,29
PCIAD27
PCIAD26

PCIAD25
PCIAD24

PCIAD23

PCIAD22
PCIAD21

PCIAD20

PCIAD19

PCIAD18
PCIAD17
PCIAD16

FRAME#
VSSPST

C270 C269 C274 C273 C267

CBEB3

CBEB2
VDD33

VDD18

VDD18

VDD33

VDD18

1
IRDY#
IDSEL

GND

GND

GND

SCD1U16V

SCD1U16V

SCD1U16V
PCLK_LAN

SCD1U16V
SC1U10V3ZY
2

2
GIGALAN: RTL8110SBL
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1

RTL8100CL-U
C276
SC10P50V2JN-1
10/100 LAN:RTL8100C
1 1
2

PCI_AD27 LDVDD
PCI_AD26 PCI_IRDY#
PCI_IRDY# 16,24,28
PCI_FRAME#
3D3V_LAN_S5
PCI_AD25 PCI_C/BE#2
PCI_FRAME# 16,24,28
Wistron Corporation
PCI_AD24 PCI_AD16 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PCI_C/BE#3 PCI_AD17 Taipei Hsien 221, Taiwan, R.O.C.
LDVDD PCI_AD18
R253 LAN_IDSEL G19 Title
PCI_AD23 3D3V_LAN_S5
PCI_AD23 1 2 LAN_IDSEL PCI_AD19 1 2
PCI_AD22 LDVDD
3D3V_S5 3D3V_LAN_S5 RTL8100CL
100R2F PCI_AD21 PCI_AD20 GAP-CLOSE-PWR Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 22 of 40
A B C D E
 A B C D E

4 4
Morar_SB 10/100M Lan Transformer

U30

22 TGP0 7 10 TDP_RJ45-1
TD+ TX+ TDN_RJ45-2
22 TGN0 8 TD- TX- 9

RD+ 1 TGP1 22
XRF_RDC 6 2 TGN1 22
CT RD-
14 CT
11 16 RDP_RJ45-3 1.route on bottom as differential pairs.
XRF_TDC CT RX+ RDN_RJ45-6
3 15
CT RX- 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
1

1
SCD1U16V

SCD1U16V

DY 3.No vias, No 90 degree bends.

XFORM-187-U
RJ45_45 Morar_SB 4.pairs must be equal lengths.
2

5.6mil trace width,12mil separation.

RJ45_78
C307 C313 6.36mil between pairs and any other trace.
4
3
2
1

7.Must not cross ground moat,except

RN35
SRN75J RJ-45 moat.

C309
5
6
7
8

LAN_TERMINAL
3 3
SC1KP2KV

Morar_SB
Link: Green - 10Mbps/100Mbps
CONN_PWR_B2
Act: Yellow
CONN_PWR LAN1
DY DY 9 LED COLOR
1

2 TIP 2
RJ11_1
EC163 EC165 RING RJ11_2
SCD1U16V SCD1U16V LINK:GREEN ON
2

22 RTL_LED1# RTL_LED1# A1 A1:GREEN

3D3V_LAN_S5 2 R307 1CONN_PWR A2
MDCW1 470R2
3

MLXCON2 A3 A3:ORANGE
RTL_LED1# L1 TDP_RJ45-1 RJ45_1
1 TIP_MDC 1 2 BLM18HG601SN1D TIP TDN_RJ45-2 RJ45_2
ACT_LED# 2 RING_MDC 1 2 BLM18HG601SN1D RING RDP_RJ45-3 RJ45_3
L2 RJ45_4
DY DY Morar_SB RJ45_45 RJ45_5
1

C308 C306 RDN_RJ45-6 RJ45_6

4

RJ45_7
SC1000P50V

SC1000P50V

Morar_SB RJ45_78 RJ45_8

2

21.D0010.102 3D3V_LAN_S5 2 R308 1 CONN_PWR_B2 B1

470R2
connector 22 ACT_LED# ACT_LED# B2 B2:YELLOW
10
Morar_SA:21.D0010.102 ACT:YELLOW BLINKING
SKT-RJ45+RJ11-2GP
Morar_SB:20.F0714.002 22.10177.721 Morar_SA:22.10177.721
connector
Morar_SB:20.D0196.102(2nd) Morar_SB:22.10177.721
ME : 22.10177.721
Morar_SB:22.10177.761(2nd)
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LAN CONN
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 23 of 40
A B C D E
 A B C D E

3D3V_S0 CBB_D[0..15] 25
CBB_A[0..25] 25

1
3D3V_S0
R566
4K7R2 3D3V_S0
R567 RN36
1

1
CB_MFUNC2 1 8

2
C546 C547 C548 CB1410_GBRST# 1 2 CB1410_GBRST#_1 CB_MFUNC3 2 7
4 SC1000P50V SCD1U16V SCD1U16V CB_MFUNC4 3 6 4
2

1
C549 CB_MFUNC5 4 5
3D3V_S0 0R2-0
SCD1U16V SRN10K

2
3D3V_S0 VCC_ASKT_S0
1

1
3D3V_S0

1
C550 C551 C552 C553
SC1000P50V SCD1U16V SCD1U16V SC1000P50V C554
2

2
SCD1U16V

1
114
130

102
122
138

126
U59 R568 R569 R570 R571

18
30
44
50

22
42
58
78
94

14
66
86

63

90
6
43KR2J 43KR2J 43KR2J 43KR2J
16,22,28 PCI_AD[31..0]
PCI_AD31 3 125 CBB_REG#

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

GND
GND
GND
GND
GND
GND
GND
GND

GRST# CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC

AUX_VCC

SOCKET_VCC
SOCKET_VCC
AD31 REG#/CCBE3# CBB_REG# 25
PCI_AD30 4 116 CBB_A25 CBB_A25 25

2
PCI_AD29 AD30 A25/CAD19 CBB_A24 CBB_OE#
5 AD29 A24/CAD17 113 CBB_A24 25
PCI_AD28 7 111 CBB_A23 CBB_A23 25 CBB_CE1#
PCI_AD27 AD28 A23/CFRAME# CBB_A22 CBB_RESET
8 AD27 A22/CTRDY# 109 CBB_A22 25
PCI_AD26 9 107 CBB_A21 CBB_A21 25 CBB_CE2#
PCI_AD25 AD26 A21/CDEVSEL# CBB_A20
10 AD25 A20/CSTOP# 105 CBB_A20 25
PCI_AD24 11 103 CBB_A19 CBB_A19 25
PCI_AD23 AD24 A19/CBLOCK# CBB_A18
15 AD23 A18/RFU 100 CBB_A18 25
PCI_AD22 16 98 CBB_A17 CBB_A17 25
PCI_AD21 AD22 A17/CAD16 A_CCLKXX R572 1
17 AD21 A16/CCLK# 108 2 33R2 CBB_A16 25
PCI_AD20 19 110 CBB_A15 CBB_A15 25
3 PCI_AD19 AD20 A15/CIRDY# CBB_A14 3
23 AD19 A14/CPERR# 104 CBB_A14 25
PCI_AD18 24 101 CBB_A13 CBB_A13 25
PCI_AD17 AD18 A13/CPAR CBB_A12
25 AD17 A12/CCBE2# 112 CBB_A12 25 Morar_SB
PCI_AD16 26 95 CBB_A11 CBB_A11 25
PCI_AD15 AD16 A11/CAD12 CBB_A10
38 AD15 A10/CAD9 89 CBB_A10 25
PCI_AD14 39 97 CBB_A9 CBB_A9 25
PCI_AD13 AD14 A9/CAD14 CBB_A8
40 AD13 A8/CCBE1# 99 CBB_A8 25
PCI_AD12 41 115 CBB_A7 CBB_A7 25
PCI_AD11 AD12 A7/CAD18 CBB_A6
43 AD11 A6/CAD20 118 CBB_A6 25
PCI_AD10 45 120 CBB_A5 CBB_A5 25
PCI_AD9 AD10 A5/CAD21 CBB_A4
46 AD9 A4/CAD22 121 CBB_A4 25
PCI_AD8 47 124 CBB_A3 CBB_A3 25
PCI_AD7 AD8 A3/CAD23 CBB_A2
49 AD7 A2/CAD24 127 CBB_A2 25
PCI_AD6 51 128 CBB_A1 CBB_A1 25
PCI_AD5 AD6 A1/CAD25 CBB_A0
52 AD5 A0/CAD26 129 CBB_A0 25
PCI_AD4 53 87 CBB_D15 CBB_D15 25
PCI_AD3 AD4 D15/CAD8 CBB_D14
54 AD3 D14/RFU 84 CBB_D14 25
PCI_AD2 55 82 CBB_D13 CBB_D13 25
PCI_AD1 AD2 D13/CAD6 CBB_D12
56 AD1 D12/CAD4 80 CBB_D12 25
PCI_AD0 57 77 CBB_D11 CBB_D11 25
AD0 D11/CAD2 CBB_D10
16,22,28 PCI_C/BE#[3..0] D10/CAD31 144 CBB_D10 25
PCI_C/BE#3 12 142 CBB_D9 CBB_D9 25
PCI_C/BE#2 C_BE3# D9/CAD30 CBB_D8
27 C_BE2# D8/CAD28 140 CBB_D8 25
PCI_C/BE#1 37 85 CBB_D7 CBB_D7 25
PCI_C/BE#0 C_BE1# D7/CAD7 CBB_D6
48 C_BE0# D6/CAD5 83 CBB_D6 25
28 81 CBB_D5 CBB_D5 25
16,22,28 PCI_FRAME# FRAME# D5/CAD3
29 79 CBB_D4 CBB_D4 25 VCC_ASKT_S0
16,22,28 PCI_IRDY# IRDY# D4/CAD1
31 76 CBB_D3 CBB_D3 25
16,22,28 PCI_TRDY# TRDY# D3/CAD0
R573 33 143 CBB_D2 25
16,22,28 PCI_STOP# STOP# D2/RFU

1
2 PCI_AD25 CARD_IDESL 13 CBB_D1 2
1 2 IDSEL D1/CAD29 141 CBB_D1 25
100R2F 32 139 CBB_D0 CBB_D0 25
16,22,28 PCI_DEVSEL# DEVSEL# D0/CAD27
34 92 CBB_OE# CBB_OE# 25 10KR2
16,22,28 PCI_PERR# PERR# OE#/CAD11
35 106 CBB_WE# 25 R574
16,22,28 PCI_SERR# SERR# WE#/CGNT# CBB_IORD#
16,22,28 PCI_PAR 36 93 CBB_IORD# 25

2
PAR IORD#/CAD13 CBB_IOWR#
3 PCLK_PCM 21 PCI_CLK IOW#/CAD15 96 CBB_IOWR# 25
16,22,28 PCIRST1# 20 RST# WP/IOIS16/CCLKRUN# 136 CBB_WP 25
1

59 RI_OUT#/PME# INPACK#/CREQ# 123 CBB_INPACK# 25

R575 TP106
16 PCI_GNT#0 2 132 CBB_RDY 25
GNT# RDY_IREQ#/CINT#
VCCD0#/SMBDATA/SDATA

10R2 1 133
16 PCI_REQ#0 REQ# WAIT#/CSERR# CBB_WAIT# 25
VCCD1#/SMBCLK/SCLK

CD2/CCD2# 137 CBB_CD2#_1 25

75 CBB_CD1#_1 25
CLK33_PCM12

CD1/CCD1# CBB_CE2#
CE2/CAD10 91 CBB_CE2# 25
1

C555 88 CBB_CE1# CBB_CE1# 25

VPPD0/SLATCH

CE1#/CCBE0#
SC22P50V2JN-1

RESET/CRST# 119 CBB_RESET 25

SPKR_OUT#

134 CBB_BVD2# 25
2

BVD2/SPKR/LED/AUDIO
SUSPEND

BVD1/STSCHG/RI/CSTSCHG 135 CBB_BVD1# 25

117
O2MF6
O2MF5
O2MF4
O2MF3
O2MF2
O2MF1
O2MF0
VPPD1

VS2/CVS2 CBB_VS2# 25
VS1/CVS1 131 CBB_VS1# 25
1

C556
SC10P50V2JN-1 CB1410B0-1-U
2

74
73
72
71
CBUS_SUSPEND70
69
68
67
65
64
61
60
62

Reduce start up noise

CB_SPKR 26
RC1 1 2 43KR3
25 VCCD1# PCM_INTA# R577 1 Check 0 1
25 VCCD0# 2 0R2-0 INT_PIRQG# 16

1
PCM_INTB# R576 1 2 0R2-0 INT_PIRQB# 16
25 VPPD1 CB_MFUNC2 R580
1 25 VPPD0 1
1 2 CB_MFUNC3 R579 1 2 0R2-0 INT_SERIRQ 16,28,29 47KR2
3D3V_S0
R578 10KR2 CB_MFUNC4
CB_MFUNC5
Wistron Corporation

2
Check suspend
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
PM_CLKRUN# 16,22,28,29
Title
CardBus_ENE CB1410
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 24 of 40
A B C D E
 A B C D E

PCMCIA Socket Cardbus I/F

Power switch
CBB_D[0..15] 24
CBB_A[0..25] 24

CBB_IORD# 24
PCH1 CBB_IOWR# 24
CBB_OE# 24 Morar_SB
1 CBB_WE# 24
35 CBB_REG# 24
CBB_D3 2 3D3V_S0
CBB_CD1# CBB_RDY 24
4 36 CBB_WP 24 4

2
CBB_D4 3 CBB_RESET 24
CBB_D11 37 R581
CBB_D5 CBB_WAIT# 24
4 CBB_INPACK# 24 4K7R2
CBB_D12 38 U60
CBB_D6 5

1
CBB_D13 39 CBB_CE1# 24 1 16 2211_SHDN#
CBB_D7 24 VCCD0# VCCD0# SHTDN#
6 CBB_CE2# 24 24 VCCD1# 2 VCCD1# VPPD0 15 VPPD0 24
CBB_D14 40 3 14 VPPD1 24
CBB_CE1# CBB_BVD1# 24 3.3V VPPD1
7 CBB_BVD2# 24 3D3V_S0 4 3.3V VCCOUT 13 VCC_ASKT_S0
CBB_D15 41 5 12
CBB_A10 5V VCCOUT
8 5V_S0 6 5V VCCOUT 11

1
CBB_CE2# 42 7 10
CBB_VS1# 24 GND VPPOUT VPP_ASKT_S0

1
VCC_ASKT_S0 CBB_OE# 9 C557 C558 8 9
CBB_VS2# 24 SCD1U16V OC# 12V
CBB_VS1# 43 SC1U10V3ZY C559 C560

2
CBB_A11 10 SCD1U16V SC1U10V3ZY

2
CBB_IORD# 44 CP2211-1
CBB_A9 11
CBB_IOWR# 45
CBB_A8 12
1

CBB_A17
SC10U10V5ZY-L

46
1

C481 CBB_A13 13
C480 SCD1U16V CBB_A18 47
2

CBB_A14 14
DY
2

CBB_A19 48 PC1
C484 CBB_WE# 15 1 2
SC1000P50V CBB_A20 49
2

CBB_RDY 16
CBB_A21 50 3 4
3 17 3
VPP_ASKT_S0 R582
51
18 CARD-SKT18-U CBB_CD1# 1 2 CBB_CD1#_1 24
52

1
CBB_A16 19
21.H0056.001 0R2-0
1

CBB_A22 53 C561
C482 CBB_A15 20 connector SC270P50V2JN

2
SCD1U16V CBB_A23 54
DY
2

CBB_A12 21 Morar_SA:21.H0056.001
CBB_A24 55
CBB_A7 22 Morar_SB:21.H0056.001 R583
CBB_A25 56
CBB_A6 23 CBB_CD2# 1 2 CBB_CD2#_1 24
CBB_VS2# 57

1
CBB_A16 CBB_A5 24
CBB_RESET 0R2-0 C562
58
CBB_A4 25 SC270P50V2JN

2
CBB_WAIT# 59
CBB_A3 26 DY
CBB_INPACK# 60
CBB_A2 27
CBB_REG# 61
Place close to pin 19. CBB_A1 28
1

CBB_BVD2# 62
C483 CBB_A0 29
DUMMY-C2 CBB_BVD1# 63
CBB_D0 30
CBB_D8 64
CBB_D1 31
2

2 CBB_D9 2
65
CBB_D2 32
CBB_D10 66
CBB_WP 33
Clock AC termination CBB_CD2# 67
33MHz clock for 32-bit 34
68
Cardbus card I/F VCC_ASKT_S0
1

R520 62.10024.131
DUMMY-R2 connector
47K
Morar_SA:62.10024.131
2

Morar_SB:62.10024.601
1

C502
SCD01U16V2KX
2

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCMCA
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 25 of 40
A B C D E
 A B C D E

G21

24 CB_SPKR C491 1 2 CB_SPKR1 1

R514
2
ALC655 AC97 AUDIO CODEC 1 2
GAP-OPEN-PWR
SCD47U10V3ZY 47KR2

R515 C504
16 ACZ_SPKR C492 1 2 ACZ_SPKR1 1 2 AUDIO_BEEP 1 2 AUDIP_PC_BEEP CD_AGND

SCD47U10V3ZY 47KR2 SCD1U16V

DY
DY

1
4 R516 CSD_GND_1 C505 1 2 SC1U10V3ZY CSD_GND_2 R525 1 2 0R3-U 4
CD_AGND
C493 1 2 KBC_BEEP1 1 2 R517 C510
29 KBC_BEEP
SC3900P50V3KX CSD_CD_R_1 C506 1 DY2 SC1U10V3ZY CSD_CD_R_2 R524 1 DY 2 27KR3 CS_CDR CS_CDR 20

2
SCD47U10V3ZY 47KR2 22KR2J
CSD_CD_L_1 C507 1 DY2 SC1U10V3ZY CSD_CD_L_2 R523 1 DY 2 27KR3 CS_CDL CS_CDL 20

1
R521 R526 R522
U58

42
26

13
12

44
43

37

19
20
18
DY DY DY

7
4

1
100KR2 100KR2 100KR2
Morar_SB DY DY ALC655-U
EC131 EC130 EC129
DY DY DY

PHONE
PC-BEEP

LFE-OUT
CEN-OUT

MONO-OUT-R

CD-L
GND
GND

AGND
AGND

CD-GND
CD-R
R587

2
C564 SCD1U16V SCD1U16V SCD1U16V

2
2 1 2 1

SCD47U10V3ZY 10R2
MIC2 22
15,21 ACZ_RST# 11 21 MIC 2 1 MIC_IN MIC_IN 27
RESET# MIC1 C509 SC1U10V3ZY

15,21 ACZ_SYNC 10 36 SOUNDR

AC97_BTCLK SYNC FRONT-OUT-R SOUNDL SOUNDR 27
6 BITCLK FRONT-OUT-L 35 SOUNDL 27
C532
R273 0R2-0 SC1U10V3ZY
1 2 CODEC_XTLSEL 46 24 LINEIN_R 2 1 LINE_IN_R LINE_IN_R 27
XTLSEL LINE-R LINEIN_L
Morar_SB 45 JD0/GPIO0 LINE-L 23 2 1 LINE_IN_L LINE_IN_L 27
0R2-0 R589 C508 SC1U10V3ZY C525 C524
15,21 ACZ_SDATAOUT 2 1 SC1000P50V SC1000P50V
5 41
EPSON 15 ACZ_SDATAIN0 1 2 AC97_SDIN 8
SDOUT SURR-OUT-R
39
3 R510 47R2 SDIN SURR-OUT-L 3
FA-365 20PF
50PPM 27 G1421_MUTE G1421_MUTE
SPDIF
47
48
SPDIFI/EAPD JD1/GPIO1 17
16
C489 27 SPDIF SPDIFO JD2
SC22P50V2JN-1
1 2 AD_XTALOUT 3 15
XTL-OUT AUX-R
2 XTL-IN AUX-L 14
2

FRONT-MIC
DY DY

VREFOUT
X5 R509
C488 X-24D576MHZ-3-U1 1 2

AFILT2
AFILT1
NC#40
NC#33
3 CLK_Audio

VRDA
AVDD
AVDD

VRAD
VREF
SC22P50V2JN-1
VDD
VDD
1

1 2 AD_XTALIN 0R2-0

DY
1
9

25
38

40
33

34
28
27

32
31

30
29
3D3V_S0
AFLT1 C528 SC1000P50V
AFLT2 C527 SC1000P50V
5VA_S0 VRDA C526 1 2 SC1U10V3ZY
SCD1U16V

SCD1U16V
1

C490 C487
SCD1U16V

ALC655_VREF
ALC655_VREF
2

C285

VREFOUT
VREFOUT
C287
SCD1U16V
2

1
1

1
C531 C530
2 C286 C529 SC1U10V3ZY SCD1U16V 2

2
SC1U10V3ZY SCD1U16V
2

*Layout*
POWER GENERATE 5VA_S0
20 mil
VREFOUT 27

U56 DY
1
1

R271 AC97_BTCLK 1 5
28K7R3F A VCC 3D3V_S0
C284
5V_S0 U24 SC22P50V2JN-1 ACZ_RST# 2
2

B R511
1 5 R270 1 2 33R2
2

SHDN# SET 5VA_SETPIN ACZ_BITCLK 15

1 2 3 GND Y 4
2 R513 1 2 33R2 ACZ_BTCLK_MDC 21
GND
1

C281 3 4 10KR3F NC7SZ08-U

SC1U10V3ZY IN OUT
2

G923-330T1U-1 R512 Morar_SB

1

1 2 AC97_BTCLK1
C283 C282
SC1U10V3ZY SC2D2U16V5ZY 0R2-0
2

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
AC'97 CODEC - ALC655
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 26 of 40

A B C D E
 A B C D E

AUDIO OP AMPLIFIER Internal Speaker

SPK1
C293 SPKR_L- 5
4
SPKR_L+ 3
SC220P50V2JN 2
R547 SPKR_R+
C540 10KR2 R288 1
SOUNDL 1 2 SOUND_L1 1 2 HP_L 1 2 SPKR_R- 6
26 SOUNDL 15KR2

1
SC2D2U16V5ZY ETY-CON4-S
4 EC203 EC204 EC206 EC205 4
20.D0122.104

SC680P50V2KX

SC680P50V2KX

SC680P50V2KX

SC680P50V2KX
C294 connector

2
OP+5V 1 2 Morar_SB
SC220P50V2JN 5V_S0
R546 Morar_SA:20.D0122.104
2 C539 10KR2 R289 Morar_SB
R542 SOUND_L2 SOUND_L_OP1 U26B Morar_SB:20.F0714.004

14
1 2 1 2 1 2
DY

4
10KR2 15KR2 TSAHCT125
SC2D2U16V5ZY CH731U-U
Morar_SB:20.D0196.104(2nd)
U25 6 5 3 4
21

G1421_MUTE 26
E Q39 4 3 SPKR_L+
DY PDTA124EU 5
LLINEIN LOUT+
10 SPKR_L- 2 5

7
L_BYPASS LHPIN LOUT- KBC_MUTE 29
B 6 LBYPASS
1 7 14
29 AMP_SHUTDOWN LVDD SE/BTL#
HP/LINE# 16 HP_IN 1 6 SYS_LOUT_IN
LINE OUT
1

1 R278 2 8 11 MUTE_5
SHUTDOWN MUTEIN

2
C
R543 10KR2 2 9
TJ MUTEOUT

1
10KR2 17 1 R276 D27 3D3V_S0 22.10257.001
3

HP-IN GND/HS R558 R559 R560

23 12 100KR2
DY VOL GND/HS
13 100KR2 10KR2 10KR2 SYS_LOUT_IN#=LOW after PLUG-IN LOUT1
2

GND/HS
18 24
DY

1
RVDD GND/HS
1

R_BYPASS 19 9

2
C295 RBYPASS SPKR_R- GND
20 RHPIN ROUT- 15 8 VCC
SC4D7U10V5ZY 21 22 SPKR_R+ 7

GND
26 SPDIF VIN
2

RLINEIN ROUT+
16
6
DY
1

G1421BF3U TC21 SYS_LOUT_IN# 5

25
1
I/P signal level C290 2nd 5VA_S0 SE100U10VM 4
SC4D7U10V5ZY R285 SPKR_L+ 1 2 SPKR_L+1 1 R292 2 SPKR_L_A1 2
2

need +5V level 22R2 3

3 0R2-0 SPKR_R+ SPKR_R+1 SPKR_R_A1 3
1 2 1 R293 2 1
5V_S0 OP+5V 22R2

1
R279 MINDIN10-1-U2
1 2 R275 R274 TC20 SE100U10VM R290 R291

1
0R3-U 2K2R2 10KR2 1KR2 1KR2 C297 C296 EC135 EC212 connector
1

R544
DY

SC680P50V2KX

SC680P50V2KX

Morar_SB:22.10251.031(2nd)
SC330P50V2KX

SC330P50V2KX
C538 C537 C534 C536 10KR2 R287

2
SC10U10V5ZY-L SCD1U16V SCD1U16V 1 2 SOUND_R2 1 2 SOUND_R_OP1 1 2 SYS_LOUT_IN BAV99LT1
2

15KR2 D51

Morar_SA:22.10147.031
Morar_SB:22.10147.031
SC2D2U16V5ZY
C291 Morar_SB

3
SC220P50V2JN Q24 Morar_SB
OUT 3
R545 R1 2 SYS_LOUT_IN#

26 SOUNDR
SOUNDR 1
C535
2 SOUND_R1 1
10KR2
2 HP_R 1
R286

15KR2
2
GND 1
R2
DTC124EKA
IN
LINE IN/MIC IN
SC2D2U16V5ZY
C292
Morar_SB 5VA_S0

SC220P50V2JN

1
R557

MIC_JKIN#_1
100KR2
1
LIN1

2
R556
26 VREFOUT 5
1KR2

2
2

2 C289 2
4
1

SC4D7U10V5ZY
R283 3
Internal Mic
1

2K2R2 1 R554 2 AUD_LINE_R

26 LINE_IN_R 1KR2 6
R282
2

26 MIC_IN R284 1 2 0R2-0 EXT_MIC_IN 1 2 AUD_LINE_L

26 LINE_IN_L 1 R555 2 AUD_LINE_L 2
Morar_SB INT_MIC_IN 1KR2

1
1

10KR2 R552
10KR2 R553
R281 1 2 0R2-0 INT_MIC_IN 300R3 1

1
C541 C542 EC211 EC210
1

SC100P50V2JN-U

SC100P50V2JN-U
Q23 Morar_SA:20.D0012.102 AUDIO-JK30-U

SC330P50V2KX

SC330P50V2KX
3 OUT 22.10088.571

2
C288 MIC_JKIN#_1 2 R1 Morar_SB:20.F0714.002
2

2
2
SC3300P50V2KX IN 1 GND connector
R2 3

Morar_SA:22.10088.571
Morar_SB:22.10088.571
DTC124EKA INT_MIC 1
2 MIC1
2

4
C1
CON2-10-U2 Morar_SB
DY
1
SC1000P50V

connector
20.D0012.102
R8
1 2

0R3-U

Morar_SB
1 1
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Audio AMP and Jack
Size Document Number Rev

MORAR SB
Date: Saturday, May 28, 2005 Sheet 27 of 40

A B C D E
 A B C D E

3D3V_S0

1
C470 C473 C474

SCD1U16V

SCD1U16V

SCD1U16V
2

2
4 4

16,22,24 PCI_AD[31..0]

MINI1
125
1 2
3D3V_S0
3 4
5 6

2
7 8
9 10 PIN 3-16 : LAN RESERVE R501
80211_ACTIVE 11 12 10KR2
29 WIRELESS_EN 13 14
15 16

1
INT_PIRQF# 17 18 3D3V_S0 WLAN_LED# 13
5V_S0
3D3V_S0 19 20 INT_PIRQF# 16
21 22

2
TP105 TPAD28 23 24
25 26 R500
3 PCLK_MINI PCIRST1# 16,22,24
27 28 3D3V_S0 10KR2
3 29 30 3
16 PCI_REQ#1 PCI_GNT#1 16
31 32

1
PCI_AD31 33 34 PME#_MINI TPAD28 TP101

3
PCI_AD29 35 36 BT_COEX1 D
37 38 PCI_AD30 TPAD28 TP100 80211_ACTIVE 1 Q36
PCI_AD27 39 40 G 2N7002
PCI_AD25 41 42 PCI_AD28 S

2
TP104 TPAD28 BT_COEX2 43 44 PCI_AD26
PCI_C/BE#3 45 46 PCI_AD24 R488
16,22,24 PCI_C/BE#3
PCI_AD23 47 48 MOD_IDSEL 1 2 PCI_AD21
49 50
PCI_AD21 51 52 PCI_AD22 10R2
PCI_AD19 53 54 PCI_AD20
55 56 PCI_PAR 16,22,24
PCI_AD17 57 58 PCI_AD18

3
PCI_C/BE#2 59 60 PCI_AD16 D
16,22,24 PCI_C/BE#2
61 62 WIRELESS_EN 1 Q35
16,22,24 PCI_IRDY# DY 63 64 PCI_FRAME# 16,22,24 G 2N7002
R498 1 2 10KR2 MINI_CLKRUN# 65 66 S
PCI_TRDY# 16,22,24

2
16,22,24 PCI_SERR# 67 68 PCI_STOP# 16,22,24
69 70
16,22,24 PCI_PERR# 71 72 PCI_DEVSEL# 16,22,24
PCI_C/BE#1 73 74
16,22,24 PCI_C/BE#1
PCI_AD14 75 76 PCI_AD15
77 78 PCI_AD13
PCI_AD12 79 80 PCI_AD11 Morar_SB
PCI_AD10 81 82 Q37
83 84 PCI_AD9 3 OUT
PCI_AD8 85 86 PCI_C/BE#0 2 R1
2 PCI_C/BE#0 16,22,24 29 WLAN_TEST_LED 2
16,22,24,29 PM_CLKRUN# 1 R499 2 PCI_AD7 87 88 IN 1 GND
0R0402-PAD 89 90 PCI_AD6 R2
PCI_AD5 91 92 PCI_AD4 DTC124EKA
93 94 PCI_AD2
PCI_AD3 95 96 PCI_AD0
5V_S0 97 98
PCI_AD1 99 100 INT_SERIRQ 16,24,29
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
Morar_SA:62.10032.001
123 124
126 Morar_SB:62.10032.001
PCIMODEM124A1U1 Morar_SA:62.10032.031(2nd)

62.10032.001
connector

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

MINI-PCI
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 28 of 40
A B C D E
 A B C D E

3D3V_AUX_S5 KCOL[1..16] 30
KROW[1..8] 30 3D3V_AUX_S5 5V_S0
KBC_XO 1 2 C221
3D3V_AUX_S5 SC8D2P50V2CC

1
L3 3D3V_S0
4 4

3
C218 C219 C209 C222 C195 C208 1 2 3D3V_KBC_AUX_S5

3
4
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V BLM11P600S X2 RN26

SCD1U16V
2

2
1
X-32D768KHZ-12-U

KBC_SDA2
RN27

KBC_SCL2
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8

BAT_SDA
BAT_SCL
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9

2
1

1
C207 KBC_XI 1 2 C220 Q18

G
C206 SC8D2P50V2CC SRN10KJ 2N7002 SRN10KJ

2
1
SCD1U16V SCD1U16V 3 2

3
4
123
136
157
166

161

153
154

163
164
169
170

160
158
16
34
45

95

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

71
72
73
74
77
78
79
80

1
U14

S
G
KBC_SCL2 SMBC_G792

VCCA

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

SCL1
SDA1
SCL2
SDA2

XCLKO
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCBAT

XCLKI
KBC_SDA2 SMBD_G792 SMBC_G792 19
3 2 SMBD_G792 19
Q19

S
2N7002
15 LPC_LAD[0..3]
LPC_LAD0 15 155
LPC_LAD1 LAD0 GPIO29 MATRIXID2# 31 3D3V_AUX_S5
14 149
LPC_LAD2 13
LAD1
LAD2
KB Matrix GPIO28
GPIO27 148
MATRIXID1# 31
PRE_CHG 38
LPC_LAD3 10 119
LAD3 LPC GPIO26 BLT_BTN# 30

2
GPIO25 118 CHG_ON# 38
15 LPC_LFRAME# 9 109 R192
LFRAME# GPIO24 A20 AD_OFF 39
3 PCLK_KBC 18 LCLK GPIO23 108 100KR2
16,24,28 INT_SERIRQ 7 107 E51TXD TP58 TP59
SERIRQ GPIO22 E51RXD TP61
106

1
GPIO21 E51CS#
GPIO20 105
KBCBIOS_RD# 150 86 STDBY_LED# 13
31 KBCBIOS_RD# KBCBIOS_WE# RD# GPIO19 TP54
31 KBCBIOS_WE# 151 WR# GPIO18 85
KBCBIOS_CS# 173 75 INTERNET# 30
TP64 31 KBCBIOS_CS# MEMCS# GPIO17
152 IOCS# GPIO16 70 MAIL# 30
69 3D3V_AUX_S5
31 KBC_D[0..7] GPIO15 PM_SLP_S4# 16,37
KBC_D0 138 63 4S1P_I 38
KBC_D1 D0 GPIO14
139 D1 GPIO13 62 PM_SUS_STAT# 16
KBC_D2 140 55 TP56
KBC_D3 D2 GPIO12 R232
141 D3 GPIO11 54 CAP_LED# 13
3 KBC_D4 144 48 FRONT_PWRLED# 13 BAT_IN# 2 1 3
KBC_D5 D4 GPIO10 TP62 100KR2
145 D5 GPIO09 22
KBC_D6 146 21 KBC_MUTE 27
KBC_D7 D6 GPIO08 KBC_BB_ENABLE#
147 D7 GPIO07 20 KEY5# 30 2 R176 1
12 FAN3FB 100KR2
GPIO06 FAN3PWM
124 11
D50 31 A0 A0 X-bus GPIO05

15 KA20GATE_1 6 1 KA20GATE
31
31
31
31
A1
A2
A3
A4
125
126
127
128
131
A1
A2
A3
A4
ROM KB3910 GPIO04
GPIO03
GPIO02
GPIO01
8
6
5
4
3
WIRELESS_BTN#

KEY4# 30
30

BAT_IN# 39
39
39
BAT_SCL
BAT_SDA
2
1
RN25
3
4

KBRCIN# 31 A5 A5 GPIO00
15 KBRCIN#_1 5 2 132 SRN8K2J
31 A6 A6 3D3V_S5
31 A7 133 A7 GPIO0F 41
143 28 ECSMI# ECSMI# 16
ECSCI# 31 A8 A8 GPIO0E PM_PWRBTN#
4 3 31 A9 142 A9 GPIO0D 27 WIRELESS_EN 28 2 1
16 ECSCI#_1 135 25 R196 10KR2
31 A10 A10 GPIO0C PM_CLKRUN# 16,22,24,28
CH731U-U 134 24 FPBACK 13
31 A11 A11 GPIO0B
Morar_SB 31 A12 130 A12 GPIO0A 23 NUM_LED# 13
KBC_SLP_WAKE 2
31 A13 129
121
A13
98 BLUETOOTH_EN 21
3D3V_S5 R233 10KR2 DY
1
31 A14 A14 GPIO1F PRE_CHG
31 A15 120 A15 GPIO1E 97 DC_BATFULL# 13 2
DY
1

1
113 94 BLT_LED# 13 R229 10KR2
31 A16 A16 GPIO1D R230
31 A17 112 A17 GPIO1C 93 WLAN_TEST_LED 28
104 92 100KR2
31 A18 A18 GPIO1B MAIL_LED# 13
103 91 CHARGE_LED# 13 C223
A19 GPIO1A 3D3V_S5

2
168 VCC3VSB

SC1U10V3ZY
5V_S0 GPIOI2D PM_PWRBTN#
30 TDATA_5 117 PSDAT3 GPIO2F 175 2 1

1
RN19 116 171 3D3V_S5 R181 10KR2
30 TCLK_5 PSCLK3 GPIO2E AMP_SHUTDOWN 27
8 1 115 165 KBC_PCIRST#1 R249 2
7 2 114
PSDAT2 PS/2 GPIO2C
162 BL_ON 0R2-0
BL_ON 7
PLT_RST1# 7,16,18

2
PSCLK2 GPIO2B CHK_PW#_KBC
6 3 111 PSDAT1 GPIO2A 156
5 4 110 PSCLK1 TP102
SRN10K-2

1
5V_S0

IN
2
DY 2

BATGND

2
ECRST#
GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6
GPWU7

ECSCI#
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0

AGND
RN18 3D3V_AUX_S5 Q16 R561
DY

GND
GND
GND
GND
GND
GND

R1
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
1 4 TDATA_5 DTC124EKA 10KR2

R2
2 3 TCLK_5

2
43
40
39
38
37
36
33
32

2
26
29
30
44
76
172
176

99
100
101
102
1
42
47
174

81
82
83
84
87
88
89
90

19
31

96
159

17
35
46
122
137
167

1
SRN10KJ CHANGE TO 71.03910.B0G
DY

3
3D3V_AUX_S5 R197
BRIGHTNESS_DA

GND

OUT
GMODULE_RST#

AC_VOL_SENSE

KBC_BB_ENABLE#
3D3V_AUX_S5 10KR2
RSMRST#_KBC

BRIGHTNESS_PWM

1
EC_RST#
BAT_SENSE

ECSCI#

2
KBC_PME#

R194 KBC_PME#
26 KBC_BEEP TP63 TP103 TP57 TP55 ICH_PME# 16,22
1

10KR2
1

R223
AD_IA

R226 R224 R234 16 ECSWI#

2
R235
DUMMY-R2

TP53
DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2

1 2
R198 0R2-0
2

1
A1 1 2
DY
2

16 PM_PWRBTN#

2
A4 C210
A5 16,32 RSMRST#_KBC AD+ BT+ Q15 R199
GAP-OPEN 1 2 1

SC10U10V5ZY-L
RSMRST# 19

2
FAN3PWM 19 S5_ENABLE CH3906 10KR2
13 BRIGHTNESS 1 R195 2 G18
FAN3FB 0R0402-PAD

3
1

DY DY
1

16,18,32,37 PM_SLP_S3#
1

R227 R225 R228 R231 R179 R177

10KR2 R236 30 KBC_PWRBTN# 100KR2F 560KR2F
DUMMY-R2

DUMMY-R2

10KR2 10KR2 38 AC_IN#

2

30 KBC_LID# KBC_SLP_WAKE AC_VOL_SENSE

2

16 KBC_SLP_WAKE BRIGHTNESS 1 BAT_SENSE

2 Place near K/B Connector (TOP side)
2

0R2-0 R193
DY
DY DY
1

TP60
A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable R180 R178
A4 for DMRP==>High=Disable,Low=Enable 13K3R2F 100KR2F
1 A5 for EMWB==>High=Enable,Low=Disable 1
GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended) 21 USB_PWR_EN#
2

GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended)

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
KBC ENE
Size Document Number Rev
Custom SB
MORAR
Date: Friday, June 24, 2005 Sheet 29 of 40
A B C D E
 A B C D E

POWER BUTTON 3D3V_AUX_S5

Cover Up Switch 3D3V_AUX_S5

1
Morar_SA:20.D0012.102
R10 R16
10KR2 47KR2 Morar_SB:20.F0714.002
Power LID1

2
R11 3
POWERSW 1 2 KBC_PWRBTN# 29 29 KBC_LID# 1 R17 2 LID_SW 1
1 PWR1 2 100R2F 2

1
470R2 4

1
4 5 EC10 C3 4
SC1000P50V C2 SC1000P50V CON2-10-U2

2
SCD1U16V connector
3 4
DY 20.D0012.102

2
SW-TACT-34-U2 3D3V_S5

Buttons 62.40009.241
connector RN3 RN2
ME : 62.40009.241 1 8 MAIL#_1 1 8 5V_S0
(ALL 11 PCS) 2
3
7
6
INTERNET#_1
KEY4#_1
KEY5#_1
INTERNET#_1
2
3
7
6
MAIL#
KEY4#
KEY5#
29
29
29
TOUCH PAD 5V_S0
4 5 4 5
INTERNET# 29 Morar_SA:20.K0063.012
SRN10K-2 SRN470J-1

1
2
RN13 Morar_SB:20.K0174.012

1
EC12 EC14 EC15 EC13 EC71 C145
DY

2
Mail Internet P1 P2 SCD1U16V SC1U10V3ZY TPAD1

2
SRN10KJ
DY DY DY DY 14

4
3
MAIL#_1 INTERNET#_1 KEY4#_1 KEY5#_1

SC100P50V2JN-U

SC100P50V2JN-U

SC100P50V2JN-U

SC100P50V2JN-U
12
1 MAIL1 2 1 NET1 2 1 P1 2 1 P2 2 11
29 TDATA_5 1 R114 2 100R2F TP_DATA 10
5 5 5 5 29 TCLK_5 1 R113 2 100R2F TP_CLK 9
TP_SCROLL_UP 8
3 4 3 4 3 4 3 4 1 SCRL1 2 EC73 EC74 7
SW-TACT-34-U2 SW-TACT-34-U2 SW-TACT-34-U2 SW-TACT-34-U2 TP_RIGHT

SC47P50V2JN

SC47P50V2JN
Morar_SB 6

1
5 TP_SCROLL_RIGHT 5
62.40009.241 62.40009.241 62.40009.241 62.40009.241 TP_SCROLL_UP 4
connector connector connector connector 3 4 TP_SCROLL_LEFT 3

2
3 SW-TACT-34-U2 TP_SCROLL_DOWN 2 3

62.40009.241 TP_LEFT 1
connector 13
BlueTooth ON/OFF Wireless ON/OFF TP_SCROLL_LEFT TP_SCROLL_RIGHT
1 SCRL2 2 1 SCRL3 2
connector
BLUE2 WLAN1 5 5 20.K0063.012
BLT_BTN#_1 1 2 WIRELESS_BTN#_1 1 2 ME : 62.40082.081
3 4 3 4
3 4 3 4 (2 PCS) SW-TACT-34-U2 SW-TACT-34-U2
PUSH-SW89 PUSH-SW89
WIRELESS_BTN# 62.40009.241 62.40009.241
BLT_BTN# connector connector connector TP_SCROLL_DOWN connector TP_LEFT TP_RIGHT
1

Morar_SA:22.40082.081 1 SCRL4 2 1 LEFT1 2 1 RIGHT1 2

EC207 EC209
SCD1U16V SCD1U16V Morar_SB:62.40009.331 3D3V_S5 5 5 5
2

DY DY RN34
SRN10KJ 3 4 3 4 3 4
1 R550 2 470R2 WIRELESS_BTN#_1 1 4 SW-TACT-34-U2 SW-TACT-34-U2 SW-TACT-34-U2
29 WIRELESS_BTN# 1 R549 2 470R2 BLT_BTN#_1 2 3
29 BLT_BTN# connector 62.40009.241 connector 62.40009.241 connector 62.40009.241

EMI Bypass cap.

Internal KeyBoard CONN KROW[1..8] 29
KCOL[1..16] 29
ERC5
Morar_SB TP_RIGHT
EC72
1 2
SC1000P50V Morar_SB

2 KROW7 2
Pin1 ==>*R01 1 8
Pin2 ==>*R02 KCOL11 2 7
KB1 KCOL12 3 6 EC60 SC1000P50V
1 25 26
Pin3 ==>*R03 KROW8 4 5 TP_SCROLL_RIGHT 1 2
NC#26 KROW1 Pin4 ==> C01
C01 1
........ 2 KROW2 Pin5 ==> C02 SRC150P
C02 KROW3 ERC3
C03 3 Pin6 ==> C03
4 KCOL1 KCOL5 1 8
R01 KCOL2 Pin7 ==>*R04 KCOL6 EC59 SC1000P50V
R02 5 2 7
R03 6 KCOL3 Pin8 ==> C04 KCOL7 3 6 TP_SCROLL_UP 1 2
7 KROW4 Pin9 ==> C05 KCOL8 4 5
C04 KCOL4
R04 8 Pin10 ==> C06
9 KCOL5 SRC150P
R05 KCOL6 Pin11 ==> C07 ERC2 EC61 SC1000P50V
R06 10
11 KCOL7 Pin12 ==> C08 KCOL2 1 8 TP_SCROLL_LEFT 1 2
R07 KCOL8 KCOL3
R08 12 Pin13 ==> C09 2 7
13 KCOL9 KROW4 3 6
R09 KROW5 Pin14 ==>*R05 KCOL4
C05 14 4 5
15 KCOL10 Pin15 ==> C10 EC62 SC1000P50V
R10 KROW6 SRC150P TP_SCROLL_DOWN
C06 16 Pin16 ==>*R06 1 2
17 KROW7 ERC4
C07 KCOL11
Pin17 ==>*R07 KCOL9
R11 18 1 8
19 KCOL12 Pin18 ==> C11 KROW5 2 7
R12
C08 20 KROW8 Pin19 ==> C12 KCOL10 3 6 EC58 SC1000P50V
21 KCOL13 Pin20 ==>*R08 KROW6 4 5 TP_LEFT 1 2
R13 KCOL14
R14 22 Pin21 ==> C13
23 KCOL15 SRC150P
R15 KCOL16 Pin22 ==> C14 ERC1
R16 24
1 25 Pin23 ==> C15 KROW1 1 8 1
NC#25 KROW2
NC#27 27 Pin24 ==> C16 2 7
KROW3 3 6
Pin25 ==> NC KCOL1 4 5
connector Wistron Corporation
SRC150P 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
20.K0090.025 ERC6 Taipei Hsien 221, Taiwan, R.O.C.
KCOL13 1 8
Morar_SA:20.K0090.025 KCOL14 2 7 Title
KCOL15 3 6
Morar_SA:20.F0736.005 KCOL16 4 5
BUTTONs / KB / TOUCHPAD
Size Document Number Rev
Morar_SA:20.D0197.103(2nd) SRC150P A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 30 of 40
A B C D E
 5 4 3 2 1

KBC_D[0..7] 29

29 KBCBIOS_WE#
29 KBCBIOS_RD#
29 KBCBIOS_CS#
D A18 29 D
A17 29
3D3V_AUX_S5 A16 29

1
C475 U53
SCD1U16V

32

22
24
31

30
2

2
CE#
OE#
WE#

A18
A17
A16
VDD
29 KBC_D0 13 DQ0 A15 3 A15 29
29 KBC_D1 14 DQ1 A14 29 A14 29
29 KBC_D2 15 DQ2 A13 28 A13 29
29 KBC_D3 17 DQ3 A12 4 A12 29
29 KBC_D4 18 DQ4 A11 25 A11 29
29 KBC_D5 19 DQ5 A10 23 A10 29
29 KBC_D6 20 DQ6 A9 26 A9 29
29 KBC_D7 21 DQ7 A8 27 A8 29

VSS

A0
A1
A2
A3
A4
A5
A6
A7
SST39VF040-70-1

16

12
11
10
9
8
7
6
5
(SOCKET) 62.10002.032 - (IC)72.39040.H03 IN DIP,SMT
C C

29 A0
29 A1
29 A2
29 A3
29
29
A4
A5
ROM SIZE MAX. 512KBYTE
29 A6
29 A7

3D3V_S0

PLCC32 Socket P/N:

SSKT3262.10002.032
DY SSKT32 62.10005.032
2
1

RN4
SRN10KJ
3
4

B B

SW1
PH at ICH6M 1 8
16 CHK_PW#
2 7

29 MATRIXID1# 3 6
Morar_SB:Can not use in Board ID
29 MATRIXID2# 4 5

SW-2184LPSTR
connector
1

62.40059.001
EC24 Board ID
SC1000P50V
2

DY 3D3V_S0
1

1
R144 R145 R147
10KR2 DUMMY-R2 DUMMY-R2

Planar ID(2,1,0)
2

2
Keyboard matrix ( from vendor ) PCB_VER0
16 PCB_VER0 PCB_VER1
SA: 0, 0, 0
A 16 PCB_VER1 A
16 PCB_VER2
PCB_VER2 SB: 0, 0, 1
US Jap Eur Other
Wistron Corporation
1

1
R143 R141 R148
SC: 0, 1, 0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DUMMY-R2 10KR2 10KR2 SD: 0, 1, 1 Taipei Hsien 221, Taiwan, R.O.C.
Low Bit MATRIXID1# 1 1 0 0 DY -1: 1, 0, 0 Title
2

-2: 1, 0, 1 BIOS ROM

2

High Bit MATRIXID2# 1 0 1 0

Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 31 of 40

5 4 3 2 1
 Run Power
Morar_SB

DCBATOUT Q10
5V_S0
U15
5V_S5
PWRGD for NB and SB
C211
TP0610K-U 1 2 1 8 3D3V_S0
S D
R110 2 S D 7
10KR2 SCD1U16V 3 S D 6
1 2RUN_POWER1 2 3 RUN_POWER_ON 4 5

D
G D

1
C144 R111 D13 AO4422 R438
SCD1U50V3ZY 330KR2 MMGZ5242B 3D3V_S0 3D3V_S5 1KR2
U7

G
1
1 8

2
S D
2 S D 7
R108 3 S D 6
1 2RUN_POWER2 4 G D 5 3,34 6218_PGOOD
R440 1 2 0R2-0 VGATE_PWRGD 7,16

1
330KR2
R109 AO4422
1KR2

PM_SLP_S3 2
3D3V_S0
PWRGD to Turn on CPU_Core_Power
Morar_SB
Q9
3 OUT 1D05V_S0
2 R1
16,18,29,37 PM_SLP_S3#

1
IN 1 GND

1
R2 R346 R350
DTC124EKA 10KR2
1KR2

2
1
R354 Q28

2
CPUCORE_ON 34
3 OUT
1KR2 2 R1
IN 1 GND
Morar_SB R2

3
DTC144EKA
1 Q29
5V_S5 PMBS3904-1-GP

2
1
R353
1

R255 100KR2
10KR2

2
Morar_SB
2
2

16,29 RSMRST#_KBC 1 Q21

CH3906
3
1

R254
10KR2 Aux Power
3D3V_AUX_S5
2

5V_S5 3D3V_AUX_S5 3D3V_AUX_S5

D22
C240
5V_S5_G913

SC22P50V2JN-1
1 2 Rx

1
1
CH521S-30 R248
5V_AUX_2951 16K5R2F

2
D21 U18 Output = 3.3V

2
1 2 1 5 3D3V_G913_SET output=1.25(1+(Rx/Ry))
SHDN# SET
2 GND
CH521S-30 3 4
IN OUT

1
C241 C239 C242 C243 C438 R247
DY

1
SC1U10V3ZY

SC1U10V3ZY

SC1U10V3ZY
G913C-U 10KR2F-U
C258 DCBATOUT

DUMMY-C3

SC10U10V5ZY-L
1 2
DY Ry

2
SCD1U16V 2
U21
1

C256 C257 1 8
OUT INPUT
SC1U10V3ZY

2 SENSE FB 7
1

SCD1U16V 3 6 <Core Design>

2

SD 5V/TAP C259 C260

4 GND 100mA ERROR 5
SC1U50V5ZY
2

LP2951ACM DUMMY-C5
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

Taipei Hsien 221, Taiwan, R.O.C.

Title

RUN POWER and 3D3V_AUX_S5

Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 32 of 40
 A B C D E

TPS5130
CPU_CORE ISL6218CV
3D3V/5V/1D05V/2D5V
VID Setting Output Signal Input Signal Output Signal
H_VID0
VID0(I / 1.05V)
6218_PGOOD
H_VID1 PGOOD(OD / 3.3V) SHUTDOWN_S5 FOR
VID1(I / 1.05V) SS_STBY1(I / 5V) 5V
TPS5130_PWRGD
4 H_VID2 SHUTDOWN_S5 FOR PGOUT(OD / 5V) 4
VID2(I / 1.05V) SS_STBY2(I / 5V) 3.3V
H_VID3 PM_SLP_S3#
VID3(I / 1.05V) SS_STBY3(I / 5V) FOR
H_VID4 Output Power 1.05V
VID4(I / 1.05V)
PM_SLP_S3#
H_VID5 STBY_LDO(I / 5V) FOR
VID5(I / 1.05V) VCC_CORE (27A) 1.8V Output Power
VCC_CORE(O)

DCBATOUT_5130 3D3V (6A)

Input Signal STBY_VREF5(I / 28V) 3D3(O)

CPUCORE_ON EN(I / 3.3V) DCBATOUT_5130

STBY_VREF3.3(I / 28V) 5V (6A)
5V(O)
PM_DPRSLPVR DRSEN(I / 3.3V)
Input Power 1D05V (5.2A)
1D05V(O)
PM_STPCPU# DSEN# (I / 3.3V) DCBATOUT
VIN (I / 28V)
3 3
2D5V (3.5A)
5V_S5 2D5V (O)
REG5V_IN(I / 5V)
Voltage Sense
5V_AUX_S5
VCC_CORE_S0 VSEN(I / 1.55V / 1.35V) 5V_AUX_S5

5V_S0
For PGOUT
Input Power

DCBATOUT VCC(I) ISL6227

1D8V/1D5V
5V_S0 VCC(I) Input Signal Output Signal

PM_SLP_S4# CPUCORE_ON
PG1
EN1 (I)
CPUCORE_ON
2
PG2/REF 2
Charger Max8725 PM_SLP_S3#_ICH
EN2 (I)

Input Signal Output Signal

CHGON#/OFF BT+SENSE Input Power Output Power
ICTL BATT
1D8V_S3 (6A)
BT_TH AC_IN 1D8V (O)
PKPRES ACOK 5V_S5
VCC (I)

1D5V_S0 (6A)
Input Power Output Power 1D5V (O)

AD+ BT+
ACIN VOUT (O)

DCBATOUT Adapter
VOUT (O)
Input Signal Output Signal
AD_OFF DC_IN+
1 (I) (O) <Core Design> 1

Wistron Corporation
Input Power Output Power 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
AD_JK AD+
VCC(I) VCC(O) Title

5V_AUX_S5 Power Diagram

VCC(I) Size Document Number Rev
A3
MORAR SB
Date: Friday, June 24, 2005 Sheet 33 of 40
A B C D E
 A B C D E

DCBATOUT_6218
Morar_SB

SC10U35V0ZY-L

SC10U35V0ZY-L

SC10U35V0ZY-L

SC10U35V0ZY-L
1

1
SCD1U50V3ZY
DCBATOUT 5V_S0
DCBATOUT_6218 C301 C305 C302 C303 EC151 TC22
SE100U25VM-1-U

2
L23
DY

1
1 2 C317
4 SC4D7U10V5ZY 4

2
1
Morar_SB BLM41PG600-GP
5V_S0 R319

2
4D7R3

1
D8

1
R318

2
BAT54-1

5
6
7
8

5
6
7
8
R330 0R2-0
10R3 6217_VBAT

D
D
D
D

D
D
D
D
2
2

3
6217_VDD VCC_CORE_S0
C319 AO4422 AO4422

1
SCD1U50V3ZY CORE_AGND U27 U28

G
S
S
S

G
S
S
S
C331 C318 2nd 2nd

4
3
2
1

4
3
2
1
SC1U10V3ZY CORE_AGND SCD33U16V3ZY

2
C30 78.33491.4B1
SCD027U50V3KX 1 2 CORE_AGND U34 3K83R3F-2-GP
L9
R331
R351 R329 1 VDD VBAT 38 1 2
100KR2F 1 2 1 2 6217_DAC 2 37 6217_ISEN1 1 2
CORE_AGND 1K21R2F 6217_DSV DACOUT ISEN1 6217_PHASE1 L-D56UH-U
64.10035.6D1 3 36
DSV PHASE1 DY

1
243KR3F 1 2 R328 6217_FSET 4 35 6217_UG1
0R2-0 FSET UG1
1 2 R31 6217_PWRCH 5 N/C BOOT1 34 6217_BOOT1 R310

1
1KR2 1 2 R327 6217_EN# 6 33 0R2-0
32 CPUCORE_ON 0R3-U 1 EN VSSP1
16 PM_DPRSLPVR 2 R349 6217_DRSEN 7 DRSEN LG1 32 6217_LG1 D34 TC6

5
6
7
8
0R3-U 1 2 R326 6217_DSEN# 8 31 ST470U2D5VDM-LGP
DY

2
3,16 PM_STPCPU# DSEN# VDDP SSM34A

5
6
7
8
D
D
D
D
H_VID0 9 30 U33
5 H_VID0 VID0 N/C

D
D
D
D
H_VID1 10 29 C2_SB:Change R100 to U29
DY

2
5 H_VID1 H_VID2 VID1 N/C
5 H_VID2 11 VID2 N/C 28 debug Core power
3 H_VID3 12 27 2nd 2nd C311 3
5 H_VID3 H_VID4 VID3 N/C SC1000P50V
5 H_VID4 13 VID4 N/C 26

G
S
S
S
H_VID5 14 25 VCC_CORE_S0
5 H_VID5 PH 10K P.45 VID5 N/C

G
S
S
S
15 24

4
3
2
1
3,32 6218_PGOOD 6217_EA+ PGOOD VSEN 6217_DRSV
16 23

4
3
2
1
6217_COMP EA+ DRSV 6217_STV
17 COMP STV 22
6217_FB 18 21 6217_OCSET
6217_SOFT FB OCSET
19 20
SOFT VSS DY
1

1
1

R325 TC5 TC2 TC1 TC7

1

ST470U2D5VDM-LGP
ST330U3VDM-1-GP
R324 ISL6218CV-T G1
DY

2
ST330U3VDM-1-GP

ST330U3VDM-1-GP
1K8R3F C328 1 2
SCD022U16V
2

6K04R3F GAP-CLOSE
2

C329
DY CORE_AGND G5
SC470P50V2KX 1 2
Morar_SB
GAP-OPEN-PWR
1

G3
C327 R323 1 2 Morar_SB
DUMMY-C3 15KR3F
GAP-OPEN-PWR R317 R25 R26
G2 1 2 1 2 1 2
1 2

1 2
2

54K9R3F 40K2R3F 80K6R3F

IMVP IV C330 GAP-OPEN-PWR 12.4uA/0.87/0.5 = 28.54uA
1

1
G4
2

Load Line Slope :3mR SC2200P50V2KX R316 C315 C29

2
1 2
DY Rds(on) *Io = Isen * Rsen 2
25A*3mV/A=> 75mV

2
174KR3D

SC1800P50V3KX

SC680P50V2KX
GAP-OPEN-PWR (5m/2)*25A=28.54uA*Rsen
Idroop = 75mV / 6.04K = 12.4uA
2
1

DY R33 = 2.18K ~ 2.15K

C326 CORE_AGND
SCD015U50V3KX R321
VCC_CORE_S0
12

3K57R3F
1

R322 CORE_AGND
DY
2

2K21R3F C316
SC1U10V3ZY
2
2

VCC_CORE_S0
1D05V_S0
CORE_AGND

1
R348 R344 R342 R341 R338 R336

DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2
2

2
H_VID0
H_VID1
1. U12,U14:AO4422 84.04422.037 H_VID2
U13,U15:AO4430 84.04430.B37 H_VID3
H_VID4
1 R100:3K83R2F H_VID5 1

2. U12,U14:IRF7413 84.07413.037
1

1
R347 R345 R343 R340 R339 R337
U13,U15:IRF7832-U 84.07832.037 Wistron Corporation
DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2

DUMMY-R2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R100:2K43R2F Taipei Hsien 221, Taiwan, R.O.C.
2

2
Title

VCC_CORE
Size Document Number Rev
A3
MORAR SB
Date: Friday, May 27, 2005 Sheet 34 of 40
A B C D E
 A B C D E

Morar_SB:OCP=6.96A
For 1.05V
SETTING=1.0515V R387
C367
1D05V_PWR TI TPS5130 for 5V, 3.3V, 1.05V and 2.5V(LDO) DCBATOUT DCBATOUT_5130
R418
DCBATOUT_5130 G31
R50
1
330R3F
2 1 2
(5V=>CH1 , 3D3V=>CH2 , 1D05V =>CH3) OCP_5V 1 2 1 2
1 2 SC5600P50V3KX 120KR3F
78.56224.2B1 5130_TRIP1 GAP-CLOSE-PWR
10KR3F 1 R388 2 C399 G29

1
5130_AGND 64.10025.651 1 2
R49 2K37R3F-L-GP
SCD1U50V3ZY GAP-CLOSE-PWR
2KR3F G28
4 64.20015.651 close to IC close to IC 1 2 4
1 2

5130_5V_LDO Morar_SB OCP=8.56A

C365
For 5V 5V_PWR 5130_5V_LDO GAP-CLOSE-PWR

2
SC3900P50V3KX 5130_INV3 SETTING=5.008V R416 C397 G30
D12 R419 DCBATOUT_5130
1 2 1 2 OCP_3.3V 1 2
2

5130_FB3 R415 1 2
330R3F SC5600P50V3KX BAT54-1
1 2 GAP-CLOSE-PWR

2
64.33005.551 R417 78.56224.2B1 83.00054.L03 5130_TRIP2 14K3R3F

1
For 3V 10K2R2F 1 2 D11 C400
3D3V_PWR 5130_AGND 64.10225.6D1 TC9

3
BAT54-1

1
SETTING=3.3V R398 C395 SE100U25VM-1-U

2
1 2 1 2 R414 49K9R2F 5130_LH1 83.00054.L03 SCD1U50V3ZY
R55 Morar_SB
1 2 330R3F SC5600P50V3KX 2KR3F close to IC C398 close to IC

3
64.33005.551 R403 78.56224.2B1 64.20015.651 1 2 5130_LL1 5130_LL1 36 G12

1 2
10K2R2F 1 2 Morar_SB:OCP=10A 1 2
1

5130_AGND 64.10225.6D1 C396 SCD1U50V3ZY

R54 SC3900P50V3KX 5130_INV1 5130_OUT1U 5130_OUT1U 36 DCBATOUT_5130 GAP-CLOSE
29K4R2F 5130_OUT1D 1 R389
5130_OUT1D 36 OCP_1.05V 2

2
2KR3F 5130_FB1 16K2R3F 5130_AGND
64.20015.651
close to IC 5130_TRIP3
1 2

5130_TRIP1 C369
DCBATOUT_5130
C383 5130_INV2 5130_TRIP2
SC3900P50V3KX SCD1U50V3ZY
2

5130_FB2 5130_FLT
close to IC

1
5130_FLT 5130_OUT2D 5130_OUT2D 36
C101 5130_INV1
3 SCD01U16V2KX 3
close to IC

2
T(soft)=1.736ms U41

48
47
46
45
44
43
42
41
40
39
38
37
5130_5V_LDO 5V_AUX_S5
5130_SS_STBY1 5130_AGND C401

FLT
INV1

LH1

OUTGND1
TRIP1

TRIP2
OUT1_U
LL1
OUT1_D

VIN_SENSE12

OUTGND2
OUT2_D
R56
5130_LH2 1 2 5130_LL2 5130_LL2 36
3

5130_5V_LDO D 5130_5V_LDO 1 2
1 Q7 SCD1U50V3ZY
1

G 2N7002 78.10494.4B1 0R3-U

1

1
S C117 DCBATOUT_5130
2

R79 SC4700P50V2KX R399 5130_FB1 1 36 C386

2

100KR2 5130_SS_STBY1 FB1 LL2 5130_OUT2U 5130_3D3V_LDO

2 SS_STBY1 OUT2_U 35 5130_OUT2U 36 1 2
5130_INV2 3 34
100KR2 5130_AGND 5130_FB2 INV2 LH2 SCD1U50V3ZY
4 33
2

2
R401 5130_SS_STBY2 FB2 VIN
5 SS_STBY2 VREF3.3 32 78.10494.4B1
T(soft)=1.736ms 1 2 5130_PWMSEL 6 31
5130_CT PWM_SEL VREF5 5130_REGIN R405 0R5J-1
7 30 1 2
5130_SS_STBY2 8
CT
GND TPS5130 REG5V_IN
LDO_IN 29 3D3V_PWR
5V_S5

1
DUMMY-R2 5130_REF 9 28 5130_LDOCUR 5130_LDOCUR 36
5130_AGND REF LDO_CUR 5130_LDOGATE C388 C387
10 STBY_VREF5 LDO_GATE 27 5130_LDOGATE 36
3

D DCBATOUT_5130 1 2 STBY_REF 11 26 SC4D7U10V5ZY SC4D7U10V5ZY

2D5V_PWR

2
3D3V_5V_S5_EN# Q5 R400 5130_STBY_LDO STBY_VREF3.3 LDO_OUT LDO_INV
1 12 STBY_LDO INV_LDO 25 78.47593.411 78.47593.411
1

1
G 2N7002 100KR2
S C98 R404
2

SC4700P50V2KX C385 19K6R3F

2

SCD1U50V3ZY 64.19625.651

VIN_SENSE3
PG_DELAY

2
3

SS_STBY3

OUTGND3
D 5130_AGND

OUT3_U

OUT3_D
Q8

PGOUT
19 S5PWR_ENABLE 1

1
TRIP3
2N7002
LDO SETTING

INV3
G

LH3
FB3
2 2

LL3
S 5130_CT R390
2

For 2.5V
1

10K2R2F

13
14
15
16
17
18
19
20
21
22
23
24
C99 TPS5130PT-U SETTING=2.516V 64.10225.6D1

2
74.05130.07T
2

SC47P50V2JN 5130_SS_STBY3
78.47034.1F1 5130_FB3
5130_AGND 5130_INV3
5130_OUT3D 5130_OUT3D 36
5130_LL3
5130_REF 5130_OUT3U 5130_OUT3U 36

R402 5130_LH3 1 2 5130_LL3 36 Condition Voltage

EN_1D05V_S0 1 2 0R2-0 5130_STBY_LDO C102
37 EN_1D05V_S0 SCD1U50V3ZY C371 SCD1U50V3ZY 78.10494.4B1
5130_5V_LDO PWM_SEL H : Auto PWM/SKIP 2.2V(Min)~
1

R586 5130_AGND 1
100KR2 3 * L : PWM fixed (300KHz) ~0.3V(Max)
5130_PG_DELAY

2 DCBATOUT_5130
DY D10
2

Morar_SB BAT54-1
TP18
83.00054.L03

T(soft)=1.736ms 5130_TRIP3
5130_SS_STBY3 TPAD28
1

1 R53 1
1 2 TPS5130_1D5V_EN# C384 C100
5130_5V_LDO
SC4700P50V2KX
Wistron Corporation
2

100KR2 78.47224.2F1
DUMMY-C3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3

D 5130_AGND ZZ.DUMMY.XC3 Taipei Hsien 221, Taiwan, R.O.C.

2

1 Q30
3

D G 2N7002 Title
1 Q6 S 5130_AGND
TI TPS5130 ---- 5V/3.3V/1.05V,2.5(LDO)
2

37 EN_1D05V_S0 2N7002
G
S Size Document Number Rev
2

A3
MORAR SB
Date: Friday, May 27, 2005 Sheet 35 of 40

A B C D E
 A B C D E

TI TPS5130 for 5V, 3.3V, 1.05V and 2.5V(LDO) 5V_PWR

G49
5V_S5

1 2
(5V=>CH1 , 3D3V=>CH2 , 1D05V =>CH3) GAP-CLOSE-PWR
G48
DCBATOUT_5130 1 2
Morar_SB
GAP-CLOSE-PWR
G46

1
1 2
EC179 C372 C341

5
6
7
8
A SCD1U50V3ZY SC10U35V0ZY-L SC10U35V0ZY-L GAP-CLOSE-PWR A

2
U40 G45

D
D
D
D
AO4422
DY 1 2
84.04422.037
2.8A(rms) @ 10KHz
GAP-CLOSE-PWR
2nd G47
1 2

G
S
S
S
4
3
2
1
L16 GAP-CLOSE-PWR
5130_OUT1U 5V_PWR
35 5130_OUT1U 5130_LL1 1 2
5V/6A
35 5130_LL1
OCP>7.8A G44
2nd 1 2

5
6
7
8
U39 D GAP-CLOSE-PWR
D
D
D

1
G43

1
C407 1 2
2nd TC12

SCD1U16V
ST220U6D3VDM-9GP GAP-CLOSE-PWR

2
G42
G
S
S
S

77.C2271.221 1 2
4
3
2
1

EPCOS,$:0.24 GAP-CLOSE-PWR
5130_OUT1D ESR=25mohm G40
35 5130_OUT1D
Morar_SB Iripple=2.2A 1 2
Morar_SB
DCBATOUT_5130 7.3/4.3/2.0 GAP-CLOSE-PWR
G41
B 1 2 B
3D3V_PWR 3D3V_S5

1
GAP-CLOSE-PWR
EC180 C340
5
6
7
8

SCD1U50V3ZY SC10U35V0ZY-L

2
U42
D
D
D
D

AO4422
DY G37
2.8A(rms) @ 10KHz 1 2 G33
84.04422.037
1 2
2nd GAP-CLOSE-PWR
G39 GAP-CLOSE-PWR
G
S
S
S

1 2 G34
4
3
2
1

1 2
3D3V_PWR GAP-CLOSE-PWR
L17
5130_OUT2U G36 GAP-CLOSE-PWR
35 5130_OUT2U 5130_LL2 1 2
3D3V/5A 1 2 G32
35 5130_LL2
OCP>6.5A GAP-CLOSE-PWR
1 2

2nd G38 GAP-CLOSE-PWR

5
6
7
8

2D5V_PWR 1 2 2D5V_S0 G35

U43
D
D
D
D

1D05V_PWR 1 2 1D05V_S0
1

GAP-CLOSE-PWR
C410 TC11 GAP-CLOSE-PWR
2nd ST220U6D3VDM-9GP Morar_SB
2

2
SCD1U16V

77.C2271.221
G
S
S
S
4
3
2
1

EPCOS,$:0.24
C
ESR=25mohm 3D3V_PWR C
5130_OUT2D
35 5130_OUT2D Iripple=2.2A R421
Morar_SB 7.3/4.3/2.0 5130_LDOCUR 1 2
35 5130_LDOCUR D015R2010

C409

5
6
7
8
SC10U10V5ZY-L
DCBATOUT_5130 U44
OCP Sense Resistor

D
D
D
D
AO4422 (1/2W)
(40mV/12mOhm=3.5A)
2nd
1

C370 C368 C366

G
S
S
S
5
6
7
8

SCD1U50V3ZY SC10U35V0ZY-L SC10U35V0ZY-L

2

4
3
2
1
U38 2D5V_PWR
D
D
D
D

AO4422
DY DY 2D5V/3A
2.8A(rms) @ 10KHz Morar_SB 5130_LDOGATE
84.04422.037 35 5130_LDOGATE
2nd
Morar_SB DY OCP=3.5A
1D05V / 4A Rds(on)=33mOhm

1
C408
G
S
S
S

TC13
,OCP>5.5A
4
3
2
1

1D05V_PWR ST150U4VBM-L2-GP

SCD1U50V3ZY
L14

2
5130_OUT3U
35 5130_OUT3U 5130_LL3
35 5130_LL3 1 2 ESR=35mOhm
Iripple=1.6A
2nd
5
6
7
8

U37 TC10
D
D
D
D

D D
1

ST220U4VDM-21GP

C373
2nd
Wistron Corporation
2

2
SCD1U16V

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

G
S
S
S

Taipei Hsien 221, Taiwan, R.O.C.

4
3
2
1

Title
5130_OUT3D
35 5130_OUT3D TI TPS5130 ---- 5V/3.3V/1.05V,2.5(LDO)
Morar_SB Size Document Number Rev
A3
MORAR SB
Date: Friday, May 27, 2005 Sheet 36 of 40
A B C D E
 A B C D E

DCBATOUT_6227
DCBATOUT DCBATOUT_6227

G14
1 2

GAP-CLOSE-PWR

1
G16
1 2 C156 EC81
SC10U25V6KX SCD1U50V3ZY
C157

2
5
6
7
8
GAP-CLOSE-PWR 6227_BOOT_2
G15 5V_S5 D14 Morar_SB

D
D
D
D
1 2 2 U9
4 3 SCD1U50V3ZY 4
GAP-CLOSE-PWR AO4422
G17 16227_BOOT_1
C435
2nd 1D8V / 6A ,OCP>7.8A Morar_SB

2
1 2

G
S
S
S
BAW56-1 SCD1U50V3ZY R116 1D8V_PWR 1D8V_S3

4
3
2
1
GAP-CLOSE-PWR
0R3-U
Morar_SB R447 L20

1
1 2 2nd G52
1 2 1 2
0R3-U
DCBATOUT_6227 GAP-CLOSE-PWR

G54

5
6
7
8

1
U8 1 2
DY

1
5V_S5 C147 R120

D
D
D
D
R455
R119 TC3 C434 TC16 GAP-CLOSE-PWR

1
SCD01U16V2KX
1 2 6227_VCC C437 10KR3F
DY

2
SC4D7U10V5ZY

SCD1U50V3ZY

ST330U3VDM-1-GP
2nd 0R2-0 G51

2
1

1
SCD1U16V

SCD1U16V

ST220U4VDM-21GP
1 2

2
10R3 C442 C443

14

G
S
S
S
GAP-CLOSE-PWR
2

4
3
2
1

1
VIN
28 6 6227_BOOT1 R121 G50
VCC BOOT1
1 2

1
10KR3F
5 6227_HDRV1 R118 Morar_SB GAP-CLOSE-PWR

2
6227_ILIM1 UGATE1 6227_SW1
11 OCSET1 PHASE1 4
1 2 6227_EN1 8 0R2-0 G53
3 16,29 PM_SLP_S4# R448 0R2-0 6227_SS1 EN1 3
12 1 2

2
SOFT1 6227_LDRV1
LGATE1 2
5V_S5 3 GAP-CLOSE-PWR
R138 PGND1
7 6227_ISNS1 1 2 2KR3F R117
ISEN1
1 21D8V_S3_PG 1 2 6227_PG1 15 PG1 VOUT1 9
R458 0R2-0 10 6227_VSEN1
VSEN1
10KR2 ISL6227
13 DCBATOUT_6227
6227_EN2 21 DDR 6227_BOOT2
16,18,29,32 PM_SLP_S3# 1 2 EN2 BOOT2 23 Morar_SB
R456 0R2-0 6227_SS217
SOFT2
6227_HDRV2
UGATE2 24 1D5V/6A

1
R459 25 6227_SW2 C174 C173
PHASE2
35 EN_1D05V_S0 1 2 0R2-0 6227_PG2 16 PG2/REF
EC88 OCP>7.8A

SC10U25V6KX

SC10U25V6KX
1 SCD1U50V3ZY

2
GND 6227_LDRV2 1D5V_PWR 1D5V_S0
27
DY LGATE2

5
6
7
8
C444 26 R133
5V_S5 PGND2 6227_ISNS2 2 2KR3F G58

D
D
D
D
ISEN2 22 1
R137 SCD1U50V3ZY 20 19 6227_VSEN2 U11 Morar_SB 1 2
VOUT2 VSEN2 6227_ILIM2
1 2 OCSET2 18
AO4422 GAP-CLOSE-PWR
10KR2 2nd

1
G57

G
S
S
S
SCD01U16V2KX

U47 R457 1 2

4
3
2
1
1

1
SCD01U16V2KX

78K7R3F

ISL6227CA 78K7R3F
C436 C445 GAP-CLOSE-PWR
R449
L21
2

2
G55
1 2 1 2
2

2 2

GAP-CLOSE-PWR

1
2nd
OCP

1
SCD01U16V2KX
C158 TC19 G59

5
6
7
8

1
7.8A=>R169=151K R136 SE150U2D5VDM 1 2

0D9V

2
1
U10 6K81R3F

D
D
D
D
9.0A=>R169=133K R135 GAP-CLOSE-PWR

2
Morar_SB 0R2-0

2
2nd G56
DY

1
1 2

2
5V_S5 DDR_VREF C452
NEED?

G
S
S
S

SCD1U16V
1D8V_S3 GAP-CLOSE-PWR

4
3
2
1

2
1

1
R134 R139
1

C116 0R2-0 10KR3F 77.C2271.191

1

SC10U10V5ZY-L C115 G10

SC10U10V5ZY-L 1 2 EPCOS,$:0.243
2

2
ESR=15mohm
2

GAP-CLOSE-PWR
U6
G9 Morar_SB Iripple=2.9A
0D9V_PWR 1 2 7.3/4.3/2.0
11 1 GAP-CLOSE-PWR
GND VDDQSNS
10 VIN VLDOIN 2 G8 Morar_SB
16,29 PM_SLP_S4# 1 2 9 3 1 2 PM_SLP_S3#
R78 0R2-0 S5 VTT
8 GND PGND 4
1 2 7 5 GAP-CLOSE-PWR
16,18,29,32 PM_SLP_S3# R77 0R2-0 S3 VTTSNS
6 VTTREF
1 G11 2 1
DDR_VREF_S3 1 2 1D8V_S3_PG 1 Q13
DY TPS51100DGQ CH3906
1

C113 GAP-CLOSE-PWR
Wistron Corporation
3
1

C114 SC10U10V5ZY-L
SCD1U16V C94 C95 R140 DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

SC10U10V5ZY-L SC10U10V5ZY-L Taipei Hsien 221, Taiwan, R.O.C.

2

100KR2
DY Title
2

1D8V/1D5V/0D9V
Size Document Number Rev
A3
MORAR SB
Date: Thursday, May 26, 2005 Sheet 37 of 40
A B C D E
 D32 DY
2 1

SSM34PT DCBATOUT
AD+
R312
U31 U12
8 D S 1 AD+_TO_SYS 1 2 1 S D 8
D S S D BT+
7 2 2 7
6 D S 3 3 S D 6
D02R3720F

1
5 D G 4 4 G D 5
EC198 EC100
DY

1
SCD1U50V3ZY SCD1U50V3ZY AO4407
DY

2
2

1
AO4407 C314
SC1U50V5ZY G26 G27 EC98
For EMI ID = 10A @

2
GAP-CLOSE SCD1U50V3ZY

2
GAP-CLOSE
VGS = 10V
Morar_SB

1
ISL6255_CSIN_1

1
R238 ISL6255_SGATE
C224 ISL6255_BGATE
18R3 SCD1U50V3ZY

2
1 2 DCBATOUT

1
R237

SC10U35V0ZY-L

SC10U35V0ZY-L
2R3J

5
6
7
8

1
C458

C453
D Q34 C226

SCD1U50V3ZY
3

1
ISL6255_CSIN

ISL6255_CSIP

C457
5V_AUX_S5 TP0610K-U

D
D
D
D
2
ISL6255_VDD SC1U50V5ZY C225

2
1 2 SCD1U50V3KX

2
ISL6255_UGATE
AO4422

2
1
U16 U50
G

G
S
S
S
3
S ISL6255HRZ D20 2nd G60

4
3
2
1
1
G61 GAP-CLOSE BT+

21

20

19

18

17

16

15
BAT54-1
1

R239 R200 GAP-CLOSE

2

1
100KR2 C227 0R2-0

CSOP

CSIP

SGATE

BGATE

PHASE

UGATE
CSIN
L22
SCD1U50V3ZY CHG_PWR-2 1 2 CHG_PWR-3 1 2

2
1 2 22 14 D03R3720F-U
2

1
CSON BOOT
1 2ISL6255_VDD 2nd R478
IND-15UH-12
AC_IN# 1 2 ISL6255_ACPRN# 23 13 R487 2R3J 10*10*4 I
29 AC_IN# ACPRN VDDP ISL6255_VDDP 1 max= 3.6A
2
R240 0R2-0 DY DY

1
24 12 ISL6255_LGATE C212 SC1U10V3ZY C462 C460 C459 C461
DCPRN LGATE

SC10U25V0KX

SC10U25V0KX

SC10U25V0KX
Near ISL6255 Pin 13

5
6
7
8

SCD1U50V3ZY
2

2
ISL6255_VREF

D
D
D
D
25 DCIN PGND 11

1
AD+ ISL6255_VDD 26 10
VDD GND R493 R490
80K6R3F 20KR3F U52

G
S
S
S
1 2 ISL6255_ACSET 27 9 2nd
DY

4
3
2
1
ACSET VADJ

2
1

R494
200KR3F R242 28 8
15K4R3 DCSET ACLIM
ACSET Threshold 1.27V typ.
1

29 VADJ Cell voltage

2

ACSET > 1.29V Max. --> AC GND

1
C228
VCOMP

DETECT SC1U10V3ZY R496 R489 C563

ICOMP
CELLS

CHLIM
2

VREF 15K8R3F 20KR3F SC2700P50V3KX

Near ISL6255 VREF 4.41V/cell

2
ICM
EN

Pin 26 DY DY

2
Float 4.20V/cell
1

7
C230
ISL6255_VDD SC680P50V2KX
1 2 GND 3.99V/cell
R241
1 2 ISL6255_EN ISL6255_CHLIM
1

Morar_SB 100KR2 ISL6255_VREF ISOURCE_MAX = (((ACLIM/VREF)*0.05+0.05)/Rsense)

Adaptor is 65W/19V : I_LIMIT = 2.9A ( 85% )
1

R585 ISL6255_VDD ISL6255_ICM

0R3-U
R244

10KR2
ISL6255_VCOMP

1
2

D R245 ICHG : 4S2P = 3.0A/

1
10KR2
R243

1 Q20 32K4R3F
1 2

29 CHG_ON# 4S1P = 1.4A

1

SC6800P25V2KX

G 2N7002 R495
C231

S R491 100R3 IPRE_CHG = 200mA

2

0R3-U
DY
2
2

2
2

1
SC100P50V2JN-U

SCD01U16V2KX
1

1
C229

C232

CELLS Operate Mode ISL6255_CELLS R202 R203 R201

C471
SCD1U50V3ZY

21K5R3F 100KR3F 1K74R3F

Wistron Corporation
1

VDD 4S R492 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

0R3-U Taipei Hsien 221, Taiwan, R.O.C.

DY
DY
3

GND 3S D D Title
2

1 Q33 Q32 1
29 4S1P_I
G 2N7002 2N7002 G
PRE_CHG 29 CHARGER ISL6225
Float 2S S S Size Document Number Rev
2

A3
(Power Team) MORAR SB
Date: Friday, May 27, 2005 Sheet 38 of 40
 A B C D E

Adaptor in to generate DCBATOUT DY

Morar_SA:22.10037.701 D33
PZM24NB1
Morar_SB:22.10037.701 2
3
Morar_SB:22.10037.B02(2nd) 1
AD+
DC1
4 AD_JK
4 4
U32
1 1 S D 8

1
2 S D 7 C310
3 S D 6 SCD1U50V3ZY
2 C304 AD+_2 4 G D 5

2
SCD1U50V3ZY
C4 AO4407

1
3
100KR2 ID = -10A/70deg

SCD1U50V3ZY
1
5 R298
Rds(ON) = 24mohm
6

2
MH1 SO-8

2
E
DC-JACK75-U
connector B
1
22.10037.701

1
Q3 C
PDTA124EU R299
Morar_SB 56KR3F

2
Q4
3 OUT
2 R1
29 AD_OFF
IN 1 GND

1
R2
R7 DTC124EKA
3 1KR2 3

2
DY 3D3V_AUX_S5
BAV99LT1
BATTERY CONNECTOR D16
DY

2
BAV99LT1 Morar_SB
D15

BAT1

3
1

2
29 BAT_SCL 1 R182 2 BATA_SCL_1 3
1 R183 2 27R3F BATA_SDA_1 4
29 BAT_SDA 27R3F
29 BAT_IN# 5
6
BT+ 7

AMP-CON7-8

1
2 EC97 EC96 2
DY DY DY

SC10P50V2JN-1

SC10P50V2JN-1
connector
EC102 EC101 EC99 EC107

2
SC1000P50V

SC1000P50V
SCD1U50V3ZY
2

2
Morar_SA:20.80269.007

SCD1U50V3ZY
Morar_SB:20.80605.007

Morar_SB

<Variant Name>
1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
AD/BATT CONN
Size Document Number Rev
A3
MORAR SB
Date: Saturday, May 28, 2005 Sheet 39 of 40

A B C D E
 5 4 3 2 1
Morar_SB
GND4 GND2 GND6 GND1 GND3 GND5 GND12 GND13 GND11 GND10 GND7
SPRING-24 SPRING-24 SPRING-24 SPRING-24 SPRING-24 SPRING-24 SPRING-23 SPRING-23 SPRING-23 SPRING-23 SPRING-U3
GND9 GND8
SPRING-1-GP SPRING-1-GP

DY DY DY DY

1
D D
1D8V_S3
Morar_SB Morar_SB Morar_SB Morar_SB Morar_SB
1

1
EC29 EC55 EC35 EC48 EC45 EC36 EC76 EC75 EC63 EC32 EC34 EC56 EC31 EC28 EC52 EC53 EC46 EC54 EC51 EC50
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
DY DY DY DY DY DY DY DY DY DY DY

DDR_VREF Morar_SB
DCBATOUT

EC87 EC77 EC169 EC5 EC150 EC7 EC167 EC174 EC173 EC172 EC178 EC67 EC170 EC33 EC65 EC213 EC214 EC215 EC216 EC217 EC218 EC219 EC220
SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U SCD1U

DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
C C
HOLE3 HOLE4 HOLE5 HOLE6 HOLE7 HOLE8
5V_S0 HOLE HOLE HOLE HOLE HOLE HOLE
1

1
EC127 EC136 EC137 EC197 EC201 EC199 EC181 EC122 EC106 EC105 EC20 EC6 EC23 EC9 EC171

1
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
HOLE9 HOLE10 HOLE2 HOLE13 HOLE14 HOLE12
HOLE HOLE HOLE
5V_S5 3D3V_S0 Morar_SB

1
1

1
EC66 EC3 EC196 EC115 EC202 EC103 EC185 EC119 EC125 EC138 EC168 EC37 EC69 EC177 EC57
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
DY DY DY DY DY DY DY DY DY DY DY DY HOLE1 HOLE16 HOLE11 HOLE19 HOLE18 HOLE20
HOLE HOLE
Morar_SB Morar_SB

B3D3V_S0 B

1
1

1
FOR NORTH BRIDGE
EC132 EC94 EC118 EC114 EC133 EC26 EC188 EC200 EC109 EC134 EC166 EC121 EC116 EC126 EC124 FOR MDC
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V HOLE21
2

2
HOLE15

HOLE23

1
3D3V_S5 3D3V_LAN_S5 HOLE17

1
ZZ.0HOLE.XXX
HOLE25

1
34.47T01.001
1

1
EC117 EC104 EC194 EC128 EC84 EC68 EC110 EC16 EC8 EC208 EC123 EC86 EC25 EC64 EC164
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

1
ZZ.0HOLE.XXX

1
34.47T01.001
ZZ.0HOLE.XXX
5V_AUX_S5 2D5V_S0 1D05V_S0
A A
Wistron Corporation
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

EC191 EC95 EC49 EC120 EC30 EC162 EC158 EC175 EC186 EC182 EC80 EC27 EC176 EC85 EC70 Taipei Hsien 221, Taiwan, R.O.C.
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

Title
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY EMI
Size Document Number Rev
A3
MORAR SB
Date: Thursday, May 26, 2005 Sheet 40 of 40
www.s-manuals.com