Scribd
Upload
76 views

To Perform HDL Based Design Entry and Simulation of ALU

1. The document describes designing and simulating an ALU using Verilog HDL in Xilinx Vivado. Key steps include writing the Verilog code, running behavioral simulation to verify the output matches expected results. 2. The design is then synthesized, implemented, and post-implementation simulation is run to verify the outputs. Resource utilization is examined after synthesis and implementation. 3. Finally, the bitstream is generated and the design is programmed onto a Zedboard to test the ALU hardware by changing input switches and checking the output LEDs.

Uploaded by

samhita santhanam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
76 views

To Perform HDL Based Design Entry and Simulation of ALU

1. The document describes designing and simulating an ALU using Verilog HDL in Xilinx Vivado. Key steps include writing the Verilog code, running behavioral simulation to verify the output matches expected results. 2. The design is then synthesized, implemented, and post-implementation simulation is run to verify the outputs. Resource utilization is examined after synthesis and implementation. 3. Finally, the bitstream is generated and the design is programmed onto a Zedboard to test the ALU hardware by changing input switches and checking the output LEDs.

Uploaded by

samhita santhanam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 6

Ex. No.

:6a HDL BASED DESIGN ENTRY AND SIMULATION OF ALU


Date:

AIM:

To perform HDL based design entry and simulation of ALU

SOFTWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015

PROCEDURE:

1. Design ALU using Verilog HDL.


2. Create new RTL project in Xilinx Vivado.
3. Choose the HDL language (Verilog) and the device (Zedboard).
4. Write the Verilog module for the designed logic circuit using any modeling style in the Code editor.
5. Simulate the source program using Xilinx Simulator tool. Run behavioural Simulation.
6. Force the inputs (and clock if any) in the object window and Run simulation.
7. Verify the output in the obtained simulation waveform.

PROGRAM CODE:
SAMPLE DATA:

SIMULATION WAVEFORM:

RESULT:
Thus the Verilog program for ALU was written, simulated and the output was verified from the
simulation waveform.

Ex. No.:6b SYNTHESIS, P&R AND POST P&R SIMULATION OF ALU


Date:

AIM:
To synthesize, implement and perform post implementation simulation of ALU

SOFTWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015


Zedboard Zynq 7000 Development Board

PROCEDURE:

1. After simulation, Click on Run Synthesis under the flow navigator pane.
2. Open Synthesized Design and view the Elaborated Synthesized Design.
3. Examine the resources utilised in the synthesized design from the project summary.
4. Perform IO pin assignment for each of the inputs and outputs as per board configuration and save
constraints.
5. Re-run the synthesis.
6. Click on Run Implementation under the Flow Navigator pane. Open and view the implemented
design.
7. Examine the resources utilised in the implemented design from the project summary.
8. Run Post-Implementation Timing Simulation under the Simulation tasks in the Flow Navigator
pane and obtain the waveform by giving test vector inputs.

OUTPUT:

1. Constraints file:

2.Elaborated design
3.Implemented design

4.Utilisation after Implementation

5. Utilization after synthesis:

6.Utilisation report:
7. Post Implementation simulation:

RESULT:
Thus Verilog program for ALU was synthesized, implemented and post implementation simulation
was performed.

Ex. No.: 6c HARDWARE TESTING AND FUSING OF ALU


Date:
AIM:

To perform hardware fusing and testing of ALU in Zedboard using Xilinx Vivado.

SOFTWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015


Zedboard Zynq 7000 Development Board

PROCEDURE:

1. Connect the Zedboard to the PC and power ON.


2. Click on Generate Bit stream entry under the Program and Debug tasks of the Flow Navigator pane.
3. Click on “Open Hardware Manager”. Click on “Open Target” and select “Auto Connect”.
4. Program the Device xc7z020_1.
1. Once the program is downloaded into the Zedboard, verify the functionality by varying the input
switches and checking the output LEDs.

RESULT:
Thus the hardware fusing and testing of ALU was performed in Zedboard using Xilinx Vivado.

You might also like