UltraScale Architecture

System Monitor

Advance Specification User Guide

UG580 (v1.0) December 10, 2013

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Revision History
The following table shows the revision history for this document.

Date Version Revision

12/10/2013 1.0 Initial Xilinx release.

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: Overview and Quick Start

Introduction to UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SYSMON Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SYSMON Pinout Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Instantiating the SYSMON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: Basic Functionality

ADC Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 3: SYSMON Register Interface

Dynamic Reconfiguration Port (DRP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DRP Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DRP JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DRP I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter 4: SYSMON Operating Modes

Single Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Automatic Channel Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Sequencer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
External Multiplexer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Automatic Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Chapter 5: Application Guidelines

Reference Inputs (VREFP and VREFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Analog Power Supply and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
External Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SYSMON Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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 Appendix A: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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 Chapter 1

Overview and Quick Start

Introduction to UltraScale Architecture

The Xilinx® UltraScale™ architecture is a revolutionary approach to creating programmable
devices capable of addressing the massive I/O and memory bandwidth requirements of next
generation applications while efficiently routing and processing the data brought on chip.
UltraScale architecture-based FPGAs address a vast spectrum of high-bandwidth,
high-utilization system requirements through industry-leading technical innovations.
UltraScale architecture-based devices share many building blocks to provide optimized
scalability across the product range, as well as numerous new power reduction features for
low total power consumption.

Kintex® UltraScale FPGAs provide high performance with a focus on optimized

performance per watt for applications including wireless, wired, and signal or image
processing. High DSP and block RAM-to-logic ratios, and next generation transceivers are
combined with low-cost packaging to enable an optimum blend of capability for these
applications.

Virtex® UltraScale FPGAs provide the highest system capacity, bandwidth, and
performance. Delivering unprecedented logic capacity, serial I/O bandwidth, and on-chip
memory, the Virtex UltraScale family pushes the performance envelope ever higher.

This user guide serves as a technical reference describing the UltraScale architecture System
Monitor (SYSMON). SYSMON monitors the physical environment via on-chip temperature
and supply sensors, up to 17 external analog inputs, and an integrated analog to digital
converter (ADC). This user guide is part of the UltraScale architecture documentation suite
available at: www.xilinx.com/ultrascale.

This chapter provides a brief overview of the SYSMON functionality with key information to
allow a basic understanding of the SYSMON block. This introduction describes the pinout
requirements and how to instantiate basic functionality in designs. Subsequent chapters
provide more detailed descriptions of the SYSMON functionality.

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SYSMON Overview
The SYSMON includes an ADC and on-chip sensors. The ADC and sensors are fully tested
and specified (see the data sheets). The ADC provides a general-purpose, high-precision
analog interface for a range of applications. Figure 1-1 shows a block diagram of the
SYSMON. The ADC supports a range of operating modes including external triggering (see
Chapter 4, SYSMON Operating Modes) and various analog input signal types, for example,
unipolar, bipolar, and differential (see Chapter 2, Basic Functionality). The ADC can access
up to 17 external analog input channels.
X-Ref Target - Figure 1-1

Temperature Supply VREFP VREFN

Sensor Sensors

°C
On-Chip Ref
1.25V

VP/VN
External Control Status
VAUXP/N[0] MUX ADC Registers Registers
Analog
Inputs
VAUXP/N[15]

DRP
SYSMONE1
JTAG I2C
DRP Interface

UG580_c1_01_041713

Figure 1-1: SYSMON Block Diagram

The SYSMON also includes several on-chip sensors that support measurement of the
on-chip power supply voltages and die temperature. The ADC conversion data is stored in
dedicated status registers. These registers are accessible through the internal logic
interconnect using a 16-bit synchronous read and write dynamic reconfiguration port
(DRP). ADC conversion data is also accessible through the JTAG test access port (TAP) and
I2C either before (preconfiguration) or after configuration. For JTAG TAP, the SYSMON does
not need to be instantiated or visible in the design because it is a dedicated interface that
uses the existing configuration JTAG infrastructure allowing access to SYSMON
preconfiguration. If the SYSMON is not instantiated in a design, the device operates in a
predefined default mode that monitors on-chip temperature and supply voltages.

SYSMON operation is user-defined by writing to the control registers, which can be

accessed through DRP, JTAG, or I2C. It is also possible to initialize these register contents
when the SYSMON is instantiated in a design using the block attributes.

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Differences from Previous Generations

The SYSMON was designed with the same functionality as the 7 series XADC except for the
functional differences described in this section. Because of these functional differences, all
XADC designs must be redesigned to the SYSMONE1 primitive.

IMPORTANT: The SYSMON contains only a single 10-bit 0.2 MSPS ADC. Consequently, the sequencer
for SYSMON does not support simultaneous sampling mode or independent ADC mode.

• 10-bit 0.2 MSPS single-channel analog-to-digital converter

• Any single I/O bank can be selected to include external analog inputs
• Eight additional alarm outputs (16 total alarms)
• Status and control registers extended to 256 addresses
• Simultaneous sampling mode and independent ADC mode are no longer supported

Table 1-1 lists the differences between the 7 series XADC primitive versus the UltraScale
architecture SYSMONE1 primitive.

Table 1-1: 7 Series XADC Primitive versus UltraScale Architecture SYSMONE1 Primitive
Feature XADC SYSMONE1
Resolution 12-bit 10-bit
Sample rate 1 MSPS 0.2 MSPS
Analog-to-digital converters 2 1
Auxiliary analog inputs 16 16
Banks supporting external analog inputs 1 All
Control registers 40h to 7Fh 40h to 7Fh
Status registers 00h to 3Fh 00h to 3Fh, 80h to 8Fh
Alarm outputs 8: ALM[7:0] 16: ALM[15:0]
USER supply sensors 0 4
Reconfiguration interfaces DRP, JTAG DRP, I2C, JTAG

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SYSMON Pinout Requirements

Dedicated Package Pins
Figure 1-2 shows the basic pinout requirements for the SYSMON. There are two
recommended configurations. On the left, the SYSMON is powered from VCCAUX (1.8V) and
uses an external 1.25V reference source. The external reference delivers the best
performance in terms of accuracy and thermal drift. A ferrite bead is used to isolate the
ground reference for the analog circuits and system ground. An additional low pass filter for
the VCCAUX supply similarly improves the ADC performance (see Chapter 5, Application
Guidelines). Shared or common ground impedance is the most common way to introduce
unwanted noise into analog circuits.
X-Ref Target - Figure 1-2

Use External Reference IC Enable On-Chip Reference

VCCAUX (1.8V ± 3%) VCCAUX (1.8V ± 3%)
1.8V – 5V
Filter VCCAUX Supply Filter VCCAUX Supply

1.25V ± 0.2%
50 ppm/°C VREFP VCCADC VREFP VCCADC
VP VP
100 nF 100 nF 470 nF 100 nF 470 nF
ADC ADC
VN
VN

VREFN GNDADC VREFN GNDADC

Ferrite bead for high frequency noise isolation Ferrite bead for high frequency noise isolation
GND GND

Package Pins
UG580_c1_02_101413

Figure 1-2: SYSMON Pinout Requirements

It is also possible to use an on-chip reference for the ADC. To enable the on-chip reference
source, the VREFP pin must be connected to GND as shown on the right of Figure 1-2. When
only basic on-chip thermal and supply monitoring is required, using the on-chip reference
provides good performance. Consult the data sheets to see the accuracy specifications
when using the external and on-chip reference sources. Table 1-2 lists the pins associated
with the SYSMON and the recommended connectivity.

IMPORTANT: It is also important to place the 100 nF decoupling capacitors as close as possible to the
VCCADC_0, VGNDADC_0, V REFP_0 (optional), and V REFN_0 (optional) package balls to minimize inductance
between the decoupling and package balls.

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Table 1-2: SYSMON Package Pins

Package Pin Type Description
This is the analog supply pin for the ADC and other analog circuits in
the SYSMON. The pin can be tied to the 1.8V VCCAUX supply. See
VCCADC Power supply Analog Power Supply and Ground for more information. This pin
should never be tied to GND. The pin should be tied to VCCAUX even
when the SYSMON is not being used.
This is the ground reference pin for the ADC and other analog circuits
in the SYSMON. It can be tied to the system ground with an isolating
ferrite bead as shown in Figure 1-2 . In a mixed-signal system this pin
GNDADC Power supply should be tied to an analog ground plane, if available, in which case
the ferrite bead is not required. See Analog Power Supply and Ground
for more information. This pin should always be tied to GND even if
the SYSMON is not being used.
This pin can be tied to an external 1.25V accurate reference IC (±0.2%)
for best performance of the ADC. It should be treated as an analog
signal that together with the VREFN signal provides a differential 1.25V
V REFP Reference voltage input voltage. By connecting this pin to GNDADC (see Figure 1-2 ) an
on-chip reference source (±1%) is activated. This pin should be
connected to GNDADC if an external reference is not supplied. See
Reference Inputs (VREFP and VREFN) for more information.
This pin should be tied to ground pin of an external 1.25V accurate
reference IC (±0.2%) for best performance of the ADC. It should be
treated as an analog signal that together with the VREFP signal
V REFN Reference voltage input
provides a differential 1.25V voltage. This pin should always be
connected to GND even if an external reference is not supplied. See
Reference Inputs (VREFP and VREFN) for more information.
This is the positive input terminal of the dedicated differential analog
input channel (VP/V N). The analog input channels are very flexible and
VP Dedicated analog input
support multiple analog input signal types. For more information, see
Analog Inputs. This pin should be connected to GNDADC if not used.
This is the negative input terminal of the dedicated differential analog
input channel (VP/V N). The analog input channels are very flexible and
VN Dedicated analog input
support multiple analog input signal types. For more information, see
Analog Inputs. This pin should be connected to GNDADC if not used.
These are multi-function pins that can support analog inputs or can
be used as regular digital I/O (see Figure 1-1 ). These pins support up
to 16 positive input terminals of the differential auxiliary analog input
_AD0P_ to Auxiliary analog
channels (VAUXP/VAUXN ). The analog input channels are very flexible
_AD15P_(1) inputs/digital I/O
and support multiple analog input signal types. For more information,
see Analog Inputs. When not being used as analog input, these pins
can be treated like any other digital I/O.
These are multi-function pins that can support analog inputs or can
be used as regular digital I/O (see Figure 1-1). These pins support up
to 16 negative input terminals of the differential auxiliary analog
_AD0N_ to Auxiliary analog
input channels (VAUXP/VAUXN). The analog input channels are very
_AD15N_ (1) inputs/digital I/O
flexible and support multiple analog input signal types. For more
information, see Analog Inputs. When not being used as analog input
these pins can be treated like any other digital I/O.

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Table 1-2: SYSMON Package Pins (Cont’d)

Package Pin Type Description
IEEE Std 1149.1 (JTAG) Test Clock
Clock for all devices on a JTAG chain. Connect to the Xilinx cable
header's TCK pin. Treat as a critical clock signal and buffer the cable
TCK Dedicated JTAG input header TCK signal as necessary for multiple device JTAG chains. If the
TCK signal is buffered, connect the buffer input to an external weak
(e.g., 10 kΩ) pull-up resistor to maintain a valid High when no cable
is connected.
JTAG Test Mode Select
Mode select for all devices on a JTAG chain. Connect to the Xilinx
cable header's TMS pin. Buffer the cable header TMS signal as
TMS Dedicated JTAG input
necessary for multiple device JTAG chains. If the TMS signal is
buffered, connect the buffer input to an external weak (e.g., 10 kΩ )
pull-up resistor to maintain a valid High when no cable is connected.
JTAG Test Data Input
JTAG chain serialized data input. For an isolated device or for the first
device in a JTAG chain, connect to the Xilinx cable header's TDI pin.
TDI Dedicated JTAG input
Otherwise, when the FPGA is not the first device in a JTAG chain,
connect to the TDO pin of the upstream JTAG device in the JTAG scan
chain.
JTAG Test Data Output
JTAG chain serialized data output. For an isolated device or for the last
TDO Dedicated JTAG input device in a JTAG chain, connect to the Xilinx cable header's TDO pin.
Otherwise, when the FPGA is not the last device in a JTAG chain,
connect to the TDI pin of the downstream JTAG device in the JTAG
scan chain.
Multi-function pin that can be used to support the I2C DRP interface
Multi-function SYSMON
I2C_SDA for SYSMON. I2C_SDA is the data pin for the DRP I2C interface. See
I2C I/O
DRP I2C Interface for more information.
Multi-function SYSMON Multi-function pin that can be used to support the I2C DRP interface
I2C_SCLK I2C I/O for SYSMON. I2C_CLK is the clock pin for the DRP I2C interface. See
DRP I2C Interface for more information.

Notes:
1. I/Os that are analog input-enabled contain the _ADxP_ and _ADxN_ designation in the package file name, e.g.,
IO_L1P_T0_AD0P_35 is the input pin for analog auxiliary channel VAUXP[0]. IO_L1N_T0_AD0N_35 is the input pin for analog
auxiliary channel VAUXN[0]. For more information, see the UltraScale Architecture Packaging and Pinout Specification.

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IMPORTANT: Consult Chapter 5, Application Guidelines before commencing any PC board layout.
Board layout and external component choices can greatly impact the performance of the ADC. For
additional PCB layout guidelines, see XADC Layout Guidelines (XAPP554) [Ref 1].

External Analog Inputs

Apart from a single dedicated analog input pair (VP/VN), the external analog inputs use
dual-purpose I/O. These digital I/Os are individually nominated as analog inputs when the
SYSMON is instantiated in a design. This user guide refers to these analog inputs as
auxiliary analog inputs. A maximum of 16 auxiliary analog inputs are available. Each I/O
bank can support up to 16 auxiliary analog inputs. The auxiliary analog inputs are enabled
by connecting the analog inputs on the SYSMONE1 primitive to the top level of the design.
When enabled as analog inputs, these package balls are unavailable as digital I/Os. It is also
possible to enable the auxiliary analog inputs preconfiguration (for example, for PCB
diagnostics) with the JTAG TAP (see JTAG DRP Commands for more information.) Bank
selection can be changed at instantiation or by using the System Management Wizard.
Preconfiguration, auxiliary inputs are set to bank 66 by writing 0001h to DRP address 02h.

The SYSMON allows any single I/O bank to support the auxiliary analog inputs. All auxiliary
analog inputs must be placed within the same I/O bank. Analog input voltages cannot
exceed the I/O bank supply (VCCO). Analog inputs must set IOSTANDARD = ANALOG. To
assign an auxiliary analog input to a particular bank, assign the input to a valid analog input
as designated by _AD[15:0]P_ <BANK #> or _AD[15:0]N_<BANK #>. The Vivado® pin
planner can be used to help identify allowable pins for each bank. For example,
_AD0P_<BANK #> should be assigned to the input connected to AUXP[0] port for the
SYSMONE1 instantiation.

All analog input channels are differential and require two package balls. See the UltraScale
Architecture Packaging and Pinout Specification (UG575) [Ref 3] for more information. See
Analog Inputs, page 20 for more information.

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Instantiating the SYSMON

It is not necessary to instantiate the SYSMON in a design to access the on-chip monitoring
capability. However, if the SYSMON is not instantiated in a design, the only way to access
this information is by using either the JTAG TAP or I2C. To allow access to the status
registers (measurement results) from the interconnect logic, the SYSMON must be
instantiated. These subsections give a brief overview of the SYSMONE1 primitive (ports and
attributes).

SYSMON Ports
Figure 1-3 shows the ports on the SYSMONE1 primitive, and Table 1-3 describes the
functionality of the ports.
X-Ref Target - Figure 1-3

SYSMONE1
DO[15:0]
DI[15:0]
Dynamic DADDR[7:0]
Reconfiguration Port DEN
(DRP) DWE
ALM[15:0]
DCLK Alarms
OT
DRDY

MUXADDR[4:0]
RESET CHANNEL[5:0]
Control EOC
and Clock CONVST
CONVSTCLK EOS
BUSY Status
VP JTAGLOCKED
External
Analog VN JTAGMODIFIED
Inputs VAUXP[15:0] JTAGBUSY
VAUXN[15:0]
I2C_SCLK_IN
DRP I2C I2C_SCLK_TS
Interface I2C_SDA_IN
I2C_SDA_TS
UG580_c1_03_111313

Figure 1-3: SYSMONE1 Primitive Ports

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Table 1-3: SYSMON Port Descriptions

Port I/O Description
DI[15:0] Inputs Input data bus for the DRP.(1)
DO[15:0] Outputs Output data bus for the DRP.(1)
DADDR[7:0] Inputs Address bus for the DRP. (1)
DEN Input Enable signal for the DRP.(1)
DWE Input Write enable for the DRP. (1)
DCLK Input Clock input for the DRP. (1)
DRDY Output Data ready signal for the DRP. (1)
Asynchronous reset signal for the SYSMON control logic. RESET is
RESET Input deasserted synchronously to DCLK or internal configuration when
DCLK is stopped.
Convert start input. This input controls the sampling instant on the
CONVST Input ADC(s) input and is only used in event mode timing. This input
comes from the general-purpose interconnect.
Convert start clock input. This input is connected to a clock net.
Like CONVST, this input controls the sampling instant on the
ADC(s) inputs and is only used in event mode timing. This input
CONVSTCLK Input
comes from the local clock distribution network. Thus, for the best
control over the sampling instant (delay and jitter), a global clock
input can be used as the CONVSTCLK source.
One dedicated analog input pair. The SYSMON has one pair of
dedicated analog input pins that provide a differential analog
V P, V N Input input. When designing with the SYSMON feature without using the
dedicated external channel of VP and V N, connect both V P and VN
to analog ground.
Sixteen auxiliary analog input pairs. In addition to the dedicated
differential analog input, the SYSMON can access 16 differential
VAUXP[15:0],
Input analog inputs by configuring digital I/O as analog inputs. These
VAUXN[15:0]
inputs can also be enabled preconfiguration with the JTAG port
(see DRP JTAG Interface).
Temperature sensor alarm output. When High, measured data
ALM[0] Output
violates alarm thresholds.
VCCINT sensor alarm output. When High, measured data violates
ALM[1] Output
alarm thresholds.
VCCAUX sensor alarm output. When High, measured data violates
ALM[2] Output
alarm thresholds.
VCCBRAM sensor alarm output. When High, measured data violates
ALM[3] Output
alarm thresholds.
ALM[6:4] Output Unused (Low).
Logic OR of bus ALM[3:0]. Can be used to flag the occurrence of
ALM[7] Output
any alarm in this group.
Alarms of user-selected sources USER[3:0]. When ALM[8] is High,
ALM[11:8] Output the measured USER0 data violates alarm thresholds (see Power and
User Supply Sensors.)

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Table 1-3: SYSMON Port Descriptions (Cont’d)

Port I/O Description
ALM[15:12] Outputs Reserved
OT Output Over-Temperature alarm output.
These outputs are used in external multiplexer mode. They indicate
the address of the next channel in a sequence to be converted.
MUXADDR[4:0] Outputs
They provide the channel address for an external multiplexer (see
External Multiplexer Mode).
Channel selection outputs. The ADC input MUX channel selection
CHANNEL[5:0] Outputs for the current ADC conversion is placed on these outputs at the
end of an ADC conversion.
End of conversion signal. This signal transitions to active High at
EOC Output the end of an ADC conversion when the measurement is written to
the status registers.
End of sequence. This signal transitions to active High when the
EOS Output measurement data from the last channel in an automatic channel
sequence is written to the status registers.
ADC busy signal. This signal transitions High during an ADC
BUSY Output conversion. This signal also transitions High for an extended
period during an ADC or sensor calibration.
Indicates that a DRP port lock request has been made by the JTAG
JTAGLOCKED Output interface (see DRP JTAG Interface). This signal is also used to
indicate that the DRP is ready for access (when Low).
JTAGMODIFIED Output Used to indicate that a JTAG write to the DRP has occurred.
JTAGBUSY Output Used to indicate that a JTAG DRP transaction is in progress.
Input for I2C_SDA. Required for DRP I2C interface. The I2C_SDA_IN
I2C_SDA_IN Input and I2C_SDA_TS ports must be connected to the dedicated
I2C_SDA package pin as described in DRP I2C Interface.
Output for I2C_SDA. Required for DRP I2C interface. The
I2C_SDA_TS Output I2C_SDA_IN and I2C_SDA_TS ports must be connected to the
dedicated I2C_SDA package pin as described in DRP I2C Interface.
Input for I2C_SCLK. Required for DRP I2C interface. The
I2C_SCLK_IN Input I2C_SCLK_IN and I2C_SCLK_TS ports must be connected to the
dedicated I2C_SCLK package pin as described in DRP I2C Interface.
Output for I2C_SCLK. Required for DRP I2C interface. The
I2C_SCLK_TS Output I2C_SCLK_IN and I2C_SCLK_TS ports must be connected to the
dedicated I2C_SCLK package pin as described in DRP I2C Interface.

Notes:
1. The DRP is the interface between the SYSMON and the device. All SYSMON registers can be accessed from the
interconnect logic using this interface.

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SYSMON Attributes
The block diagram in Figure 1-1 shows the 16-bit control registers that define the
operation of the SYSMON. These registers can be read and written using the DRP, JTAG, or
I2C ports. It is also possible to initialize the contents of these registers during the
configuration using attributes for the SYSMONE1 primitive. The attributes are called
INIT_xx, where xx corresponds to the hexadecimal address of the register on the DRP. For
example, INIT_40 corresponds to the first control register at address 40h on the DRP. The
control registers and the INIT_xx values are described in detail in Figure 3-1.

Table 1-4: SYSMONE1 Primitive Attributes

Attribute Type Allowed Values Description
SIM_MONITOR_FILE String - Simulation analog entry file name.
Initialization values for control register
INIT_40 to INIT_7F Integer 0000h to FFFFh
addresses 40h to 7Fh. See Table 3-4.
Specific to device and SYSMON_VUSER[3:0]_BANK and
package SYSMON_VUSER[3:0]_MONITOR are both
required for selecting a power supply to be
SYSMON_VUSER[3:0]_BANK Integer
measured by V USER. Restrictions apply. Use
the System Management Wizard for
selecting.
VCCO(1), VCCO_TOP (2), SYSMON_VUSER[3:0]_BANK and
VCCO_BOT(2), VCCINT, SYSMON_VUSER[3:0]_MONITOR are both
VCCAUX , AVCC, AVTT, required for selecting a power supply to be
SYSMON_VUSER[3:0]_MONITOR String
MGTVCCAUX measured by V USER. Restrictions apply. Use
the System Management Wizard for
selecting.

Notes:
1. Only supported in HP I/O banks.
2. Only supported in HR I/O banks.

The SYSMONE1 primitive also has the SIM_MONITOR_FILE attribute that points to the
analog stimulus file. This attribute is required to support simulation. This attribute points to
the path and file name of a text file that contains analog information (e.g., temperature and
voltage). UNISIM and SIMPRIM models use this text file during simulation. This is the only
way analog signals can be introduced into a simulation of the SYSMON. For more
information, see SYSMON Software Support.

SYSMON_VUSER[3:0]_BANK and SYSMON_VUSER[3:0]_MONITOR attributes must be used

together to select the on-chip user supply monitor. For example, if VUSER0 is used to
measure the VCCO in bank 66, SYSMONE1 must be set to SYSMON_VUSER0_bank(66) and
SYSMON_VUSER0_MONITOR(VCCO). UltraScale architecture-based FPGAs support VCCO
supplies differently in HR I/O banks and HP I/O banks. In HP I/O banks,
SYSMON_VUSER[3:0]_MONITOR must be set to VCCO when the VCCO supply is being
measured. In UltraScale architecture-based FPGAs, HR I/O banks are split into either the top
or bottom of the HR I/O bank. HR I/O banks must be set to either VCCO_TOP or VCCO_BOT.

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Every on-chip user supply can be independently set. Due to routing restrictions, the System
Management Wizard should be used for setting the on-chip user supplies.

ADC and Sensors

For more comprehensive information on the operation of the ADCs and on-chip sensors,
see Chapter 2, Basic Functionality. This section provides a brief overview on how to quickly
interpret data read from the status registers and verify the operation of the SYSMON.

Analog-to-Digital Converter
The ADC has a nominal analog input range from 0V to 1V. In unipolar mode (default), the
analog inputs of the ADC produce a full scale code of 3FFh (10 bits) when the input is 1V.
Thus, an analog input signal of 200 mV in unipolar mode produces an output code of:

( ( 0.2 ⁄ 1.0 ) × 3FFh ) = 204 or CCh Equation 1-1

In bipolar mode, the ADC uses two’s complement coding and produces a full scale code of
1FFh with +0.5V input and 200h with –0.5V input.

Temperature Sensor
The temperature sensor has a transfer function of:

Temperature ( °C ) = ADC
Code × 503.975
---------------------------------------------- – 273.15 Equation 1-2
1024
For example, ADC code 606 (25Eh) = 25°C. The temperature sensor result is found in the
status register 00h.

Power and User Supply Sensors

The SYSMON power supply sensors have a transfer function that generates a full scale ADC
output code of 3FFh with a 3V input voltage. This voltage is outside the allowed supply
range, but the device supply measurements map into this measurement range. Thus,
VCCINT = 1V generates an output code of 1/3 x 1024 = 341 = 155h. The SYSMON monitors
VCCINT, VCCAUX , and VCCBRAM. The measurement results are stored in status registers 01h,
02h, and 06h, respectively.

Furthermore, the SYSMON allows four additional supplies (VUSER[3:0]) to be measured in

status registers 80h, 81h, 82h, and 83h. The System Management Wizard connects
VUSER[3:0] to a bank's VCCO, VCCO_TOP, VCCO_BOT, AVCC, AVTT, MGTVCCAUX , VCCINT, or VCCAUX
supply pins. The four measured supplies can be located in different banks. The System
Management Wizard provides the allowable connections. Because the user supplies can be
used with HR I/O banks, a wider input range is required. As a result, the user supplies can
have a full scale ADC output code of 3FFh with a 6V input voltage for HR I/O banks. See
Power Supply Sensor, page 25 for more information.

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 Chapter 2

Basic Functionality
The SYSMON block contains a 10-bit, 0.2 MSPS ADC. The ADC can be used with both
external analog inputs and on-chip sensors. Several predefined operating modes are
available that cover the most typical use cases for the ADC. These operating modes are
described in Chapter 4. This chapter focuses on the detailed operation of the ADC and the
on-chip sensors. The various input configurations for the external analog inputs are also
covered. All operating modes of the ADC, sensors, and analog inputs are configured using
the SYSMON control registers. A detailed description of the control registers is covered in
Chapter 3.

ADC Transfer Functions

The ADC has transfer functions as shown in Figure 2-1 and Figure 2-2. These transfer
functions reflect unipolar and bipolar operating modes, respectively. All on-chip sensors
use the unipolar mode of operation for the ADC. External analog input channels can
operate in unipolar or bipolar modes (see Analog Inputs and ADC Channel Analog-Input
Mode (4Ch, 4Dh, and 78h)).

IMPORTANT: For the ADC to function as specified, the power supplies and reference options must be
configured correctly.

The required package ball connections are shown in Figure 1-2. The PCB layout and external
component selection are important for ensuring optimal ADC performance and are covered
in Chapter 5.

RECOMMENDED: Read Chapter 5 before the board design is started.

TIP: The ADC always produces a 16-bit conversion result, and the full 16-bit result is stored in the
16-bit status registers. The 10-bit transfer functions shown in this section correspond to the 10 MSBs
(most significant or left-most bits) in the 16-bit status registers. The six LSBs can be used to minimize
quantization effects or improve resolution through averaging or filtering.

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Unipolar Mode
Figure 2-1 shows the 10-bit unipolar transfer function for the ADC. The nominal analog
input range to the ADC is 0V to 1V in this mode. The ADC produces a zero code (000h)
when 0V is present on the ADC input and a full scale code of all 1s (3FFh) when 1V is
present on the input.

The ADC output coding in unipolar mode is straight binary. The designed code transitions
occur at successive integer LSB values such as one LSB, two LSBs, and three LSBs (and so
on). The LSB size in volts is equal to 1V/210 or 1V/1024 = 977 µV. The analog input channels
are differential and require both the positive (VP) and negative (VN) inputs of the differential
input to be driven. For more information, see the Analog Inputs section.
X-Ref Target - Figure 2-1

Output Code Full Scale

Transition
3FF
Full Scale Input = 1V
3FE 1 LSB = 1V / 1024 = 977 μV

3FD
10-Bit Output Code (Hex)

004

003

002

001

000
1 2 3 999

Input Voltage (mV)

UG580_c2_01_100712

Figure 2-1: Unipolar Transfer Function

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Bipolar Mode
When the external analog input channels of the ADC are configured as bipolar, they can
accommodate true differential and bipolar analog signal types (see the Analog Inputs
section). When dealing with differential signal types, it is useful to have both sign and
magnitude information about the analog input signal. Figure 2-2 shows the ideal transfer
function for bipolar mode operation. The output coding of the ADC in bipolar mode is two’s
complement and indicates the sign of the input signal on V P relative to V N. The designed
code transitions occur at successive integer LSB values, that is, one LSB, two LSBs,
three LSBs, etc. The LSB size in volts is equal to 1V/2 10 or 1V/1024 = 977 µV.
X-Ref Target - Figure 2-2

Output Code
(Two’s Complement Coding)

1FFh
Full Scale Input = 1V
1FEh 1 LSB = 1V / 1024 = 977 μV

002h
10-Bit Output Code

001h

000h

3FFh

3FEh

3FDh

201h

200h

–500 –3 –2 –1 0 +1 +2 +499

Input Voltage (mV)

UG580_c2_02_032813

Figure 2-2: Bipolar Transfer Function

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 Chapter 2: Basic Functionality

Analog Inputs
The analog inputs of the ADC use a differential sampling scheme to reduce the effects of
common-mode noise signals. This common-mode rejection improves the ADC performance
in noisy digital environments. Figure 2-3 shows the benefits of a differential sampling
scheme. Common ground impedances (RG) easily couple noise voltages (switching digital
currents) into other parts of a system. These noise signals can be 100 mV or more. For the
ADC, this noise voltage is equivalent to hundreds of LSBs, thus inducing large measurement
errors. The differential sampling scheme samples both the signal and any common mode
noise voltages at both analog inputs (VP and VN). The common mode signal is effectively
subtracted because the track-and-hold amplifier captures the difference between VP and
VN or V P minus VN. To take advantage of the high common mode rejection, connect VP and
VN in a differential configuration.
X-Ref Target - Figure 2-3

Differential
Sampling
VP +
Noise T/H
Current –
VN
Noise
Voltage RG(1)

Common Noise Common Mode

on VP and VN 1V Rejection removes
1V
VP noise VP – VN

VN

0V 0V

Note 1: RG is common ground impedance.

UG580_c2_03_110612

Figure 2-3: Common Mode Noise Rejection

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Auxiliary Analog Inputs

The auxiliary analog inputs (VAUXP[15:0] and VAUXN[15:0]) are analog inputs that are
shared with regular digital I/O package balls. Only the auxiliary inputs connected in a
design are enabled as analog inputs. The SYSMON auxiliary inputs pins are labeled in the
UltraScale Architecture Packaging and Pinout Specification (UG575) [Ref 3] by appending
_ADxP_ and _ADxN_ to the I/O name, where x is the auxiliary pair number. For example, the
auxiliary input VAUXP[15] could be designated IO_LxxP_xx_AD15P_xx in the pinout
specification.

When designated as analog inputs, these inputs are unavailable for use as digital I/Os. If the
I/O is used as a digital I/O, it is subject to the specifications of the configured I/O standard.

IMPORTANT: If the I/O is used as an analog input, the input voltage must adhere to the specifications
given in the analog-to-digital converter table in the data sheets.

Additionally, the I/O standard should be set to ANALOG. As an example, to assign VAUXP0
and VAUXN0 to the ANALOG I/O standard:

set_property PACKAGE_PIN <arg> [get_ports VAUXP0]

set_property PACKAGE_PIN <arg> [get_ports VAUXN0]
set_property IOSTANDARD ANALOG [get_ports VAUXP0]
set_property IOSTANDARD ANALOG [get_ports VAUXN0]

It is possible to enable any number of auxiliary analog inputs in an I/O bank and use the
remaining as digital I/Os. If there is a mixture of analog and digital I/Os in a bank, the I/O
bank must be powered by a supply required to meet the specifications of the digital I/O
standard in used. The analog input signal should not exceed the I/O bank supply voltage
(VCCO) in this case.

Adjusting the Acquisition Settling Time

The maximum conversion rate specified for the ADC is 0.2 MSPS or a conversion time of
5 µs. In continuous sampling mode, 26 ADCCLK cycles are required to acquire an analog
signal and perform a conversion. This implies a maximum ADCCLK frequency of 5.2 MHz. If
the ACQ (see Control Registers) bit has not been set, four ADCCLKs or 769 ns is allowed for
the final stages of the acquisition. This settling time ensures that the analog input voltage
is acquired to a 10-bit accuracy. The settling time can be increased by reducing the ADCCLK
frequency or setting the ACQ bit (single channel, 40h) or the associated ACQ bit for the
sequencer (SEQACQ[2:0], 4Eh, 4Fh, 79h). In the latter case, assuming 5.2 MHz clock, the
settling time is increased to 1923 ns (10 ADCCLK cycles), and the conversion rate would be
reduced to 162 kSPS for the same ADCCLK frequency. In event timing mode, initiate the
conversion cycle by using CONVST or CONVSTCLK, allowing more control over the
acquisition time, if required.

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Analog Input Description

Figure 2-4 illustrates an equivalent analog input circuit for the external analog input
channels in both unipolar and bipolar configurations. The analog inputs consist of a
sampling switch and a sampling capacitor used to acquire the analog input signal for
conversion. During the ADC acquisition phase, the sampling switch is closed, and the
sampling capacitor is charged up to the voltage on the analog input. The time needed to
charge this capacitor to its final value (±0.5 LSBs at 10 bits) is determined by the
capacitance of the sampling capacitor (CSAMPLE), the resistance of the analog multiplexer
circuit (RMUX), and any external (source) impedance.
X-Ref Target - Figure 2-4

Unipolar Mode Bipolar Mode

RMUX RMUX
VP VP

Dedicated Inputs 100Ω Dedicated Inputs 100Ω

Auxiliary Inputs 10 kΩ CSAMPLE Auxiliary Inputs 10 kΩ CSAMPLE

3 pF To ADC 3 pF To ADC
RMUX RMUX
VN VN
Dedicated Inputs 100Ω Dedicated Inputs 100Ω
Auxiliary Inputs 10 kΩ Auxiliary Inputs 10 kΩ CSAMPLE

3 pF
UG580_c2_04_110612

Figure 2-4: Equivalent Analog Input Circuits

The required 10-bit acquisition time (assuming no additional external or source resistance)
in bipolar mode for example is approximated by:

t ACQ = 7.6 × R MUX × C SAMPLE Equation 2-1

The time constant 7.6 is derived from TC = Ln 2 (N + m), where N = 10 for a 10-bit system and
m = 1 additional resolution bit. The required 10-bit acquisition time in unipolar mode is
approximated:

t ACQ = 7.6 × ( R MUX + R MUX ) × C SAMPLE Equation 2-2

For the dedicated channel (VP/VN), the minimum acquisition time (bipolar mode) required
is given by:
– 12
t ACQ = 7.6 × 100 × 3 × 10 = 2.3 ns Equation 2-3

The auxiliary analog channels (such as, VAUXP[15:0] and VAUXN[15:0]) have a much larger
R MUX resistance that is approximately equal to 10 kΩ. Equation 2-4 shows the minimum
acquisition time in bipolar mode.
3 – 12
t ACQ = 7.6 × ( 10 × 10 ) × ( 3 × 10 ) = 230 ns Equation 2-4

Any additional external resistance, such as the anti-alias filter or resistor divider, increases
the acquisition time requirement due to the increased RMUX value in Equation 2-1. To

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 Chapter 2: Basic Functionality

calculate the new acquisition time, convert any external resistance to a series equivalent
resistance value and add to the RMUX resistance specified in Equation 2-3 and Equation 2-4.
For more information and design considerations for driving the ADC inputs, see Driving the
Xilinx Analog-to-Digital Converter (XAPP795) [Ref 5].

Unipolar Input Signals

When measuring unipolar analog input signals, the ADC must operate in a unipolar input
mode. This mode is selected by writing to configuration register 0 (see Control Registers,
page 36). When unipolar operation is enabled, the differential analog inputs (VP and VN)
have an input range of 0V to 1.0V. In this mode, the voltage on VP (measured with respect
to VN) must always be positive. Figure 2-5 shows a typical application of unipolar mode.
The V N input should always be driven by an external analog signal. VN is typically connected
to a local ground or common mode signal. The common mode signal on V N can vary from
0V to +0.5V (measured with respect to GNDADC). Because the differential input range is
from 0V to 1.0V (V P to V N), the maximum signal on V P is 1.5V. Figure 2-5 shows the
maximum signal levels on V N and VP in unipolar mode, measured with respect to analog
ground (GNDADC package ball).
X-Ref Target - Figure 2-5

VP, VN

2.5V VP

2V 0V to 1V ADC
Peak voltage on VP
1.5V VN
(Volts)

VP
Common Voltage
1V
0V to 0.5V
0.5V Common
Mode Range
0V
VN (Common Mode)
UG580_c2_05_110612

Figure 2-5: Unipolar Input Signal Range

Bipolar Input Signals

The analog inputs can accommodate analog input signals that are positive and negative
with respect to a common mode or reference. To accommodate these types of signals, the
analog input must be configured to bipolar mode. Bipolar mode is selected by writing to
configuration register 0 (see Control Registers). All input voltages must be positive with
respect to analog ground (GNDADC).

When bipolar operation is enabled, the differential analog input (VP – VN) can have a
maximum input range of ±0.5V. The common mode or reference voltage should not exceed
0.5V in this case (see Figure 2-6).

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X-Ref Target - Figure 2-6

VP, VN
±0.5V
VP

2V
ADC

Volts
1.5V
0.5V VN
1V
VP= ±0.5V
0.5V
VN = 0.5V
0V
UG580_c2_06_110612

Figure 2-6: Bipolar Input Signal Range

The bipolar input mode also accommodates inputs signals driven from a true differential
source, for example, a balanced bridge. In this case, VN and V P can swing positive and
negative relative to a common mode or reference voltage (see Figure 2-7). The maximum
differential input (VP – VN) is ±0.5V. With maximum differential input voltages of ±0.5V and
assuming balanced inputs on V N and VP,, the common mode voltage must lie in the range
0.25V to 0.75V.
X-Ref Target - Figure 2-7

VP, VN

2.5V
Common + ±0.25V VP
2V Common Mode Range Voltage
0.25V to 0.75V 0.25V to 0.75V
Volts

1.5V VCM = (VP + VN) / 2 + ADC

VN
VP
1V ±0.25V
VN

0.5V

0V
UG580_c2_07_110612

Figure 2-7: Differential Input Signal Range

Temperature Sensor
The SYSMON contains a temperature sensor that produces a voltage output proportional to
the die temperature. Equation 2-5 shows the output voltage of the temperature sensor.
κT
Voltage = 10 × ----- × ln ( 10 ) Equation 2-5
q
Where:

κ = Boltzmann’s constant = 1.38 x 10 –23 J/K

T = Temperature K (Kelvin) = °C + 273.15

q = Charge on an electron = 1.6 x 10–19 C

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 Chapter 2: Basic Functionality

The output voltage of this sensor is digitized by the ADC to produce a 10-bit digital output
code (ADC code). Figure 2-8 illustrates the digital output transfer function for this
temperature sensor.

For simplification, the temperature sensor plus the ADC transfer function is rewritten as:
ADC Code × 503.975
Temperatur e ( °C ) = ---------------------------------------------- – 273.15 Equation 2-6
1024
X-Ref Target - Figure 2-8

3FFh

3FEh

3FDh
Full Scale
10-Bit Output Code (Hex)

Transition
1LSB = 0.49°C

004h

003h

002h

001h

000h

0 1 2 3 605 1022 1023

–273°C

–272.5°C

–272°C

–271.5°C

+24.76°C

+230.5°C

Temperature (°C)
UG580_c2_08_100712

Figure 2-8: Temperature Sensor Transfer Function

The temperature measurement result is stored in the status registers at DRP address 00h.
Monitoring device on-chip temperature avoids functional and irreversible failures by
ensuring critical operating temperatures are not exceeded.

Power Supply Sensor

The SYSMON also includes on-chip sensors that allow monitoring of the device
power-supply voltages using the ADC. The sensors sample and attenuate the power supply
voltages VUSER[3:0], VCCINT,VCCAUX , and VCCBRAM on the package power supply balls.
Supply voltages are attenuated by a factor of three. The exception is when VUSER is
connected to a supply in an HRIO bank and the voltage is attenuated by a factor of six.

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Figure 2-9 shows the power-supply sensor transfer function after digitizing by the ADC. The
power supply sensor can be used to measure voltages in the range 0V to VCCAUX + 3% with
a resolution of approximately 2.93 mV. The transfer function for the supply sensor is shown
in Equation 2-7.
ADC Code
Voltage = ------------------------ × 3V Equation 2-7
1024
The power-supply measurement results for VCCINT,VCCAUX , and VCCBRAM are stored in the
status registers at DRP addresses 01h, 02h, and 06h, respectively.
X-Ref Target - Figure 2-9

Output Code
Full Scale
Transition
3FFh

3FEh
1 LSB = 2.93 mV

355h
10-Bit Output Code

155h

004h

003h

002h

001h

000h
2.93 mV

5.86 mV

8.79 mV

1.00V

2.50V

2.994V

2.997V

Supply Voltage (Volts)

UG580_c2_09_100712

Figure 2-9: Ideal Power Supply Transfer Function (All Supplies, Excluding VUSER HRIO)
The power supply measurement results for VUSER0, VUSER1, VUSER2, and VUSER3 are stored in
the status registers at DRP addresses 80h, 81h, 82h, and 83h, respectively. When the VUSER
supply is attached to an HP I/O bank, the transfer function is:
ADC Code
Voltage = ------------------------ × 3V Equation 2-8
1024

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 Chapter 2: Basic Functionality

To support the wider voltage ranges of HR I/O banks, when the VUSER supply is attached to
an HR I/O bank, the transfer function is attenuated, as shown in Equation 2-9. See
Figure 2-10.
ADC Code
Voltage = ------------------------ × 6V Equation 2-9
1024
X-Ref Target - Figure 2-10

Output Code
Full Scale
Transition
3FFh

3FEh
1 LSB = 5.86 mV

355h
10-Bit Output Code

155h

004h

003h

002h

001h

000h
5.86 mV

11.72 mV

17.58 mV

1.00V

1.998V

4.998V

5.988V

5.994V
Supply Voltage (Volts)
UG580_c2_10_101413

Figure 2-10: Ideal Power Supply Transfer Function for USER Supply (HRIO)

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 Chapter 3

SYSMON Register Interface

Figure 3-1 illustrates the SYSMON register interface. All registers in the register interface
are accessible through the dynamic reconfiguration port (DRP). The DRP can be accessed by
the SYSMONE1 DRP interface, the I2C interface, or the JTAG TAP. Access is governed by an
arbitrator (see DRP Arbitration). The DRP allows access up to 128 16-bit registers
(DADDR[7:0] = 00h to 7Fh). The access locations DADDR[7:0] = 00h to 3Fh and
DADDR[7:0] = 80h to FFh are read-only and contain the ADC measurement data. These
registers are status registers. The control registers are located at addresses 40h to 7Fh and
are readable or writable through the DRP.
X-Ref Target - Figure 3-1

6WDWXV5HJLVWHUV
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8*BFBB

Figure 3-1: SYSMON Register Interface

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 Chapter 3: SYSMON Register Interface

For a detailed description of the DRP timing, see Dynamic Reconfiguration Port (DRP)
Timing. For more information on the JTAG DRP interface, see DRP JTAG Interface.

Dynamic Reconfiguration Port (DRP) Timing

Figure 3-2 illustrates a DRP read and write operation. When the DEN is pulsed High for a
single clock cycle, the DRP address (DADDR) and write enable (DWE) inputs are captured on
the next rising edge of DCLK. DEN should only transition High for one DCLK period.

If DWE is a logic Low, a DRP read operation is carried out. The data for this read operation
is valid on the DO bus when DRDY transitions High. Thus, DRDY should be used to capture
the DO bus. For a write operation, the DWE signal is a logic High and the DI bus and DRP
address (DADDR) is captured on the next rising edge of DCLK. The DRDY signal transitions
to a logic High when the data has been successfully written to the DRP register. A new read
or write operation cannot be initiated until the DRDY signal transitions Low.

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X-Ref Target - Figure 3-2

t1
DCLK 1 2 3 4 5
t2
t3
DEN
t5
t4
DWE
t7
t6
DADDR[7:0]

t8 t9

DI[15:0]

t10

DO[15:0]
t11
t11
DRDY
t12
t12
EOC/EOS

t13
ALM[2.0]/OT

t14 t11 t14

BUSY

t15

CHANNEL[5:0]

UG580_c3_02_100712

Figure 3-2: DRP Detailed Timing

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Status Registers
The status registers ( 00h-3Fh, 80h-BFh) contain the measurement results of the
analog-to-digital conversions, the flag registers, and the calibration coefficients as shown
in Table 3-1.

Table 3-1: Status Registers (Read Only)

Name Address Description
The result of the on-chip temperature sensor measurement is stored in this
Temperature 00h location. The data is MSB justified in the 16-bit register. The 10 MSBs
correspond to the temperature sensor transfer function shown in Figure 2-8.
The result of the on-chip VCCINT supply monitor measurement is stored at this
VCCINT 01h location. The data is MSB justified in the 16-bit register. The 10 MSBs
correspond to the supply sensor transfer function shown in Figure 2-9.
The result of the on-chip VCCAUX data supply monitor measurement is stored
VCCAUX 02h at this location. The data is MSB justified in the 16-bit register. The 10 MSBs
correspond to the supply sensor transfer function shown in Figure 2-9.
The result of a conversion on the dedicated analog input channel is stored in
this register. The data is MSB justified in the 16-bit register. The 10 MSBs
V P/V N 03h
correspond to the transfer function shown in Figure 2-5 or Figure 2-6
depending on analog input mode settings.
The result of a conversion on the reference input V REFP is stored in this register.
The 10 MSBs correspond to the ADC transfer function shown in Figure 2-9. The
V REFP 04h
data is MSB justified in the 16-bit register. The supply sensor is used when
measuring VREFP.
The result of a conversion on the reference input VREFN is stored in this register.
This channel is measured in bipolar mode with a two’s complement output
coding as shown in Figure 2-2. By measuring in bipolar mode, small positive
V REFN 05h
and negative offset around 0V (VREFN ) can be measured. The supply sensor is
also used to measure VREFN , thus 1 LSB = 3V/1024. The data is MSB justified in
the 16-bit register.
The result of the on-chip VCCBRAM supply monitor measurement is stored at
VCCBRAM 06h this location. The data is MSB justified in the 16-bit register. The 10 MSBs
correspond to the supply sensor transfer function shown in Figure 2-9.
Reserved 07h This location is reserved.
The calibration coefficient for the supply sensor offset using ADC is stored at
Supply Offset 08h
this location.
ADC Offset 09h The calibration coefficient for the ADC offset is stored at this location.
ADC Gain 0Ah The calibration coefficient for the ADC gain error is stored at this location.
Undefined 0Bh to 0Fh These locations are unused and contain invalid data.
The results of the conversions on auxiliary analog input channels are stored in
VAUXP[15:0]/ this register. The data is MSB justified in the 16-bit register. The 10 MSBs
10h to 1Fh
VAUXN[15:0] correspond to the transfer function shown in Figure 2-1 or Figure 2-2
depending on analog input mode settings.

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Table 3-1: Status Registers (Read Only) (Cont’d)

Name Address Description
Maximum temperature measurement recorded since power-up or the last
Max Temp 20h
SYSMON reset.
Maximum VCCINT measurement recorded since power-up or the last SYSMON
Max VCCINT 21h
reset.
Maximum VCCAUX measurement recorded since power-up or the last SYSMON
Max VCCAUX 22h
reset.
Maximum VCCBRAM measurement recorded since power-up or the last
Max VCCBRAM 23h
SYSMON reset.
Minimum temperature measurement recorded since power-up or the last
Min Temp 24h
SYSMON reset.
Minimum VCCINT measurement recorded since power-up or the last SYSMON
Min VCCINT 25h
reset.
Minimum VCCAUX measurement recorded since power-up or the last SYSMON
Min VCCAUX 26h
reset.
Minimum VCCBRAM measurement recorded since power-up or the last SYSMON
Min VCCBRAM 27h
reset.
Reserved 28h to 3Dh These locations are reserved.
Flag1, Flag0 3Eh to 3Fh This register contains general status information (see Flag Register).
The result of the on-chip V USER0 supply monitor measurement is stored at this
V USER0 80h
location. The data is MSB justified in the 16-bit register.
The result of the on-chip V USER1 supply monitor measurement is stored at this
V USER1 81h
location. The data is MSB justified in the 16-bit register.
The result of the on-chip VUSER2 supply monitor measurement is stored at this
V USER2 82h
location. The data is MSB justified in the 16-bit register.
The result of the on-chip V USER3 supply monitor measurement is stored at this
V USER3 83h
location. The data is MSB justified in the 16-bit register.
Maximum V USER0 measurement recorded since power-up or the last SYSMON
Max VUSER0 A0h
reset.
Maximum V USER1 measurement recorded since power-up or the last SYSMON
Max VUSER1 A1h
reset.
Maximum V USER2 measurement recorded since power-up or the last SYSMON
Max VUSER2 A2h
reset.
Maximum V USER3 measurement recorded since power-up or the last SYSMON
Max VUSER3 A3h
reset.
Minimum V USER0 measurement recorded since power-up or the last SYSMON
Min V USER0 A8h
reset.
Minimum V USER1 measurement recorded since power-up or the last SYSMON
Min V USER1 A9h
reset.
Minimum V USER2 measurement recorded since power-up or the last SYSMON
Min V USER2 AAh
reset.
Minimum V USER3 measurement recorded since power-up or the last SYSMON
Min V USER3 ABh
reset.

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Measurement Registers
Measurement results from the analog-to-digital conversions are stored as 16-bit results in
the status registers. As shown in Figure 3-3, the 10-bit data corresponds to the 10 MSBs
(most significant or left-most bits) in the 16-bit registers. The unreferenced LSBs can be
used to minimize quantization effects or improve the resolution through averaging or
filtering.

Maximum and minimum measurements are additionally recorded for the on-chip sensors
from the device power-up or the last user reset of the SYSMON. Table 3-1 defines the status
registers.

The SYSMON also tracks the minimum and maximum values recorded for the internal
sensors since the last power-up or since the last reset of the SYSMON control logic (see
Figure 3-1 and Table 3-1 for minimum/maximum register addresses.) On power-up or after
reset, all minimum registers are set to FFFFh, and all maximum registers are set to 0000h.
Each new measurement generated for an on-chip sensor is compared to the contents of its
maximum and minimum registers. If the measured value is greater than the contents of its
maximum registers, the measured value is written to the maximum register. Similarly, for the
minimum register, if the measured value is less than the contents of its minimum register,
the measured value is written to the minimum register. This check is carried out every time
a measurement result is written to the status registers.
X-Ref Target - Figure 3-3

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Measurement Registers
DATA[9:0] Note
(00h-07h, 10h-2Fh)
UG580_c3_02a_022813

Figure 3-3: Measurement Registers

IMPORTANT: The ADCs always produce a 16-bit conversion result, and the full 16-bit result is stored in
the 16-bit status registers. The 10-bit data correspond to the 10 MSBs (most significant or left-most
bits) in the 16-bit status registers. The unreferenced LSBs can be used to minimize quantization effects
or improve resolution through averaging or filtering.

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Flag Register
The flag register is shown in Figure 3-4. The bit definitions are described in Table 3-2.
X-Ref Target - Figure 3-4

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X X X X X REF X X X X ALM3 OT ALM2 ALM1 ALM0 Flag Register 0 (3Fh)

X X X X X X X X X X X X ALM11 ALM10 ALM9 ALM8 Flag Register 1 (3Eh)

UG580_c3_03_100713

Figure 3-4: Flag Registers

Table 3-2: Flag Register Bit Definitions

Name Description
ALM11 to ALM0 Indicates the status of the alarm outputs ALM[11:8, 2:0]
OT Status of Over Temperature logic output
REF Indicates System Monitor ADC is using the internal voltage reference (High) or
external reference (Low)

SYSMON Calibration Coefficients

The SYSMON can digitally calibrate out any offset and gain errors in the ADC and power
supply sensor using the calibration registers (see Figure 3-5). By connecting known
voltages (VREFP and VREFN as opposed to the internal reference) to the ADC and the supply
sensor, the offset and gain errors can be calculated and correction coefficients generated.
These calibration coefficients are stored in status registers 08h to 0Ah (see Table 3-1).
X-Ref Target - Figure 3-5

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SYSMON Supply Offset (08h)

DATA[9:0] NOTE
SYSMON Bipolar Offset (09h)

N/A Sign MAG[5:0] SYSMON Gain (0Ah)

Note: The ADCs always produce a 16-bit conversion result. The 10-bit data correspond to the 10 MSBs (most significant)
in the 16-bit status registers. The unreferenced LSBs can be used to minimize quantization. UG580_c3_03a_120213

Figure 3-5: Calibration Registers

Table 3-3: Calibration Register Bit Definitions

Name Description
CAL_OFFSET[9:0] Offset correction factor for the supply sensor (unipolar mode) recorded in two’s
complement.
CAL_BIPOLAR_OFFSET[9:0] Offset correction for the supply sensor (bipolar mode).
SIGN Sign bit for calibration. Positive when 1 or negative when 0.
MAG[5:0] Magnitude of calibration.

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The SYSMON has a built-in calibration function that automatically calculates these
coefficients. By initiating a conversion on channel 8 (08h), all calibration coefficients are
calculated. The SYSMON default operating mode automatically uses calibration. When not
operating in the default mode, these calibration coefficients are applied to all ADC
measurements by enabling the calibration bits (CAL0–3) in configuration register 1 (41h)
(see Table 3-6).

BUSY transitions High for the duration of the entire calibration sequence (conversion on
channel 8). This calibration sequence is six times longer than a regular conversion on a
sensor channel as offset and gain are measured for the ADC and the power supply sensor.

Calibration Coefficients Definition

The offset and gain calibration coefficients are stored in the status registers. This section
explains how to interpret the values in these registers. These are read-only registers, and
the contents cannot be modified using the DRP.

Offset Coefficients

The offset calibration registers store the offset correction factor for the supply sensor and
ADC. The offset correction factor is a 10-bit, two’s complement number and is expressed in
LSBs. Similar to other status registers, the 10-bit values are MSB justified in the registers.
For example, if the ADC has an offset of +10 LSBs (approximately 10 x 977 μV = 9.77 mV),
the offset coefficient records –10 LSBs or FF6h (status register 08h). For the supply sensor,
the LSB size is approximately 2930 μV, thus a +10 LSB offset is equivalent to 29.3 mV of
offset in the supply measurement.

Gain Coefficients

The ADC gain calibration coefficient stores the correction factor for any gain error in the
ADC. The correction factor is stored in the seven LSBs of register 0Ah. These seven bits store
both sign and magnitude information for the gain correction factor. If the seventh bit is a
logic 1, the correction factor is positive. If it is 0, the correction factor is negative. The next
six bits store the magnitude of the gain correction factor. Each bit is equivalent to 0.1%.

For example, if the ADC has a positive gain error of +1%, then the gain calibration
coefficient records –1% (the –1% correction applied to cancel the +1% error). Because the
correction factor is negative, the seventh bit is set to zero. The remaining magnitude bits
record 1%, where 1% = 10 x 0.1% and 10 = 1010 binary. The status register 0Ah records
0000 0000 0000 1010. With six bits assigned to the magnitude, the calibration can
correct errors in the range ± 0.1% x (25 – 1), or ± 3.1%.

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 Chapter 3: SYSMON Register Interface

Control Registers
The SYSMON control registers are used to configure the SYSMON operation. All SYSMON
functionality is controlled through these registers.

These control registers are initialized using the SYSMON attributes when the SYSMON is
instantiated in a design. This means that the SYSMON can be configured to start in a
predefined mode after device configuration.

Table 3-4: SYSMON Control Registers

Name Address SYSMONE1 Attribute(1) Description
Configuration Registers 40h to 44h INIT_40 to INIT_44 These are SYSMON configuration
registers (see Configuration Registers
(40h to 43h)).
Sequence registers 46h to 4Fh, 78, 79 INIT_46 to INIT_4F, These registers are used to program
INIT_78, INIT_79 the channel sequencer function (see
SYSMON Operating Modes in
Chapter 4).
Alarm registers 50h to 6Fh INIT_50 to INIT_6F These are the alarm threshold
registers for the SYSMON alarm
function (see Automatic Alarms).
1. SYSMONE1 attributes set SYSMONE1 operation after configuration is completed.

Configuration Registers (40h to 43h)

The SYSMON configuration registers are the first four registers in the control register block,
and are used to configure the SYSMON operating modes. The configuration register bit
definitions are listed in Figure 3-6.

IMPORTANT: Bits shown as 0 should always be set to 0.

The configuration registers can be modified through the DRP after the device has been
configured. For example, a soft microprocessor or state machine can be used to alter the
contents of the SYSMON control registers at any time during normal operation. Table 3-5
through Table 3-7 define the bits for the three configuration registers.
X-Ref Target - Figure 3-6

', ', ', ', ', ', ', ', ', ', ', ', ', ', ', ',
&$9* ; $9* $9* 08; %8 (& $&4 ; ; &+ &+ &+ &+ &+ &+ &RQILJ5HJK
6(4 6(4 6(4 6(4 $/0 $/0 $/0 $/0 &$/ &$/ &$/ &$/ $/0 $/0 $/0 27 &RQILJ5HJK
&' &' &' &' &' &' &' &' ; ; ; 3' ; ; ; ; &RQILJ5HJK
,&B25 ,&B$>@ ,&B$>@ ,&B$>@ ,&B$>@ ,&B$>@ ,&B$>@ ,&B$>@ ,&B(1 ; ; ; $/0 $/0 $/0 $/0 &RQILJ5HJK
8*BFBB

Figure 3-6: Configuration Registers Bit Definitions

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Table 3-5: Configuration Register Bit Definitions

Name Description
CH5 to CH0 When operating in Single Channel mode or External Multiplexer mode,
these bits are used to select the ADC input channel. See Table 3-6.
ACQ Adjusts acquisition time available on external analog inputs in Continuous
Sampling mode. Four ADCCLK cycles (Low) or ten ADCCLK cycles (High).
See ADC Channel Settling Time (4Eh, 4Fh, and 79h)for controlling the
acquisition times using the automatic channel sequencer.
BU In Single Channel mode, selects Unipolar (Low) or Bipolar (High) operating
mode for the ADC analog inputs (see Analog Inputs ).
EC Selects Continuous (Low) or Event (High) driven sampling mode for the
ADC (see Dynamic Reconfiguration Port (DRP) Timing).
MUX Enables (High) external multiplexer mode. See Chapter 4, SYSMON
Operating Modes for more information.
AVG1, AVG0 Sets the amount of sample averaging on selected channels in both Single
Channel and Sequence modes (see Table 3-7).
CAVG Disables (High) averaging for the calculation of the calibration coefficients.
Averaging is enabled by default (Low). Averaging is fixed at 16 samples.
OT Disables (High) the Over-Temperature signal.
ALM0 to ALM6 and ALM8 to ALM11 Disables (High) individual alarm outputs for the corresponding alarm.
SEQ0 to, SEQ3 Enables (High) the channel-sequencer function (see Table 3-8).
CAL0 to CAL3 Enables (High) the application of the calibration coefficients to the ADC
and on-chip supply sensor measurements. A logic 1 enables calibration
and a logic 0 disables calibration.
PD0 Power down System Monitor when PD0 (High). By default enabled with
PD0 (Low). If powered down for an extended length of time, performance
might degrade. SYSMON should not be used.
CD7 to CD0 Selects the division ratio between the DRP clock (DCLK) and the lower
frequency ADC clock (ADCCLK) used for the ADC (Dynamic
Reconfiguration Port (DRP) Timing).
I2C_EN I2C Enable. When High allows I2C interface to be used after configuration.
I2C_A[6:0] I2C Address used only when I2C_OR is High.
I2C_OR I2C Address override. When High, I2C address is based on I2C_A[6:0]. When
Low, I2C address is determined at power-up by the four MSBs of the
dedicated analog input channel (Vp/Vn) as shown in Table 3-12.

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Table 3-6: ADC Channel Select

ADC
Channel CH5 CH4 CH3 CH2 CH1 CH0 Description

0 0 0 0 0 0 0 On-chip temperature
1 0 0 0 0 0 1 Average on-chip VCCINT
2 0 0 0 0 1 0 Average on-chip VCCAUX
3 0 0 0 0 1 1 V P, V N - Dedicated analog inputs
4 0 0 0 1 0 0 V REFP (1.25V)
5 0 0 0 1 0 1 V REFN (0V)
6 0 0 0 1 1 0 Average on-chip VCCBRAM
7 0 0 0 1 1 1 Invalid channel selection
8 0 0 1 0 0 0 Carry out a SYSMON calibration
15–9 0 ... ... ... ... ... Invalid channel selection
16 0 1 0 0 0 0 VAUXP[0], VAUXN[0] – Auxiliary channel 1
17 0 1 0 0 0 1 VAUXP[1], VAUXN[1] – Auxiliary channel 2
VAUXP[2:15], VAUXN[2:15] – Auxiliary channels
31–18 0 ... ... ... ... ...
3to 16
32 1 0 0 0 0 0 V User0 User Supply 0
33 1 0 0 0 0 1 V User1 User Supply 1
34 1 0 0 0 1 0 V User2 User Supply 2
35 1 0 0 0 1 1 V User3 User Supply 3
36+ 1 ... ... ... ... ... Invalid channel selection

Table 3-7: Averaging Filter Settings

AVG1 AVG0 Function
0 0 No averaging
0 1 Average 16 samples
1 0 Average 64 samples
1 1 Average 256 samples

Table 3-8: Sequencer Operation Settings

SEQ3 SEQ2 SEQ1 SEQ0 Function
0 0 0 0 Default mode
0 0 0 1 Single pass sequence
0 0 1 0 Continuous sequence mode
0 0 1 1 Single channel mode (sequencer off)
1 1 X X Default mode

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Table 3-9: Calibration Enables

Name Description
CAL0 ADC offset correction enable
CAL1 ADC offset and gain correction enable
CAL2 Supply sensor offset correction enable
CAL3 Supply sensor offset and gain correction enable

Table 3-10: DCLK Division Selections(1)

CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 Division
0 0 0 0 0 0 0 0 2
0 0 0 0 0 0 0 1 2
0 0 0 0 0 0 1 0 2
0 0 0 0 0 0 1 1 3
0 0 0 0 0 1 0 0 4
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
1 1 1 1 1 1 1 0 254
1 1 1 1 1 1 1 1 255

Notes:
1. Minimum division ratio is 2, for example, ADCCLK = DCLK/2.

Channel Sequencer Registers (46h to 4Fh, 78h, 79h)

These registers are used to program the channel sequencer functionality. For more
information, see Automatic Channel Sequencer.

Alarm Registers (50h to 6Fh)

These registers are used to program the alarm thresholds for the automatic alarms. For
more information, see Automatic Alarms.

DRP Arbitration
Because the DRP registers are accessed from three different ports (SYSMONE1 DRP
interface, I2C, and JTAG TAP), an arbitrator is implemented to manage potential conflicts.
Arbitration is managed on a per transaction basis (a transaction is a single read/write
operation to the DRP).

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Three status signals help manage access through the interconnect when the JTAG or I2C
port is also being used: JTAGBUSY, JTAGMODIFIED, and JTAGLOCKED.

DRP JTAG Interface

The SYSMON uses a full JTAG interface extension to the DRP interface. This allows
read/write access to the SYSMON DRP through the existing on-chip JTAG infrastructure. No
instantiation is required to access the DRP interface over JTAG. A boundary-scan instruction
(6-bit instruction = 110111) called SYSMON_DRP, added to UltraScale architecture-based
devices, allows access to the DRP through the JTAG TAP. All SYSMON JTAG instructions are
32 bits wide. For more information on the boundary-scan instructions and usage, see the
UltraScale Architecture Configuration User Guide (UG570) [Ref 4]. Read and write operations
using the SYSMON JTAG DRP interface are described in the next sections.

RECOMMENDED: If you are unfamiliar with basic JTAG functionality, you should become familiar with
the JTAG standard (IEEE standard 1149.1) before proceeding.

IMPORTANT: JTAG access can be limited to read only or completely disabled. To adjust the JTAG access,
add the following to an XDC file:
set_property BITSTREAM.GENERAL.JTAG_XADC <Enable|Disable|StatusOnly>
current_design_name
See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 2] for more
information on device configuration bitstream settings.

SYSMON DRP JTAG Write Operation

Figure 3-7 shows a timing diagram for a write operation to the SYSMON DRP through the
JTAG TAP. The DRP is accessed through the SYSMON data register (SYSMON DR). Before the
SYSMON DR is accessed, the instruction register (IR) must first be loaded with the SYSMON
instruction. The controller is placed in the IR-scan mode, and the SYSMON instruction is
shifted to the IR.

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X-Ref Target - Figure 3-7

TAP Controller States

TLR TLR RTI DRS IRS CIR SIR SIR SIR SIR EIR UIR DRS CDR SDR SDR SDR SDR SDR EDR UDR RTI RTI RTI DRS CDR

TCK

TMS

0 9 0 30 31

TDI LSB MSB LSB MSB

Load IR with Write DRP Command shifted into

SYSMON_DRP instructions SYSMON_DRP DR

TDO LSB MSB LSB MSB

Old IR Contents Old Contents of

SYSMON_DRP DR shifted out
Idle between successive
Writes to allow DRP Write
operation to finish
UG580_c3_05_112912

Figure 3-7: SYSMON JTAG DRP Write

After the SYSMON instruction is loaded, all data register (DR)-scan operations are carried
out on the SYSMON DR. When the data shifted into SYSMON DR is a JTAG DRP write
command, the SYSMON DRP arbitrator carries out a DRP write. The format of this write
command is described in JTAG DRP Commands. The SYSMON DR contents are transferred
to the SYSMON DRP arbitrator (see DRP Arbitration) during the Update-DR state. After the
Update-DR state, the arbitrator manages the new data transfer to the SYSMON DRP
register. This takes up to six DRP clock (DCLK) cycles if a DRP access from the interconnect
logic is already in progress.

During the Capture-DR phase (just before data is shifted into the SYSMON DR), DRP data is
captured from the arbitrator. Depending on the last JTAG DRP command, this data can be
old data, previously written to the DRP, or requested new read data (see SYSMON DRP JTAG
Read Operation). This captured data is shifted out (LSB first) on DO as the new JTAG DRP
command is shifted in. The 16 LSBs of this 32-bit word contain the JTAG DRP data. The
16 MSBs are set to zero.

If multiple writes to the SYSMON DR are taking place, it might be necessary to idle the TAP
controller for several TCK cycles before advancing to the next write operation (see
Figure 3-7). The idle cycles allow the arbitrator to complete the write operation to the
SYSMON DRP register. If DCLK is running approximately 6 x TCK, these idle states are not
necessary. However, inserting 10 or so idle states ensures all transfers are inherently safe.

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SYSMON DRP JTAG Read Operation

Figure 3-8 shows the timing for an SYSMON DR read operation. The IR should contain the
DR-scan operation (SYSMON_DRP instruction). A JTAG read from the SYSMON DRP is a
two-step operation.
X-Ref Target - Figure 3-8

TAP Controller States

UIR DRS CDR SDR SDR SDR SDR SDR EDR UDR RTI RTI RTI RTI DRS CDR SDR SDR SDR SDR SDR EDR UDR RTI RTI RTI RTI

TCK

TMS

0 30 31 0 30 31
TDI LSB MSB LSB MSB

Read Command shifted into Read Command shifted into

SYSMON DRP register SYSMON DRP Register

TDO LSB MSB LSB MSB

Old contents of Result of DRP Read

SYSMON DRP register shifted out

Monitor DRP instructions

Idle to allow DRP Read Idle to allow DRP Read
previously shifted into IR
to complete before to complete before
shifting out result shifting out result
UG580_c3_06_032913

Figure 3-8: SYSMON JTAG DRP Read

First, the SYSMON DR is loaded with the read DRP instruction. This instruction is transferred
to the arbitrator during the Update-DR state. Then the arbitrator reads the selected DRP
register and stores the newly read 16-bit data. This operation takes several DCLK cycles to
complete.

During the DR-Capture phase of the next DR-scan operation, newly read data is transferred
from the arbitrator to the SYSMON DR. This 16-bit data (stored in the 16 LSBs of the 32-bit
word) is then shifted out on TDO during the subsequent shift operation (see Figure 3-8).
The timing diagram shows several idle states at the end of the first DR-scan operation,
allowing the arbitrator enough time to fetch the SYSMON DRP data.

However, if the DCLK frequency is significantly faster than the TCK, these idle states might
not be required.

Implementing a DR-scan operation before the arbitrator has completed the DRP-read
operation results in old DRP data being transferred to the SYSMON DR during the
DR-capture phase.

To ensure reliable operation over all operating clock frequencies, a minimum of

10 run-test-idle (RTI) states should be inserted. Multiple read operations can be pipelined,

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as shown in Figure 3-8. Thus, as the result of a read operation is being shifted out of the
SYSMON DR, an instruction for the next read can be shifted in.

JTAG DRP Commands

The data shifted into the 32-bit SYSMON DR during a DR-scan operation instructs the
arbitrator to carry out a write, read, or no operation on the SYSMON DRP. Figure 3-9 shows
the data format of the JTAG DRP command loaded into the SYSMON DR. The first 16 LSBs
of SYSMON DR [15:0] contain the DRP register data. For both read and write operations, the
address bits SYSMON DR [25:16] hold the DRP target register address. The command bits
SYSMON DR [29:26] specify a read, write, or no operation (see Table 3-11).
X-Ref Target - Figure 3-9

31 30 29 26 25 16 15 0
X X CMD[3:0] DRP Address [9:0] DRP Data [15:0]

MSB SYSMON Data Register (SYSMON DR) LSB

UG580_c3_07_110612

Figure 3-9: SYSMON JTAG DRP Command

Table 3-11: JTAG DRP Commands

CMD[3:0] Operation
0 0 0 0 No operation
0 0 0 1 DRP read
0 0 1 0 DRP write
- - - - Not defined

It is also possible to enable the auxiliary analog input channel preconfiguration of the
device, allowing external analog voltages (on the PCB) to be monitored using the JTAG TAP
before configuration. The auxiliary channels are enabled by writing 0001h to DRP address
02h. This address lies within the read-only status register address space and normally holds
the result of a VCCAUX measurement. However, a write to this address enables the auxiliary
inputs. This function only works prior to configuration. After configuration, these inputs
must be explicitly instantiated in the design.

JTAGBUSY
JTAGBUSY becomes active during the update phase of a DRP transaction through the JTAG
TAP. This signal resets when the JTAG SYSMON DR transaction is completed. Each read/write
to the SYSMON DR is treated as an individual transaction. If DRP access initiates through
the interconnect port when JTAGBUSY is High, then the arbitrator queues this request for a
read/write through the interconnect logic. DRDY does not transition active until JTAGBUSY
transitions Low and the interconnect transaction is completed. A second DRP access
through the interconnect logic must not be initiated until the DRDY for the initial access

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becomes active and indicates the read/write was successful. If an interconnect access is in
progress when a JTAG DRP transaction initiates, the interconnect access is completed
before the JTAG transaction.

JTAGMODIFIED
Whenever there is a JTAG write (JTAG reads typically occur more often) to any register in the
DRP, the application (device) must be notified about the potential change of configuration.
Thus, the JTAGMODIFIED signal transitions High after a JTAG write. A subsequent DRP
read/write resets the signal.

JTAGLOCKED
When JTAG is used, in some cases it is simpler to take DRP ownership for a period by locking
out access through the interconnect. This is useful in a diagnostic situation where a large
number of DRP registers are modified through the JTAG TAP. When a JTAGLOCKED request
is made, the JTAGLOCKED signal transitions to the active-High state. The signal remains
High until the port is unlocked again. No read or write access is possible via the DRP port
when the JTAGLOCKED signal is High. The JTAGLOCKED signal is activated by writing 0001h
to DRP address 00h. The JTAGLOCKED signal is reset by writing 0000h to DRP address 00h.

JTAGLOCKED is also used to indicate when the DRP is ready for a read or write when the
DCLK is first connected or when DCLK becomes active again after a period of inactivity. It
can take up to 10 DCLK cycles for JTAGLOCKED to deassert Low after DCLK becomes active.

TIP: The SYSMON automatically switches over to an on-chip clock oscillator if a missing DCLK is
detected.

SYSMON JTAG Reset

A user reset of the SYSMON can also be initiated using the JTAG interface. The SYSMON is
reset by writing xxxxh (any 16-bit value) to DRP address 03h. The JTAG reset has the same
effect as pulsing the RESET pin.

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DRP I2C Interface

SYSMONE1 can be addressed as an I2C slave device allowing read/write access to the
SYSMONE1 DRP interface. I2C is a standardized 2-wire bus that is commonly used by device
manufacturers.

SYSMONE1 supports transfers up to 400 Kb/s, Standard-mode (Sm) and Fast-mode (Fm).
For slow interfaces, clock stretching is supported at the bit level, which means that the
I2C_SCLK low pulse will be extended if the I2C_SDA setup times are not met.
X-Ref Target - Figure 3-10

9&&

,&6ODYH
,&0DVWHU
6<6021(
,&6'$ ,2%8)
,2 2 ,&B6'$B,1
, ,&B6'$B76

,&6&/. ,2%8)
,2 2 ,&B6&/.B,1
, ,&B6&/.B76

8*BFBB

Figure 3-10: SYSMONE1 I2C DRP Interface

As shown in Figure 3-10, two package pins are required for the I2C serial clock (I2C_SCLK)
and I2C serial data (I2C_SDA) lines. Within the UltraScale architecture-based devices, the
I2C_SCLK and I2C_SDA contain dedicated connections to the SYSMONE1. The I2C_SCLK_IN,
I2C_SCLK_TS, I2C_SDA_IN, and I2C_SDA_TS must be connected to bidirectional buffers in
the design. These dedicated I2C connections are not accessible to the FPGA.

For post-configuration use of the DRP I2C interface, the System Management Wizard
should be used. The System Management Wizard sets the I2C_EN bit of the Control Register
43h High. The I2C_SDA (bidirectional) and I2C_SCLK (bidirectional) should be connected at
the top level with the I/O standard set to SYSMON_I2C.

When not used for I2C, the dual-purpose package pins for I2C_SDA and I2C_SCLK can be
used as general purpose I/O. The I2C_EN bit of the Control Register 43h must be set Low.

See the UltraScale Architecture Packaging and Pinout Specification (UG575) [Ref 3] for pin
location.

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I2C Read/Write Transfers

Access to the control and status registers is provided using I2C Write and Read transfers.
X-Ref Target - Figure 3-11

8*BFBB

Figure 3-11: SYSMONE1 I2C DRP Write

A M [6:0] 7-bit I2C slave address – master to slave

R/WM Read (1)/Write (0) command – master to slave
D M[31:0] 32-bit DRP command – master to slave
(uses same commands as listed in JTAG DRP Commands
Table 3-11)
ACKS Acknowledge – slave to master
SM Start command – master to slave
PM Stop command – master to slave

I2C uses open-collector signaling, which allows bidirectional data on I2C_SDA. Figure 3-11
shows how I2C_SDA and I2C_SCLK are used to send a write to SYSMONE1 DRP. Because
I2C_SDA is bidirectional, the master and slave devices control the I2C interface at different
times during a transfer. Data is transmitted eight bits at a time with an acknowledge from
the receiving device every eight bits. The transfer ends with the master device terminating
the transfer with a stop command.
X-Ref Target - Figure 3-12

8*BFBB

Figure 3-12: SYSMONE1 I2C DRP Combined Read

A M [6:0] 7-bit I2C slave address – master to slave

R/WM Read (1)/Write (0) command – master to slave
D M[31:0] 32-bit DRP read command – master to slave
D S[15:0] 16-bit DRP read data – slave to master
ACKM Acknowledge – master to slave
ACKS Acknowledge – slave to master
NACKS Not acknowledge – slave to master

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SM Start command – master to slave

Sr M Repeated start command – master to slave
PM Stop command – master to slave

Reading from status or control registers is performed with a combined format transfer, as
shown in Figure 3-12. After writing the 32-bit DRP command, a repeated start command is
sent followed by the read command. SYSMONE1 then takes over the transfer and sends the
data back to the master. After the master acknowledges the transfer, the master terminates
the transfer with a stop command.

I2C Slave Address Assignment

The I2C slave address is determined at power-up using the voltages on the dedicated
analog input channel VP/VN. After VCCADC is powered-up, the initial voltages on the VP/VN
channels are measured. This initial conversion occurs by the time INIT_B has been released.
The four MSBs are decoded to create the I2C slave address as shown in Table 3-12. After the
initial conversion, the VP/VN channels can be used for normal operation without affecting
the I2C slave address.

IMPORTANT: When using an external reference supply (V REF) and using the I2C slave address
(preconfiguration or post-configuration with I2C_OR = 0), ensure VREF is stable when the I2C slave
address is set.

When the I2C address override enable bit is set, the I2C_OR bit of Control Register 43h, the
value set in the I2C_A field of Control Register 43h is used as the slave address instead of
the decoded address from the dedicated inputs. The override address and override enable
can be set using DRP JTAG interface preconfiguration, in the configuration bitstream, or
after configuration using the DRP port or JTAG.

A simple external resistor divider circuit on the dedicated analog input channel V P/V N can
be used to adjust the voltage.

Table 3-12: I2C Slave Address Decoding

Vp/Vn Decoded
Vp/Vn (V) Status Reg I2C Slave Address
D[15:12] 04H (I2C_OR=0)
0.000 - 0.061 0000 0110010
0.062 - 0.124 0001 0001011
0.125 - 0.186 0010 0010011
0.187 - 0.249 0011 0011011
0.250 - 0.311 0100 0100011
0.312 - 0.374 0101 0101011
0.375 - 0.436 0110 0110011

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Table 3-12: I2C Slave Address Decoding

Vp/Vn Decoded
Vp/Vn (V) Status Reg I2C Slave Address
D[15:12] 04H (I2C_OR=0)
0.437 - 0.499 0111 0111011
0.500 - 0.561 1000 1000011
0.562 - 0.624 1001 1001011
0.625 - 0.686 1010 1010011
0.687 - 0.749 1011 1011011
0.750 - 0.811 1100 1100011
0.812 - 0.874 1101 1101011
0.875 – 0.9365 1110 1110011
0.9375 – 1.000 1111 0111010

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SYSMON Operating Modes

The SYSMON includes several operating modes that cover some of the most common use
cases for this kind of functionality. The most basic mode of operation is called default mode,
where the SYSMON monitors all on-chip sensors and requires no configuration of the
SYSMON.

Single Channel Mode

The single-channel mode is enabled when bits SEQ3 to SEQ0 in control register 41h are set
to 0011 (see Table 3-8). In this mode, select the channel for analog-to-digital conversion by
writing to bit locations CH4 to CH0 in control register 40h. Various configurations for single
channel mode, such as analog input mode (BU) and settling time (ACQ), must also be set by
writing to control register 40h. In applications where many channels need to be monitored,
there can be a significant overhead for the microprocessor or other controller. To automate
this task, a function called the automatic channel sequencer is provided.

Automatic Channel Sequencer

The automatic channel sequencer sets up a range of predefined operating modes, where a
number of channels (on-chip sensors and external inputs) are used. The sequencer
automatically selects the next channel for conversion, sets the averaging, configures the
analog input channels, sets the required settling time for acquisition, and stores the results
in the status registers based on a once off setting. The sequencer modes are set by writing
to the SEQ3, SEQ2, SEQ1, and SEQ0 bits in configuration register 1 (see Table 3-8).

The channel sequencer functionality is implemented using twelve control registers (46h -
4Fh, 78h, 79h); see Control Registers:

• ADC Channel Selection Registers (46h, 48h, and 49h)

• ADC Channel Averaging (47h, 4Ah, and 4Bh)
• ADC Channel Analog-Input Mode (4Ch, 4Dh, and 78h)
• ADC Channel Settling Time (4Eh, 4Fh, and 79h)

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ADC Channel Selection Registers (46h, 48h, and 49h)

The ADC channel selection registers enable and disable a channel in the automatic channel
sequencer. The bits for these registers are defined in Table 4-1 and Table 4-2. The 16-bit
registers are used to enable or disable the associated channels. A logic 1 enables a
particular channel in the sequence. The sequence order is additionally listed.

Table 4-1: Sequencer Registers (Channel Selection)

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X X X X X X X X X X X CHSEL_ CHSEL_ CHSEL_ CHSEL_ SEQCHSEL0

USER3 USER2 USER1 USER0 (46h)

X CHSEL_ CHSEL_V CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ X X X X X X X CHSEL_ SEQCHSEL1

BRAM_A REFN VREFP Vp Vn AUX_AVG INT_AVG TEMP SYSMON (48h)
VG _CAL

CHSEL_ CHSEL_ CHSEL_A CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ CHSEL_ SEQCHSEL2
AUX15 AUX14 UX13 AUX12 AUX11 AUX10 AUX9 AUX8 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 (49h)

Table 4-2: Sequencer Register (Channel Selection) Bit Definitions

Name Sequence ADC Channel Description

Number CH[5:0]
CHSEL_SYSMON_CAL 1 001000 (8) Enables System Monitor calibration in the
sequencer (High)
CHSEL_TEMP 2 000000 (0) Enables On-Chip temperature for sequencer
(High)
CHSEL_INT_AVG 3 000001 (1) Enables On-Chip VCCINT for sequencer (High)
CHSEL_AUX_AVG 4 000010 (2) Enables On-Chip VCCAUX for sequencer (High)
CHSEL_Vp Vn 5 000011 (3) Enabled for sequencer (high) for VP, V N;
dedicated analog inputs
CHSEL_VREFP 6 000100 (4) Enables VREFP for sequencer (High)
CHSEL_VREFN 7 000101 (5) Enables VREFN for sequencer (High)
CHSEL_BRAM_AVG 8 000110 (6) Enables On-Chip VCCBRAM for sequencer (High)
CHSEL_AUX15 to 24 to 9 011111 to Enables Auxiliary channels for sequencer (High)
CHSEL_AUX0 010000
(31 to 16)
CHSEL_USER3 to 28 to 25 100011 to Enables VUSER supplies for sequencer (High)
CHSEL_USER0 100000
(35 to 32)

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ADC Channel Averaging (47h, 4Ah, and 4Bh)

The ADC channel averaging registers enable and disable the averaging of the channel data
in a sequence. The result of a measurement on an averaged channel is generated by using
16, 64, or 256 samples. The amount of averaging is selected by using the AVG1 and AVG0
bits in configuration register 0 (see Control Registers). These registers also have the same
bit assignments as the channel sequence registers listed in Table 4-3 and Table 4-4.

Table 4-3: Sequencer Registers (Averaging)

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X X X X X X X X X X X AVG_ AVG_ AVG_ AVG_ SEQAVG0 (47h)

USER3 USER2 USER1 USER0

X AVG_ X X AVG_ AVG_ AVG_ AVG_ X X X X X X X AVG_ SEQAVG1 (4Ah)

BRAM VpVn AUX_ INT_ TEMP SYSMON
_AVG AVG AVG _CAL

AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ AVG_ SEQAVG2 (4Bh)
AUX15 AUX14 AUX13 AUX12 AUX11 AUX10 AUX9 AUX8 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

Table 4-4: Sequencer Register (Averaging) Bit Definitions

Name Description
AVG_SYSMON_CAL Enables Averaging (High) for System Monitor calibration
AVG_TEMP Enables Averaging (High) for On-Chip temperature
AVG_INT_AVG Enables Averaging (High) for Average On-Chip VCCINT
AVG_AUX_AVG Enables Averaging (High) for Average On-Chip VCCAUX
AVG_VpVn Enables Averaging (High) for Vp , Vn; dedicated analog inputs
AVG_BRAM_AVG Enables Averaging (High) for Average On-Chip VCCBRAM
AVG_AUX15 to AVG_AUX0 Enable averaging (High) for Auxiliary channels
AVG_USER3 to AVG_USER0 Enable averaging (High) for VUSER supplies

Averaging can be selected independently for each channel in the sequence. When
averaging is enabled for some of the channels of the sequence, the EOS is only pulsed after
the sequence has completed the amount of averaging selected by using AVG1 and AVG0
bits (see Table 3-7). If a channel in the sequence does not have averaging enabled, its status
register is updated for every pass through the sequencer. When a channel has averaging
enabled, its status register is only updated after the averaging is complete. An example
sequence is temperature and VAUX[1], where an averaging of 16 is enabled on VAUX[1]. The
sequence is temperature, VAUX[1], temperature, VAUX[1], ..., temperature, VAUX[1] for each of
the conversions where the temperature status register is updated. The VAUX[1] status
register is updated after the averaging of the 16 conversions.

If averaging is enabled for the calibration channel by setting CAVG to a logic 0 (see Control
Registers), the coefficients are updated after the first pass through the sequence.
Subsequent updates to coefficient registers require 16 conversions before the coefficients
are updated. Averaging is fixed at 16 samples for calibration.

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ADC Channel Analog-Input Mode (4Ch, 4Dh, and 78h)

These registers are used to configure an ADC channel as either unipolar or bipolar in the
automatic sequence (see Analog Inputs). These registers also have the same bit
assignments as the channel sequence registers listed in Table 4-5 and Table 4-6. However,
only external analog input channels, such as the dedicated input channels (V P and VN) and
the auxiliary analog inputs (VAUXP[15:0] and VAUXN[15:0]) can be configured in this
manner. Setting a bit to logic 1 enables a bipolar input mode for the associated channel.
Setting a bit to logic 0 (default) enables a unipolar input mode. All internal sensors use a
unipolar transfer function.

Table 4-5: Sequencer Registers (Analog Input Mode)

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X X X INSEL_ X X X X X X X X X X X SEQINMODE0
VpVn (4Ch)

INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ INSEL_ SEQINMODE1
AUX15 AUX14 AUX13 AUX12 AUX11 AUX10 AUX9 AUX8 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 (4Dh)

X X X X X X X X X X X X INSEL_ INSEL_ INSEL_ INSEL_ SEQINMODE2

USER3 USER2 USER1 USER0 (78h)

Table 4-6: Sequencer Registers (Analog Input Mode) Bit Definitions

Name Description
INSEL_Vp Vn Selects analog input-mode as Unipolar (Low) or Bipolar (High) input for Vp , Vn;
dedicated analog inputs
INSEL_AUX15 to Selects analog input-mode as Unipolar (Low) or Bipolar (High) for Auxiliary
INSEL_AUX0 channels
INSEL_USER3 to Selects analog input-mode as Unipolar (Low) or Bipolar (High) for VUSER
INSEL_USER0 supplies

ADC Channel Settling Time (4Eh, 4Fh, and 79h)

The default settling time for an external channel in continuous sampling mode is four
ADCCLK cycles. The settling time is additional acquisition time after the end of a conversion.
However, by setting the corresponding bits (for external channels) to logic 1 in registers
4Eh and 4Fh, the associated channel can extend its settling time to 10 ADCCLK cycles. The
bit definitions (the bits that correspond to specific external channels) for these registers are
the same as the sequencer channel selection shown in Table 4-7 and Table 4-8.

Table 4-7: Sequencer Registers (Acquisition)

DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

X X X X ACQ_ X X X X X X X X X X X SEQACQ0 (4Eh)

VpVn

ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ ACQ_ SEQACQ1 (4Fh)
AUX15 AUX14 AUX13 AUX12 AUX11 AUX10 AUX9 AUX8 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0

X X X X X X X X X X X X ACQ_ ACQ_ ACQ_ ACQ_ SEQACQ2 (79h)

USER3 USER2 USER1 USER0

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Table 4-8: Sequencer Registers (Acquisition) Bit Definitions

Name Description
ACQ_VpVn Selects Acquisition time as 4 (Low) or 10 (High) ADCCLK cycles for V P, V N;
dedicated analog inputs
ACQ_AUX15 to ACQ_AUX0 Selects Acquisition time as 4 (Low) or 10 (High) ADCCLK cycles for Auxiliary
channels
INSEL_USER3 to INSEL_USER0 Selects Acquisition time as 4 (Low) or 10 (High) ADCCLK cycles for V USER
supplies

Sequencer Modes
There are several sequencer modes, as defined by Table 3-8. These modes are described in
this section.

Default Mode
The default mode is enabled by setting SEQ[3:0] = 0h. In this mode of operation, the
SYSMON automatically monitors the on-chip sensors and stores the results in the status
registers. The ADC is calibrated in this mode and an averaging of 16 samples is applied to
all sensors. The SYSMON operates independently of any other control register settings in
this mode. The SYSMON also operates in default mode after initial power up and during
device configuration. Table 4-9 shows the default sequence for the SYSMON.

TIP: All alarm outputs (ALM[15:0]) except OT are disabled in default mode. ADC calibration is
automatically enabled in default mode.

Table 4-9: Default Mode Sequence

Order Channel Address Description
1 Calibration 08h Calibration of the ADC
2 Temperature 00h Temperature Sensor
3 VCCINT 01h VCCINT supply sensor
4 VCCAUX 02h VCCAUX supply sensor
5 VCCBRAM 06h VCCBRAM supply sensor

Single Pass Mode

In single pass mode, the sequencer operates for one pass through the sequencer channel
select registers (46h, 48h, and 49h) and then halts. A sequence of channels as selected in
these registers is converted. When the sequence bits as shown in Table 3-8 are set to enable
the automatic channel sequencer in single pass mode, the sequence starts. The settings in
sequencer registers 46h-4fh, 78h-79h are used to operate the sequence in a user-defined
mode of operation. All channels listed in Table 4-1 and Table 4-2 are available to be used in

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a sequence. For an explanation of the sequencer registers, see Automatic Channel

Sequencer. Another single pass can be started by writing to the sequence bits again. When
the single pass is complete, the SYSMON defaults to Single Channel Mode described at the
start of this chapter. Thus, the SYSMON converts the channel selected by bits CH5 to CH0 in
configuration register 0.

Continuous Sequence Mode

The continuous sequence mode is similar to single pass mode; however, the sequence
automatically restarts as long as the mode is enabled.

The channel sequencer registers can also be reconfigured via the DRP at run time. The
sequencer must first be disabled by writing to sequence bits SEQ3 to SEQ0 before writing
to any of the sequencer channel registers.

IMPORTANT: The SYSMON must be placed in default mode by writing zeros to SEQ0 and SEQ1 while
updating these registers.

The SYSMON is automatically reset whenever SEQ3 to SEQ0 are written to. The current
status register contents are not reset at this time. Restarting the sequencer by writing to
bits SEQ3 to SEQ0 resets all channel averaging.

External Multiplexer Mode

The SYSMON supports the use of an external analog multiplexer to implement several
external analog inputs in situations where I/O resources are limited and auxiliary analog
inputs are not available.

The SYSMON track/hold amplifiers return to track mode as soon as a conversion starts.
Therefore, the acquisition on the next channel can start during the current conversion cycle.
An output bus called MUXADDR[4:0] allows the SYSMON to control an external multiplexer.
The address on this bus reflects the channel currently being acquired, and it changes state
as soon as the SYSMON enters acquisition mode. The channel can also be nominated to be
used with an external multiplexer.

External Multiplexer Operation

Figure 4-1 illustrates the external multiplexer concept. In this example, an external
16:1 analog multiplexer is used instead of consuming the 32 I/Os required to implement the
16 auxiliary analog input channels using the internal multiplexer. Any four I/Os can be used
for the external multiplexer decode operation. As shown in Figure 4-1, the dedicated
analog inputs (VP/VN) are used to connect the external multiplexer to the SYSMON block,
thereby making 16 analog inputs available. The external multiplexer mode of operation is
enabled by setting the MUX bit in configuration register 0 (see Control Registers).

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X-Ref Target - Figure 4-1

Temperature Supply Device

Sensor Sensors
External Analog Multiplexer
16:1 °C
VAUXP[0]
VAUXN[0]
VAUXP[1]
VAUXN[1]
VP
10-Bit,
MUX MUX 0.2 MSPS
VN ADC

VAUXP[15]
VAUXN[15] MUXADDR[3:0]
ADDR
4

UG580_c4_01_052913

Figure 4-1: External Multiplexer Mode

When the MUX bit is set to 1, the channel selection bits (CH0 to CH4) in configuration
register 0 are used to nominate the channel for connection to the external multiplexer. For
example, as shown in Figure 4-1, the dedicated analog input channel V P/VN is used. In this
case, channel 3 (00011b) should be written to CH4 to CH0 in control register 40h. Any one
of the auxiliary channels can also be used for connection to the external multiplexer.

Automatic Alarms
The SYSMON also generates an alarm signal on the logic outputs ALM[15:0] when an
internal sensor measurement exceeds some user-defined thresholds. Only the values
written to the status registers are used to generate alarms. If averaging has been enabled
for a sensor channel, the averaged value is compared to the alarm threshold register
contents. The alarm outputs are disabled by writing a 1 to bits ALM15 to ALM0 in
configuration register 1. The alarm thresholds are stored in control registers 50h to 6Dh.
Table 4-10 defines the alarm thresholds that are associated with specific control registers.
The limits written to the threshold registers are MSB justified. Limits are derived from the
temperature and power-supply sensor transfer functions (see Figure 2-8 and Figure 2-9).

Table 4-10: Alarm Threshold Registers

Control Register Description Alarm
50h Temperature upper ALM[0]
51h VCCINT upper ALM[1]
52h VCCAUX upper ALM[2]
53h OT upper (1) OT

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Table 4-10: Alarm Threshold Registers (Cont’d)

Control Register Description Alarm
54h Temperature lower ALM[0]
55h VCCINT lower ALM[1]
56h VCCAUX lower ALM[2]
57h OT lower (1) OT
58h VCCBRAM upper ALM[3]
5Ah-5Bh Reserved
5Ch VCCBRAM lower ALM[3]
5Dh-5Fh Reserved
60h V USER0 upper ALM[8]
61h V USER1 upper ALM[9]
62h V USER2 upper ALM[10]
63h V USER3 upper ALM[11]
68h V USER0 lower ALM[8]
69h V USER1 lower ALM[9]
6Ah V USER2 lower ALM[10]
6Bh V USER3 lower ALM[11]
1. OT upper and OT lower are described in Thermal Management.

Supply Sensor Alarms

When the measured value on the supply sensor for VCCINT, VCCAUX , VCCBRAM, or VUSER[3:0] is
greater than the upper thresholds (51h, 52h, 58h, 60h to 63h) or less than the lower
thresholds (55h, 56h, 5Ch, 68h to 6Bh), the corresponding alarm will be High. The alarms
are reset when a subsequently measured value falls inside the threshold.

Four additional user selectable alarms have been added to SYSMONE1 USER3 to USER0 and
can be connected to different voltage supplies using the System Management Wizard.

Thermal Management
The on-chip temperature measurement is used for critical temperature warnings. The
default over temperature threshold is 125°C. This threshold is used for preconfiguration or
when the contents of the OT upper alarm register have not been configured (see
Table 4-10). To override this default condition, the 12 MSBs of the OT upper register
(control register 53h) must be set using the temperature sensor transfer function (see
Figure 2-8). In addition, the four LSBs must be set to 0011b.

When the die temperature exceeds a factory set limit of 125°C or a user-defined threshold,
the over-temperature alarm logic output (OT) becomes active. This feature can be disabled
when the SYSMON is instantiated in a design. The OT function is disabled by writing a 1 to

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the OT bit in the SYSMON Config Reg1 (41h). The OT signal resets when the device
temperature has fallen below a user-programmable limit in OT lower 57h (see Table 4-10).
When the automatic power-down feature is enabled, the OT signal can be used to trigger a
device power down. When OT transitions High, the device enters power down
approximately 10 ms later. The power-down feature initiates a configuration shutdown
sequence, disabling the device when finished and asserts GHIGH to prevent any contention
(see the UltraScale Architecture Configuration User Guide (UG570) [Ref 4]. When OT is
deasserted, GHIGH also is deasserted and the start-up sequence is initiated releasing all
global resources. By default this functionality is disabled and must be explicitly enabled.

The automatic power down is enabled by using a configuration option in the software
design tools. To power down the device when the device temperature is higher than the
maximum value temperature allowed, add the following to the XDC file:

set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable current_design_name

See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 2] for
additional details on device configuration bitstream settings. Enable and Disable are
allowable values. When the device enters power down, the SYSMON continues to operate in
whatever mode was configured prior to power down using an internal clock oscillator. The
device automatically powers up after the temperature has fallen below the
user-programmable lower limit. The SYSMON OT signal can also be reset by writing a 1 to
the OT bit in SYSMON configuration register 1 via the JTAG DRP interface. On-chip sensors
are monitored via the JTAG TAP during device power down. During power down, the
SYSMON uses an internal oscillator instead of DCLK. On power-up, several DCLK cycles are
required to resynchronize the DRP. JTAGLOCKED remains High until the DRP is ready for use.

A second user-programmable temperature threshold level (control register 50h) is used to

carry out a user-defined thermal management procedure, such as powering on or
controlling the speed of a fan. An alarm signal (ALM[0]) becomes active when the device
temperature exceeds the limit in this register. The signal is available through the
interconnect and is routed using the interconnect logic resources. The alarm signal resets
when the temperature falls below the threshold in control register 54h. This operation
differs for the supply sensor alarm because the supply alarm resets when the measurement
is between the upper and lower thresholds.

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Application Guidelines
The SYSMON is a precision analog measurement system based on a 10-bit analog-to-digital
converter (ADC) with an LSB size approximately equal to 1mV. To achieve the best possible
performance and accuracy with all measurements (both on-chip and external), several
dedicated pins for the ADC reference and power supply are provided. When connecting
these pins, follow the guidelines in this chapter to ensure the best possible performance
from the ADC. This chapter outlines the basic design guidelines to consider as part of the
requirements for board design.

Reference Inputs (VREFP and VREFN)

These high-impedance inputs are used to deliver a differential reference voltage for the
analog-to-digital conversion process. The ADC is only as accurate as the reference
provided. Any reference-voltage error results in a gain error versus the ideal ADC transfer
function (see Chapter 2, Basic Functionality). Errors in the reference voltage affect the
accuracy of absolute measurements for both on-chip sensors and external channels. Noise
on the reference voltage also adds noise to the ADC conversion and results in more code
transition noise or poorer than expected SNR.

For typical usage, the reference voltage between VREFP and VREFN should be maintained at
1.25V ± 0.2% using an external reference IC. Reference voltage ICs that deliver 1.25V are
widely available from several vendors. Many vendors offer reference voltage ICs in small
packages (SOT-23 and SC70).

RECOMMENDED: The 1.25V reference should be placed as close as possible to the reference pins and
connected directly to the V REFP input, using the decoupling capacitors recommended in the reference IC
data sheet. The recommended reference connections are illustrated in Figure 5-1.

The SYSMON also has an on-chip reference option that is selected by connecting VREFP and
VREFN to ADCGND as shown in Figure 5-1. Due to reduced accuracy, the on-chip reference
does impact the measurement performance of the SYSMON. The performance with on-chip
reference is specified in the data sheets.

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Analog Power Supply and Ground

The analog power supply (VCCADC) and ground (GNDADC) inputs provide the power supply
and ground reference for the analog circuitry in the SYSMON. A common mechanism for
the coupling of noise into an analog circuit is from the power supply and ground
connections. Excessive noise on the analog supply or ground reference affects the ADC
measurement accuracy. For example, I/O switching activity can cause significant
disturbance of the digital ground reference plane. Thus, it is not advisable to use the digital
ground as an analog ground reference for SYSMON.

Similarly, for the digital supplies for the interconnect logic, high switching rates easily result
in high-frequency voltage variations on the supply, even with decoupling. In an effort to
mitigate these effects on the ADC performance, a dedicated supply and ground reference is
provided. Figure 5-1 illustrates how to use the 1.8V VCCAUX supply to power the analog
circuitry. VCCAUX is filtered using a low-pass network. The filter design depends on the
ripple and ripple frequency (if any) on the VCCAUX supply if, for example, a switching
regulator is used. There is also a power-supply rejection specification for the external
reference circuit to consider. The filtering should ensure no more than 1 LSB (1mV) of noise
on the reference output to minimize any impact on ADC accuracy at 12 bits. If the low-pass
network filtering of VCCAUX contains more than 1 LSB of noise, an additional regulator might
be required (for example, ADP123). See XADC Layout Guidelines (XAPP554) [Ref 1] for
additional details.

The other source of noise coupling into the ADC is from the ground reference GNDADC. In
mixed-signal designs, it is common practice to use a separate analog ground plane for
analog circuits to isolate the analog and digital ground return paths to the supply. Common
ground impedance is a mechanism for noise coupling and needs to be carefully considered
when designing the PCB. This is shown in Figure 2-3, where the common ground impedance
RG converts digital switching currents into a noise voltage for the analog circuitry. While a
separate analog ground plan is recommended for 10-bit operation, it is often not possible
or practical to implement a separate analog ground plane in a design. For example, if only
the on-chip sensors are used, one low-cost solution is to isolate V REFN and GNDADC ground
references (such as a trace) from the digital ground (plane) using a ferrite bead as shown in
Figure 5-1.

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X-Ref Target - Figure 5-1

External Reference On-Chip Reference

Filter VCCAUX Supply Filter VCCAUX Supply
VCCAUX VCCAUX
1.8V ± 3% 1.8V ± 3%

~ 20 mA 100 nF ~ 20 mA 100 nF
(Note 1) (Note 1)
470 nF 1.25V ± 0.2% 470 nF
REF3012
REF3112 ~50 µA 100 nF VREFP
(Note 1) VCCADC VREFP VCCADC

10 µF
SYSMON SYSMON

~50 µA
VREFN GNDADC VREFN GNDADC

Digital Analog Ground Trace

Ground ~20 mA ~20 mA
Reference Ferrite beads provide Ferrite beads provide
high-frequency isolation high-frequency isolation
UG580_c5_01_102813

Figure 5-1: ADC Power and Ground Connections

Notes relevant to Figure 5-1:

1. Place the 100 nF capacitor as close as possible to the package balls.

The ferrite bead behaves like a resistor at high frequencies and functions as a lossy inductor.
A typical ferrite impedance versus frequency plot is shown in Figure 5-2. The ferrite helps
provide high frequency isolation between digital and analog grounds. The reference IC
maintains a 1.25V difference of between VREFP and VREFN. The ferrite offers little resistance
to the analog DC return current.

The reference inputs should be routed as a tightly coupled differential pair from the
reference IC to the package pins. If routed on the same signal layer, the supply and analog
ground traces (VCCADC and GNDADC) should be used to shield the reference inputs because
they have a higher tolerance to any coupled noise.
X-Ref Target - Figure 5-2

Z , R, and XL vs Frequency
1200

1000 Z

R
800
Impedance (Ω)

XL
600
R
400
Z
200
XL
0
1 10 100 1000 10000
Frequency (MHz)
UG580_c5_02_110612

Figure 5-2: Ferrite Bead Characteristics

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External Analog Inputs

The analog inputs are high-impedance differential inputs. The differential input scheme
enables the rejection on common mode noise on any externally applied analog-input
signal. Because of the high impedance of each input (such as VP and VN), the input AC
impedance is typically determined by the sensor, the output impedance of the driving
circuitry, or other external components. Figure 5-3 illustrates a simple resistor divider
network is used to monitor an external 2.5V supply rail in unipolar input mode. To ensure
that noise coupled onto the analog inputs is common to both inputs (reduce differential
noise), the impedance on each input should be matched. Analog-input traces on the PCB
should also be routed as tightly coupled differential pairs.
X-Ref Target - Figure 5-3

VIN Anti-Aliasing Filter

V2 R1
+
AC 10 9k
– R3 VCAFFP
VAUXP[x]
25
R2 RAAF
C1
1k CAAF
680 pF
R5 R4
VAUXN[x]
1 k 25 VCAFFN
RAAF

UG580_c5_03_120213

Figure 5-3: Voltage Attenuation

Anti-Alias Filters
Also shown in Figure 5-3, is a low-pass filter network at the analog differential inputs. This
filter network is commonly referred to as the anti-alias filter and should be placed as close
as possible to the package pins. The sensor can be placed remotely from the package as
long as the differential input traces are closely coupled. The anti-alias filter attenuates
high-frequency signal components entering the ADC where they could be sampled and
aliased, resulting in ADC measurement corruption. A discussion of aliasing in sampled
systems is beyond the scope of this document. A reference book on data converters can
provide more information on this topic.

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Over and Under Voltages

The input voltage can exceed VCCADC (1.8V) or go below GNDADC by as much as 100 mV
without damage to the SYSMON. A current-limiting resistor of at least 100Ω should be
placed in series with the analog inputs. The resistors in the anti-alias filters fulfill this
requirement. If the analog input range (1V) is exceeded, the ADC output code clips at the
maximum output code shown in Figure 2-1 or Figure 2-2, depending on the analog input
mode. Negative input voltages clip at zero code.

SYSMON Software Support

Example Design Instantiation
The rdf0304-ultrascale-sysmon.zip design file can be accessed at:

https://secure.xilinx.com/webreg/clickthrough.do?cid=352493

This HDL example sets up the SYSMON to monitor all the on-chip sensors, i.e., temperature,
VCCINT, VCCAUX , and VCCBRAM. See Temperature Sensor and Power and User Supply Sensors.
In addition, four auxiliary analog input channels are also monitored. The SYSMON is also set
to automatically generate alarm outputs when the defined operating ranges for the device
supply voltages and temperature are exceeded (see Automatic Alarms). The SYSMON is
operated in continuous sequence mode for this example (see Sequencer Modes). For clarity
(and shorter simulations), the averaging function is disabled by the design. The disabling of
the averaging function can be seen during the DRP write. Averaging does not have any
impact on the simulation results because an ideal model of the SYSMON is used.

RECOMMENDED: Enable averaging when monitoring the on-chip sensors in a typical application to
minimize any noise impacts. This is especially true if the automatic alarm functions are used.

Averaging is enabled for the on-chip sensors in this instantiation example.

Apart from initializing the alarm threshold registers and the automatic channel sequencer
register, the configuration registers need to be initialized to enable alarm outputs,
sequencer modes, and ADC clock divider (see Configuration Registers (40h to 43h) for more
information). Here is an instantiation in Verilog of the SYSMON example design:

`timescale 1ns / 1ps

module ug580 (
input DCLK, // Clock input for DRP
input RESET,
input [15:0] VAUXP, VAUXN, // Auxiliary analog channel inputs
input VP, VN,// Dedicated and Hardwired Analog Input Pair
// inout I2C_SCLK, // uncomment when using I2C DRP interface
// inout I2C_SDA, // uncomment when using I2C DRP interface

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output reg [15:0] MEASURED_TEMP, MEASURED_VCCINT,

output reg [15:0] MEASURED_VCCAUX, MEASURED_VCCBRAM,
output reg [15:0] MEASURED_AUX0, MEASURED_AUX1,
output reg [15:0] MEASURED_AUX2, MEASURED_AUX3,

output wire [15:0] ALARM,

output wire [5:0] CHANNEL,
output wire OT,
output wire SYSMON_EOC,
output wire SYSMON_EOS
);

wire busy;
wire [5:0] channel;
wire drdy;
wire eoc;
wire eos;

// .I2C_SCLK_IN (i2c_sclk_in), // uncomment when using I2C DRP interface

// .I2C_SCLK_TS (i2c_sclk_ts), // uncomment when using I2C DRP interface
// .I2C_SDA_IN (i2c_sda_in), // uncomment when using I2C DRP interface
// .I2C_SDA_TS (i2c_sda_ts), // uncomment when using I2C DRP interface
reg [7:0] daddr;
reg [15:0] di_drp;
wire [15:0] do_drp;

reg [1:0] den_reg;

reg [1:0] dwe_reg;

reg [7:0] state = init_read;

parameter init_read = 8'h00,
read_waitdrdy = 8'h01,
write_waitdrdy = 8'h03,
read_reg00 = 8'h04,
reg00_waitdrdy = 8'h05,
read_reg01 = 8'h06,
reg01_waitdrdy = 8'h07,
read_reg02 = 8'h08,
reg02_waitdrdy = 8'h09,
read_reg06 = 8'h0a,
reg06_waitdrdy = 8'h0b,
read_reg10 = 8'h0c,
reg10_waitdrdy = 8'h0d,
read_reg11 = 8'h0e,
reg11_waitdrdy = 8'h0f,
read_reg12 = 8'h10,
reg12_waitdrdy = 8'h11,
read_reg13 = 8'h12,
reg13_waitdrdy = 8'h13;

always @(posedge DCLK)

if (RESET) begin
state <= init_read;
den_reg <= 2'h0;
dwe_reg <= 2'h0;
di_drp <= 16'h0000;
end
else
case (state)

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init_read : begin
daddr = 8'h40;
den_reg = 2'h2; // performing read
if (busy == 0 ) state <= read_waitdrdy;
end
read_waitdrdy :
if (drdy ==1) begin
di_drp = do_drp & 16'h03_FF; //Clearing AVG bits for Configreg0
daddr = 8'h40;
den_reg = 2'h2;
dwe_reg = 2'h2; // performing write
state = write_waitdrdy;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
write_waitdrdy :
if (drdy ==1) begin
state = read_reg00;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg00 : begin
daddr = 8'h00;
den_reg = 2'h2; // performing read
if (eos == 1) state <=reg00_waitdrdy;
end
reg00_waitdrdy :
if (drdy ==1) begin
MEASURED_TEMP = do_drp;
state <=read_reg01;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg01 : begin
daddr = 8'h01;
den_reg = 2'h2; // performing read
state <=reg01_waitdrdy;
end
reg01_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCINT = do_drp;
state <=read_reg02;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg02 : begin
daddr = 8'h02;

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den_reg = 2'h2; // performing read

state <=reg02_waitdrdy;
end
reg02_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCAUX = do_drp;
state <=read_reg06;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg06 : begin
daddr = 8'h06;
den_reg = 2'h2; // performing read
state <=reg06_waitdrdy;
end
reg06_waitdrdy :
if (drdy ==1) begin
MEASURED_VCCBRAM = do_drp;
state <= read_reg10;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg10 : begin
daddr = 8'h10;
den_reg = 2'h2; // performing read
state <= reg10_waitdrdy;
end
reg10_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX0 = do_drp;
state <= read_reg11;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg11 : begin
daddr = 8'h11;
den_reg = 2'h2; // performing read
state <= reg11_waitdrdy;
end
reg11_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX1 = do_drp;
state <= read_reg12;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg12 : begin

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daddr = 8'h12;
den_reg = 2'h2; // performing read
state <= reg12_waitdrdy;
end
reg12_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX2= do_drp;
state <= read_reg13;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
read_reg13 : begin
daddr = 8'h13;
den_reg = 2'h2; // performing read
state <= reg13_waitdrdy;
end
reg13_waitdrdy :
if (drdy ==1) begin
MEASURED_AUX3= do_drp;
state <=read_reg00;
daddr = 8'h00;
end
else begin
den_reg = { 1'b0, den_reg[1] } ;
dwe_reg = { 1'b0, dwe_reg[1] } ;
state = state;
end
endcase

SYSMONE1 #(// Initializing the SYSMON Control Registers

.INIT_40(16'h9000),// averaging of 16 selected for external channels
.INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration
.INIT_42(16'h0400),// Set DCLK divides
.INIT_43(16'h2ef0),// CONFIG3
.INIT_46(16'h0001),// CHSEL0 - enable USER0
.INIT_47(16'h0000),// SEQAVG0 disabled
.INIT_48(16'h4701),// CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
.INIT_49(16'h000f),// CHSEL2 - enable aux analog channels 0 - 3
.INIT_4A(16'h0000),// SEQAVG1 disabled
.INIT_4B(16'h0000),// SEQAVG2 disabled
.INIT_4C(16'h0000),// SEQINMODE0
.INIT_4D(16'h0000),// SEQINMODE1
.INIT_4E(16'h0000),// SEQACQ0
.INIT_4F(16'h0000),// SEQACQ1
.INIT_50(16'hb5ed),// Temp upper alarm trigger 85°C
.INIT_51(16'h5999),// Vccint upper alarm limit 1.05V
.INIT_52(16'hA147),// Vccaux upper alarm limit 1.89V
.INIT_53(16'hdddd),// OT upper alarm limit 125°C - see Thermal Management
.INIT_54(16'ha93a),// Temp lower alarm reset 60°C
.INIT_55(16'h5111),// Vccint lower alarm limit 0.95V
.INIT_56(16'h91Eb),// Vccaux lower alarm limit 1.71V
.INIT_57(16'hae4e),// OT lower alarm reset 70°C - see Thermal Management
.INIT_58(16'h5999),// VCCBRAM upper alarm limit 1.05V
.INIT_5C(16'h5111), // VUSER0 upper alarm limit 1.05V
.INIT_60(16'h5999), // VUSER1 upper alarm limit 1.05V
.INIT_61(16'h5999), // VUSER2 upper alarm limit 1.05V

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.INIT_62(16'h5999), // VUSER3 upper alarm limit 1.05V

.INIT_63(16'h5999), // VCCBRAM lower alarm limit 1.05V
.INIT_64(16'h5999), // VCCSYSMON upper alarm limit 1.05V
.INIT_68(16'h5111), // VUSER0 lower alarm limit 0.95V
.INIT_69(16'h5111), // VUSER1 lower alarm limit 0.95V
.INIT_6A(16'h5111), // VUSER2 lower alarm limit 0.95V
.INIT_6B(16'h5111), // VUSER3 lower alarm limit 0.95V
.INIT_6C(16'h5111), // VCCBRAM lower alarm limit 0.95V
.INIT_78(16'h0000), // SEQINMODE2
.INIT_79(16'h0000), // SEQACQ2
.SYSMON_VUSER0_BANK(66),
.SYSMON_VUSER0_MONITOR("VCCO"),
.SIM_MONITOR_FILE("design.txt")// Analog Stimulus file for simulation
)
SYSMON_INST (// Connect up instance IO. See UG580 for port descriptions
.CONVST (1'b0),// not used
.CONVSTCLK (1'b0), // not used
.DADDR (daddr),
.DCLK (DCLK),
.DEN (den_reg[0]),
.DI (di_drp),
.DWE (dwe_reg[0]),
.RESET (RESET),
.VAUXN (VAUXN),
.VAUXP (VAUXP),
.ALM (ALARM),
.BUSY (busy),
.CHANNEL(CHANNEL),
.DO (do_drp),
.DRDY (drdy),
.EOC (eoc),
.EOS (eos),
.JTAGBUSY (),// not used
.JTAGLOCKED (),// not used
.JTAGMODIFIED (),// not used
// .I2C_SCLK_IN (i2c_sclk_in), // uncomment when using I2C DRP interface
// .I2C_SCLK_TS (i2c_sclk_ts), // uncomment when using I2C DRP interface
// .I2C_SDA_IN (i2c_sda_in), // uncomment when using I2C DRP interface
// .I2C_SDA_TS (i2c_sda_ts), // uncomment when using I2C DRP interface
.OT (OT),
.MUXADDR (),// not used
.VP (VP),
.VN (VN)
);

////// Uncomment when using I2C//////

// IOBUF I2C_SCLK_inst (
// .O(i2c_sclk_in), // Buffer output
// .IO(I2C_SCLK), // Buffer inout port (connect directly to top-level port)
// .I(1'b0), // Buffer input
// .T(i2c_sclk_in) // 3-state enable input, high=input, low=output
// );
//
// IOBUF I2C_SDA_inst (
// .O(i2c_sda_in), // Buffer output
// .IO(I2C_SDA), // Buffer inout port (connect directly to top-level port)
// .I(1'b0), // Buffer input
// .T(i2c_sda_ts) // 3-state enable input, high=input, low=output
// );

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//
assign SYSMON_EOC = eoc;
assign SYSMON_EOS = eos;

endmodule

Example Design Test Bench

The next example is a test bench that sets up a DCLK of 50 MHz. Analog signals are read
from the analog stimulus file by the simulation model. The SIM_MONITOR_FILE attribute
used in the SYSMONE1 instantiation points the model to the location of this file. The analog
stimulus file used for this example is shown here:

TIME VAUXP[0] VAUXN[0] VAUXP[1] VAUXN[1] VAUXP[2] VAUXN[2] VAUXP[3] VAUXN[3] Temp VCCINT VCCAUX VCCBRAM VUSER0
00000 0.005 0.0 0.2 0.0 0.5 0.0 0.1 0.0 25 1.0 1.8 1.0 1.0
34000 0.020 0.0 0.400 0.0 0.49 0.0 0.2 0.0 85 1.05 1.9 1.05 1.0
67000 0.049 0.0 0.600 0.0 0.51 0.0 0.5 0.0 105 0.95 1.71 0.95 1.0
100000 0.034 0.0 0.900 0.0 0.53 0.0 0.0 0.0 0 1.00 1.8 1.0 1.0

The format of the analog stimulus file is based on space- or tab-delimited data and can be
created in a spreadsheet. Many tools such as SPICE simulators or equipment such as
oscilloscopes export comma-separated value (CSV) formats, that can be manipulated in a
spreadsheet to generate an analog stimulus file for simulation. All time stamp information
must be listed in the first column. Other columns list the analog values for the on-chip
sensors and external analog inputs. The order of the columns is not important. The only
requirement is that time stamp information is listed in the first column. For each time stamp
added to the first column, a corresponding value is added to the other columns. Only the
required analog input channel columns must be listed. In this example, only the on-chip
sensors and auxiliary channels zero to three are listed in the analog stimulus file. In this
stimulus file, the temperature moves 85°C to 105°C at 67 µs after the start of the simulation.
The temperature alarm (ALARM[0]) becomes active High shortly after this event when the
temperature is measured by the ADC (see Figure 5-4). The upper alarm threshold for
temperature has been set to B5EDh or 85°C.

`timescale 1ns / 1ps

module ug580_tb;
reg [15:0] VAUXP, VAUXN;
reg RESET;
reg DCLK;

wire [15:0] MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX;

wire [15:0] MEASURED_VCCBRAM, MEASURED_AUX0, MEASURED_AUX1;
wire [15:0] MEASURED_AUX2, MEASURED_AUX3;
wire [15:0] ALARM;

initial
begin
DCLK = 0;
RESET = 1;
#100 RESET = 0;
end

always #(10) DCLK= ~DCLK;

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 Chapter 5: Application Guidelines

// Instantiate the Unit Under Test (UUT)

ug580 uut (
.VAUXP (VAUXP),
.VAUXN (VAUXN),
.RESET (RESET),
.ALARM (ALARM),
.DCLK (DCLK),

.MEASURED_TEMP (MEASURED_TEMP),
.MEASURED_VCCINT (MEASURED_VCCINT),
.MEASURED_VCCAUX (MEASURED_VCCAUX),
.MEASURED_VCCBRAM (MEASURED_VCCBRAM),
.MEASURED_AUX0 (MEASURED_AUX0),
.MEASURED_AUX1 (MEASURED_AUX1),
.MEASURED_AUX2 (MEASURED_AUX2),
.MEASURED_AUX3 (MEASURED_AUX3)
);

endmodule

Simulation Output
The simulation output in Figure 5-4 shows the user-defined sequence in continuous
sampling mode. The channels monitored in the sequence can be seen by looking at the
CHANNEL[5:0] bus. The sequence is 8, 0, 1, 2, 3, 6, 10, 11, 12, and 13, which corresponds to
calibration, temperature, VCCINT, VCCAUX , VCCBRAM, Aux0, Aux1, Aux2, and Aux3. Then the
sequence repeats. The calibration channel takes longer to complete than the other
channels. This is because the calibration routine involves three conversions (measurements)
using the ADC. The measured results are shown using the analog waveform settings for the
Vivado simulator.

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 Chapter 5: Application Guidelines

X-Ref Target - Figure 5-4

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Figure 5-4: SYSMON Simulation Output (iSim)

The design initially performs a DRP write to register 40h (configuration register 0) to set the
AVG1 and AVG0 bits to 00 (see Figure 5-5). This disables the averaging functionality for
simulation. The DRP Write (see Figure 5-5) has been simulated with Config Reg0 (40H) set
to 903FH to show how the DRP writes 003FH. Do_drp is updated to 003FH after the DRP
write is completed.
X-Ref Target - Figure 5-5

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Figure 5-5: DRP Write at 4 μ s

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 Chapter 5: Application Guidelines

As shown in Figure 5-6, when the EOS signal pulses High for one DCLK period at the end of
a sequence, the test bench reads the status registers. The simulation model uses the full
16-bit ADC conversion result because it is an ideal model of the ADC. For example, VCCINT
is shown as 5999h for 1.05V. From Equation 2-8, 1.05V is 166h for 10-bit data. For 16-bit
data, 5999h = 1.05 x (65536/3). This is a 10-bit MSB justified result. However, the six LSBs
of the status register also contain data that would be 011001b if the ADC was an ideal
16-bit ADC.
X-Ref Target - Figure 5-6

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Figure 5-6: DRP Read of Status Register at EOS

The temperature output transitions High (see Figure 5-4). The ALARM[0] becomes active at
the end of the conversion on the temperature channel (00h) when the result is loaded in the
status register. The result is read from the status register by the design when EOS next
transitions High. The temperature is 105°C (as set in the stimulus file) and is greater than
85°C limit set when the SYSMONE1 was instantiated in the design (.INIT_50(16'hb5ed)).

The VCCAUX_ALARM output transitions High during the second pass through the sequence
(see Figure 5-4). The alarm becomes active at the end of the conversion on the VCCAUX
channel when the result is loaded in the status register. The result is read from the status
register by the test bench when EOS next transitions High. The VCCAUX is ~1.9V (as set in the
stimulus).

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 Appendix A

Additional Resources

Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.

For a glossary of technical terms used in Xilinx documentation, see the Xilinx Glossary.

Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.

References
These documents provide supplemental material useful with this guide:

1. XADC Layout Guidelines (XAPP554 )

2. Vivado Design Suite User Guide: Programming and Debugging ( UG908)
3. UltraScale Architecture Packaging and Pinout User Guide (UG575)
4. UltraScale Architecture Configuration User Guide (UG570)
5. Driving the Xilinx Analog-to-Digital Converter (XAPP795)
6. LogiCORE IP AXI XADC Product Guide (PG019)
7. 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS
Analog-to-Digital Converter User Guide (UG480)

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