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Lab 5

The document is a lab report that describes minimizing complex logic functions using automated tools. It discusses implementing a 4 variable and 8 variable function using Xilinx. For the 4 variable function, the student shows the original and minimized expressions, K-map, circuit, and truth table. For the 8 variable function, the student shows the original minterms, K-map, and Verilog code using both structural and data flow modeling, along with simulation waveforms. The student concludes they learned to minimize large variable expressions using a K-map minimizer tool and verified results using Xilinx simulation.

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Saim Ashraf
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49 views

Lab 5

The document is a lab report that describes minimizing complex logic functions using automated tools. It discusses implementing a 4 variable and 8 variable function using Xilinx. For the 4 variable function, the student shows the original and minimized expressions, K-map, circuit, and truth table. For the 8 variable function, the student shows the original minterms, K-map, and Verilog code using both structural and data flow modeling, along with simulation waveforms. The student concludes they learned to minimize large variable expressions using a K-map minimizer tool and verified results using Xilinx simulation.

Uploaded by

Saim Ashraf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital Logic Design

Lab report 5

Submitted by
M SAIM ASHRAF
Registration No:
FA21-BEE-128
Submitted to
DR ADNAN QURESHI
LAB #5 Logic Minimization of complex functions
using automated tools

Equipment Required:
 Xilinx
 Bread Board
 Logic Gate IC’s

Background Theory:
The process of minimizing the tables has been
made simpler by using automated tools. Automated tools are
important when simplifying equations with high number of bits and can
easily simplify any equation. Many minimization tools have been which
implement different algorithms to solve k-maps.

Pre lab:
Lab Tasks:
Implement random 4 variable function using Xilinx
Procedure:
 Select the number of bits for which K-map will be made.
 Specify given inputs and output.
 Select the form of result. (SOP or POS)
 Create project in Xilinx.
 Implement given equation using gate functions in Verilog.
 Output variable will give the output of random function.
 An example for 4-bit is performed below.

In lab Task 1:

F (A, B, C, D) = ∑ (2,5,6,8)
Functions in sum of Min-terms form: A'B'CD'+A'BC'D+A'BCD'+AB'C'D'
Function in a simplified form using K-Maps: A'CD'+AB'C'D'+A'BC'D
K-MAP:

Minterms Equation Circuit:

Reduced Form Equation:


Truth Table:

In Lab Task 2:
F (A, B, C, D, E, F, G, H) = ∑ (4,5,6,9)
K-Map:

Simulation and verifying the results by Xilinx ISE Tool


VeryLog Code:
module My_Module(

input A,

input B,

input C,

input D,

input E,

input F,

input G,

input H,

output Y

);

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20,w21;

not n1(w1,A);

not n2(w2,A);
not n3(w3,B);

not n4(w4,C);

not n5(w5,C);

not n6(w6,D);

not n7(w7,E);

not n8(w8,E);

not n9(w9,E);

not n10(w10,F);

not n11(w11,F);

not n12(w12,F);

not n13(w13,G);

not n14(w14,G);

not n15(w15,G);

not n16(w16,H);

not n17(w17,H);

not n18(w18,H);

and a1(w19,A,w3,w4,D,w16,w13,w7,w10);

and a2(w20,w1,B,w5,w17,w14,w8,w11);

and a3(w21,w2,B,w6,w18,w15,w9,w12);

or o1(Y,w19,w20,w21);

endmodule
Simulation Wave Form
Post Lab
Verilog description by using DATA FLOW for 8-bit variables

module My_Module(

input A,

input B,

input C,

input D,

input E,

input F,

input G,

input H,

output Y

);

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20,w21;

assign w1 = ~A;

assign w2 = ~A;

assign w3 = ~B;

assign w4 = ~C;

assign w5 = ~C;

assign w6 = ~D;
assign w7 = ~E;

assign w8 = ~E;

assign w9 = ~E;

assign w10 = ~F;

assign w11 = ~F;

assign w12 = ~F;

assign w13 = ~G;

assign w14 = ~G;

assign w15 = ~G;

assign w16 = ~H;

assign w17 = ~H;

assign w18 = ~H;

assign w19 = A & w3 & w4 & D & w16 & w13 & w7 & w10;

assign w20 = w1 & B & w5 & w17 & w14 & w8 & w11;

assign w21 = w2 & B & w6 & w18 & w15 & w9 & w12;

assign Y= w19 | w20 | w21;

endmodule
Simulation Wave Form

Critical Analysis:
In this lab we learnt how to minimize large variables expression just by using an automated tool
known as K-map minimizer and later we verified the results bu using the Xilinx software with
the help of Verilog code of both structural and data flow coding and simulated the wave forms as
well.

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