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Mechatronics Interfacing Sensors-1

The document discusses interfacing between microprocessors and peripheral devices. It describes various interfacing requirements including buffers for electrical isolation, handshaking for timing control, code conversion, changing data bus widths, and serial to parallel conversion. It also discusses analog to digital conversion and the use of tristate buffers and handshaking for data transfer. Interrupts and polling are described as methods for controlling input/output transfers.

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Tanvi Chaudhary
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0% found this document useful (0 votes)
64 views

Mechatronics Interfacing Sensors-1

The document discusses interfacing between microprocessors and peripheral devices. It describes various interfacing requirements including buffers for electrical isolation, handshaking for timing control, code conversion, changing data bus widths, and serial to parallel conversion. It also discusses analog to digital conversion and the use of tristate buffers and handshaking for data transfer. Interrupts and polling are described as methods for controlling input/output transfers.

Uploaded by

Tanvi Chaudhary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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LECTURE ON INTERFACING

1. Introduction
2. Interfacing
3. Interfacing requirements
3.1 Buffers
3.2 Handshaking
3.3 Polling and Interrupts
3.4 Serial Interfacing
4. Peripheral Interface Adapters
5. Data Conversion Devices
6. Basic components used in ADCs and DACs
When a microprocessor is used to control some system it has to accept input
information, respond to it and produce output signals to implement the required control
action. Thus there can be inputs from sensors to feed data in and outputs to such
external devices as relays and motors. The term peripheral is used for a device, such as a
sensor, keyboard, actuator, etc., which is connected to a microprocessor. It is, however,
not normally possible to connect directly such peripheral devices to a microprocessor
bus system due to a lack of compatibility in signal forms and levels. Because of such
incompatibility, a circuit known as an interface is used between the peripheral items and
the microprocessor. Figure 13.1 illustrates the arrangement. The interface is where this
incompatibility is resolved.
The following are some of the actions that are often required of an
interface circuit.

A. Electrical buffering/isolation
This is needed when the peripheral operates at a different voltage or
current to that on the microprocessor bus system or there are different
ground references. The term buffer is used for a device that provides
isolation and current or voltage amplification. For example, if the output
of a microprocessor is connected to the base of a transistor, the base
current required to switch the transistor is greater than that supplied by the
microprocessor and so a buffer is used to step up the current. There also
has often to be isolation between the microprocessor and the higher power
system.
B. Timing control

Timing control is needed when the data transfer rates of the peripheral and
the microprocessor are different, e.g. when interfacing a microprocessor to a
slower peripheral. This can be achieved by using special lines between the
microprocessor and the peripheral to control the timing of data transfers.
Such lines are referred to as handshake lines and the process as
handshaking.

C. Code conversion
This is needed when the codes used by the peripherals differ from those
used by the microprocessor. For example, an LED display might require a
decoder to convert the BCD output from a microprocessor into the code
required to operate the seven display elements.
D. Changing the number of lines
Microprocessors operate on a fixed word length of 4 bits, 8 bits or 16 bits.
This determines the number of lines in the microprocessor data bus.
Peripheral equipment may have a different number of lines, perhaps
requiring a longer word than that of the microprocessor.

E. Serial-to-parallel, and vice versa, data transfer


Within an 8-bit microprocessor, data is generally manipulated 8 bits at a
time. To transfer 8 bits simultaneously to a peripheral thus requires eight
data paths. Such a form of transfer is termed parallel data transfer. It is,
however, not always possible to transfer data in this way. For example,
data transfer over the public telephone system can only involve one data
path. The data has thus to be transferred sequentially 1 bit at a time. Such
a form of transfer is termed serial data transfer.
Serial data transfer is a slower method of data transfer than parallel data
transfer. Thus, if serial data transfer is used, there will be a need to convert
incoming serial data into parallel data for the microprocessor and vice
versa for outputs from the microprocessor.

F. Conversion from analogue to digital and vice versa


The output from sensors is generally analogue and this requires
conversion to digital signals for the microprocessor. The output from a
microprocessor is digital and this might require conversion to an analogue
signal in order to operate some actuator. Many microcontrollers have
built-in analogue-to-digital converters, e.g. PIC 16C74/74A and Motorola
M68HC11 so can handle analogue inputs. However, where required to
give analogue outputs, the microcontroller output has generally to pass
through an external digital to-analogue converter.
A buffer is a device that is connected between two parts of a system to
prevent unwanted interference between the two parts. An important use of
a buffer is in the microprocessor input port to isolate input data from the
microprocessor data bus until the microprocessor requests it. The
commonly used buffer is a tristate buffer. The tristate buffer is enabled by a
control signal to provide logic 0 or 1 outputs, when not enabled it has a
high impedance and so effectively disconnects circuits.
Figure 13.2 shows the symbols for tristate buffers and the conditions under
which each is enabled. Figure 13.2(a) and (b) shows the symbol for buffers
that does not change the logic of the input and Figure 13.2(c) and (d) for
ones that do.
With PIC microcontrollers, the TRIS bit is connected to the enable input
of a tristate buffer. If the bit is 0, the tristate buffer is enabled and simply
passes its input value to its output, if it is 1 the tristate buffer is disabled
and the output becomes high impedance (as in Figure 13.2(b)).
Such tristate buffers are used when a number of peripheral devices have to
share the same data lines from the microprocessor, i.e. they are connected
to the data bus, and thus there is a need for the microprocessor to be able
to enable just one of the devices at a time with the others disabled. Figure
13.3 shows how such buffers can be used. Such buffers are available as
integrated circuits, e.g. the 74125 with four non-inverting, active-low
buffers and the 74126 with four non-inverting, active-high buffers.
Unless two devices can send and receive data at identical rates, handshaking is
necessary to exchange data. With handshaking the slower device controls the rate at
which the data is transferred.
For parallel data transfer strobe-and-acknowledge is the commonly used form of
handshaking. The peripheral sends a DATA READY signal to the input/output section.
The CPU then determines that the DATA READY signal is active. The CPU then reads
the data from the input/output section and sends an INPUT ACKNOWLEDGED
signal to the peripheral. This signal indicates that the transfer has been completed and
thus the peripheral can send more data. For an output, the peripheral sends an
OUTPUT REQUEST or PERIPHERAL READY signal to the input/output section.
The CPU determines that the PERIPHERAL READY signal is active and sends the
data to the peripheral. The next PERIPHERAL READY signal may be used to inform
the CPU that the transfer has been completed.
With the microcontroller MC68HC11, the basic strobed input/output
operates as follows. The handshaking control signals use pins STRA and
STRB (Figure 13.4(a), port C is used for the strobed input and port B for
the strobed output. When data is ready to be sent by the microcontroller a
pulse is produced at STRA and sent to the peripheral device. When the
microcontroller receives either a rising or falling edge to a signal on STRB,
then the relevant output port of the microcontroller sends the data to the
peripheral. When data is ready to be transmitted to the microcontroller,
the peripheral sends a signal to STRA that it is ready and then a rising or
falling edge to a signal on STRB is used to indicate readiness to receive.
Before handshaking can occur, the parallel input/output register PIOC at
address $1002 has to be first configured. Figure 13.4(b) shows the states
required of the relevant bits in that register.
Full handshake input/output involves two signals being sent along STRB, the first
being to indicate ready to receive data and the next one that the data has been read.
This mode of operation requires that in PIOC the HNDS bit is set to 1 and if PLS is
set to 0 the full handshake is said to be pulsed and if to 1 it is interlocked. With pulsed
operation a pulse is sent as acknowledgement; with interlocked STRB there is a reset
(Figure 13.5).
Consider the situation where all input/output transfers of data are controlled by the
program. When peripherals need attention they signal the microprocessor by changing
the voltage level of an input line. The microprocessor can then respond by jumping to a
program service routine for the device. On completion of the routine, a return to the
main program occurs. Program control of inputs/outputs is thus a loop to read inputs
and update outputs continuously, with jumps to service routines as required. This
process of repeatedly checking each peripheral device to see if it is ready to send or
accept a new byte of data is called polling.
An alternative to program control is interrupt control. An interrupt involves a
peripheral device activating a separate interrupt request line. The reception of an
interrupt results in the microprocessor suspending execution of its main program and
jumping to the service routine for the peripheral.
The interrupt must not lead to a loss of data and an interrupt handling routine has to
be incorporated in the software so that the state of processor registers and the last
address accessed in the main program are stored in dedicated locations in memory.
After the interrupt service routine, the contents of the memory are restored and the
microprocessor can continue executing the main program from where it was
interrupted (Figure 13.6).
Thus, the following take place when an interrupt occurs.

1. The CPU waits until the end of the instruction it is currently executing
before dealing with the interrupt.

2. All the CPU registers are pushed onto the stack and a bit set to stop further
interrupts occurring during this interruption. The stack is a special area of
memory in which program counter values can be stored when a subroutine is
to be executed. The program counter gives the address of the next program
instruction in a program and thus storing this value enables the program to
be resumed at the place where it broke off to execute the interrupt.
3. The CPU then determines the address of the interrupt service routine to be
executed. Some microprocessors have dedicated interrupt pins and the pin that is
chosen determines which address is to be used. Other microprocessors have only one
interrupt pin and the interrupting device must then supply data that tells the
microprocessor where the interrupt service routine is located. Some microprocessors
have both kinds of interrupt inputs. The starting address of an interrupt service
routine is called an interrupt vector. The block of memory assigned to store the vectors
is known as the vector table. Vector addresses are fixed by the chip manufacturer.

4. The CPU branches to the interrupt service routine.

5. After completion of this routine, the CPU registers are returned from the stack and
the main program continues from the point it left off.
With the parallel transmission of data, one line is used for each bit; serial
systems, however, use a single line to transmit data in sequential bits. There
are two basic types of serial data transfer: asynchronous and synchronous.
With asynchronous transmission, the receiver and the transmitter each use
their own clock signals so it is not possible for a receiver to know when a
word starts or stops. Thus it is necessary for each transmitted data word to
carry its own start and stop bits so that it is possible for the receiver to tell
where one word stops and another starts (Figure 13.9). With such a mode
of transmission, the transmitter and receiver are typically remote. With
synchronous transmission, the transmitter and receiver have a common
clock signal and thus transmission and reception can be synchronised.
The microcontroller MC68HC11 has a serial communications interface
(SCI) which can be used for asynchronous transmission and thus can be
used to communicate with remote peripheral devices. The SCI uses port D
pin PD1 as a transmit line and port PD0 as a receive line. These lines can
be enabled or disabled by the SCI control register. The microcontroller also
has a serial peripheral interface (SPI) for synchronous transmission. This
can be used for local serial communication, local meaning essentially
inside the machine in which the chip is located.
Interfaces can be specifically designed for particular inputs/outputs;
however, programmable input/output interface devices are available which
permit various different input and output options to be selected by means of
software. Such devices are known as peripheral interface adapters (PIAs). A
commonly used PIA parallel interface is the Motorola MC 6821. It is part
of the MC6800 family and thus can be directly attached to Motorola
MC6800 and MC68HC11 buses. The device can be considered to be
essentially just two parallel input/output ports, with their control logic, to
link up with the host microprocessor.
Figure 13.10 shows the basic structure of the MC6821 PIA and the pin
connections.
https://www.youtube.com/watch?v=JUtzG-9RdFM

https://slideplayer.com/slide/4205670/

https://www.youtube.com/watch?v=dbotS09aorE
The PIA contains two 8-bit parallel data ports, termed A and B. Each port
has the following.

1. A peripheral interface register. An output port has to operate in a


different way to an input port because the data must be held for the
peripheral. Thus for output a register is used to store data temporarily. The
register is said to be latched, i.e. connected, when a port is used for output
and unlatched when used for input.
2. A data direction register that determines whether the input/output lines
are inputs or outputs.
3. A control register that determines the active logical connections in the
peripheral.
4. Two control lines, CA1 and CA2 or CB1 and CB2.
Two microprocessor address lines connect the PIA directly through the two register
select lines RS0 and RS1. This gives the PIA four addresses for the six registers. When
RS1 is low, side A is addressed and when it is high, side B. RS0 addresses registers on a
particular side, i.e. A or B. When RS0 is high, the control register is addressed, when
low the data register or the data direction register. For a particular side, the data register
and the data direction register have the same address. Which of them is addressed is
determined by bit 2 of the control register (see below).
Each of the bits in the A and B control registers is concerned with some features of the
operation of the ports. Thus for the A control register we have the bits shown in Figure
13.11. A similar pattern is used for the B control register.
Bits 0 and 1

The first two bits control the way that CA1 or CB1 input control lines operate. Bit 0
determines whether the interrupt output is enabled. B0=0 disables the IRQA(B)
microprocessor interrupt, B0 = 1 enables the interrupt. CA1 and CB1 are not set by the
static level of the input but are edge triggered, i.e. set by a changing signal. Bit 1
determines whether bit 7 is set by a high-to-low transition (a trailing edge) or a low-to-
high transition (a leading edge). B1 = 0 sets a high-to-low transition, B1 = 1 sets a low-
to-high transition.

Bit 2

Bit 2 determines whether data direction registers or peripheral data registers are
addressed. With B2 set to 0, data direction registers are addressed, with B2 set to 1,
peripheral data registers are selected.
Bits 3, 4 and 5

These bits allow the PIA to perform a variety of functions. Bit 5 determines whether
control line 2 is an input or an output. If bit 5 is set to 0, control line 2 is an input, if set
to 1, it is an output. In input mode, both CA2 and CB2 operate in the same way. Bits 3
and 4 determine whether the interrupt output is active and which transitions set bit 6.
With B5 = 0, i.e. CA2(CB2) set as an input: B3 = 0 disables IRQA(B) microprocessor
interrupt by CA2(CB2); B3 = 1 enables IRQA(B) microprocessor interrupt by
CA2(CB2); B4 = 0 determines that the interrupt flag IRQA(B), bit B6, is set by a high-to-
low transition on CA2(CB2); B4 = 1 determines that it is set by a low-to-high transition.
B5 5 1 sets CA2(CB2) as an output. In output mode CA2 and CB2 behave differently.
For CA2: with B4 = 0 and B3 = 0, CA2 goes low on the first high-to-low ENABLE (E)
transition following a microprocessor read of peripheral data register A and is returned
high by the next CA1 transition; with B4 = 0 and B3 = 1, CA2 goes low on the first
high-to-low ENABLE transition following a microprocessor read of the peripheral data
register A and is returned to high by the next high-to-low ENABLE transition. For CB2:
with B4 = 0 and B3 = 0, CB2 goes low on the first low-to-high ENABLE transition
following a microprocessor write into peripheral data register B and is returned to high
by the next CB1 transition; with B4 = 0 and B3 = 1, CB2 goes low on the first low-to-
high ENABLE transition following a microprocessor write into peripheral data register
B and is returned high by the next low-to-high ENABLE transition. With B4 = 1 and B3
= 0, CA2(CB2) goes low as the microprocessor writes B3 = 0 into the control register.
With B4 = 0 and B3 = 1, CA2(CB2) goes high as the microprocessor writes B3 = 1 into
the control register.
Bit 6

This is the CA2(CB2) interrupt flag, being set by transitions on CA2(CB2).


With CA2(CB2) as an input (B5 = 0), it is cleared by a microprocessor read
of the data register A(B). With CA2(CB2) as an output (B5 = 1), the flag is 0
and is not affected by CA2(CB2) transitions.

Bit 7

This is the CA1(CB1) interrupt flag, being cleared by a microprocessor read


of data register A(B). The process of selecting which options are to be used
is termed configuring or initialising the PIA. The RESET connection is used
to clear all the registers of the PIA. The PIA must then be initialised.
Data Conversion Devices are very important components of a Machine
Control Unit (MCU). MCUs are controlled by various computers or
microcontrollers which are accepting signals only in Digital Form i.e. in
the form of 0s and 1s, while the signals received from signal conditioning
module or sensors are generally in analogue form (continuous).
Therefore a system is essentially required to convert analog signals into
digital form and vis-à-vis. Analog to Digital Converter is abbreviated as
ADC. Figure 9.1 shows a typical control system with data conversion
devices.
Figure 9.1 A control system with ADC and DAC devices
Based on the signals received from sensors, MCU generates actuating
signals in the Digital form. Most of the actuators e.g. DC servo motors
only accept analogue signals. Therefore the digital signals must be
converted into Analog form so that the required actuator can be
operated accordingly. For this purpose Digital to Analog Converters are
used, which are abbreviated as DACs. In subsequent sections we will be
discussing about various types of ADC and DAC devices, their
principle of working and circuitry.
6.1 Comparators

In general ADCs and DACs comprise of Comparators. Comparator is a


combination of diodes and Operational Amplifiers. A comparator is a device
which compares the voltage input or current input at its two terminals and
gives output in form of digital signal i.e. in form of 0s and 1s indicating which
voltage is higher. If V+ and V- be input voltages at two terminals of
comparator then output of comparator will be as
V+ > V-  Output 1
V+ < V-  Output 0
6.2. Encoders

Though the output obtained from comparators are in the form of 0s and
1s, but can’t be called as binary output. A sequence of 0s and 1s will be
converted into binary form by using a circuit called Encoder. A simple
encoder converts 2n input lines into ‘n’ output lines. These ‘n’ output
lines follow binary algebra.
6.3. Analog to Digital Converter (ADC)

As discussed in previous section ADCs are used to convert analog signals into
Digital Signals. There are various techniques of converting Analog Signals into
Digital signals which are enlisted as follows. However we will be discussing only
Direct Conversion ADC, detail study of other techniques is out of the scope of the
present course.
1. Direct Conversion ADC or Flash ADC
2. Successive Approximation ADC
3. A ramp-compare ADC
4. Wilkinson ADC
5. Integrating ADC
6. Delta-encoded ADC or counter-ramp
7. Pipeline ADC (also called subranging quantizer)
8. Sigma-delta ADC (also known as a delta-sigma ADC)
9. Time-interleaved ADC
Figure 9.2 shows the circuit of Direct conversion or Flash ADC. To convert a digital
signal of N-bits, Flash ADC requires 2N-1 comparators and 2N resistors. The circuit
provides the reference voltage to all the comparators. Each comparator gives an output
of 1 when its analog voltage is higher than reference voltage or otherwise the output is 0.
In the above circuit, reference voltages to comparators are provided by means of resistor
ladder logic.
The circuit described in figure 9.2 acts as 3 Bit ADC device. Let us assume this ADC
works between the range of 0-10 Volts. The circuit requires 7 comparators and 8 resisters.
Now the voltages across each resistor are divided in such a way that a ladder of 1 volt is
built with the help of 1K-Ohm resistances. Therefore the reference voltages across all the
comparators are 1-7 volts.
Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To
increase the storage capacity in terms of number of bits, we have to use a group of
flip-flop. Such a group of flip-flop is known as a Register.
Figure 9.2 Circuit of Flash ADC
Now let us assume that an input voltage signal of 2.5 V is to be converted
into its related digital form. As 2.5V is greater than 1V and 2V, first two
comparators will give output as 1, 1. But 2.5V is less than 3,4,5,6,7 V
values therefore all other comparators will give 0s.
Thus we will have output from comparators as 0000011 (from top). This
will be fed to the encoder logic circuit. This circuit will first change the
output in single high line format and then converts it into 3 output lines
format by using binary algebra. Then this digital output from ADC may
be used for manipulation or actuation by the microcontrollers or
computers.
Flash ADC (Parallel ADC) and Half-Flash ADC Explained

https://www.youtube.com/watch?v=NASkjo7s8f4

https://www.youtube.com/watch?v=lhnKZDLtYvQ

https://www.youtube.com/watch?v=A9NinZYWyo8
As discussed in previous section DACs are used to convert digital signals
into Analog Signals. There are various techniques of converting Digital
Signals into Analog signals which are as follows however we will be
discussing only few important techniques in detail:
1. Pulse-width modulator
2. Oversampling DACs or interpolating DACs
3. The binary-weighted DAC
4. Switched resistor DAC
5. Switched current source DAC
6. Switched capacitor DAC
7. The R-2R ladder
8. The Successive-Approximation or Cyclic DAC,
9. The thermometer-coded DAC
Figure 9.3 Circuit of binary weighted DAC
As name indicates, in binary weighted
DAC, output voltage can be calculated by
expression which works on binary weights.
Its circuit can be realized in Figure 9.3.
From the figure it can be noted that most
significant bit of digital input is connected
to minimum resistance and vice versa.
Digital bits can be connected to resistance
through a switch which connects
resistance-end to the ground. The digital
input is zero when former bit is connected
to reference voltage and if it is 1. This can Figure 9.4 An op-amp used in DAC
be understood from Figure 9.4.
DAC output voltage can be calculated from property of operational amplifiers. If V1
be input voltage at MSB (most significant bit), V2 be input voltage at next bit and so on
then for four bit DAC we can write,
However, Binary weighted DAC doesn’t work for multiple or higher bit
systems as the value of resistance doubles in each case.
Thus simple and low bit digital signals from a transducer can be
converted into a related continuous value of voltages (analogue) by using
binary weighted DAC. These will further be used for manipulation or
actuation.
Binary Weighted Resistor DAC Explained

https://www.youtube.com/watch?v=PoOm_G4s1dE

https://www.youtube.com/watch?v=XSnjBCAWvxM
Figure 9.5 R-2R Ladder based DAC
In R-2R ladder logic, shortcoming of Binary Logic has been removed by
making the value of maximum resistance double however the rest of the
circuit remains same. Figure 9.5 shows the circuit of R-2R Ladder based
DAC. If we apply voltage division rule in above case, then we can calculate
that output voltage as,

In this way output voltage is obtained by converting the digital signals received from
microprocessor/ microcontroller. These voltages will further be used to actuate the
desired actuator viz. DC/AC motors.
R-2R Ladder DAC Explained (with Solved Example)

https://www.youtube.com/watch?v=Pc1aFloxSMw

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