LX2160A

Layerscape LX2160A, LX2120A, LX2080A Data Sheet

Rev. 3 — 09/2021 Data Sheet: Technical Data

• Arm Cortex®-A72 cores: • Ethernet interfaces supporting IEEE 1588

— Up to 2.2 GHz — Up to 18 Ethernet MACs
— Single-threaded cores with 48KB L1 instruction — Support for 10G-SXGMII (USXGMII)
cache and 32 KB L1 data cache
— Support for SGMII (and 1000Base-KX)
— Layerscape® LX2160A has 16 cores, 8 MB L2
— Support for XFI, SFI, and 10GBase-KR
cache; LX2120A has 12 cores, 6 MB L2 cache;
LX2080A has 8 cores, 8 MB L2 cache — Support for CAUI4 (100G), 50GAUI-2 (50G), 25G-
AUI (25G)
• Cache Coherent Interconnect Fabric
— Support for XLAUI4 (and 40GBase-KR4) for 40G
— Up to 1500 MHz
— Support for two RGMII parallel interfaces
— 8 MB Level 3 cache with ECC and On-Chip
Memory (OCM) mode — Energy-efficient support (802.3az)

• Two 72-bit (64-bit + ECC) 3.2 GT/s DDR4 SDRAM • Additional peripheral interfaces
memory controllers with ECC — Two USB 3.0 controllers with integrated PHY
• Datapath acceleration architecture 2.0 (DPAA2) — Two enhanced secure digital host controllers
— Packet parsing, classification, and distribution — Two Controller Area Network (CAN) modules,
(WRIOP) optionally supporting Flexible Data rate
— Queue and hardware buffer management — Flexible Serial Peripheral Interface (FlexSPI) and
— Cryptography acceleration (SEC) at up to 50 Gbps three Serial Peripheral Interface (SPI) controllers

— Decompression/compression acceleration (DCE) at — Eight I2C controllers

up to 100 Gbps — Four UARTs
— Queue Direct Memory Access (QDMA) engine — General Purpose IO (GPIO)
— Management complex (MC) • Support for hardware virtualization and partitioning
— 2 MB Packet express buffer enforcement (Arm MMU-500)

— L2 Switching (114 Gbps) • QorIQ platform trust architecture 3.0 with 256 KB on-chip
RAM for trusted accesses
• 24 SerDes lanes at up to 25 Gbps
• Global interrupt controller (Arm GIC-500)
• High-speed peripheral interfaces
• Two Flextimers, one secure watchdog timer and one
— Two PCI express Gen 3.0 8-lane controllers
non-secure watchdog timer
supporting SR-IOV
• Debug supporting run control, data acquisition, high-
— Four PCI express Gen 3.0 4-lane controllers
speed trace, and performance/event monitoring
— Four serial ATA (SATA 3.0) controllers
• Support for Voltage ID (VID) for yield improvement

NXP reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products.
 Contents

1 Introduction.........................................................4 3.4 Power-down requirements............................ 94

1.1 Device selection..............................................5 3.5 Power-on ramp rate...................................... 94
2 Pin assignments................................................. 6 3.6 Power characteristics....................................95
2.1 1517 ball layout diagrams............................... 6 3.7 Input clocks................................................... 95
2.2 Pinout list...................................................... 12 3.7.1 USB reference clock specifications...............95
2.2.1 DDR1 pins.....................................................84 3.7.2 Gigabit Ethernet reference clock timing........ 96
2.2.2 DDR2 pins.....................................................84 3.7.3 DDR clock (DDRCLK)................................... 96
2.2.3 I2C1 pins.......................................................84 3.7.4 Differential system clock (DIFF_SYSCLK_P/
2.2.4 I2C2 pins.......................................................84 DIFF_SYSCLK_N) timing specifications....... 97
2.2.5 I2C3 pins.......................................................84 3.7.5 Other input clocks......................................... 98
2.2.6 I2C4 pins.......................................................84 3.8 Reset initialization timing specifications........ 99
2.2.7 I2C5 pins.......................................................85 3.9 Battery-backed security monitor and tamper
2.2.8 I2C6 pins.......................................................85 detect............................................................ 99
2.2.9 I2C7 pins.......................................................85 3.9.1 Battery-backed security monitor and tamper
2.2.10 I2C8 pins.......................................................85 detect DC electrical characteristics............... 99
2.2.11 XSPI1 pins.................................................... 85 3.9.2 Battery-backed security monitor AC timing
2.2.12 eSDHC1 pins................................................ 85 specifications.............................................. 100
2.2.13 eSDHC2 pins................................................ 85 3.10 DDR4 SDRAM controller............................ 101
2.2.14 UART pins.....................................................85 3.10.1 DDR4 SDRAM controller DC electrical
2.2.15 Interrupt controller pins................................. 85 characteristics............................................. 101
2.2.16 Trust pins...................................................... 85 3.10.2 DDR4 SDRAM controller AC timing
2.2.17 System control pins.......................................85 specifications.............................................. 101
2.2.18 Clocking pins.................................................85 3.11 Universal asynchronous receiver/transmitter
2.2.19 Debug pins....................................................85 (UART)........................................................105
2.2.20 DFT pins....................................................... 85 3.11.1 UART DC electrical characteristics............. 105
2.2.21 JTAG pins..................................................... 86 3.11.2 UART AC timing specifications................... 106
2.2.22 Analog pins................................................... 86 3.12 Enhanced secure digital host controller
2.2.23 SerDes1 pins................................................ 86 (eSDHC)..................................................... 106
2.2.24 SerDes2 pins................................................ 86 3.12.1 eSDHC DC electrical characteristics.......... 106
2.2.25 SerDes3 pins................................................ 86 3.12.2 eSDHC AC timing specifications.................107
2.2.26 USB PHY pins...............................................86 3.13 Ethernet interface (EMI, RGMII, and IEEE Std
™
2.2.27 EC1 pins....................................................... 86 1588 )........................................................ 119
2.2.28 EC2 pins....................................................... 86 3.13.1 Ethernet management interface (EMI)........ 119
2.2.29 GPIO pins..................................................... 86 3.13.2 Reduced media-independent interface (RGMII)
2.2.30 FlexTimer pins.............................................. 86 .................................................................... 120
2.2.31 CAN pins.......................................................86 3.13.3 IEEE 1588...................................................122
2.2.32 Power-on-reset configuration pins................ 86 3.14 General purpose input/output (GPIO)......... 124
2.2.33 SPI1 pins.......................................................86 3.14.1 GPIO DC electrical characteristics..............125
2.2.34 SPI2 pins.......................................................86 3.14.2 GPIO AC timing specifications.................... 125
2.2.35 SPI3 pins.......................................................87 3.15 Flextimer interface...................................... 126
2.2.36 IEEE 1588 pins............................................. 87 3.15.1 Flextimer DC electrical characteristics........ 126
2.2.37 Power and ground pins................................. 87 3.15.2 Flextimer AC timing specifications.............. 126
2.2.38 No connect pins............................................ 87 3.16 Generic interrupt controller (GIC)................127
3 Electrical characteristics................................... 87 3.16.1 GIC DC electrical characteristics................ 127
3.1 Overall DC electrical characteristics............. 87 3.16.2 GIC AC timing specifications...................... 127
3.1.1 Absolute maximum ratings............................87 3.17 I2C.............................................................. 128
3.1.2 Recommended Operating Conditions........... 89 3.17.1 I2C DC electrical characteristics................. 128
3.1.3 Output drive capabilities................................92 3.17.2 I2C AC timing specifications....................... 128
3.2 General AC timing.........................................92 3.18 JTAG...........................................................130
3.3 Power sequencing........................................ 93 3.18.1 JTAG DC electrical characteristics............. 130
3.18.2 JTAG AC timing specifications....................130 3.23.10 1000Base-KX..............................................180
3.19 Flex serial peripheral interface (FlexSPI).... 133 3.23.11 10GBase-KR...............................................181
3.19.1 FlexSPI DC electrical characteristics.......... 133 3.23.12 CAUI-4, 50GAUI-2, and 25G-AUI interface 183
3.19.2 FlexSPI AC timing specifications................ 133 3.23.13 USXGMII interface (USXGMII)................... 185
3.20 Serial peripheral interface (SPI)..................138 3.23.14 XLAUI interface (XLAUI)............................. 186
3.20.1 SPI DC electrical characteristics................. 138 3.23.15 SerDes Recovered Clock Outputs.............. 188
3.20.2 SPI AC timing specifications....................... 138 4 Hardware design considerations.................... 189
3.21 Universal serial bus 3.0 (USB).................... 141 4.1 Clock ranges............................................... 189
3.21.1 USB 3.0 DC electrical characteristics......... 141 4.2 Platform clock requirements for Ethernet....189
3.21.2 USB 3.0 AC timing specifications............... 142 4.3 Power supply design...................................190
3.22 Controller Automatic Network interface (CAN) 4.3.1 Voltage ID (VID) controllable supply........... 190
.................................................................... 143 5 Thermal.......................................................... 190
3.22.1 CAN DC electrical characteristics............... 143 5.1 Recommended thermal model.................... 190
3.22.2 CAN AC electrical characteristics............... 144 5.2 Temperature diode......................................191
3.23 High-speed serial interfaces (HSSI)............144 5.3 Thermal management information.............. 191
3.23.1 Signal terms definitions...............................145 5.3.1 Thermal interface materials........................ 191
3.23.2 SerDes reference clocks............................. 146 6 Package information.......................................191
3.23.3 SerDes transmitter and receiver reference 6.1 Package parameters for the FC-PBGA.......192
circuits.........................................................152 6.2 Mechanical dimensions of the FC-PBGA....192
3.23.4 PCI Express................................................ 152 7 Security fuse processor..................................194
3.23.5 Serial ATA (SATA)...................................... 162 8 Ordering information.......................................194
3.23.6 SGMII interface........................................... 168 8.1 Part numbering nomenclature.....................194
3.23.7 XFI.............................................................. 173 8.2 Part marking ...............................................196
3.23.8 SFI.............................................................. 176 9 Revision history.............................................. 196
3.23.9 SFP+ direct attach copper.......................... 179
NXP Semiconductors
Introduction

1 Introduction
The Layerscape® LX2160A processor is built on NXP's software-aware, core-agnostic DPAA2 architecture, which delivers
scalable acceleration elements sized for application needs, unprecedented efficiency, and smarter, more capable networks.
When coupled with ease-of-use facilities such as real-time monitoring and debug, virtualization, and software management
utilities, the available toolkits allow for both hardware and software engineers to bring a complete solution to market faster
than ever.
The device integrated multicore processor combines sixteen Arm Cortex®-A72 processor cores with high-performance data
path acceleration logic and network and peripheral bus interfaces required for networking, storage, telecom/datacom, wireless
infrastructure, automotive, and military/aerospace applications.
The device processor is supported by a consistent API that provides both basic and complex manipulation of the hardware
peripherals in the device, releasing the developer from the classic programming challenges of interfacing with new peripherals at
the hardware level.

A72 A72 A72 A72 A72 A72 A72 A72

A72 A72 A72 A72 A72 A72 A72 A72

72-bit
DDR4
1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 with
ECC

Interconnect

8MB Platform Cache

IO MMU IO MMU IO MMU IO MMU

Secure Boot
2MB PEB
Trust Zone

SATA3

SATA3
Power Management WRIOP
x8 Gen3 PCle

x8 Gen3 PCle

x4 Gen3 PCle

x4 Gen3 PCle
x4 Gen3 PCle

x4 Gen3 PCle
SEC - 50G 72-bit
2x SD/eMMC DDR4
122 Gbps
4x UART with

SATA3

SATA3
1G/2.5G/10G/ 25G/40G/50G/
8x I2C DCE - 100G ECC
100G Ethernet
SPI, GPIO, JTAG
2x USB3.0 +PHY QB-
Man 24 lanes @ up to 25GHz
2x CAN-FD

Figure 1. LX2160A Block diagram

The LX2120A integrated multicore processor combines twelve Arm® v8 A72 cores. This figure shows the major functional units
within the chip.

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 4 / 198
NXP Semiconductors
Introduction

A72 A72 A72 A72 A72 A72

A72 A72 A72 A72 A72 A72

72-bit
DDR4
with
1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2
ECC

Interconnect

8MB Platform Cache

IO MMU IO MMU IO MMU IO MMU

Secure Boot
2MB PEB
Trust Zone

SATA3

SATA3
x4 Gen3 PCle
Power Management WRIOP

x8 Gen3 PCle

x8 Gen3 PCle

x4 Gen3 PCle

x4 Gen3 PCle
x4 Gen3 PCle
SEC - 50G 72-bit
2x SD/eMMC DDR4
122 Gbps
4x UART with

SATA3

SATA3
1G/2.5G/10G/ 25G/40G/50G/
8x I2C DCE - 100G ECC
100G Ethernet
SPI, GPIO, JTAG
2x USB3.0 +PHY QB-
24 lanes @ up to 25GHz
2x CAN-FD Man

Figure 2. LX2120A Block diagram

The LX2080A integrated multicore processor combines eight Arm® v8 A72 cores. This figure shows the major functional units
within the chip.

A72 A72 A72 A72 A72 A72 A72 A72

1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 1MB L2 72-bit

DDR4
with
Interconnect
ECC
8MB Platform Cache

IO MMU IO MMU IO MMU IO MMU

Secure Boot
2MB PEB
Trust Zone
SATA3

SATA3

Power Management WRIOP

x8 Gen3 PCle

x8 Gen3 PCle

x4 Gen3 PCle

x4 Gen3 PCle
x4 Gen3 PCle

x4 Gen4 PCle

SEC - 50G
2x SD/eMMC 72-bit
122 Gbps
4x UART DDR4
SATA3

SATA3

1G/2.5G/10G/ 25G/40G/50G/
with
8x I2C DCE - 100G 100G Ethernet
ECC
SPI, GPIO, JTAG
2x USB3.0 +PHY QB-
24 lanes @ up to 25GHz
2x CAN-FD Man

Figure 3. LX2080A Block diagram

1.1 Device selection

This table shows how to set the TEST_SEL_B and the cfg_svr[0:1] pins to select between LX2160A, LX2120A, and LX2080A.

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 5 / 198
NXP Semiconductors
Pin assignments

Table 1. Device Personality Selection

Personality TEST_SEL_B cfg_svr0 cfg_svr1

(primary (primary
signal XSPI1_A_CS0_B) signal XSPI1_A_CS1_B)

LX2160A 1 1 1

LX2120A 0 1 1

LX2080A 1 0 1

2 Pin assignments

2.1 1517 ball layout diagrams

This figure shows the complete view of the LX2160A BGA ball map diagram. Figure 5, Figure 6, Figure 7, and Figure 8 show
quadrant views.

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 6 / 198
NXP Semiconductors
Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

A A

B B

C C

D D

E E

F F

G
SEE DETAIL A SEE DETAIL B G

H H

J J

K K

L L

M M

N N

P P

R R

T T

U U

V V

W W

Y Y

AA AA

AB AB

AC AC

AD AD

AE AE

AF AF

SEE DETAIL C SEE DETAIL D

AG AG

AH AH

AJ AJ

AK AK

AL AL

AM AM

AN AN

AP AP

AR AR

AT AT

AU AU

AV AV

AW AW

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

DDRC1 DDRC2 I2C1 I2C2 I2C3

I2C4 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 GIC500 SNVS System Control

Clocking EPU DFT JTAG Analog Signals

Serdes 1 Serdes 2 Serdes 3 USB PHY 1 and 2 EC1

EC2 RCLK Ethernet MI 1 Ethernet MI 2 SPI3

DDR Power Ground No-Connects

Figure 4. Complete BGA Map for the LX2160A

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 7 / 198
NXP Semiconductors
Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
USB1_ USB1_ USB2_ SD3_ SD3_ SD3_ SD3_
SPI3_ SPI3_ UART1_ UART1_ DRV GND002 TX_ GND003 TX_ SD3_ SD3_ SD3_ SD3_ SD3_
A GND001
PCS0 PCS1 RTS_B CTS_B VBUS P P GND01
RX0_
P GND02
RX2_
P
PLLS_
GND03REF_CLK_NGND04
RX5_
P GND05 A
USB1_ USB1_ USB2_ SD3_ SD3_ SD3_ SD3_
SPI3_ SPI3_ GND007 UART1_ UART1_ PWR GND008 TX_ GND009 TX_ GND010 SD3_ SD3_ SD3_ SD3_
B GND006
SCK PCS2 SIN SOUT FAULT M M
RX0_
N GND07
RX2_
N
PLLS_
GND08REF_CLK_PGND09
RX5_
N GND10 B
SDHC1_ SDHC1_ SPI3_ SPI3_ UART2_ UART2_ GND016 USB1_ USB2_
RX_ GND017 RX_ GND018 USB1_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
C DAT2 DAT3 PCS3 SOUT RTS_B CTS_B P P RESREF GND12
RX1_
P GND13
RX3_
P GND14
RX4_
P GND15
RX6_
P C
USB1_ USB2_ SD3_ SD3_ SD3_ SD3_
SDHC1_ GND022 SPI3_ GND023 UART2_ UART2_ GND024 RX_ GND025 RX_ GND026 USB2_ SD3_ SD3_ SD3_ SD3_
D CLK SIN SIN SOUT M M RESREF GND17
RX1_
N GND18
RX3_
N GND19
RX4_
N GND20
RX6_
N D
SDHC1_ SDHC1_ IIC2_ IIC2_ PORESET_BTEST_ USB2_ SD3_
DRV GND030 USB1_ GND031 USB2_ GND032 SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
E CMD DAT1 SCL SDA SEL_B VBUS ID ID
PLLF_
GND22 GND23 GND24 GND25REF_CLK_NGND26 GND27 GND28 E
SDHC1_ GND036 EC1_ IIC1_ HRESET_BGND038 USB1_ USB1_ USB2_ USB2_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
F DAT0 GTX_
CLK
GND037
SCL D_
P
D_
M
D_
P
D_
M
GND30 TX0_
P GND31 TX2_
P GND32 PLLF_ GND33
REF_CLK_P
TX5_
P GND34 F
EC1_ EC1_ EC1_ EC1_ IIC1_
USB2_
USB1_ GND044 USB2_ GND045 SD3_
SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
G RX_
CLK RXD3 TXD3 TXD2 SDA
EVT2_B PWR
FAULT VBUS VBUS GND36
TX0_
N GND37
TX2_
N GND38 GND39 GND40
TX5_
N GND41 G
SD3_ SD3_ SD3_ SD3_
EC1_ GND049 EC1_ IIC3_ SD3_ SD3_ SD3_ SD3_
H RXD2 TXD1
GND050
SCL IRQ06 IRQ08 IRQ10 IRQ00 IRQ01 IRQ02 GND051 GND43 TX1_
P
GND44 TX3_
P
GND45 TX4_
P
GND46 TX6_
P H
EC1_ SD3_ SD3_ SD3_ SD3_
EC1_ EC1_ EC1_ IIC3_ TD2_ SD3_ SD3_ SD3_ SD3_
J RXD1 RXD0 TXD0 TX_
EN
SDA
GND058 IRQ03 GND059 IRQ05 GND060 IRQ04
ANODE GND49
TX1_
N
GND50
TX3_
N
GND51
TX4_
N
GND52
TX6_
N J
EC1_ EC2_ IIC4_ SCAN_ NC_ TD2_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
K RX_
DV
GND063 GTX_
CLK
GND064
SCL IRQ07 IRQ09 IRQ11 EVT0_B MODE_B K11 CATHODE GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 K
EC2_ SD3_ AVDD_ SD3_ SD3_ AVDD_ SD3_
EC2_ EC2_ EC2_ IIC4_ CLK_ NC_ NC_ SD3_
L RX_
CLK
RXD3 TXD3 TXD2 SDA OUT
GND072
L8 L9
EVT3_B EVT1_B GND073 GND074 GND63 IMP_ SD3_
CAL_RX PLLF
PLLF_
TPA
PLLF_
TPD
SD3_ IMP_
PLLS CAL_TX L
EC2_ EC2_ NC_
GND079 ASLEEP GND080 RESET_
USB_ USB_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
M RXD2 GND077 TXD1
GND078
M5 REQ_B EVT4_B GND081 HVDD1 SVDD1 OVDD1 OVDD2 OVDD3 OVDD4 OVDD5 OVDD6 OVDD7 M
EC2_ EC2_ EC2_ EC2_ TA_ USB_ GND092 USB_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
N RXD1 RXD0 TXD0
TX_
EN
GND089 RCLK0 GND090 RCLK1 TMP_ GND091 HVDD2
DETECT_B
SVDD2 GND65 GND66 GND67 GND68 GND69 GND70 GND71 N
EC2_ EC_
EMI2_ GND099 GND100 GND101 GND102 GND103 GND104 USB_ USB_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_ SD3_
P RX_
DV
GND098 GTX_C
LK125
MDC SDVDD1 SDVDD2 GND105 SVDD1 SVDD2 SVDD3 SVDD4 SVDD5 SVDD6 SVDD7 P
EMI1_ EMI1_ EMI2_ GND112 NC_ NC_ NC_ NC_ NC_
R MDIO MDC MDIO R5 R6 R7 R8 R9
GND113 OVDD06 GND114 VDD05 GND115 VDD06 GND116 VDD07 GND117 VDD08 GND118
R
NC_ NC_ NC_ NC_ NC_ NC_
T GND126
T2
GND127
T4 T5
GND128
T7 T8 T9
GND129 OVDD07 EVDD GND130 VDD12 GND131 VDD13 GND132 VDD14 GND133 VDD15
T
NC_ NC_ NC_ NC_ NC_ NC_ NC_
U U1 U2 U3
GND140
U5 U6 U7
GND141
U9
GND142 OVDD08 GND143 VDD19 GND144 VDD20 GND145 VDD21 GND146 VDD22 GND147
U
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
V V1 V2 V3 V4 V5
GND154
V7 V8 V9
GND155 OVDD09 VDD26 GND156 VDD27 GND157 VDD28 GND158 VDD29 GND159 VDD30
V
NC_ NC_ NC_ NC_ NC_ NC_ NC_
W W1 W2 W3
GND166
W5 W6 W7
GND167
W9
GND168 OVDD10 GND169 VDD34 GND170 VDD35 GND171 VDD36 GND172 VDD37 GND173
W
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
Y Y1 Y2 Y3 Y4 Y5
GND179
Y7 Y8 Y9
GND180
Y11
OVDD11 GND181 VDD41 GND182 VDD42 GND183 VDD43 GND184 VDD44
Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

DDRC1 DDRC2 I2C1 I2C2 I2C3

I2C4 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 GIC500 SNVS System Control

Clocking EPU DFT JTAG Analog Signals

Serdes 1 Serdes 2 Serdes 3 USB PHY 1 and 2 EC1

EC2 RCLK Ethernet MI 1 Ethernet MI 2 SPI3

DDR Power Ground No-Connects

Figure 5. Detail A

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 8 / 198
NXP Semiconductors
Pin assignments

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SD3_ SD3_ SD3_ SDHC2_ SDHC2_ SDHC2_ SDHC2_ SDHC2_ GND004 D1_ D1_ D1_ D1_ D1_ D1_ GND005 D1_ D1_ G1VDD01
A GND05 RX7_
P GND06 DAT0 DAT3 CLK DAT6 DAT7 MDQ13 MDQ09 MDQ28 MDQ25MDQS03_BMDQ30 MCKE3 MCKE2 A
SD3_
SD3_ SD3_ SDHC2_ GND011 SDHC2_ GND012 SDHC2_ GND013 D1_ GND014 D1_ GND015 D1_ D1_ D1_ G1VDD02 D1_ D1_ G1VDD03
B GND10
RX7_
N GND11 DAT2 CMD DAT5 MDQ08 MDQ29 MDQS03 MDQ31 MDQ27 MCKE0 MACT_B B
SD3_ SD3_ GND019 XSPI1_ SDHC2_ SDHC2_ SDHC2_ IIC6_ D1_ D1_ D1_ D1_ D1_ D1_ GND021 D1_ D1_ D1_ D1_
C RX6_
P GND16
A_
CS0_B DAT1 DS DAT4 SDA
GND020
MDQS10MDQS10_BMDQ24 MDQS12MDQS12_BMDQ26 MCKE1 MBG0 MBG1 MALERT_B C
SD3_ XSPI1_ XSPI1_ XSPI1_ XSPI1_
SD3_ A_ _A_DATA GND027 _A_DATA IIC6_ FA2_ D1_ GND028 D1_ D1_ GND029 D1_ D1_ D1_ D1_ G1VDD04 D1_
D RX6_
N GND21
A_
SCK CS1_B SCL DGV MDQ12 MDQ14 MDQS11 MECC5 MECC0 MECC1 MA12 MA09 D
SD3_ SD3_ GND033 XSPI1_ XSPI1_ XSPI1_ XSPI1_ XSPI1_
A_ _A_DATA_A_DATA_A_DATA_A_DATA GND034 D1_ D1_ D1_ D1_ D1_ D1_ D1_ GND035 D1_ D1_ D1_
E GND28 GND29 DQS MDQS01_BMDQS01 MDQ21MDQS11_BMECC4 MDQS17MDQS17_B MA11 MA07 MA08 E
SD3_ SD3_ SD3_ TBSCAN_ XSPI1_ XSPI1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
F GND34 TX7_
P GND35 EN_B GND039 _A_DATA GND040 _A_DATA GND041 MDQ15 GND042 MDQ20MDQS02_BMDQS02 GND043MDQS08_BMDQS08 MA06 G1VDD05 MA05 F
SD3_ SD3_ SD3_ TH_ TH_ D1_ D1_ D1_ GND047 D1_ D1_ D1_ GND048 D1_ D1_ D1_
G GND41
TX7_
N GND42 VDD TPA
TMS TCK TDO GND046
MDQ10 MDQ11 MDQ16 MDQ22 MECC6 MECC7 MA04 MA03 MA01 G
SD3_ SD3_ SD3_ D1_ GND056 D1_ D1_ D1_ GND057 D1_ D1_ D1_ D1_
H TX6_
P
GND47 GND48 GND052 GND053 GND054 TRST_B TDI GND055 MDQ05
MDQ17 MDQ23 MDQ18 MECC2 MECC3 MDIC G1VDD06 MA02 H
SD3_ SD3_ SD3_ SENSE SENSE TA_BB_
FA2_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
J TX6_
N
GND53
PLLS_
TPA
AVDD1 GND_
CA
VDD_ TA_BB_TMP_DETECT_B
CA
VDD DPIN MDQ04 MDQS09MDQS09_BGND061 MDQ19 MDQ45 MDQ44 GND062 MCK0 MCK0_BG1VDD07 J
SD3_ SD3_ NC_ TD1_ GND069 D1_ GND070 D1_ D1_ D1_ D1_ D1_ D1_ D1_
K GND61 GND62 K22
GND065 GND066 GND067 GND068 ANODE
MDQ00 MDQS00_BMDQS00 MDQ36 GND071 MDQ41 MDQ40 G1VDD08 MCK1 MCK1_B K
SD3_ SD3_
SD3_ TD1_ FA2_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
L IMP_
CAL_TX GND64
PLLS_
TPD
AVDD2 AVDD3 AVDD4 AVDD5 CATHODE
DVL MDQ01 MDQ06 MDQ07 GND075 MDQ37MDQS14_BMDQS14 GND076 MCK2 MCK2_BG1VDD09 L
SD3_ TA_ PROG_ GND087 D1_ D1_ D1_ D1_ D1_ D1_ D1_ G1VDD10 D1_ D1_
M OVDD7 GND082 GND083 GND084 GND085 GND086 PROG_
SFP
MTR MDQ02 MDQ03 MDQS13 MDQ32 MDQ33 GND088 MDQS05MDQS05_B MCK3 MCK3_B M
SD3_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
N GND71 OVDD01 OVDD02 OVDD03 OVDD04 OVDD05 GND093 VDD01 GND094 G1VDD11 GND095MDQS13_BGND096MDQS04_BMDQ47 MDQ46 GND097 MBA1 MA00 MPAR N
SD3_ NC_ G1VDD12 GND110 D1_ D1_ D1_ D1_ D1_ D1_ D1_
P SVDD7 GND106 VDD02 GND107 VDD03 GND108 VDD04 GND109 P28 MDQ39 MDQ38 MDQS04 GND111 MDQ43 MDQ42 MBA0 G1VDD13 MA10 P
NC_ D1_ GND124 D1_ D1_ D1_ D1_ D1_ D1_
R GND118 VDD09 GND119 VDD10 GND120 VDD11 GND121
R27
GND122 G1VDD14 GND123 MDQ35
MDQ34 MDQ61 MDQ60 GND125 MCS0_B MWE_B MRAS_B R
VDD15 GND134 VDD16 GND135 VDD17 GND136 VDD18 GND137 AVDD_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
T D1 G1VDD15 GND138 MDQ49 MDQ53 MDQ52 GND139 MDQ57 MDQ56 MCAS_BG1VDD16 MCS2_B T
NC_ D1_ D1_ GND152 D1_ D1_ D1_ D1_ D1_ D1_
U GND147 VDD23 GND148 VDD24 GND149 VDD25 GND150
U27 TPA
G1VDD17 GND151 MDQ55
MDQ48MDQS16_BMDQS16 GND153 MA13 MODT0 MODT2 U
NC_ G1VDD18 GND164 D1_ D1_ D1_ D1_ D1_ D1_ D1_
V VDD30 GND160 VDD31 GND161 VDD32 GND162 VDD33 GND163
V28 MDQ50MDQS15_BMDQS15 GND165 MDQS07MDQS07_BMCS1_B G1VDD19 MCS3_B V
NC_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
W GND173 VDD38 GND174 VDD39 GND175 VDD40 GND176
W27
GND177 G1VDD20 GND178 MDQ51
MDQS06MDQS06_BMDQ58 MDQ63 MDQ62 MODT1 MODT3 MA17 W
D2_ GND190 D1_ D1_ D2_ D1_ D2_
Y VDD44 GND185 VDD45 GND186 VDD46 GND187 VDD47 GND188 OVDD12 DDRCLK GND189 MDQ50
MDQ54 MDQ59 GND191 MDQ59 GND192MRESET_B
MRESET_B Y
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

DDRC1 DDRC2 I2C1 I2C2 I2C3

I2C4 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 GIC500 SNVS System Control

Clocking EPU DFT JTAG Analog Signals

Serdes 1 Serdes 2 Serdes 3 USB PHY 1 and 2 EC1

EC2 RCLK Ethernet MI 1 Ethernet MI 2 SPI3

DDR Power Ground No-Connects

Figure 6. Detail B

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 9 / 198
NXP Semiconductors
Pin assignments

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
Y Y1 Y2 Y3 Y4 Y5 GND179 Y7 Y8 Y9 GND180 Y11
OVDD11 GND181 VDD41 GND182 VDD42 GND183 VDD43 GND184 VDD44
Y
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
AA AA1 AA2 AA3
GND193
AA5 AA6 AA7
GND194
AA9
GND195
AA11
GND196 VDD48 GND197 VDD49 GND198 VDD50 GND199 VDD51 GND200
AA
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
AB AB1 AB2 AB3 AB4 AB5
GND206
AB7 AB8 AB9
GND207
AB11 AB12
GND208 VDD55 GND209 VDD56 GND210 VDD57 GND211 VDD58
AB
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
AC AC1 AC2 AC3
GND218
AC5 AC6 AC7
GND219
AC9
GND220
AC11 AC12
VDD62 GND221 VDD63 GND222 VDD64 GND223 VDD65 GND224
AC
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
AD AD1 AD2 AD3 AD4 AD5 GND231 AD7 AD8 AD9 GND232 AD11
VDD69 GND233 VDD70 GND234 VDD71 GND235 VDD72 GND236 VDD73
AD
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_
AE AE1 AE2 AE3 GND243 AE5 AE6 AE7 GND244 AE9 GND245 AE11 GND246 VDD77 GND247 VDD78 GND248 VDD79 GND249 VDD80 GND250
AE
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AF AF1 AF2 AF3 AF4 AF5 GND258 AF7 AF8 AF9 GND259 AF11 SVDD01 SVDD02 SVDD03 SVDD04 SVDD05 SVDD06 SVDD07 SVDD08 SVDD09 AF
NC_ NC_ NC_ NC_ NC_ NC_ NC_ SENSE
GND264 VDD_ GND265 SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AG AG1 AG2 AG3
GND263
AG5 AG6 AG7 AG8 PL GND01 GND02 GND03 GND04 GND05 GND06 GND07 GND08 GND09 AG
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AH AH1 AH2 AH3 AH4 AH5 AH6
GND269
AH8 AH9 AH10
GND270 OVDD01 OVDD02 OVDD03 OVDD04 GND15 OVDD05 OVDD06 GND16 OVDD07 AH
NC_ NC_ NC_ NC_ NC_ NC_ NC_ NC_ SENSE SD_
SD1_ SD1_ SD1_ AVDD_ SD1_ SD1_ AVDD_ SD1_
AJ AJ1 AJ2 AJ3 AJ4
GND273
AJ6 AJ7 AJ8 AJ9
GND274 GND_
PL
IMP_ PLLS_
GND20 CAL_TX TPD
PLLS_
TPA
SD1_
PLLS
PLLF_
TPD
PLLF_
TPA
SD1_ IMP_
PLLF CAL_RX AJ
NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AK AK1 AK2 AK3
GND277
AK5 AK6
GND278
AK8
GND279 GND21
GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 AK
SD1_ SD1_ SD1_ SD1_ SD2_
NC_ NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ NC_ SD_
AL AL1 AL2 AL3 AL4
GND283
AL6 AL7 AL8 GND39
TX1_
N GND40
TX3_
N GND41
TX4_
N GND42
TX6_
N GND43 AL18 GND44
TX1_
N AL
SD1_ SD1_ SD1_ SD1_ SD2_
NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AM AM1 AM2
GND286
AM4 AM5 AM6 AM7
GND287 GND49 TX1_
P GND50
TX3_
P GND51
TX4_
P GND52
TX6_
P GND53 GND54 GND55
TX1_
P AM
SD1_ SD1_ SD1_ SD1_ SD2_
NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AN AN1 AN2 AN3 AN4 AN5
GND291
AN7 GND60
TX0_
N GND61
TX2_
N GND62 GND63 GND64
TX5_
N GND65
TX7_
N GND66
TX0_
N GND67 AN
SD1_ SD1_ SD1_ SD1_ SD1_ SD2_
NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AP AP1 AP2
GND294
AP4
GND295
AP6 AP7 GND73
TX0_
P GND74
TX2_
P
PLLS_
GND75REF_CLK_NGND76
TX5_
P GND77
TX7_
P GND78
TX0_
P GND79 AP
SD1_
NC_ NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AR AR1 AR2 AR3 AR4 AR5 AR6 AR7
GND298 GND84 PLLS_
GND85 GND86 GND87REF_CLK_PGND88 GND89 GND90 GND91 GND92 GND93 GND94 AR
SD1_ SD1_ SD1_ SD1_ DIFF_ SD2_
NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SYSCLK_ SD_
AT AT1 AT2 AT3 GND301 AT5 GND302 AT7 AT8 GND101
RX1_
N GND102
RX3_
N GND103
RX4_
N GND104
RX6_
N GND105 N GND106
RX1_
N AT
SD1_ SD1_ SD1_ SD1_ DIFF_ SD2_
NC_ NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SYSCLK_ SD_
AU AU1 AU2 GND305 AU4 AU5 AU6 AU7 GND306 GND111 RX1_
P GND112
RX3_
P GND113
RX4_
P GND114
RX6_
P GND115 P GND116
RX1_
P AU
SD1_ SD1_ SD1_ SD1_ SD1_ SD2_
NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AV AV1 AV2 AV3 GND309 AV5 GND310 AV7 GND121
RX0_
N GND122
RX2_
N
PLLF_
GND123REF_CLK_NGND124
RX5_
N GND125
RX7_
N GND126
RX0_
N GND127 AV
SD1_ SD1_ SD1_ SD1_ SD1_ SD2_
NC_ NC_ NC_ NC_ NC_ SD_ SD_ SD_ SD_ SD_ SD_ SD_
AW GND313 AW3 AW4 AW5 AW6 AW7 GND132
RX0_
P GND133
RX2_
P
PLLF_
GND134REF_CLK_PGND135
RX5_
P GND136
RX7_
P GND137
RX0_
P GND138 AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

DDRC1 DDRC2 I2C1 I2C2 I2C3

I2C4 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 GIC500 SNVS System Control

Clocking EPU DFT JTAG Analog Signals

Serdes 1 Serdes 2 Serdes 3 USB PHY 1 and 2 EC1

EC2 RCLK Ethernet MI 1 Ethernet MI 2 SPI3

DDR Power Ground No-Connects

Figure 7. Detail C

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 10 / 198
NXP Semiconductors
Pin assignments

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
D2_ D1_ D1_ D2_ D1_ D2_
Y VDD44 GND185 VDD45 GND186 VDD46 GND187 VDD47 GND188 OVDD12 DDRCLK GND189 MDQ50 GND190 MDQ54 MDQ59 GND191 MDQ59 GND192MRESET_B
MRESET_B Y
NC_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AA GND200 VDD52 GND201 VDD53 GND202 VDD54 GND203
AA27
GND204 G2VDD01 GND205 MDQ51 MDQS06MDQS06_BMDQ58 MDQ63 MDQ62 MODT1 MODT3 MA17 AA
D2_
G2VDD02 GND216 D2_ MDQS15_BMDQS15 GND217 MDQS07MDQS07_BMCS1_B G2VDD03 MCS3_B
D2_ D2_ D2_ D2_ D2_ D2_
AB VDD58 GND212 VDD59 GND213 VDD60 GND214 VDD61 GND215 TPA MDQ55 AB
NC_ AVDD_ G2VDD04 D2_ D2_ D2_ D2_ D2_ D2_ D2_
AC GND224 VDD66 GND225 VDD67 GND226 VDD68 GND227
AC27 D2 GND228 MDQ54 GND229 MDQ48MDQS16_BMDQS16 GND230 MA13 MODT0 MODT2 AC
NC_ G2VDD05 GND241 D2_ D2_ D2_ D2_ D2_ D2_ D2_
AD VDD73 GND237 VDD74 GND238 VDD75 GND239 VDD76 GND240
AD28 MDQ49 MDQ53 MDQ52 GND242 MDQ57 MDQ56 MCAS_BG2VDD06 MCS2_B AD
NC_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AE GND250 VDD81 GND251 VDD82 GND252 VDD83 GND253 AE27 GND254 G2VDD07 GND255 MDQ35 GND256 MDQ34 MDQ61 MDQ60 GND257 MCS0_B MWE_B MRAS_B
AE
SD_ SD_ SD_ SD_ SD_ SD_ NC_ G2VDD08 GND261 D2_ D2_ D2_ D2_ D2_ D2_ D2_
AF SVDD09 SVDD10 SVDD11 SVDD12 SVDD13 SVDD14 VDD84 GND260 AF28 MDQ39 MDQ38 MDQS04 GND262 MDQ43 MDQ42 MBA0 G2VDD09 MA10 AF
SD_ SD_ SD_ SD_ SD_ SD_ SENSE SENSE NC_ G2VDD10 GND266 D2_ GND267 D2_ D2_ D2_ D2_ D2_ D2_
AG GND09 GND10 GND11 GND12 GND13 GND14
GND_
CB
VDD_
CB AG28 MDQS13_B MDQS04_BMDQ47 MDQ46 GND268 MBA1 MA00 MPAR AG
SD2_
SD_ SD_ SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AH OVDD07 OVDD08 GND17 OVDD09 OVDD10 GND18
PLLS_
TPD
G2VDD11 MCK3 MCK3_B
GND19 GND271 MDQ02 MDQ03 MDQS13 MDQ32 MDQ33 GND272 MDQS05MDQS05_B AH
SD1_ SD2_ AVDD_ SD2_ SD2_ AVDD_ SD2_ SD2_
FA1_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AJ IMP_ IMP_ SD2_
CAL_RX CAL_RX PLLF
PLLF_
TPA
PLLF_
TPD
SD2_
PLLS
PLLS_ IMP_
TPA CAL_TX CVL MDQ01 MDQ06 MDQ07 GND275 MDQ37MDQS14_BMDQS14 GND276 MCK2 MCK2_BG2VDD12 AJ
SD_ SD_ SD_ SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ G2VDD13 D2_ D2_
AK GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND280 MDQ00 GND281MDQS00_BMDQS00 MDQ36 GND282 MDQ41 MDQ40 MCK1 MCK1_B AK
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ FA1_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AL TX1_
N GND45
TX3_
N GND46
TX4_
N GND47
TX6_
N GND48 CPIN MDQ04 MDQS09MDQS09_BGND284 MDQ19 MDQ45 MDQ44 GND285 MCK0 MCK0_BG2VDD14 AL
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AM TX1_
P GND56
TX3_
P GND57
TX4_
P GND58
TX6_
P GND59 GND288 MDQ05 GND289 MDQ17 MDQ23 MDQ18 GND290 MECC2 MECC3 MDIC G2VDD15 MA02 AM
SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AN GND67
TX2_
N GND68 GND69 GND70
TX5_
N GND71
TX7_
N GND72 MDQ10 MDQ11 MDQ16 GND292 MDQ22 MECC6 MECC7 GND293 MA04 MA03 MA01 AN
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AP GND79
TX2_
P
PLLF_
GND80REF_CLK_PGND81
TX5_
P GND82
TX7_
P GND83 MDQ15 GND296 MDQ20MDQS02_BMDQS02 GND297MDQS08_BMDQS08 MA06
G2VDD16 MA05
AP
SD2_
SD_ SD_ SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AR PLLF_
GND94 GND95 GND96REF_CLK_NGND97 GND98 GND99 GND100 GND299MDQS01_BMDQS01 MDQ21MDQS11_BMECC4 MDQS17MDQS17_BGND300 MA11 MA07 MA08 AR
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ FA1_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AT RX1_
N GND107
RX3_
N GND108
RX4_
N GND109
RX6_
N GND110 CGV MDQ12 GND303 MDQ14 MDQS11 GND304 MECC5 MECC0 MECC1 MA12 G2VDD17 MA09 AT
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AU RX1_
P GND117
RX3_
P GND118
RX4_
P GND119
RX6_
P GND120 GND307 MDQS10MDQS10_BMDQ24 MDQS12MDQS12_BMDQ26 GND308 MCKE1 MBG0 MBG1 MALERT_B AU
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ G2VDD18 D2_ D2_
AV GND127
RX2_
N
PLLS_
GND128REF_CLK_PGND129
RX5_
N GND130
RX7_
N GND131 MDQ08 GND311 MDQ29 GND312 MDQS03 MDQ31 MDQ27 MCKE0 MACT_BG2VDD19 AV
SD2_ SD2_ SD2_ SD2_
SD_ SD_ SD_ SD_ SD_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AW GND138
RX2_
P
PLLS_
GND139REF_CLK_NGND140
RX5_
P GND141
RX7_
P GND142 MDQ13 MDQ09 MDQ28 MDQ25MDQS03_BMDQ30 GND314 MCKE3 MCKE2
G2VDD20
AW
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

DDRC1 DDRC2 I2C1 I2C2 I2C3

I2C4 I2C6 XSPI1 ESDHC1 ESDHC2

UART1 UART2 GIC500 SNVS System Control

Clocking EPU DFT JTAG Analog Signals

Serdes 1 Serdes 2 Serdes 3 USB PHY 1 and 2 EC1

EC2 RCLK Ethernet MI 1 Ethernet MI 2 SPI3

DDR Power Ground No-Connects

Figure 8. Detail D

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 11 / 198
NXP Semiconductors
Pin assignments

2.2 Pinout list

This table provides the pinout listing for the LX2160A by bus. Primary functions are bolded in the table.

Table 2. Pinout list by bus

Signal Signal Description Package Pin Power Supply Notes

pin type
number

DDR SDRAM Memory Interface 1

D1_MA00 Address N38 O G1V DD ---

D1_MA01 Address G39 O G1V DD ---

D1_MA02 Address H39 O G1V DD ---

D1_MA03 Address G38 O G1V DD ---

D1_MA04 Address G37 O G1V DD ---

D1_MA05 Address F39 O G1V DD ---

D1_MA06 Address F37 O G1V DD ---

D1_MA07 Address E38 O G1V DD ---

D1_MA08 Address E39 O G1V DD ---

D1_MA09 Address D39 O G1V DD ---

D1_MA10 Address P39 O G1V DD ---

D1_MA11 Address E37 O G1V DD ---

D1_MA12 Address D37 O G1V DD ---

D1_MA13 Address U37 O G1V DD ---

D1_MA17 Address W39 O G1V DD ---

D1_MACT_B Activate B38 O G1V DD ---

D1_MALERT_B Alert C39 I G1V DD 1, 16

D1_MBA0 Bank Select P37 O G1V DD ---

D1_MBA1 Bank Select N37 O G1V DD ---

D1_MBG0 Bank Group C37 O G1V DD ---

D1_MBG1 Bank Group C38 O G1V DD ---

D1_MCAS_B Column Address Strobe / T37 O G1V DD ---

MA[15]

D1_MCK0 Clock J37 O G1V DD ---

D1_MCK0_B Clock Complement J38 O G1V DD ---

D1_MCK1 Clock K38 O G1V DD ---

D1_MCK1_B Clock Complement K39 O G1V DD ---

D1_MCK2 Clock L37 O G1V DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 12 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MCK2_B Clock Complement L38 O G1V DD ---

D1_MCK3 Clock M38 O G1V DD ---

D1_MCK3_B Clock Complement M39 O G1V DD ---

D1_MCKE0 Clock Enable B37 O G1V DD 2

D1_MCKE1 Clock Enable C36 O G1V DD 2

D1_MCKE2 Clock Enable A37 O G1V DD 2

D1_MCKE3 Clock Enable A36 O G1V DD 2

D1_MCS0_B Chip Select R37 O G1V DD ---

D1_MCS1_B Chip Select V37 O G1V DD ---

D1_MCS2_B Chip Select / MCID[0] T39 O G1V DD ---

D1_MCS3_B Chip Select / MCID[1] V39 O G1V DD ---

D1_MDIC Driver Impedence Calibration H37 IO G1V DD 3

D1_MDQ00 Data K29 IO G1V DD ---

D1_MDQ01 Data L29 IO G1V DD ---

D1_MDQ02 Data M29 IO G1V DD ---

D1_MDQ03 Data M30 IO G1V DD ---

D1_MDQ04 Data J29 IO G1V DD ---

D1_MDQ05 Data H29 IO G1V DD ---

D1_MDQ06 Data L30 IO G1V DD ---

D1_MDQ07 Data L31 IO G1V DD ---

D1_MDQ08 Data B29 IO G1V DD ---

D1_MDQ09 Data A30 IO G1V DD ---

D1_MDQ10 Data G29 IO G1V DD ---

D1_MDQ11 Data G30 IO G1V DD ---

D1_MDQ12 Data D29 IO G1V DD ---

D1_MDQ13 Data A29 IO G1V DD ---

D1_MDQ14 Data D31 IO G1V DD ---

D1_MDQ15 Data F29 IO G1V DD ---

D1_MDQ16 Data G31 IO G1V DD ---

D1_MDQ17 Data H31 IO G1V DD ---

D1_MDQ18 Data H33 IO G1V DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 13 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MDQ19 Data J33 IO G1V DD ---

D1_MDQ20 Data F31 IO G1V DD ---

D1_MDQ21 Data E31 IO G1V DD ---

D1_MDQ22 Data G33 IO G1V DD ---

D1_MDQ23 Data H32 IO G1V DD ---

D1_MDQ24 Data C31 IO G1V DD ---

D1_MDQ25 Data A32 IO G1V DD ---

D1_MDQ26 Data C34 IO G1V DD ---

D1_MDQ27 Data B35 IO G1V DD ---

D1_MDQ28 Data A31 IO G1V DD ---

D1_MDQ29 Data B31 IO G1V DD ---

D1_MDQ30 Data A34 IO G1V DD ---

D1_MDQ31 Data B34 IO G1V DD ---

D1_MDQ32 Data M32 IO G1V DD ---

D1_MDQ33 Data M33 IO G1V DD ---

D1_MDQ34 Data R33 IO G1V DD ---

D1_MDQ35 Data R31 IO G1V DD ---

D1_MDQ36 Data K33 IO G1V DD ---

D1_MDQ37 Data L33 IO G1V DD ---

D1_MDQ38 Data P32 IO G1V DD ---

D1_MDQ39 Data P31 IO G1V DD ---

D1_MDQ40 Data K36 IO G1V DD ---

D1_MDQ41 Data K35 IO G1V DD ---

D1_MDQ42 Data P36 IO G1V DD ---

D1_MDQ43 Data P35 IO G1V DD ---

D1_MDQ44 Data J35 IO G1V DD ---

D1_MDQ45 Data J34 IO G1V DD ---

D1_MDQ46 Data N35 IO G1V DD ---

D1_MDQ47 Data N34 IO G1V DD ---

D1_MDQ48 Data U33 IO G1V DD ---

D1_MDQ49 Data T31 IO G1V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 14 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MDQ50 Data V31 IO G1V DD ---

D1_MDQ51 Data W31 IO G1V DD ---

D1_MDQ52 Data T33 IO G1V DD ---

D1_MDQ53 Data T32 IO G1V DD ---

D1_MDQ54 Data Y33 IO G1V DD ---

D1_MDQ55 Data U31 IO G1V DD ---

D1_MDQ56 Data T36 IO G1V DD ---

D1_MDQ57 Data T35 IO G1V DD ---

D1_MDQ58 Data W34 IO G1V DD ---

D1_MDQ59 Data Y34 IO G1V DD ---

D1_MDQ60 Data R35 IO G1V DD ---

D1_MDQ61 Data R34 IO G1V DD ---

D1_MDQ62 Data W36 IO G1V DD ---

D1_MDQ63 Data W35 IO G1V DD ---

D1_MDQS00 Data Strobe K32 IO G1V DD ---

D1_MDQS00_B Data Strobe K31 IO G1V DD ---

D1_MDQS01 Data Strobe E30 IO G1V DD ---

D1_MDQS01_B Data Strobe E29 IO G1V DD ---

D1_MDQS02 Data Strobe F33 IO G1V DD ---

D1_MDQS02_B Data Strobe F32 IO G1V DD ---

D1_MDQS03 Data Strobe B33 IO G1V DD ---

D1_MDQS03_B Data Strobe A33 IO G1V DD ---

D1_MDQS04 Data Strobe P33 IO G1V DD ---

D1_MDQS04_B Data Strobe N33 IO G1V DD ---

D1_MDQS05 Data Strobe M35 IO G1V DD ---

D1_MDQS05_B Data Strobe M36 IO G1V DD ---

D1_MDQS06 Data Strobe W32 IO G1V DD ---

D1_MDQS06_B Data Strobe W33 IO G1V DD ---

D1_MDQS07 Data Strobe V35 IO G1V DD ---

D1_MDQS07_B Data Strobe V36 IO G1V DD ---

D1_MDQS08 Data Strobe F36 IO G1V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 15 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MDQS08_B Data Strobe F35 IO G1V DD ---

D1_MDM00_B/D1_MDBI00_B/ Data Mask/Data Bus J30 IO G1V DD ---

D1_MDQS09 Inversion/Data Strobe (x4)

D1_MDQS09_B Data Strobe (x4 support) J31 IO G1V DD ---

D1_MDM01_B/D1_MDBI01_B/ Data Mask/Data Bus C29 IO G1V DD ---

D1_MDQS10 Inversion/Data Strobe (x4)

D1_MDQS10_B Data Strobe (x4 support) C30 IO G1V DD ---

D1_MDM02_B/D1_MDBI02_B/ Data Mask/Data Bus D32 IO G1V DD ---

D1_MDQS11 Inversion/Data Strobe (x4)

D1_MDQS11_B Data Strobe (x4 support) E32 IO G1V DD ---

D1_MDM03_B/D1_MDBI03_B/ Data Mask/Data Bus C32 IO G1V DD ---

D1_MDQS12 Inversion/Data Strobe (x4)

D1_MDQS12_B Data Strobe (x4 support) C33 IO G1V DD ---

D1_MDM04_B/D1_MDBI04_B/ Data Mask/Data Bus M31 IO G1V DD ---

D1_MDQS13 Inversion/Data Strobe (x4)

D1_MDQS13_B Data Strobe (x4 support) N31 IO G1V DD ---

D1_MDM05_B/D1_MDBI05_B/ Data Mask/Data Bus L35 IO G1V DD ---

D1_MDQS14 Inversion/Data Strobe (x4)

D1_MDQS14_B Data Strobe (x4 support) L34 IO G1V DD ---

D1_MDM06_B/D1_MDBI06_B/ Data Mask/Data Bus V33 IO G1V DD ---

D1_MDQS15 Inversion/Data Strobe (x4)

D1_MDQS15_B Data Strobe (x4 support) V32 IO G1V DD ---

D1_MDM07_B/D1_MDBI07_B/ Data Mask/Data Bus U35 IO G1V DD ---

D1_MDQS16 Inversion/Data Strobe (x4)

D1_MDQS16_B Data Strobe (x4 support) U34 IO G1V DD ---

D1_MDM08_B/D1_MDBI08_B/ Data Mask/Data Bus E34 IO G1V DD ---

D1_MDQS17 Inversion/Data Strobe (x4)

D1_MDQS17_B Data Strobe (x4 support) E35 IO G1V DD ---

D1_MECC0 Error Correcting Code D35 IO G1V DD ---

D1_MECC1 Error Correcting Code D36 IO G1V DD ---

D1_MECC2 Error Correcting Code H35 IO G1V DD ---

D1_MECC3 Error Correcting Code H36 IO G1V DD ---

D1_MECC4 Error Correcting Code E33 IO G1V DD ---

D1_MECC5 Error Correcting Code D34 IO G1V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 16 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D1_MECC6 Error Correcting Code G34 IO G1V DD ---

D1_MECC7 Error Correcting Code G35 IO G1V DD ---

D1_MODT0 On Die Termination U38 O G1V DD 2

D1_MODT1 On Die Termination / MCID[2] W37 O G1V DD 2

D1_MODT2 On Die Termination U39 O G1V DD 2

D1_MODT3 On Die Termination W38 O G1V DD 2

D1_MPAR Address Parity Out N39 O G1V DD ---

D1_MRAS_B Row Address Strobe / MA[16] R39 O G1V DD ---

D1_MRESET_B Reset to DRAM Y38 O G1V DD 16

D1_MWE_B Write Enable / MA[14] R38 O G1V DD ---

DDR SDRAM Memory Interface 2

D2_MA00 Address AG38 O G2V DD ---

D2_MA01 Address AN39 O G2V DD ---

D2_MA02 Address AM39 O G2V DD ---

D2_MA03 Address AN38 O G2V DD ---

D2_MA04 Address AN37 O G2V DD ---

D2_MA05 Address AP39 O G2V DD ---

D2_MA06 Address AP37 O G2V DD ---

D2_MA07 Address AR38 O G2V DD ---

D2_MA08 Address AR39 O G2V DD ---

D2_MA09 Address AT39 O G2V DD ---

D2_MA10 Address AF39 O G2V DD ---

D2_MA11 Address AR37 O G2V DD ---

D2_MA12 Address AT37 O G2V DD ---

D2_MA13 Address AC37 O G2V DD ---

D2_MA17 Address AA39 O G2V DD ---

D2_MACT_B Activate AV38 O G2V DD ---

D2_MALERT_B Alert AU39 I G2V DD 1, 16

D2_MBA0 Bank Select AF37 O G2V DD ---

D2_MBA1 Bank Select AG37 O G2V DD ---

D2_MBG0 Bank Group AU37 O G2V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 17 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D2_MBG1 Bank Group AU38 O G2V DD ---

D2_MCAS_B Column Address Strobe / AD37 O G2V DD ---

MA[15]

D2_MCK0 Clock AL37 O G2V DD ---

D2_MCK0_B Clock Complement AL38 O G2V DD ---

D2_MCK1 Clock AK38 O G2V DD ---

D2_MCK1_B Clock Complement AK39 O G2V DD ---

D2_MCK2 Clock AJ37 O G2V DD ---

D2_MCK2_B Clock Complement AJ38 O G2V DD ---

D2_MCK3 Clock AH38 O G2V DD ---

D2_MCK3_B Clock Complement AH39 O G2V DD ---

D2_MCKE0 Clock Enable AV37 O G2V DD 2

D2_MCKE1 Clock Enable AU36 O G2V DD 2

D2_MCKE2 Clock Enable AW37 O G2V DD 2

D2_MCKE3 Clock Enable AW36 O G2V DD 2

D2_MCS0_B Chip Select AE37 O G2V DD ---

D2_MCS1_B Chip Select AB37 O G2V DD ---

D2_MCS2_B Chip Select / MCID[0] AD39 O G2V DD ---

D2_MCS3_B Chip Select / MCID[1] AB39 O G2V DD ---

D2_MDIC Driver Impedence Calibration AM37 IO G2V DD 3

D2_MDQ00 Data AK29 IO G2V DD ---

D2_MDQ01 Data AJ29 IO G2V DD ---

D2_MDQ02 Data AH29 IO G2V DD ---

D2_MDQ03 Data AH30 IO G2V DD ---

D2_MDQ04 Data AL29 IO G2V DD ---

D2_MDQ05 Data AM29 IO G2V DD ---

D2_MDQ06 Data AJ30 IO G2V DD ---

D2_MDQ07 Data AJ31 IO G2V DD ---

D2_MDQ08 Data AV29 IO G2V DD ---

D2_MDQ09 Data AW30 IO G2V DD ---

D2_MDQ10 Data AN29 IO G2V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 18 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D2_MDQ11 Data AN30 IO G2V DD ---

D2_MDQ12 Data AT29 IO G2V DD ---

D2_MDQ13 Data AW29 IO G2V DD ---

D2_MDQ14 Data AT31 IO G2V DD ---

D2_MDQ15 Data AP29 IO G2V DD ---

D2_MDQ16 Data AN31 IO G2V DD ---

D2_MDQ17 Data AM31 IO G2V DD ---

D2_MDQ18 Data AM33 IO G2V DD ---

D2_MDQ19 Data AL33 IO G2V DD ---

D2_MDQ20 Data AP31 IO G2V DD ---

D2_MDQ21 Data AR31 IO G2V DD ---

D2_MDQ22 Data AN33 IO G2V DD ---

D2_MDQ23 Data AM32 IO G2V DD ---

D2_MDQ24 Data AU31 IO G2V DD ---

D2_MDQ25 Data AW32 IO G2V DD ---

D2_MDQ26 Data AU34 IO G2V DD ---

D2_MDQ27 Data AV35 IO G2V DD ---

D2_MDQ28 Data AW31 IO G2V DD ---

D2_MDQ29 Data AV31 IO G2V DD ---

D2_MDQ30 Data AW34 IO G2V DD ---

D2_MDQ31 Data AV34 IO G2V DD ---

D2_MDQ32 Data AH32 IO G2V DD ---

D2_MDQ33 Data AH33 IO G2V DD ---

D2_MDQ34 Data AE33 IO G2V DD ---

D2_MDQ35 Data AE31 IO G2V DD ---

D2_MDQ36 Data AK33 IO G2V DD ---

D2_MDQ37 Data AJ33 IO G2V DD ---

D2_MDQ38 Data AF32 IO G2V DD ---

D2_MDQ39 Data AF31 IO G2V DD ---

D2_MDQ40 Data AK36 IO G2V DD ---

D2_MDQ41 Data AK35 IO G2V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 19 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D2_MDQ42 Data AF36 IO G2V DD ---

D2_MDQ43 Data AF35 IO G2V DD ---

D2_MDQ44 Data AL35 IO G2V DD ---

D2_MDQ45 Data AL34 IO G2V DD ---

D2_MDQ46 Data AG35 IO G2V DD ---

D2_MDQ47 Data AG34 IO G2V DD ---

D2_MDQ48 Data AC33 IO G2V DD ---

D2_MDQ49 Data AD31 IO G2V DD ---

D2_MDQ50 Data Y31 IO G2V DD ---

D2_MDQ51 Data AA31 IO G2V DD ---

D2_MDQ52 Data AD33 IO G2V DD ---

D2_MDQ53 Data AD32 IO G2V DD ---

D2_MDQ54 Data AC31 IO G2V DD ---

D2_MDQ55 Data AB31 IO G2V DD ---

D2_MDQ56 Data AD36 IO G2V DD ---

D2_MDQ57 Data AD35 IO G2V DD ---

D2_MDQ58 Data AA34 IO G2V DD ---

D2_MDQ59 Data Y36 IO G2V DD ---

D2_MDQ60 Data AE35 IO G2V DD ---

D2_MDQ61 Data AE34 IO G2V DD ---

D2_MDQ62 Data AA36 IO G2V DD ---

D2_MDQ63 Data AA35 IO G2V DD ---

D2_MDQS00 Data Strobe AK32 IO G2V DD ---

D2_MDQS00_B Data Strobe AK31 IO G2V DD ---

D2_MDQS01 Data Strobe AR30 IO G2V DD ---

D2_MDQS01_B Data Strobe AR29 IO G2V DD ---

D2_MDQS02 Data Strobe AP33 IO G2V DD ---

D2_MDQS02_B Data Strobe AP32 IO G2V DD ---

D2_MDQS03 Data Strobe AV33 IO G2V DD ---

D2_MDQS03_B Data Strobe AW33 IO G2V DD ---

D2_MDQS04 Data Strobe AF33 IO G2V DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 20 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D2_MDQS04_B Data Strobe AG33 IO G2V DD ---

D2_MDQS05 Data Strobe AH35 IO G2V DD ---

D2_MDQS05_B Data Strobe AH36 IO G2V DD ---

D2_MDQS06 Data Strobe AA32 IO G2V DD ---

D2_MDQS06_B Data Strobe AA33 IO G2V DD ---

D2_MDQS07 Data Strobe AB35 IO G2V DD ---

D2_MDQS07_B Data Strobe AB36 IO G2V DD ---

D2_MDQS08 Data Strobe AP36 IO G2V DD ---

D2_MDQS08_B Data Strobe AP35 IO G2V DD ---

D2_MDM00_B/D2_MDBI00_B/ Data Mask/Data Bus AL30 IO G2V DD ---

D2_MDQS09 Inversion/Data Strobe (x4)

D2_MDQS09_B Data Strobe (x4 support) AL31 IO G2V DD ---

D2_MDM01_B/D2_MDBI01_B/ Data Mask/Data Bus AU29 IO G2V DD ---

D2_MDQS10 Inversion/Data Strobe (x4)

D2_MDQS10_B Data Strobe (x4 support) AU30 IO G2V DD ---

D2_MDM02_B/D2_MDBI02_B/ Data Mask/Data Bus AT32 IO G2V DD ---

D2_MDQS11 Inversion/Data Strobe (x4)

D2_MDQS11_B Data Strobe (x4 support) AR32 IO G2V DD ---

D2_MDM03_B/D2_MDBI03_B/ Data Mask/Data Bus AU32 IO G2V DD ---

D2_MDQS12 Inversion/Data Strobe (x4)

D2_MDQS12_B Data Strobe (x4 support) AU33 IO G2V DD ---

D2_MDM04_B/D2_MDBI04_B/ Data Mask/Data Bus AH31 IO G2V DD ---

D2_MDQS13 Inversion/Data Strobe (x4)

D2_MDQS13_B Data Strobe (x4 support) AG31 IO G2V DD ---

D2_MDM05_B/D2_MDBI05_B/ Data Mask/Data Bus AJ35 IO G2V DD ---

D2_MDQS14 Inversion/Data Strobe (x4)

D2_MDQS14_B Data Strobe (x4 support) AJ34 IO G2V DD ---

D2_MDM06_B/D2_MDBI06_B/ Data Mask/Data Bus AB33 IO G2V DD ---

D2_MDQS15 Inversion/Data Strobe (x4)

D2_MDQS15_B Data Strobe (x4 support) AB32 IO G2V DD ---

D2_MDM07_B/D2_MDBI07_B/ Data Mask/Data Bus AC35 IO G2V DD ---

D2_MDQS16 Inversion/Data Strobe (x4)

D2_MDQS16_B Data Strobe (x4 support) AC34 IO G2V DD ---

Table continues on the next page...

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Data Sheet: Technical Data 21 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

D2_MDM08_B/D2_MDBI08_B/ Data Mask/Data Bus AR34 IO G2V DD ---

D2_MDQS17 Inversion/Data Strobe (x4)

D2_MDQS17_B Data Strobe (x4 support) AR35 IO G2V DD ---

D2_MECC0 Error Correcting Code AT35 IO G2V DD ---

D2_MECC1 Error Correcting Code AT36 IO G2V DD ---

D2_MECC2 Error Correcting Code AM35 IO G2V DD ---

D2_MECC3 Error Correcting Code AM36 IO G2V DD ---

D2_MECC4 Error Correcting Code AR33 IO G2V DD ---

D2_MECC5 Error Correcting Code AT34 IO G2V DD ---

D2_MECC6 Error Correcting Code AN34 IO G2V DD ---

D2_MECC7 Error Correcting Code AN35 IO G2V DD ---

D2_MODT0 On Die Termination AC38 O G2V DD 2

D2_MODT1 On Die Termination / MCID[2] AA37 O G2V DD 2

D2_MODT2 On Die Termination AC39 O G2V DD 2

D2_MODT3 On Die Termination AA38 O G2V DD 2

D2_MPAR Address Parity Out AG39 O G2V DD ---

D2_MRAS_B Row Address Strobe / MA[16] AE39 O G2V DD ---

D2_MRESET_B Reset to DRAM Y39 O G2V DD 16

D2_MWE_B Write Enable / MA[14] AE38 O G2V DD ---

I2C1

IIC1_SCL /GPIO1_DAT03 Serial Clock F5 IO OV DD 5, 6

IIC1_SDA /GPIO1_DAT02 Serial Data G5 IO OV DD 5, 6

I2C2

IIC2_SCL /GPIO1_DAT31 / Serial Clock E3 IO OV DD 5, 6

FTM1_CH0 /SDHC1_CD_B

IIC2_SDA /GPIO1_DAT30 / Serial Data E4 IO OV DD 5, 6

FTM2_CH0 /SDHC1_WP

I2C3

IIC3_SCL /GPIO1_DAT29 / Serial Clock H5 IO OV DD 5, 6

CAN1_TX /EVT5_B

IIC3_SDA /GPIO1_DAT28 / Serial Data J5 IO OV DD 5, 6

CAN1_RX /EVT6_B

I2C4

Table continues on the next page...

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Data Sheet: Technical Data 22 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

IIC4_SCL /GPIO1_DAT27 / Serial Clock K5 IO OV DD 5, 6

CAN2_TX /EVT7_B

IIC4_SDA /GPIO1_DAT26 / Serial Data L5 IO OV DD 5, 6

CAN2_RX /EVT8_B

I2C5

IIC5_SCL/ SPI3_SOUT / Serial Clock C4 IO OV DD 5, 6

GPIO1_DAT25 /
SDHC1_CLK_SYNC_OUT

IIC5_SDA/ SPI3_SIN / Serial Data D3 IO OV DD 5, 6

GPIO1_DAT24 /
SDHC1_CLK_SYNC_IN

I2C6

IIC6_SCL /GPIO1_DAT23 / Serial Clock D27 IO OV DD 5, 6

SDHC2_CLK_SYNC_OUT

IIC6_SDA /GPIO1_DAT22 / Serial Data C27 IO OV DD 5, 6

SDHC2_CLK_SYNC_IN

I2C7

IIC7_SCL/ SDHC2_DAT5 / Serial Clock B27 IO OV DD 5, 6

GPIO2_DAT16 /
XSPI1_B_DATA5

IIC7_SDA/ SDHC2_DAT4 / Serial Data C26 IO OV DD 5, 6

GPIO2_DAT15 /
XSPI1_B_DATA4

I2C8

IIC8_SCL/ SDHC2_DAT7 / Serial Clock A27 IO OV DD 5, 6

GPIO2_DAT18 /
XSPI1_B_DATA7

IIC8_SDA/ SDHC2_DAT6 / Serial Data A26 IO OV DD 5, 6

GPIO2_DAT17 /
XSPI1_B_DATA6

XSPI1

XSPI1_A_CS0_B / Chip Select C23 O OV DD 1

GPIO2_DAT21

XSPI1_A_CS1_B / Chip Select D23 O OV DD 1

GPIO2_DAT20

XSPI1_A_DATA0 / Data F25 IO OV DD ---

GPIO2_DAT24

Table continues on the next page...

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Data Sheet: Technical Data 23 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

XSPI1_A_DATA1 / Data E24 IO OV DD ---

GPIO2_DAT25

XSPI1_A_DATA2 / Data E26 IO OV DD ---

GPIO2_DAT26

XSPI1_A_DATA3 / Data E27 IO OV DD ---

GPIO2_DAT27

XSPI1_A_DATA4 / Data F27 IO OV DD ---

GPIO2_DAT28

XSPI1_A_DATA5 / Data D26 IO OV DD ---

GPIO2_DAT29

XSPI1_A_DATA6 / Data E25 IO OV DD ---

GPIO2_DAT30

XSPI1_A_DATA7 / Data D24 IO OV DD ---

GPIO2_DAT31

XSPI1_A_DQS / Data Strobe E23 IO OV DD ---

GPIO2_DAT23

XSPI1_A_SCK / Clock D22 O OV DD 1

GPIO2_DAT22 /cfg_eng_use0

XSPI1_B_CS1_B/ Chip Select B25 O OV DD 1

SDHC2_CMD /
GPIO2_DAT19 /SPI2_SOUT

XSPI1_B_DATA0/ Data A23 IO OV DD

SDHC2_DAT0 /
GPIO2_DAT11 /SPI2_SIN /
cfg_gpinput4

XSPI1_B_DATA1/ Data C24 IO OV DD

SDHC2_DAT1 /
GPIO2_DAT12 /SPI2_PCS2 /
cfg_gpinput5

XSPI1_B_DATA2/ Data B23 IO OV DD

SDHC2_DAT2 /
GPIO2_DAT13 /SPI2_PCS1 /
cfg_gpinput6

XSPI1_B_DATA3/ Data A24 IO OV DD

SDHC2_DAT3 /
GPIO2_DAT14 /SPI2_PCS0 /
cfg_gpinput7

XSPI1_B_DATA4/ Data C26 IO OV DD ---

SDHC2_DAT4 /
GPIO2_DAT15 /IIC7_SDA

Table continues on the next page...

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Data Sheet: Technical Data 24 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

XSPI1_B_DATA5/ Data B27 IO OV DD ---

SDHC2_DAT5 /
GPIO2_DAT16 /IIC7_SCL

XSPI1_B_DATA6/ Data A26 IO OV DD ---

SDHC2_DAT6 /
GPIO2_DAT17 /IIC8_SDA

XSPI1_B_DATA7/ Data A27 IO OV DD ---

SDHC2_DAT7 /
GPIO2_DAT18 /IIC8_SCL

XSPI1_B_DQS/ SDHC2_DS / Data Strobe C25 IO OV DD ---

GPIO2_DAT10 /SPI2_PCS3

XSPI1_B_SCK/ SDHC2_CLK / Clock A25 O OV DD 1

GPIO2_DAT09 /SPI2_SCK

eSDHC 1

SDHC1_CD_B/ IIC2_SCL / Card Detect E3 I OV DD 1

GPIO1_DAT31 /FTM1_CH0

SDHC1_CLK /GPIO1_DAT16 / Host to Card Clock D1 O EV DD 1

SPI1_SCK

SDHC1_CLK_SYNC_IN/ Input Synchronous Clock D3 I OV DD 1

SPI3_SIN /GPIO1_DAT24 /
IIC5_SDA

SDHC1_CLK_SYNC_OUT/ Output Synchronuous Clock C4 O OV DD 1

SPI3_SOUT /GPIO1_DAT25 /
IIC5_SCL

SDHC1_CMD / Command/Response E1 IO EV DD 5
GPIO1_DAT21 /SPI1_SOUT

SDHC1_CMD_DIR/ Command Direction A4 O OV DD 1

SPI3_PCS1 /GPIO1_DAT14 /
SDHC1_DAT5

SDHC1_DAT0 / Data F1 IO EV DD 5
GPIO1_DAT17 /SPI1_SIN /
cfg_gpinput0

SDHC1_DAT0_DIR/ DAT0 Direction B3 O OV DD 1

SPI3_PCS2 /GPIO1_DAT13 /
SDHC1_DAT6

SDHC1_DAT1 / Data E2 IO EV DD 5
GPIO1_DAT18 /SPI1_PCS2 /
cfg_gpinput1

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 25 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SDHC1_DAT123_DIR/ DATA[1:3] Direction C3 O OV DD 1

SPI3_PCS3 /GPIO1_DAT12 /
SDHC1_DAT7

SDHC1_DAT2 / Data C1 IO EV DD 5
GPIO1_DAT19 /SPI1_PCS1 /
cfg_gpinput2

SDHC1_DAT3 / Data C2 IO EV DD 5
GPIO1_DAT20 /SPI1_PCS0 /
cfg_gpinput3

SDHC1_DAT4/ SPI3_PCS0 / Data A3 IO OV DD ---

GPIO1_DAT15 /SPI1_PCS3 /
SDHC1_VSEL

SDHC1_DAT5/ SPI3_PCS1 / Data A4 IO OV DD ---

GPIO1_DAT14 /
SDHC1_CMD_DIR

SDHC1_DAT6/ SPI3_PCS2 / Data B3 IO OV DD ---

GPIO1_DAT13 /
SDHC1_DAT0_DIR

SDHC1_DAT7/ SPI3_PCS3 / Data C3 IO OV DD ---

GPIO1_DAT12 /
SDHC1_DAT123_DIR

SDHC1_DS/ SPI3_SCK / Data Strobe (eMMC HS400 B2 I OV DD 1

GPIO4_DAT29 mode)

SDHC1_VSEL/ SPI3_PCS0 / SDHC Voltage Select A3 O OV DD 1

GPIO1_DAT15 /SPI1_PCS3 /
SDHC1_DAT4

SDHC1_WP/ IIC2_SDA / Write Protect E4 I OV DD 1

GPIO1_DAT30 /FTM2_CH0

eSDHC 2

SDHC2_CLK /GPIO2_DAT09 / Host to Card Clock A25 O OV DD 1

SPI2_SCK /XSPI1_B_SCK

SDHC2_CLK_SYNC_IN/ Input Synchronous Clock C27 I OV DD 1

IIC6_SDA /GPIO1_DAT22

SDHC2_CLK_SYNC_OUT/ Output Synchronuous Clock D27 O OV DD 1

IIC6_SCL /GPIO1_DAT23

SDHC2_CMD / Command/Response B25 IO OV DD 5

GPIO2_DAT19 /SPI2_SOUT /
XSPI1_B_CS1_B

SDHC2_DAT0 / Data A23 IO OV DD 5

GPIO2_DAT11 /SPI2_SIN /

Table continues on the next page...

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Data Sheet: Technical Data 26 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

XSPI1_B_DATA0 /
cfg_gpinput4

SDHC2_DAT1 / Data C24 IO OV DD 5

GPIO2_DAT12 /SPI2_PCS2 /
XSPI1_B_DATA1 /
cfg_gpinput5

SDHC2_DAT2 / Data B23 IO OV DD 5

GPIO2_DAT13 /SPI2_PCS1 /
XSPI1_B_DATA2 /
cfg_gpinput6

SDHC2_DAT3 / Data A24 IO OV DD 5

GPIO2_DAT14 /SPI2_PCS0 /
XSPI1_B_DATA3 /
cfg_gpinput7

SDHC2_DAT4 / Data C26 IO OV DD 5

GPIO2_DAT15 /IIC7_SDA /
XSPI1_B_DATA4

SDHC2_DAT5 / Data B27 IO OV DD 5

GPIO2_DAT16 /IIC7_SCL /
XSPI1_B_DATA5

SDHC2_DAT6 / Data A26 IO OV DD 5

GPIO2_DAT17 /IIC8_SDA /
XSPI1_B_DATA6

SDHC2_DAT7 / Data A27 IO OV DD 5

GPIO2_DAT18 /IIC8_SCL /
XSPI1_B_DATA7

SDHC2_DS /GPIO2_DAT10 / Data Strobe (eMMC HS400 C25 I OV DD 1, 11

SPI2_PCS3 /XSPI1_B_DQS mode)

UART

UART1_CTS_B / Clear To Send A6 I OV DD 1

GPIO1_DAT08 /UART3_SIN

UART1_RTS_B / Ready to Send A5 O OV DD 1

GPIO1_DAT09 /
UART3_SOUT

UART1_SIN /GPIO1_DAT10 Receive Data B5 I OV DD 1

UART1_SOUT / Transmit Data B6 O OV DD 1

GPIO1_DAT11 /cfg_rcw_src1

UART2_CTS_B / Clear To Send C6 I OV DD 1

GPIO1_DAT04 /UART4_SIN

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 27 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

UART2_RTS_B / Ready to Send C5 O OV DD 1

GPIO1_DAT05 /
UART4_SOUT /cfg_eng_use2

UART2_SIN /GPIO1_DAT06 Receive Data D5 I OV DD 1

UART2_SOUT / Transmit Data D6 O OV DD 1

GPIO1_DAT07 /cfg_rcw_src0

UART3_SIN/ UART1_CTS_B / Serial Input A6 I OV DD 1

GPIO1_DAT08

UART3_SOUT/ Serial Output A5 O OV DD 1

UART1_RTS_B /
GPIO1_DAT09

UART4_SIN/ UART2_CTS_B / Serial Input C6 I OV DD 1

GPIO1_DAT04

UART4_SOUT/ Serial Output C5 O OV DD 1

UART2_RTS_B /
GPIO1_DAT05 /cfg_eng_use2

Interrupt Controller

IRQ00 /GPIO3_DAT00 / External Interrupt H9 I OV DD 1

FTM1_CH4

IRQ01 /GPIO3_DAT01 / External Interrupt H10 I OV DD 1

FTM2_CH4

IRQ02 /GPIO3_DAT02 / External Interrupt H11 I OV DD 1

FTM1_CH5

IRQ03 /GPIO3_DAT03 / External Interrupt J7 I OV DD 1

FTM2_CH5

IRQ04 /GPIO3_DAT04 / External Interrupt J11 I OV DD 1

FTM1_CH6

IRQ05 /GPIO3_DAT05 / External Interrupt J9 I OV DD 1

FTM2_CH6

IRQ06 /GPIO3_DAT06 / External Interrupt H6 I OV DD 1

FTM1_CH7

IRQ07 /GPIO3_DAT07 / External Interrupt K6 I OV DD 1

FTM2_CH7

IRQ08 /GPIO3_DAT08 External Interrupt H7 I OV DD 1

IRQ09 /GPIO3_DAT09 External Interrupt K7 I OV DD 1

IRQ10 /GPIO3_DAT10 External Interrupt H8 I OV DD 1

IRQ11 /GPIO3_DAT11 External Interrupt K8 I OV DD 1

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 28 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

Trust

TA_BB_TMP_DETECT_B Battery Backed Tamper Detect J27 I TA_BB_V DD ---

TA_TMP_DETECT_B Tamper Detect N9 I OV DD ---

System Control

HRESET_B Hard Reset F6 IO OV DD 5, 6

PORESET_B Power On Reset E5 I OV DD ---

RESET_REQ_B / Reset Request (POR or Hard) M9 O OV DD 1, 17

GPIO2_DAT08

Clocking

DDRCLK DDR Controller Clock Y29 I OV DD ---

DIFF_SYSCLK_N Differential System Clock AT18 I SD3_SV DD ---

(negative)

DIFF_SYSCLK_P Differential System Clock AU18 I SD3_SV DD ---

(positive)

EC_GTX_CLK125 / Reference Clock P3 I OV DD 1

GPIO4_DAT24

Debug

ASLEEP /GPIO2_DAT06 / Asleep M7 O OV DD 1, 4

EVT9_B /cfg_rcw_src2

CLK_OUT /GPIO2_DAT07 / Clock Out L6 O OV DD 2

FTM1_CH1 /cfg_rcw_src3

CLK_OUT2/ EC1_TXD0 / Clock Output J3 O OV DD 1

GPIO4_DAT03

EVT0_B /GPIO3_DAT12 / Event 0 K9 IO OV DD 7

FTM2_CH1

EVT1_B /GPIO3_DAT13 / Event 1 L11 IO OV DD 7

FTM1_CH2

EVT2_B /GPIO3_DAT14 / Event 2 G6 IO OV DD 7

FTM2_CH2

EVT3_B /GPIO3_DAT15 / Event 3 L10 IO OV DD 7

FTM1_CH3

EVT4_B /GPIO3_DAT16 / Event 4 M10 IO OV DD 7

FTM2_CH3

EVT5_B/ IIC3_SCL / Event 5 H5 IO OV DD ---

GPIO1_DAT29 /CAN1_TX

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 29 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EVT6_B/ IIC3_SDA / Event 6 J5 IO OV DD ---

GPIO1_DAT28 /CAN1_RX

EVT7_B/ IIC4_SCL / Event 7 K5 IO OV DD ---

GPIO1_DAT27 /CAN2_TX

EVT8_B/ IIC4_SDA / Event 8 L5 IO OV DD ---

GPIO1_DAT26 /CAN2_RX

EVT9_B/ ASLEEP / Event 9 M7 O OV DD 1, 4

GPIO2_DAT06 /cfg_rcw_src2

DFT

SCAN_MODE_B Internal Use Only K10 I OV DD 8

TEST_SEL_B Internal Use Only E6 I OV DD 5

JTAG

TBSCAN_EN_B Test Boundary Scan Enable F23 I OV DD 5

TCK Test Clock G26 I OV DD ---

TDI Test Data In H27 I OV DD 7

TDO Test Data Out G27 O OV DD 2

TMS Test Mode Select G25 I OV DD 7

TRST_B Test Reset H26 I OV DD 7

Analog Signals

D1_TPA DDR Controller 1 Test Point U28 IO - 10

Analog

D2_TPA DDR Controller 2 Test Point AB28 IO G2V DD 10

Analog

FA1_CGV Internal Use Only AT28 IO - 12

FA1_CPIN Internal Use Only AL28 IO - 12

FA2_DGV Internal Use Only D28 IO - 12

FA2_DPIN Internal Use Only J28 IO - 12

TD1_ANODE Thermal diode anode K27 IO - 14

TD1_CATHODE Thermal diode cathode L27 IO - 14

TD2_ANODE Thermal diode anode J12 IO - 14

TD2_CATHODE Thermal diode cathode K12 IO - 14

TH_TPA Thermal Test Point Analog G24 - - 10

Serdes 1

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 30 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD1_IMP_CAL_RX SerDes Receive Impedence AJ20 I SD_SV DD 9

Calibration

SD1_IMP_CAL_TX SerDes Transmit Impedance AJ13 I SD_OV DD 13

Calibration

SD1_PLLF_REF_CLK_N SerDes PLL Fast Reference AV13 I SD_SV DD ---

Clock Complement

SD1_PLLF_REF_CLK_P SerDes PLL Fast Reference AW13 I SD_SV DD ---

Clock

SD1_PLLF_TPA SerDes PLL Fast Analog Test AJ18 O AVDD_SD1_PLLF 10

Point

SD1_PLLF_TPD SerDes PLL Fast Digital Test AJ17 O SD_SV DD 10

Point

SD1_PLLS_REF_CLK_N SerDes PLL Slow Reference AP13 I SD_SV DD ---

Clock Complement

SD1_PLLS_REF_CLK_P SerDes PLL Slow Reference AR13 I SD_SV DD ---

Clock

SD1_PLLS_TPA SerDes PLL Slow Analog Test AJ15 O AVDD_SD1_PLLS 10

Point

SD1_PLLS_TPD SerDes PLL Slow Digital Test AJ14 O SD_SV DD 10

Point

SD1_RX0_N SerDes Receive Data AV9 I SD_SV DD ---

(negative)

SD1_RX0_P SerDes Receive Data AW9 I SD_SV DD ---

(positive)

SD1_RX1_N SerDes Receive Data AT10 I SD_SV DD ---

(negative)

SD1_RX1_P SerDes Receive Data AU10 I SD_SV DD ---

(positive)

SD1_RX2_N SerDes Receive Data AV11 I SD_SV DD ---

(negative)

SD1_RX2_P SerDes Receive Data AW11 I SD_SV DD ---

(positive)

SD1_RX3_N SerDes Receive Data AT12 I SD_SV DD ---

(negative)

SD1_RX3_P SerDes Receive Data AU12 I SD_SV DD ---

(positive)

SD1_RX4_N SerDes Receive Data AT14 I SD_SV DD ---

(negative)

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 31 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD1_RX4_P SerDes Receive Data AU14 I SD_SV DD ---

(positive)

SD1_RX5_N SerDes Receive Data AV15 I SD_SV DD ---

(negative)

SD1_RX5_P SerDes Receive Data AW15 I SD_SV DD ---

(positive)

SD1_RX6_N SerDes Receive Data AT16 I SD_SV DD ---

(negative)

SD1_RX6_P SerDes Receive Data AU16 I SD_SV DD ---

(positive)

SD1_RX7_N SerDes Receive Data AV17 I SD_SV DD ---

(negative)

SD1_RX7_P SerDes Receive Data AW17 I SD_SV DD ---

(positive)

SD1_TX0_N SerDes Transmit Data AN9 O SD_OV DD ---

(negative)

SD1_TX0_P SerDes Transmit Data AP9 O SD_OV DD ---

(positive)

SD1_TX1_N SerDes Transmit Data AL10 O SD_OV DD ---

(negative)

SD1_TX1_P SerDes Transmit Data AM10 O SD_OV DD ---

(positive)

SD1_TX2_N SerDes Transmit Data AN11 O SD_OV DD ---

(negative)

SD1_TX2_P SerDes Transmit Data AP11 O SD_OV DD ---

(positive)

SD1_TX3_N SerDes Transmit Data AL12 O SD_OV DD ---

(negative)

SD1_TX3_P SerDes Transmit Data AM12 O SD_OV DD ---

(positive)

SD1_TX4_N SerDes Transmit Data AL14 O SD_OV DD ---

(negative)

SD1_TX4_P SerDes Transmit Data AM14 O SD_OV DD ---

(positive)

SD1_TX5_N SerDes Transmit Data AN15 O SD_OV DD ---

(negative)

SD1_TX5_P SerDes Transmit Data AP15 O SD_OV DD ---

(positive)

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 32 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD1_TX6_N SerDes Transmit Data AL16 O SD_OV DD ---

(negative)

SD1_TX6_P SerDes Transmit Data AM16 O SD_OV DD ---

(positive)

SD1_TX7_N SerDes Transmit Data AN17 O SD_OV DD ---

(negative)

SD1_TX7_P SerDes Transmit Data AP17 O SD_OV DD ---

(positive)

Serdes 2

SD2_IMP_CAL_RX SerDes Receive Impedence AJ21 I SD_SV DD 9

Calibration

SD2_IMP_CAL_TX SerDes Transmit Impedance AJ27 I SD_OV DD 13

Calibration

SD2_PLLF_REF_CLK_N SerDes PLL Fast Reference AR23 I SD_SV DD ---

Clock Complement

SD2_PLLF_REF_CLK_P SerDes PLL Fast Reference AP23 I SD_SV DD ---

Clock

SD2_PLLF_TPA SerDes PLL Fast Analog Test AJ23 O AVDD_SD2_PLLF 10

Point

SD2_PLLF_TPD SerDes PLL Fast Digital Test AJ24 O SD_SV DD 10

Point

SD2_PLLS_REF_CLK_N SerDes PLL Slow Reference AW23 I SD_SV DD ---

Clock Complement

SD2_PLLS_REF_CLK_P SerDes PLL Slow Reference AV23 I SD_SV DD ---

Clock

SD2_PLLS_TPA SerDes PLL Slow Analog Test AJ26 O AVDD_SD2_PLLS 10

Point

SD2_PLLS_TPD SerDes PLL Slow Digital Test AH26 O SD_SV DD 10

Point

SD2_RX0_N SerDes Receive Data AV19 I SD_SV DD ---

(negative)

SD2_RX0_P SerDes Receive Data AW19 I SD_SV DD ---

(positive)

SD2_RX1_N SerDes Receive Data AT20 I SD_SV DD ---

(negative)

SD2_RX1_P SerDes Receive Data AU20 I SD_SV DD ---

(positive)

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 33 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD2_RX2_N SerDes Receive Data AV21 I SD_SV DD ---

(negative)

SD2_RX2_P SerDes Receive Data AW21 I SD_SV DD ---

(positive)

SD2_RX3_N SerDes Receive Data AT22 I SD_SV DD ---

(negative)

SD2_RX3_P SerDes Receive Data AU22 I SD_SV DD ---

(positive)

SD2_RX4_N SerDes Receive Data AT24 I SD_SV DD ---

(negative)

SD2_RX4_P SerDes Receive Data AU24 I SD_SV DD ---

(positive)

SD2_RX5_N SerDes Receive Data AV25 I SD_SV DD ---

(negative)

SD2_RX5_P SerDes Receive Data AW25 I SD_SV DD ---

(positive)

SD2_RX6_N SerDes Receive Data AT26 I SD_SV DD ---

(negative)

SD2_RX6_P SerDes Receive Data AU26 I SD_SV DD ---

(positive)

SD2_RX7_N SerDes Receive Data AV27 I SD_SV DD ---

(negative)

SD2_RX7_P SerDes Receive Data AW27 I SD_SV DD ---

(positive)

SD2_TX0_N SerDes Transmit Data AN19 O SD_OV DD ---

(negative)

SD2_TX0_P SerDes Transmit Data AP19 O SD_OV DD ---

(positive)

SD2_TX1_N SerDes Transmit Data AL20 O SD_OV DD ---

(negative)

SD2_TX1_P SerDes Transmit Data AM20 O SD_OV DD ---

(positive)

SD2_TX2_N SerDes Transmit Data AN21 O SD_OV DD ---

(negative)

SD2_TX2_P SerDes Transmit Data AP21 O SD_OV DD ---

(positive)

SD2_TX3_N SerDes Transmit Data AL22 O SD_OV DD ---

(negative)

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 34 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD2_TX3_P SerDes Transmit Data AM22 O SD_OV DD ---

(positive)

SD2_TX4_N SerDes Transmit Data AL24 O SD_OV DD ---

(negative)

SD2_TX4_P SerDes Transmit Data AM24 O SD_OV DD ---

(positive)

SD2_TX5_N SerDes Transmit Data AN25 O SD_OV DD ---

(negative)

SD2_TX5_P SerDes Transmit Data AP25 O SD_OV DD ---

(positive)

SD2_TX6_N SerDes Transmit Data AL26 O SD_OV DD ---

(negative)

SD2_TX6_P SerDes Transmit Data AM26 O SD_OV DD ---

(positive)

SD2_TX7_N SerDes Transmit Data AN27 O SD_OV DD ---

(negative)

SD2_TX7_P SerDes Transmit Data AP27 O SD_OV DD ---

(positive)

Serdes 3

SD3_IMP_CAL_RX SerDes Receive Impedence L15 I SD3_SV DD 9

Calibration

SD3_IMP_CAL_TX SerDes Transmit Impedance L20 I SD3_OV DD 13

Calibration

SD3_PLLF_REF_CLK_N SerDes PLL Fast Reference E17 I SD3_SV DD ---

Clock Complement

SD3_PLLF_REF_CLK_P SerDes PLL Fast Reference F17 I SD3_SV DD ---

Clock

SD3_PLLF_TPA SerDes PLL Fast Analog Test L17 O AVDD_SD3_PLLF 10

Point

SD3_PLLF_TPD SerDes PLL Fast Digital Test L18 O SD3_SV DD 10

Point

SD3_PLLS_REF_CLK_N SerDes PLL Slow Reference A17 I SD3_SV DD ---

Clock Complement

SD3_PLLS_REF_CLK_P SerDes PLL Slow Reference B17 I SD3_SV DD ---

Clock

SD3_PLLS_TPA SerDes PLL Slow Analog Test J22 O AVDD_SD3_PLLS 10

Point

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 35 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_PLLS_TPD SerDes PLL Slow Digital Test L22 O SD3_SV DD 10

Point

SD3_RX0_N SerDes Receive Data B13 I SD3_SV DD ---

(negative)

SD3_RX0_P SerDes Receive Data A13 I SD3_SV DD ---

(positive)

SD3_RX1_N SerDes Receive Data D14 I SD3_SV DD ---

(negative)

SD3_RX1_P SerDes Receive Data C14 I SD3_SV DD ---

(positive)

SD3_RX2_N SerDes Receive Data B15 I SD3_SV DD ---

(negative)

SD3_RX2_P SerDes Receive Data A15 I SD3_SV DD ---

(positive)

SD3_RX3_N SerDes Receive Data D16 I SD3_SV DD ---

(negative)

SD3_RX3_P SerDes Receive Data C16 I SD3_SV DD ---

(positive)

SD3_RX4_N SerDes Receive Data D18 I SD3_SV DD ---

(negative)

SD3_RX4_P SerDes Receive Data C18 I SD3_SV DD ---

(positive)

SD3_RX5_N SerDes Receive Data B19 I SD3_SV DD ---

(negative)

SD3_RX5_P SerDes Receive Data A19 I SD3_SV DD ---

(positive)

SD3_RX6_N SerDes Receive Data D20 I SD3_SV DD ---

(negative)

SD3_RX6_P SerDes Receive Data C20 I SD3_SV DD ---

(positive)

SD3_RX7_N SerDes Receive Data B21 I SD3_SV DD ---

(negative)

SD3_RX7_P SerDes Receive Data A21 I SD3_SV DD ---

(positive)

SD3_TX0_N SerDes Transmit Data G13 O SD3_OV DD ---

(negative)

SD3_TX0_P SerDes Transmit Data F13 O SD3_OV DD ---

(positive)

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 36 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_TX1_N SerDes Transmit Data J14 O SD3_OV DD ---

(negative)

SD3_TX1_P SerDes Transmit Data H14 O SD3_OV DD ---

(positive)

SD3_TX2_N SerDes Transmit Data G15 O SD3_OV DD ---

(negative)

SD3_TX2_P SerDes Transmit Data F15 O SD3_OV DD ---

(positive)

SD3_TX3_N SerDes Transmit Data J16 O SD3_OV DD ---

(negative)

SD3_TX3_P SerDes Transmit Data H16 O SD3_OV DD ---

(positive)

SD3_TX4_N SerDes Transmit Data J18 O SD3_OV DD ---

(negative)

SD3_TX4_P SerDes Transmit Data H18 O SD3_OV DD ---

(positive)

SD3_TX5_N SerDes Transmit Data G19 O SD3_OV DD ---

(negative)

SD3_TX5_P SerDes Transmit Data F19 O SD3_OV DD ---

(positive)

SD3_TX6_N SerDes Transmit Data J20 O SD3_OV DD ---

(negative)

SD3_TX6_P SerDes Transmit Data H20 O SD3_OV DD ---

(positive)

SD3_TX7_N SerDes Transmit Data G21 O SD3_OV DD ---

(negative)

SD3_TX7_P SerDes Transmit Data F21 O SD3_OV DD ---

(positive)

USB PHY 1 and 2

USB1_DRVVBUS / USB PHY Digital signal - Drive A7 O OV DD 1

GPIO4_DAT25 /cfg_soc_use VBUS

USB1_D_M USB PHY Data Minus F9 IO USB_HV DD ---

USB1_D_P USB PHY Data Plus F8 IO USB_HV DD ---

USB1_ID USB PHY ID Detect E9 I - ---

USB1_PWRFAULT / USB PHY Digital signal - B7 I OV DD 1

GPIO4_DAT26 Power Fault

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 37 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

USB1_RESREF USB PHY Impedance C12 IO - 15

Calibration

USB1_RX_M USB PHY 3.0 Receive Data D8 I USB_SV DD ---

(negative)

USB1_RX_P USB PHY 3.0 Receive Data C8 I USB_SV DD ---

(positive)

USB1_TX_M USB PHY 3.0 Transmit Data B9 O USB_SV DD ---

(negative)

USB1_TX_P USB PHY 3.0 Transmit Data A9 O USB_SV DD ---

(positive)

USB1_VBUS USB PHY VBUS G8 I - 18

USB2_DRVVBUS / USB PHY Digital signal - Drive E7 O OV DD 1

GPIO4_DAT27 VBUS

USB2_D_M USB PHY Data Minus F11 IO USB_HV DD ---

USB2_D_P USB PHY Data Plus F10 IO USB_HV DD ---

USB2_ID USB PHY ID Detect E11 I - ---

USB2_PWRFAULT / USB PHY Digital signal - G7 I OV DD 1

GPIO4_DAT28 Power Fault

USB2_RESREF USB PHY Impedance D12 IO - 15

Calibration

USB2_RX_M USB PHY 3.0 Receive Data D10 I USB_SV DD ---

(negative)

USB2_RX_P USB PHY 3.0 Receive Data C10 I USB_SV DD ---

(positive)

USB2_TX_M USB PHY 3.0 Transmit Data B11 O USB_SV DD ---

(negative)

USB2_TX_P USB PHY 3.0 Transmit Data A11 O USB_SV DD ---

(positive)

USB2_VBUS USB PHY VBUS G10 I - 18

Ethernet Controller 1

EC1_GTX_CLK / Transmit Clock Out F3 O OV DD 1

GPIO4_DAT05

EC1_RXD0 /GPIO4_DAT09 Receive Data J2 I OV DD 1

EC1_RXD1 /GPIO4_DAT08 Receive Data J1 I OV DD 1

EC1_RXD2 /GPIO4_DAT07 Receive Data H1 I OV DD 1

EC1_RXD3 /GPIO4_DAT06 Receive Data G2 I OV DD 1

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 38 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EC1_RX_CLK /GPIO4_DAT10 Receive Clock G1 I OV DD 1

EC1_RX_DV /GPIO4_DAT11 Receive Data Valid K1 I OV DD 1

EC1_TXD0 /GPIO4_DAT03 / Transmit Data J3 O OV DD 1

CLK_OUT2

EC1_TXD1 /GPIO4_DAT02 Transmit Data H3 O OV DD 1

EC1_TXD2 /GPIO4_DAT01 Transmit Data G4 O OV DD 1

EC1_TXD3 /GPIO4_DAT00 Transmit Data G3 O OV DD 1

EC1_TX_EN /GPIO4_DAT04 Transmit Enable J4 O OV DD 1, 11

Ethernet Controller 2

EC2_GTX_CLK / Transmit Clock Out K3 O OV DD 1

GPIO4_DAT17

EC2_RXD0 /GPIO4_DAT21 / Receive Data N2 I OV DD 1

TSEC_1588_TRIG_IN2

EC2_RXD1 /GPIO4_DAT20 / Receive Data N1 I OV DD 1

TSEC_1588_PULSE_OUT1

EC2_RXD2 /GPIO4_DAT19 Receive Data M1 I OV DD 1

EC2_RXD3 /GPIO4_DAT18 Receive Data L2 I OV DD 1

EC2_RX_CLK / Receive Clock L1 I OV DD 1

GPIO4_DAT22 /
TSEC_1588_CLK_IN

EC2_RX_DV /GPIO4_DAT23 / Receive Data Valid P1 I OV DD 1

TSEC_1588_TRIG_IN1

EC2_TXD0 /GPIO4_DAT15 / Transmit Data N3 O OV DD 1

TSEC_1588_PULSE_OUT2

EC2_TXD1 /GPIO4_DAT14 / Transmit Data M3 O OV DD 1

TSEC_1588_CLK_OUT

EC2_TXD2 /GPIO4_DAT13 / Transmit Data L4 O OV DD 1

TSEC_1588_ALARM_OUT1

EC2_TXD3 /GPIO4_DAT12 / Transmit Data L3 O OV DD 1

TSEC_1588_ALARM_OUT2

EC2_TX_EN /GPIO4_DAT16 Transmit Enable N4 O OV DD 1, 11

Sync Ethernet ClockOut

RCLK0 Reconstructed Clock N6 O OV DD ---

RCLK1 Reconstructed Clock N8 O OV DD ---

Ethernet Management Interface 1

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 39 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

EMI1_MDC Management Data Clock R2 O OV DD ---

EMI1_MDIO Management Data In/Out R1 IO OV DD ---

Ethernet Management Interface 2

EMI2_MDC Management Data Clock P4 O OV DD ---

EMI2_MDIO Management Data In/Out R3 IO OV DD 5, 6

General Purpose Input/Output

GPIO1_DAT02/ IIC1_SDA General Purpose Input/Output G5 IO OV DD ---

GPIO1_DAT03/ IIC1_SCL General Purpose Input/Output F5 IO OV DD ---

GPIO1_DAT04/ General Purpose Input/Output C6 IO OV DD ---

UART2_CTS_B /UART4_SIN

GPIO1_DAT05/ General Purpose Input/Output C5 O OV DD 1

UART2_RTS_B /
UART4_SOUT /cfg_eng_use2

GPIO1_DAT06/ UART2_SIN General Purpose Input/Output D5 IO OV DD ---

GPIO1_DAT07/ General Purpose Input/Output D6 O OV DD 1

UART2_SOUT /cfg_rcw_src0

GPIO1_DAT08/ General Purpose Input/Output A6 IO OV DD ---

UART1_CTS_B /UART3_SIN

GPIO1_DAT09/ General Purpose Input/Output A5 O OV DD 1

UART1_RTS_B /
UART3_SOUT

GPIO1_DAT10/ UART1_SIN General Purpose Input/Output B5 IO OV DD ---

GPIO1_DAT11/ General Purpose Input/Output B6 O OV DD 1

UART1_SOUT /cfg_rcw_src1

GPIO1_DAT12/ SPI3_PCS3 / General Purpose Input/Output C3 IO OV DD ---

SDHC1_DAT123_DIR /
SDHC1_DAT7

GPIO1_DAT13/ SPI3_PCS2 / General Purpose Input/Output B3 IO OV DD ---

SDHC1_DAT0_DIR /
SDHC1_DAT6

GPIO1_DAT14/ SPI3_PCS1 / General Purpose Input/Output A4 IO OV DD ---

SDHC1_CMD_DIR /
SDHC1_DAT5

GPIO1_DAT15/ SPI3_PCS0 / General Purpose Input/Output A3 IO OV DD ---

SPI1_PCS3 /SDHC1_VSEL /
SDHC1_DAT4

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 40 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO1_DAT16/ SDHC1_CLK / General Purpose Input/Output D1 IO EV DD ---

SPI1_SCK

GPIO1_DAT17/ General Purpose Input/Output F1 IO EV DD

SDHC1_DAT0 /SPI1_SIN /
cfg_gpinput0

GPIO1_DAT18/ General Purpose Input/Output E2 IO EV DD

SDHC1_DAT1 /SPI1_PCS2 /
cfg_gpinput1

GPIO1_DAT19/ General Purpose Input/Output C1 IO EV DD

SDHC1_DAT2 /SPI1_PCS1 /
cfg_gpinput2

GPIO1_DAT20/ General Purpose Input/Output C2 IO EV DD

SDHC1_DAT3 /SPI1_PCS0 /
cfg_gpinput3

GPIO1_DAT21/ General Purpose Input/Output E1 IO EV DD ---

SDHC1_CMD /SPI1_SOUT

GPIO1_DAT22/ IIC6_SDA / General Purpose Input/Output C27 IO OV DD ---

SDHC2_CLK_SYNC_IN

GPIO1_DAT23/ IIC6_SCL / General Purpose Input/Output D27 IO OV DD ---

SDHC2_CLK_SYNC_OUT

GPIO1_DAT24/ SPI3_SIN / General Purpose Input/Output D3 IO OV DD ---

SDHC1_CLK_SYNC_IN /
IIC5_SDA

GPIO1_DAT25/ SPI3_SOUT / General Purpose Input/Output C4 IO OV DD ---

SDHC1_CLK_SYNC_OUT /
IIC5_SCL

GPIO1_DAT26/ IIC4_SDA / General Purpose Input/Output L5 IO OV DD ---

CAN2_RX /EVT8_B

GPIO1_DAT27/ IIC4_SCL / General Purpose Input/Output K5 IO OV DD ---

CAN2_TX /EVT7_B

GPIO1_DAT28/ IIC3_SDA / General Purpose Input/Output J5 IO OV DD ---

CAN1_RX /EVT6_B

GPIO1_DAT29/ IIC3_SCL / General Purpose Input/Output H5 IO OV DD ---

CAN1_TX /EVT5_B

GPIO1_DAT30/ IIC2_SDA / General Purpose Input/Output E4 IO OV DD ---

FTM2_CH0 /SDHC1_WP

GPIO1_DAT31/ IIC2_SCL / General Purpose Input/Output E3 IO OV DD ---

FTM1_CH0 /SDHC1_CD_B

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 41 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO2_DAT06/ ASLEEP / General Purpose Input/Output M7 O OV DD 1

EVT9_B /cfg_rcw_src2

GPIO2_DAT07/ CLK_OUT / General Purpose Input/Output L6 O OV DD 1

FTM1_CH1 /cfg_rcw_src3

GPIO2_DAT08/ General Purpose Input/Output M9 O OV DD 1

RESET_REQ_B

GPIO2_DAT09/ SDHC2_CLK / General Purpose Input/Output A25 IO OV DD ---

SPI2_SCK /XSPI1_B_SCK

GPIO2_DAT10/ SDHC2_DS / General Purpose Input/Output C25 IO OV DD ---

SPI2_PCS3 /XSPI1_B_DQS

GPIO2_DAT11/ General Purpose Input/Output A23 IO OV DD

SDHC2_DAT0 /SPI2_SIN /
XSPI1_B_DATA0 /
cfg_gpinput4

GPIO2_DAT12/ General Purpose Input/Output C24 IO OV DD

SDHC2_DAT1 /SPI2_PCS2 /
XSPI1_B_DATA1 /
cfg_gpinput5

GPIO2_DAT13/ General Purpose Input/Output B23 IO OV DD

SDHC2_DAT2 /SPI2_PCS1 /
XSPI1_B_DATA2 /
cfg_gpinput6

GPIO2_DAT14/ General Purpose Input/Output A24 IO OV DD

SDHC2_DAT3 /SPI2_PCS0 /
XSPI1_B_DATA3 /
cfg_gpinput7

GPIO2_DAT15/ General Purpose Input/Output C26 IO OV DD ---

SDHC2_DAT4 /IIC7_SDA /
XSPI1_B_DATA4

GPIO2_DAT16/ General Purpose Input/Output B27 IO OV DD ---

SDHC2_DAT5 /IIC7_SCL /
XSPI1_B_DATA5

GPIO2_DAT17/ General Purpose Input/Output A26 IO OV DD ---

SDHC2_DAT6 /IIC8_SDA /
XSPI1_B_DATA6

GPIO2_DAT18/ General Purpose Input/Output A27 IO OV DD ---

SDHC2_DAT7 /IIC8_SCL /
XSPI1_B_DATA7

GPIO2_DAT19/ General Purpose Input/Output B25 IO OV DD ---

SDHC2_CMD /SPI2_SOUT /
XSPI1_B_CS1_B

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 42 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO2_DAT20/ General Purpose Input/Output D23 O OV DD 1

XSPI1_A_CS1_B

GPIO2_DAT21/ General Purpose Input/Output C23 O OV DD 1

XSPI1_A_CS0_B

GPIO2_DAT22/ General Purpose Input/Output D22 O OV DD 1

XSPI1_A_SCK /cfg_eng_use0

GPIO2_DAT23/ General Purpose Input/Output E23 IO OV DD ---

XSPI1_A_DQS

GPIO2_DAT24/ General Purpose Input/Output F25 IO OV DD ---

XSPI1_A_DATA0

GPIO2_DAT25/ General Purpose Input/Output E24 IO OV DD ---

XSPI1_A_DATA1

GPIO2_DAT26/ General Purpose Input/Output E26 IO OV DD ---

XSPI1_A_DATA2

GPIO2_DAT27/ General Purpose Input/Output E27 IO OV DD ---

XSPI1_A_DATA3

GPIO2_DAT28/ General Purpose Input/Output F27 IO OV DD ---

XSPI1_A_DATA4

GPIO2_DAT29/ General Purpose Input/Output D26 IO OV DD ---

XSPI1_A_DATA5

GPIO2_DAT30/ General Purpose Input/Output E25 IO OV DD ---

XSPI1_A_DATA6

GPIO2_DAT31/ General Purpose Input/Output D24 IO OV DD ---

XSPI1_A_DATA7

GPIO3_DAT00/ IRQ00 / General Purpose Input/Output H9 IO OV DD ---

FTM1_CH4

GPIO3_DAT01/ IRQ01 / General Purpose Input/Output H10 IO OV DD ---

FTM2_CH4

GPIO3_DAT02/ IRQ02 / General Purpose Input/Output H11 IO OV DD ---

FTM1_CH5

GPIO3_DAT03/ IRQ03 / General Purpose Input/Output J7 IO OV DD ---

FTM2_CH5

GPIO3_DAT04/ IRQ04 / General Purpose Input/Output J11 IO OV DD ---

FTM1_CH6

GPIO3_DAT05/ IRQ05 / General Purpose Input/Output J9 IO OV DD ---

FTM2_CH6

GPIO3_DAT06/ IRQ06 / General Purpose Input/Output H6 IO OV DD ---

FTM1_CH7

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 43 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO3_DAT07/ IRQ07 / General Purpose Input/Output K6 IO OV DD ---

FTM2_CH7

GPIO3_DAT08/ IRQ08 General Purpose Input/Output H7 IO OV DD ---

GPIO3_DAT09/ IRQ09 General Purpose Input/Output K7 IO OV DD ---

GPIO3_DAT10/ IRQ10 General Purpose Input/Output H8 IO OV DD ---

GPIO3_DAT11/ IRQ11 General Purpose Input/Output K8 IO OV DD ---

GPIO3_DAT12/ EVT0_B / General Purpose Input/Output K9 IO OV DD ---

FTM2_CH1

GPIO3_DAT13/ EVT1_B / General Purpose Input/Output L11 IO OV DD ---

FTM1_CH2

GPIO3_DAT14/ EVT2_B / General Purpose Input/Output G6 IO OV DD ---

FTM2_CH2

GPIO3_DAT15/ EVT3_B / General Purpose Input/Output L10 IO OV DD ---

FTM1_CH3

GPIO3_DAT16/ EVT4_B / General Purpose Input/Output M10 IO OV DD ---

FTM2_CH3

GPIO4_DAT00/ EC1_TXD3 General Purpose Input/Output G3 IO OV DD ---

GPIO4_DAT01/ EC1_TXD2 General Purpose Input/Output G4 IO OV DD ---

GPIO4_DAT02/ EC1_TXD1 General Purpose Input/Output H3 IO OV DD ---

GPIO4_DAT03/ EC1_TXD0 / General Purpose Input/Output J3 IO OV DD ---

CLK_OUT2

GPIO4_DAT04/ EC1_TX_EN General Purpose Input/Output J4 IO OV DD ---

GPIO4_DAT05/ General Purpose Input/Output F3 IO OV DD ---

EC1_GTX_CLK

GPIO4_DAT06/ EC1_RXD3 General Purpose Input/Output G2 IO OV DD ---

GPIO4_DAT07/ EC1_RXD2 General Purpose Input/Output H1 IO OV DD ---

GPIO4_DAT08/ EC1_RXD1 General Purpose Input/Output J1 IO OV DD ---

GPIO4_DAT09/ EC1_RXD0 General Purpose Input/Output J2 IO OV DD ---

GPIO4_DAT10/ EC1_RX_CLK General Purpose Input/Output G1 IO OV DD ---

GPIO4_DAT11/ EC1_RX_DV General Purpose Input/Output K1 IO OV DD ---

GPIO4_DAT12/ EC2_TXD3 / General Purpose Input/Output L3 IO OV DD ---

TSEC_1588_ALARM_OUT2

GPIO4_DAT13/ EC2_TXD2 / General Purpose Input/Output L4 IO OV DD ---

TSEC_1588_ALARM_OUT1

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 44 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GPIO4_DAT14/ EC2_TXD1 / General Purpose Input/Output M3 IO OV DD ---

TSEC_1588_CLK_OUT

GPIO4_DAT15/ EC2_TXD0 / General Purpose Input/Output N3 IO OV DD ---

TSEC_1588_PULSE_OUT2

GPIO4_DAT16/ EC2_TX_EN General Purpose Input/Output N4 IO OV DD ---

GPIO4_DAT17/ General Purpose Input/Output K3 IO OV DD ---

EC2_GTX_CLK

GPIO4_DAT18/ EC2_RXD3 General Purpose Input/Output L2 IO OV DD ---

GPIO4_DAT19/ EC2_RXD2 General Purpose Input/Output M1 IO OV DD ---

GPIO4_DAT20/ EC2_RXD1 / General Purpose Input/Output N1 IO OV DD ---

TSEC_1588_PULSE_OUT1

GPIO4_DAT21/ EC2_RXD0 / General Purpose Input/Output N2 IO OV DD ---

TSEC_1588_TRIG_IN2

GPIO4_DAT22/ General Purpose Input/Output L1 IO OV DD ---

EC2_RX_CLK /
TSEC_1588_CLK_IN

GPIO4_DAT23/ EC2_RX_DV / General Purpose Input/Output P1 IO OV DD ---

TSEC_1588_TRIG_IN1

GPIO4_DAT24/ General Purpose Input/Output P3 IO OV DD ---

EC_GTX_CLK125

GPIO4_DAT25/ General Purpose Input/Output A7 IO OV DD 1

USB1_DRVVBUS /
cfg_soc_use

GPIO4_DAT26/ General Purpose Input/Output B7 IO OV DD ---

USB1_PWRFAULT

GPIO4_DAT27/ General Purpose Input/Output E7 IO OV DD ---

USB2_DRVVBUS

GPIO4_DAT28/ General Purpose Input/Output G7 IO OV DD ---

USB2_PWRFAULT

GPIO4_DAT29/ SPI3_SCK / General Purpose Input/Output B2 IO OV DD ---

SDHC1_DS

FlexTimer Module

FTM1_CH0/ IIC2_SCL / Channel 0 E3 IO OV DD ---

GPIO1_DAT31 /
SDHC1_CD_B

FTM1_CH1/ CLK_OUT / Channel 1 L6 O OV DD 1

GPIO2_DAT07 /cfg_rcw_src3

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 45 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

FTM1_CH2/ EVT1_B / Channel 2 L11 IO OV DD ---

GPIO3_DAT13

FTM1_CH3/ EVT3_B / Channel 3 L10 IO OV DD ---

GPIO3_DAT15

FTM1_CH4/ IRQ00 / Channel 4 H9 IO OV DD ---

GPIO3_DAT00

FTM1_CH5/ IRQ02 / Channel 5 H11 IO OV DD ---

GPIO3_DAT02

FTM1_CH6/ IRQ04 / Channel 6 J11 IO OV DD ---

GPIO3_DAT04

FTM1_CH7/ IRQ06 / Channel 7 H6 IO OV DD ---

GPIO3_DAT06

FTM2_CH0/ IIC2_SDA / Channel 0 E4 IO OV DD ---

GPIO1_DAT30 /SDHC1_WP

FTM2_CH1/ EVT0_B / Channel 1 K9 IO OV DD ---

GPIO3_DAT12

FTM2_CH2/ EVT2_B / Channel 2 G6 IO OV DD ---

GPIO3_DAT14

FTM2_CH3/ EVT4_B / Channel 3 M10 IO OV DD ---

GPIO3_DAT16

FTM2_CH4/ IRQ01 / Channel 4 H10 IO OV DD ---

GPIO3_DAT01

FTM2_CH5/ IRQ03 / Channel 5 J7 IO OV DD ---

GPIO3_DAT03

FTM2_CH6/ IRQ05 / Channel 6 J9 IO OV DD ---

GPIO3_DAT05

FTM2_CH7/ IRQ07 / Channel 7 K6 IO OV DD ---

GPIO3_DAT07

Controller Area Network

CAN1_RX/ IIC3_SDA / Receive Data J5 I OV DD 1

GPIO1_DAT28 /EVT6_B

CAN1_TX/ IIC3_SCL / Transmit Data H5 O OV DD 1

GPIO1_DAT29 /EVT5_B

CAN2_RX/ IIC4_SDA / Receive Data L5 I OV DD 1

GPIO1_DAT26 /EVT8_B

CAN2_TX/ IIC4_SCL / Transmit Data K5 O OV DD 1

GPIO1_DAT27 /EVT7_B

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 46 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

Power-On-Reset Configuration

cfg_eng_use0/ Power-on-Reset Configuration D22 I OV DD 1, 4

XSPI1_A_SCK /
GPIO2_DAT22

cfg_eng_use2/ Power-on-Reset Configuration C5 I OV DD 1, 4

UART2_RTS_B /
GPIO1_DAT05 /
UART4_SOUT

cfg_gpinput0/ SDHC1_DAT0 / General Input F1 I EV DD 1, 4

GPIO1_DAT17 /SPI1_SIN

cfg_gpinput1/ SDHC1_DAT1 / General Input E2 I EV DD 1, 4

GPIO1_DAT18 /SPI1_PCS2

cfg_gpinput2/ SDHC1_DAT2 / General Input C1 I EV DD 1, 4

GPIO1_DAT19 /SPI1_PCS1

cfg_gpinput3/ SDHC1_DAT3 / General Input C2 I EV DD 1, 4

GPIO1_DAT20 /SPI1_PCS0

cfg_gpinput4/ SDHC2_DAT0 / General Input A23 I OV DD 1, 4

GPIO2_DAT11 /SPI2_SIN /
XSPI1_B_DATA0

cfg_gpinput5/ SDHC2_DAT1 / General Input C24 I OV DD 1, 4

GPIO2_DAT12 /SPI2_PCS2 /
XSPI1_B_DATA1

cfg_gpinput6/ SDHC2_DAT2 / General Input B23 I OV DD 1, 4

GPIO2_DAT13 /SPI2_PCS1 /
XSPI1_B_DATA2

cfg_gpinput7/ SDHC2_DAT3 / General Input A24 I OV DD 1, 4

GPIO2_DAT14 /SPI2_PCS0 /
XSPI1_B_DATA3

cfg_rcw_src0/ UART2_SOUT / Reset Configuration Word D6 I OV DD 1, 4

GPIO1_DAT07

cfg_rcw_src1/ UART1_SOUT / Reset Configuration Word B6 I OV DD 1, 4

GPIO1_DAT11

cfg_rcw_src2/ ASLEEP / Reset Configuration Word M7 I OV DD 1, 4

GPIO2_DAT06 /EVT9_B

cfg_rcw_src3/ CLK_OUT / Reset Configuration Word L6 I OV DD 1, 4

GPIO2_DAT07 /FTM1_CH1

cfg_soc_use/ Power-on-Reset Configuration A7 I OV DD 1, 4

USB1_DRVVBUS /
GPIO4_DAT25

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 47 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

cfg_svr0/ XSPI1_A_CS0_B / Power-on-Reset Configuration C23 I OV DD 1, 4

GPIO2_DAT21

cfg_svr1/ XSPI1_A_CS1_B / Power-on-Reset Configuration D23 I OV DD 1, 4

GPIO2_DAT20

SPI1

SPI1_PCS0/ SDHC1_DAT3 / SPI Chip Select C2 O EV DD 1

GPIO1_DAT20 /cfg_gpinput3

SPI1_PCS1/ SDHC1_DAT2 / SPI Chip Select C1 O EV DD 1

GPIO1_DAT19 /cfg_gpinput2

SPI1_PCS2/ SDHC1_DAT1 / SPI Chip Select E2 O EV DD 1

GPIO1_DAT18 /cfg_gpinput1

SPI1_PCS3/ SPI3_PCS0 / SPI Chip Select A3 O OV DD 1

GPIO1_DAT15 /
SDHC1_VSEL /SDHC1_DAT4

SPI1_SCK/ SDHC1_CLK / Serial Clock D1 O EV DD 1

GPIO1_DAT16

SPI1_SIN/ SDHC1_DAT0 / Serial Data Input F1 I EV DD 1

GPIO1_DAT17 /cfg_gpinput0

SPI1_SOUT/ SDHC1_CMD / Serial Data Output E1 O EV DD 1

GPIO1_DAT21

SPI2

SPI2_PCS0/ SDHC2_DAT3 / SPI Chip Select A24 O OV DD 1

GPIO2_DAT14 /
XSPI1_B_DATA3 /
cfg_gpinput7

SPI2_PCS1/ SDHC2_DAT2 / SPI Chip Select B23 O OV DD 1

GPIO2_DAT13 /
XSPI1_B_DATA2 /
cfg_gpinput6

SPI2_PCS2/ SDHC2_DAT1 / SPI Chip Select C24 O OV DD 1

GPIO2_DAT12 /
XSPI1_B_DATA1 /
cfg_gpinput5

SPI2_PCS3/ SDHC2_DS / SPI Chip Select C25 O OV DD 1

GPIO2_DAT10 /
XSPI1_B_DQS

SPI2_SCK/ SDHC2_CLK / Serial Clock A25 O OV DD 1

GPIO2_DAT09 /
XSPI1_B_SCK

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 48 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SPI2_SIN/ SDHC2_DAT0 / Serial Data Input A23 I OV DD 1

GPIO2_DAT11 /
XSPI1_B_DATA0 /
cfg_gpinput4

SPI2_SOUT/ SDHC2_CMD / Serial Data Output B25 O OV DD 1

GPIO2_DAT19 /
XSPI1_B_CS1_B

SPI3

SPI3_PCS0 /GPIO1_DAT15 / SPI Chip Select A3 O OV DD 1

SPI1_PCS3 /SDHC1_VSEL /
SDHC1_DAT4

SPI3_PCS1 /GPIO1_DAT14 / SPI Chip Select A4 O OV DD 1

SDHC1_CMD_DIR /
SDHC1_DAT5

SPI3_PCS2 /GPIO1_DAT13 / SPI Chip Select B3 O OV DD 1

SDHC1_DAT0_DIR /
SDHC1_DAT6

SPI3_PCS3 /GPIO1_DAT12 / SPI Chip Select C3 O OV DD 1

SDHC1_DAT123_DIR /
SDHC1_DAT7

SPI3_SCK /GPIO4_DAT29 / Serial Clock B2 O OV DD 1

SDHC1_DS

SPI3_SIN /GPIO1_DAT24 / Serial Data Input D3 I OV DD 1

SDHC1_CLK_SYNC_IN /
IIC5_SDA

SPI3_SOUT /GPIO1_DAT25 / Serial Data Output C4 O OV DD 1

SDHC1_CLK_SYNC_OUT /
IIC5_SCL

IEEE 1588

TSEC_1588_ALARM_OUT1/ Alarm Out L4 O OV DD 1

EC2_TXD2 /GPIO4_DAT13

TSEC_1588_ALARM_OUT2/ Alarm Out L3 O OV DD 1

EC2_TXD3 /GPIO4_DAT12

TSEC_1588_CLK_IN/ Clock Input L1 I OV DD 1

EC2_RX_CLK /GPIO4_DAT22

TSEC_1588_CLK_OUT/ Clock Out M3 O OV DD 1

EC2_TXD1 /GPIO4_DAT14

TSEC_1588_PULSE_OUT1/ Pulse Out N1 O OV DD 1

EC2_RXD1 /GPIO4_DAT20

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 49 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

TSEC_1588_PULSE_OUT2/ Pulse Out N3 O OV DD 1

EC2_TXD0 /GPIO4_DAT15

TSEC_1588_TRIG_IN1/ Trigger In P1 I OV DD 1
EC2_RX_DV /GPIO4_DAT23

TSEC_1588_TRIG_IN2/ Trigger In N2 I OV DD 1
EC2_RXD0 /GPIO4_DAT21

Power and Ground Signals

GND001 GND A2 --- --- ---

GND002 GND A8 --- --- ---

GND003 GND A10 --- --- ---

GND004 GND A28 --- --- ---

GND005 GND A35 --- --- ---

GND006 GND B1 --- --- ---

GND007 GND B4 --- --- ---

GND008 GND B8 --- --- ---

GND009 GND B10 --- --- ---

GND010 GND B12 --- --- ---

GND011 GND B24 --- --- ---

GND012 GND B26 --- --- ---

GND013 GND B28 --- --- ---

GND014 GND B30 --- --- ---

GND015 GND B32 --- --- ---

GND016 GND C7 --- --- ---

GND017 GND C9 --- --- ---

GND018 GND C11 --- --- ---

GND019 GND C22 --- --- ---

GND020 GND C28 --- --- ---

GND021 GND C35 --- --- ---

GND022 GND D2 --- --- ---

GND023 GND D4 --- --- ---

GND024 GND D7 --- --- ---

GND025 GND D9 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 50 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND026 GND D11 --- --- ---

GND027 GND D25 --- --- ---

GND028 GND D30 --- --- ---

GND029 GND D33 --- --- ---

GND030 GND E8 --- --- ---

GND031 GND E10 --- --- ---

GND032 GND E12 --- --- ---

GND033 GND E22 --- --- ---

GND034 GND E28 --- --- ---

GND035 GND E36 --- --- ---

GND036 GND F2 --- --- ---

GND037 GND F4 --- --- ---

GND038 GND F7 --- --- ---

GND039 GND F24 --- --- ---

GND040 GND F26 --- --- ---

GND041 GND F28 --- --- ---

GND042 GND F30 --- --- ---

GND043 GND F34 --- --- ---

GND044 GND G9 --- --- ---

GND045 GND G11 --- --- ---

GND046 GND G28 --- --- ---

GND047 GND G32 --- --- ---

GND048 GND G36 --- --- ---

GND049 GND H2 --- --- ---

GND050 GND H4 --- --- ---

GND051 GND H12 --- --- ---

GND052 GND H23 --- --- ---

GND053 GND H24 --- --- ---

GND054 GND H25 --- --- ---

GND055 GND H28 --- --- ---

GND056 GND H30 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 51 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND057 GND H34 --- --- ---

GND058 GND J6 --- --- ---

GND059 GND J8 --- --- ---

GND060 GND J10 --- --- ---

GND061 GND J32 --- --- ---

GND062 GND J36 --- --- ---

GND063 GND K2 --- --- ---

GND064 GND K4 --- --- ---

GND065 GND K23 --- --- ---

GND066 GND K24 --- --- ---

GND067 GND K25 --- --- ---

GND068 GND K26 --- --- ---

GND069 GND K28 --- --- ---

GND070 GND K30 --- --- ---

GND071 GND K34 --- --- ---

GND072 GND L7 --- --- ---

GND073 GND L12 --- --- ---

GND074 GND L13 --- --- ---

GND075 GND L32 --- --- ---

GND076 GND L36 --- --- ---

GND077 GND M2 --- --- ---

GND078 GND M4 --- --- ---

GND079 GND M6 --- --- ---

GND080 GND M8 --- --- ---

GND081 GND M11 --- --- ---

GND082 GND M21 --- --- ---

GND083 GND M22 --- --- ---

GND084 GND M23 --- --- ---

GND085 GND M24 --- --- ---

GND086 GND M25 --- --- ---

GND087 GND M28 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 52 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND088 GND M34 --- --- ---

GND089 GND N5 --- --- ---

GND090 GND N7 --- --- ---

GND091 GND N10 --- --- ---

GND092 GND N12 --- --- ---

GND093 GND N26 --- --- ---

GND094 GND N28 --- --- ---

GND095 GND N30 --- --- ---

GND096 GND N32 --- --- ---

GND097 GND N36 --- --- ---

GND098 GND P2 --- --- ---

GND099 GND P5 --- --- ---

GND100 GND P6 --- --- ---

GND101 GND P7 --- --- ---

GND102 GND P8 --- --- ---

GND103 GND P9 --- --- ---

GND104 GND P10 --- --- ---

GND105 GND P13 --- --- ---

GND106 GND P21 --- --- ---

GND107 GND P23 --- --- ---

GND108 GND P25 --- --- ---

GND109 GND P27 --- --- ---

GND110 GND P30 --- --- ---

GND111 GND P34 --- --- ---

GND112 GND R4 --- --- ---

GND113 GND R10 --- --- ---

GND114 GND R12 --- --- ---

GND115 GND R14 --- --- ---

GND116 GND R16 --- --- ---

GND117 GND R18 --- --- ---

GND118 GND R20 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 53 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND119 GND R22 --- --- ---

GND120 GND R24 --- --- ---

GND121 GND R26 --- --- ---

GND122 GND R28 --- --- ---

GND123 GND R30 --- --- ---

GND124 GND R32 --- --- ---

GND125 GND R36 --- --- ---

GND126 GND T1 --- --- ---

GND127 GND T3 --- --- ---

GND128 GND T6 --- --- ---

GND129 GND T10 --- --- ---

GND130 GND T13 --- --- ---

GND131 GND T15 --- --- ---

GND132 GND T17 --- --- ---

GND133 GND T19 --- --- ---

GND134 GND T21 --- --- ---

GND135 GND T23 --- --- ---

GND136 GND T25 --- --- ---

GND137 GND T27 --- --- ---

GND138 GND T30 --- --- ---

GND139 GND T34 --- --- ---

GND140 GND U4 --- --- ---

GND141 GND U8 --- --- ---

GND142 GND U10 --- --- ---

GND143 GND U12 --- --- ---

GND144 GND U14 --- --- ---

GND145 GND U16 --- --- ---

GND146 GND U18 --- --- ---

GND147 GND U20 --- --- ---

GND148 GND U22 --- --- ---

GND149 GND U24 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 54 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND150 GND U26 --- --- ---

GND151 GND U30 --- --- ---

GND152 GND U32 --- --- ---

GND153 GND U36 --- --- ---

GND154 GND V6 --- --- ---

GND155 GND V10 --- --- ---

GND156 GND V13 --- --- ---

GND157 GND V15 --- --- ---

GND158 GND V17 --- --- ---

GND159 GND V19 --- --- ---

GND160 GND V21 --- --- ---

GND161 GND V23 --- --- ---

GND162 GND V25 --- --- ---

GND163 GND V27 --- --- ---

GND164 GND V30 --- --- ---

GND165 GND V34 --- --- ---

GND166 GND W4 --- --- ---

GND167 GND W8 --- --- ---

GND168 GND W10 --- --- ---

GND169 GND W12 --- --- ---

GND170 GND W14 --- --- ---

GND171 GND W16 --- --- ---

GND172 GND W18 --- --- ---

GND173 GND W20 --- --- ---

GND174 GND W22 --- --- ---

GND175 GND W24 --- --- ---

GND176 GND W26 --- --- ---

GND177 GND W28 --- --- ---

GND178 GND W30 --- --- ---

GND179 GND Y6 --- --- ---

GND180 GND Y10 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 55 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND181 GND Y13 --- --- ---

GND182 GND Y15 --- --- ---

GND183 GND Y17 --- --- ---

GND184 GND Y19 --- --- ---

GND185 GND Y21 --- --- ---

GND186 GND Y23 --- --- ---

GND187 GND Y25 --- --- ---

GND188 GND Y27 --- --- ---

GND189 GND Y30 --- --- ---

GND190 GND Y32 --- --- ---

GND191 GND Y35 --- --- ---

GND192 GND Y37 --- --- ---

GND193 GND AA4 --- --- ---

GND194 GND AA8 --- --- ---

GND195 GND AA10 --- --- ---

GND196 GND AA12 --- --- ---

GND197 GND AA14 --- --- ---

GND198 GND AA16 --- --- ---

GND199 GND AA18 --- --- ---

GND200 GND AA20 --- --- ---

GND201 GND AA22 --- --- ---

GND202 GND AA24 --- --- ---

GND203 GND AA26 --- --- ---

GND204 GND AA28 --- --- ---

GND205 GND AA30 --- --- ---

GND206 GND AB6 --- --- ---

GND207 GND AB10 --- --- ---

GND208 GND AB13 --- --- ---

GND209 GND AB15 --- --- ---

GND210 GND AB17 --- --- ---

GND211 GND AB19 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 56 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND212 GND AB21 --- --- ---

GND213 GND AB23 --- --- ---

GND214 GND AB25 --- --- ---

GND215 GND AB27 --- --- ---

GND216 GND AB30 --- --- ---

GND217 GND AB34 --- --- ---

GND218 GND AC4 --- --- ---

GND219 GND AC8 --- --- ---

GND220 GND AC10 --- --- ---

GND221 GND AC14 --- --- ---

GND222 GND AC16 --- --- ---

GND223 GND AC18 --- --- ---

GND224 GND AC20 --- --- ---

GND225 GND AC22 --- --- ---

GND226 GND AC24 --- --- ---

GND227 GND AC26 --- --- ---

GND228 GND AC30 --- --- ---

GND229 GND AC32 --- --- ---

GND230 GND AC36 --- --- ---

GND231 GND AD6 --- --- ---

GND232 GND AD10 --- --- ---

GND233 GND AD13 --- --- ---

GND234 GND AD15 --- --- ---

GND235 GND AD17 --- --- ---

GND236 GND AD19 --- --- ---

GND237 GND AD21 --- --- ---

GND238 GND AD23 --- --- ---

GND239 GND AD25 --- --- ---

GND240 GND AD27 --- --- ---

GND241 GND AD30 --- --- ---

GND242 GND AD34 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 57 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND243 GND AE4 --- --- ---

GND244 GND AE8 --- --- ---

GND245 GND AE10 --- --- ---

GND246 GND AE12 --- --- ---

GND247 GND AE14 --- --- ---

GND248 GND AE16 --- --- ---

GND249 GND AE18 --- --- ---

GND250 GND AE20 --- --- ---

GND251 GND AE22 --- --- ---

GND252 GND AE24 --- --- ---

GND253 GND AE26 --- --- ---

GND254 GND AE28 --- --- ---

GND255 GND AE30 --- --- ---

GND256 GND AE32 --- --- ---

GND257 GND AE36 --- --- ---

GND258 GND AF6 --- --- ---

GND259 GND AF10 --- --- ---

GND260 GND AF27 --- --- ---

GND261 GND AF30 --- --- ---

GND262 GND AF34 --- --- ---

GND263 GND AG4 --- --- ---

GND264 GND AG9 --- --- ---

GND265 GND AG11 --- --- ---

GND266 GND AG30 --- --- ---

GND267 GND AG32 --- --- ---

GND268 GND AG36 --- --- ---

GND269 GND AH7 --- --- ---

GND270 GND AH11 --- --- ---

GND271 GND AH28 --- --- ---

GND272 GND AH34 --- --- ---

GND273 GND AJ5 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 58 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND274 GND AJ10 --- --- ---

GND275 GND AJ32 --- --- ---

GND276 GND AJ36 --- --- ---

GND277 GND AK4 --- --- ---

GND278 GND AK7 --- --- ---

GND279 GND AK9 --- --- ---

GND280 GND AK28 --- --- ---

GND281 GND AK30 --- --- ---

GND282 GND AK34 --- --- ---

GND283 GND AL5 --- --- ---

GND284 GND AL32 --- --- ---

GND285 GND AL36 --- --- ---

GND286 GND AM3 --- --- ---

GND287 GND AM8 --- --- ---

GND288 GND AM28 --- --- ---

GND289 GND AM30 --- --- ---

GND290 GND AM34 --- --- ---

GND291 GND AN6 --- --- ---

GND292 GND AN32 --- --- ---

GND293 GND AN36 --- --- ---

GND294 GND AP3 --- --- ---

GND295 GND AP5 --- --- ---

GND296 GND AP30 --- --- ---

GND297 GND AP34 --- --- ---

GND298 GND AR8 --- --- ---

GND299 GND AR28 --- --- ---

GND300 GND AR36 --- --- ---

GND301 GND AT4 --- --- ---

GND302 GND AT6 --- --- ---

GND303 GND AT30 --- --- ---

GND304 GND AT33 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 59 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

GND305 GND AU3 --- --- ---

GND306 GND AU8 --- --- ---

GND307 GND AU28 --- --- ---

GND308 GND AU35 --- --- ---

GND309 GND AV4 --- --- ---

GND310 GND AV6 --- --- ---

GND311 GND AV30 --- --- ---

GND312 GND AV32 --- --- ---

GND313 GND AW2 --- --- ---

GND314 GND AW35 --- --- ---

SENSEGND_CA GND Sense pin J24 --- --- ---

SENSEGND_CB GND Sense pin AG26 --- --- ---

SENSEGND_PL GND Sense pin AJ11 --- --- ---

SD_GND01 SerDes 1 and SerDes 2 AG12 --- --- ---

Ground

SD_GND02 SerDes 1 and SerDes 2 AG13 --- --- ---

Ground

SD_GND03 SerDes 1 and SerDes 2 AG14 --- --- ---

Ground

SD_GND04 SerDes 1 and SerDes 2 AG15 --- --- ---

Ground

SD_GND05 SerDes 1 and SerDes 2 AG16 --- --- ---

Ground

SD_GND06 SerDes 1 and SerDes 2 AG17 --- --- ---

Ground

SD_GND07 SerDes 1 and SerDes 2 AG18 --- --- ---

Ground

SD_GND08 SerDes 1 and SerDes 2 AG19 --- --- ---

Ground

SD_GND09 SerDes 1 and SerDes 2 AG20 --- --- ---

Ground

SD_GND10 SerDes 1 and SerDes 2 AG21 --- --- ---

Ground

SD_GND11 SerDes 1 and SerDes 2 AG22 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 60 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND12 SerDes 1 and SerDes 2 AG23 --- --- ---

Ground

SD_GND13 SerDes 1 and SerDes 2 AG24 --- --- ---

Ground

SD_GND14 SerDes 1 and SerDes 2 AG25 --- --- ---

Ground

SD_GND15 SerDes 1 and SerDes 2 AH16 --- --- ---

Ground

SD_GND16 SerDes 1 and SerDes 2 AH19 --- --- ---

Ground

SD_GND17 SerDes 1 and SerDes 2 AH22 --- --- ---

Ground

SD_GND18 SerDes 1 and SerDes 2 AH25 --- --- ---

Ground

SD_GND19 SerDes 1 and SerDes 2 AH27 --- --- ---

Ground

SD_GND20 SerDes 1 and SerDes 2 AJ12 --- --- ---

Ground

SD_GND21 SerDes 1 and SerDes 2 AK10 --- --- ---

Ground

SD_GND22 SerDes 1 and SerDes 2 AK11 --- --- ---

Ground

SD_GND23 SerDes 1 and SerDes 2 AK12 --- --- ---

Ground

SD_GND24 SerDes 1 and SerDes 2 AK13 --- --- ---

Ground

SD_GND25 SerDes 1 and SerDes 2 AK14 --- --- ---

Ground

SD_GND26 SerDes 1 and SerDes 2 AK15 --- --- ---

Ground

SD_GND27 SerDes 1 and SerDes 2 AK16 --- --- ---

Ground

SD_GND28 SerDes 1 and SerDes 2 AK17 --- --- ---

Ground

SD_GND29 SerDes 1 and SerDes 2 AK18 --- --- ---

Ground

SD_GND30 SerDes 1 and SerDes 2 AK19 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 61 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND31 SerDes 1 and SerDes 2 AK20 --- --- ---

Ground

SD_GND32 SerDes 1 and SerDes 2 AK21 --- --- ---

Ground

SD_GND33 SerDes 1 and SerDes 2 AK22 --- --- ---

Ground

SD_GND34 SerDes 1 and SerDes 2 AK23 --- --- ---

Ground

SD_GND35 SerDes 1 and SerDes 2 AK24 --- --- ---

Ground

SD_GND36 SerDes 1 and SerDes 2 AK25 --- --- ---

Ground

SD_GND37 SerDes 1 and SerDes 2 AK26 --- --- ---

Ground

SD_GND38 SerDes 1 and SerDes 2 AK27 --- --- ---

Ground

SD_GND39 SerDes 1 and SerDes 2 AL9 --- --- ---

Ground

SD_GND40 SerDes 1 and SerDes 2 AL11 --- --- ---

Ground

SD_GND41 SerDes 1 and SerDes 2 AL13 --- --- ---

Ground

SD_GND42 SerDes 1 and SerDes 2 AL15 --- --- ---

Ground

SD_GND43 SerDes 1 and SerDes 2 AL17 --- --- ---

Ground

SD_GND44 SerDes 1 and SerDes 2 AL19 --- --- ---

Ground

SD_GND45 SerDes 1 and SerDes 2 AL21 --- --- ---

Ground

SD_GND46 SerDes 1 and SerDes 2 AL23 --- --- ---

Ground

SD_GND47 SerDes 1 and SerDes 2 AL25 --- --- ---

Ground

SD_GND48 SerDes 1 and SerDes 2 AL27 --- --- ---

Ground

SD_GND49 SerDes 1 and SerDes 2 AM9 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 62 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND50 SerDes 1 and SerDes 2 AM11 --- --- ---

Ground

SD_GND51 SerDes 1 and SerDes 2 AM13 --- --- ---

Ground

SD_GND52 SerDes 1 and SerDes 2 AM15 --- --- ---

Ground

SD_GND53 SerDes 1 and SerDes 2 AM17 --- --- ---

Ground

SD_GND54 SerDes 1 and SerDes 2 AM18 --- --- ---

Ground

SD_GND55 SerDes 1 and SerDes 2 AM19 --- --- ---

Ground

SD_GND56 SerDes 1 and SerDes 2 AM21 --- --- ---

Ground

SD_GND57 SerDes 1 and SerDes 2 AM23 --- --- ---

Ground

SD_GND58 SerDes 1 and SerDes 2 AM25 --- --- ---

Ground

SD_GND59 SerDes 1 and SerDes 2 AM27 --- --- ---

Ground

SD_GND60 SerDes 1 and SerDes 2 AN8 --- --- ---

Ground

SD_GND61 SerDes 1 and SerDes 2 AN10 --- --- ---

Ground

SD_GND62 SerDes 1 and SerDes 2 AN12 --- --- ---

Ground

SD_GND63 SerDes 1 and SerDes 2 AN13 --- --- ---

Ground

SD_GND64 SerDes 1 and SerDes 2 AN14 --- --- ---

Ground

SD_GND65 SerDes 1 and SerDes 2 AN16 --- --- ---

Ground

SD_GND66 SerDes 1 and SerDes 2 AN18 --- --- ---

Ground

SD_GND67 SerDes 1 and SerDes 2 AN20 --- --- ---

Ground

SD_GND68 SerDes 1 and SerDes 2 AN22 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 63 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND69 SerDes 1 and SerDes 2 AN23 --- --- ---

Ground

SD_GND70 SerDes 1 and SerDes 2 AN24 --- --- ---

Ground

SD_GND71 SerDes 1 and SerDes 2 AN26 --- --- ---

Ground

SD_GND72 SerDes 1 and SerDes 2 AN28 --- --- ---

Ground

SD_GND73 SerDes 1 and SerDes 2 AP8 --- --- ---

Ground

SD_GND74 SerDes 1 and SerDes 2 AP10 --- --- ---

Ground

SD_GND75 SerDes 1 and SerDes 2 AP12 --- --- ---

Ground

SD_GND76 SerDes 1 and SerDes 2 AP14 --- --- ---

Ground

SD_GND77 SerDes 1 and SerDes 2 AP16 --- --- ---

Ground

SD_GND78 SerDes 1 and SerDes 2 AP18 --- --- ---

Ground

SD_GND79 SerDes 1 and SerDes 2 AP20 --- --- ---

Ground

SD_GND80 SerDes 1 and SerDes 2 AP22 --- --- ---

Ground

SD_GND81 SerDes 1 and SerDes 2 AP24 --- --- ---

Ground

SD_GND82 SerDes 1 and SerDes 2 AP26 --- --- ---

Ground

SD_GND83 SerDes 1 and SerDes 2 AP28 --- --- ---

Ground

SD_GND84 SerDes 1 and SerDes 2 AR9 --- --- ---

Ground

SD_GND85 SerDes 1 and SerDes 2 AR10 --- --- ---

Ground

SD_GND86 SerDes 1 and SerDes 2 AR11 --- --- ---

Ground

SD_GND87 SerDes 1 and SerDes 2 AR12 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 64 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND88 SerDes 1 and SerDes 2 AR14 --- --- ---

Ground

SD_GND89 SerDes 1 and SerDes 2 AR15 --- --- ---

Ground

SD_GND90 SerDes 1 and SerDes 2 AR16 --- --- ---

Ground

SD_GND91 SerDes 1 and SerDes 2 AR17 --- --- ---

Ground

SD_GND92 SerDes 1 and SerDes 2 AR18 --- --- ---

Ground

SD_GND93 SerDes 1 and SerDes 2 AR19 --- --- ---

Ground

SD_GND94 SerDes 1 and SerDes 2 AR20 --- --- ---

Ground

SD_GND95 SerDes 1 and SerDes 2 AR21 --- --- ---

Ground

SD_GND96 SerDes 1 and SerDes 2 AR22 --- --- ---

Ground

SD_GND97 SerDes 1 and SerDes 2 AR24 --- --- ---

Ground

SD_GND98 SerDes 1 and SerDes 2 AR25 --- --- ---

Ground

SD_GND99 SerDes 1 and SerDes 2 AR26 --- --- ---

Ground

SD_GND100 SerDes 1 and SerDes 2 AR27 --- --- ---

Ground

SD_GND101 SerDes 1 and SerDes 2 AT9 --- --- ---

Ground

SD_GND102 SerDes 1 and SerDes 2 AT11 --- --- ---

Ground

SD_GND103 SerDes 1 and SerDes 2 AT13 --- --- ---

Ground

SD_GND104 SerDes 1 and SerDes 2 AT15 --- --- ---

Ground

SD_GND105 SerDes 1 and SerDes 2 AT17 --- --- ---

Ground

SD_GND106 SerDes 1 and SerDes 2 AT19 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 65 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND107 SerDes 1 and SerDes 2 AT21 --- --- ---

Ground

SD_GND108 SerDes 1 and SerDes 2 AT23 --- --- ---

Ground

SD_GND109 SerDes 1 and SerDes 2 AT25 --- --- ---

Ground

SD_GND110 SerDes 1 and SerDes 2 AT27 --- --- ---

Ground

SD_GND111 SerDes 1 and SerDes 2 AU9 --- --- ---

Ground

SD_GND112 SerDes 1 and SerDes 2 AU11 --- --- ---

Ground

SD_GND113 SerDes 1 and SerDes 2 AU13 --- --- ---

Ground

SD_GND114 SerDes 1 and SerDes 2 AU15 --- --- ---

Ground

SD_GND115 SerDes 1 and SerDes 2 AU17 --- --- ---

Ground

SD_GND116 SerDes 1 and SerDes 2 AU19 --- --- ---

Ground

SD_GND117 SerDes 1 and SerDes 2 AU21 --- --- ---

Ground

SD_GND118 SerDes 1 and SerDes 2 AU23 --- --- ---

Ground

SD_GND119 SerDes 1 and SerDes 2 AU25 --- --- ---

Ground

SD_GND120 SerDes 1 and SerDes 2 AU27 --- --- ---

Ground

SD_GND121 SerDes 1 and SerDes 2 AV8 --- --- ---

Ground

SD_GND122 SerDes 1 and SerDes 2 AV10 --- --- ---

Ground

SD_GND123 SerDes 1 and SerDes 2 AV12 --- --- ---

Ground

SD_GND124 SerDes 1 and SerDes 2 AV14 --- --- ---

Ground

SD_GND125 SerDes 1 and SerDes 2 AV16 --- --- ---

Ground

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 66 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_GND126 SerDes 1 and SerDes 2 AV18 --- --- ---

Ground

SD_GND127 SerDes 1 and SerDes 2 AV20 --- --- ---

Ground

SD_GND128 SerDes 1 and SerDes 2 AV22 --- --- ---

Ground

SD_GND129 SerDes 1 and SerDes 2 AV24 --- --- ---

Ground

SD_GND130 SerDes 1 and SerDes 2 AV26 --- --- ---

Ground

SD_GND131 SerDes 1 and SerDes 2 AV28 --- --- ---

Ground

SD_GND132 SerDes 1 and SerDes 2 AW8 --- --- ---

Ground

SD_GND133 SerDes 1 and SerDes 2 AW10 --- --- ---

Ground

SD_GND134 SerDes 1 and SerDes 2 AW12 --- --- ---

Ground

SD_GND135 SerDes 1 and SerDes 2 AW14 --- --- ---

Ground

SD_GND136 SerDes 1 and SerDes 2 AW16 --- --- ---

Ground

SD_GND137 SerDes 1 and SerDes 2 AW18 --- --- ---

Ground

SD_GND138 SerDes 1 and SerDes 2 AW20 --- --- ---

Ground

SD_GND139 SerDes 1 and SerDes 2 AW22 --- --- ---

Ground

SD_GND140 SerDes 1 and SerDes 2 AW24 --- --- ---

Ground

SD_GND141 SerDes 1 and SerDes 2 AW26 --- --- ---

Ground

SD_GND142 SerDes 1 and SerDes 2 AW28 --- --- ---

Ground

SD3_GND01 SerDes3 core logic ground A12 --- --- ---

SD3_GND02 SerDes3 core logic ground A14 --- --- ---

SD3_GND03 SerDes3 core logic ground A16 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 67 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_GND04 SerDes3 core logic ground A18 --- --- ---

SD3_GND05 SerDes3 core logic ground A20 --- --- ---

SD3_GND06 SerDes3 core logic ground A22 --- --- ---

SD3_GND07 SerDes3 core logic ground B14 --- --- ---

SD3_GND08 SerDes3 core logic ground B16 --- --- ---

SD3_GND09 SerDes3 core logic ground B18 --- --- ---

SD3_GND10 SerDes3 core logic ground B20 --- --- ---

SD3_GND11 SerDes3 core logic ground B22 --- --- ---

SD3_GND12 SerDes3 core logic ground C13 --- --- ---

SD3_GND13 SerDes3 core logic ground C15 --- --- ---

SD3_GND14 SerDes3 core logic ground C17 --- --- ---

SD3_GND15 SerDes3 core logic ground C19 --- --- ---

SD3_GND16 SerDes3 core logic ground C21 --- --- ---

SD3_GND17 SerDes3 core logic ground D13 --- --- ---

SD3_GND18 SerDes3 core logic ground D15 --- --- ---

SD3_GND19 SerDes3 core logic ground D17 --- --- ---

SD3_GND20 SerDes3 core logic ground D19 --- --- ---

SD3_GND21 SerDes3 core logic ground D21 --- --- ---

SD3_GND22 SerDes3 core logic ground E13 --- --- ---

SD3_GND23 SerDes3 core logic ground E14 --- --- ---

SD3_GND24 SerDes3 core logic ground E15 --- --- ---

SD3_GND25 SerDes3 core logic ground E16 --- --- ---

SD3_GND26 SerDes3 core logic ground E18 --- --- ---

SD3_GND27 SerDes3 core logic ground E19 --- --- ---

SD3_GND28 SerDes3 core logic ground E20 --- --- ---

SD3_GND29 SerDes3 core logic ground E21 --- --- ---

SD3_GND30 SerDes3 core logic ground F12 --- --- ---

SD3_GND31 SerDes3 core logic ground F14 --- --- ---

SD3_GND32 SerDes3 core logic ground F16 --- --- ---

SD3_GND33 SerDes3 core logic ground F18 --- --- ---

SD3_GND34 SerDes3 core logic ground F20 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 68 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_GND35 SerDes3 core logic ground F22 --- --- ---

SD3_GND36 SerDes3 core logic ground G12 --- --- ---

SD3_GND37 SerDes3 core logic ground G14 --- --- ---

SD3_GND38 SerDes3 core logic ground G16 --- --- ---

SD3_GND39 SerDes3 core logic ground G17 --- --- ---

SD3_GND40 SerDes3 core logic ground G18 --- --- ---

SD3_GND41 SerDes3 core logic ground G20 --- --- ---

SD3_GND42 SerDes3 core logic ground G22 --- --- ---

SD3_GND43 SerDes3 core logic ground H13 --- --- ---

SD3_GND44 SerDes3 core logic ground H15 --- --- ---

SD3_GND45 SerDes3 core logic ground H17 --- --- ---

SD3_GND46 SerDes3 core logic ground H19 --- --- ---

SD3_GND47 SerDes3 core logic ground H21 --- --- ---

SD3_GND48 SerDes3 core logic ground H22 --- --- ---

SD3_GND49 SerDes3 core logic ground J13 --- --- ---

SD3_GND50 SerDes3 core logic ground J15 --- --- ---

SD3_GND51 SerDes3 core logic ground J17 --- --- ---

SD3_GND52 SerDes3 core logic ground J19 --- --- ---

SD3_GND53 SerDes3 core logic ground J21 --- --- ---

SD3_GND54 SerDes3 core logic ground K13 --- --- ---

SD3_GND55 SerDes3 core logic ground K14 --- --- ---

SD3_GND56 SerDes3 core logic ground K15 --- --- ---

SD3_GND57 SerDes3 core logic ground K16 --- --- ---

SD3_GND58 SerDes3 core logic ground K17 --- --- ---

SD3_GND59 SerDes3 core logic ground K18 --- --- ---

SD3_GND60 SerDes3 core logic ground K19 --- --- ---

SD3_GND61 SerDes3 core logic ground K20 --- --- ---

SD3_GND62 SerDes3 core logic ground K21 --- --- ---

SD3_GND63 SerDes3 core logic ground L14 --- --- ---

SD3_GND64 SerDes3 core logic ground L21 --- --- ---

SD3_GND65 SerDes3 core logic ground N14 --- --- ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 69 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_GND66 SerDes3 core logic ground N15 --- --- ---

SD3_GND67 SerDes3 core logic ground N16 --- --- ---

SD3_GND68 SerDes3 core logic ground N17 --- --- ---

SD3_GND69 SerDes3 core logic ground N18 --- --- ---

SD3_GND70 SerDes3 core logic ground N19 --- --- ---

SD3_GND71 SerDes3 core logic ground N20 --- --- ---

OVDD01 General I/O supply N21 --- OV DD ---

OVDD02 General I/O supply N22 --- OV DD ---

OVDD03 General I/O supply N23 --- OV DD ---

OVDD04 General I/O supply N24 --- OV DD ---

OVDD05 General I/O supply N25 --- OV DD ---

OVDD06 General I/O supply R11 --- OV DD ---

OVDD07 General I/O supply T11 --- OV DD ---

OVDD08 General I/O supply U11 --- OV DD ---

OVDD09 General I/O supply V11 --- OV DD ---

OVDD10 General I/O supply W11 --- OV DD ---

OVDD11 General I/O supply Y12 --- OV DD ---

OVDD12 General I/O supply Y28 --- OV DD ---

EVDD SDHC 1.8V T12 --- EV DD ---

G1VDD01 DDR supply for port 1 A38 --- G1V DD ---

G1VDD02 DDR supply for port 1 B36 --- G1V DD ---

G1VDD03 DDR supply for port 1 B39 --- G1V DD ---

G1VDD04 DDR supply for port 1 D38 --- G1V DD ---

G1VDD05 DDR supply for port 1 F38 --- G1V DD ---

G1VDD06 DDR supply for port 1 H38 --- G1V DD ---

G1VDD07 DDR supply for port 1 J39 --- G1V DD ---

G1VDD08 DDR supply for port 1 K37 --- G1V DD ---

G1VDD09 DDR supply for port 1 L39 --- G1V DD ---

G1VDD10 DDR supply for port 1 M37 --- G1V DD ---

G1VDD11 DDR supply for port 1 N29 --- G1V DD ---

G1VDD12 DDR supply for port 1 P29 --- G1V DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 70 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

G1VDD13 DDR supply for port 1 P38 --- G1V DD ---

G1VDD14 DDR supply for port 1 R29 --- G1V DD ---

G1VDD15 DDR supply for port 1 T29 --- G1V DD ---

G1VDD16 DDR supply for port 1 T38 --- G1V DD ---

G1VDD17 DDR supply for port 1 U29 --- G1V DD ---

G1VDD18 DDR supply for port 1 V29 --- G1V DD ---

G1VDD19 DDR supply for port 1 V38 --- G1V DD ---

G1VDD20 DDR supply for port 1 W29 --- G1V DD ---

G2VDD01 DDR supply for port 2 AA29 --- G2V DD ---

G2VDD02 DDR supply for port 2 AB29 --- G2V DD ---

G2VDD03 DDR supply for port 2 AB38 --- G2V DD ---

G2VDD04 DDR supply for port 2 AC29 --- G2V DD ---

G2VDD05 DDR supply for port 2 AD29 --- G2V DD ---

G2VDD06 DDR supply for port 2 AD38 --- G2V DD ---

G2VDD07 DDR supply for port 2 AE29 --- G2V DD ---

G2VDD08 DDR supply for port 2 AF29 --- G2V DD ---

G2VDD09 DDR supply for port 2 AF38 --- G2V DD ---

G2VDD10 DDR supply for port 2 AG29 --- G2V DD ---

G2VDD11 DDR supply for port 2 AH37 --- G2V DD ---

G2VDD12 DDR supply for port 2 AJ39 --- G2V DD ---

G2VDD13 DDR supply for port 2 AK37 --- G2V DD ---

G2VDD14 DDR supply for port 2 AL39 --- G2V DD ---

G2VDD15 DDR supply for port 2 AM38 --- G2V DD ---

G2VDD16 DDR supply for port 2 AP38 --- G2V DD ---

G2VDD17 DDR supply for port 2 AT38 --- G2V DD ---

G2VDD18 DDR supply for port 2 AV36 --- G2V DD ---

G2VDD19 DDR supply for port 2 AV39 --- G2V DD ---

G2VDD20 DDR supply for port 2 AW38 --- G2V DD ---

FA1_CVL Internal Use Only AJ28 --- FA1_CVL 12

FA2_DVL Internal Use Only L28 --- FA2_DVL 12

PROG_MTR Internal Use Only M27 --- PROG_MTR 12

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 71 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

TA_PROG_SFP SFP Fuse Programming M26 --- TA_PROG_SFP ---

Override supply

TH_VDD Thermal Monitor Unit supply G23 --- TH_V DD ---

VDD01 Supply for cores and platform N27 --- V DD ---

VDD02 Supply for cores and platform P22 --- V DD ---

VDD03 Supply for cores and platform P24 --- V DD ---

VDD04 Supply for cores and platform P26 --- V DD ---

VDD05 Supply for cores and platform R13 --- V DD ---

VDD06 Supply for cores and platform R15 --- V DD ---

VDD07 Supply for cores and platform R17 --- V DD ---

VDD08 Supply for cores and platform R19 --- V DD ---

VDD09 Supply for cores and platform R21 --- V DD ---

VDD10 Supply for cores and platform R23 --- V DD ---

VDD11 Supply for cores and platform R25 --- V DD ---

VDD12 Supply for cores and platform T14 --- V DD ---

VDD13 Supply for cores and platform T16 --- V DD ---

VDD14 Supply for cores and platform T18 --- V DD ---

VDD15 Supply for cores and platform T20 --- V DD ---

VDD16 Supply for cores and platform T22 --- V DD ---

VDD17 Supply for cores and platform T24 --- V DD ---

VDD18 Supply for cores and platform T26 --- V DD ---

VDD19 Supply for cores and platform U13 --- V DD ---

VDD20 Supply for cores and platform U15 --- V DD ---

VDD21 Supply for cores and platform U17 --- V DD ---

VDD22 Supply for cores and platform U19 --- V DD ---

VDD23 Supply for cores and platform U21 --- V DD ---

VDD24 Supply for cores and platform U23 --- V DD ---

VDD25 Supply for cores and platform U25 --- V DD ---

VDD26 Supply for cores and platform V12 --- V DD ---

VDD27 Supply for cores and platform V14 --- V DD ---

VDD28 Supply for cores and platform V16 --- V DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 72 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

VDD29 Supply for cores and platform V18 --- V DD ---

VDD30 Supply for cores and platform V20 --- V DD ---

VDD31 Supply for cores and platform V22 --- V DD ---

VDD32 Supply for cores and platform V24 --- V DD ---

VDD33 Supply for cores and platform V26 --- V DD ---

VDD34 Supply for cores and platform W13 --- V DD ---

VDD35 Supply for cores and platform W15 --- V DD ---

VDD36 Supply for cores and platform W17 --- V DD ---

VDD37 Supply for cores and platform W19 --- V DD ---

VDD38 Supply for cores and platform W21 --- V DD ---

VDD39 Supply for cores and platform W23 --- V DD ---

VDD40 Supply for cores and platform W25 --- V DD ---

VDD41 Supply for cores and platform Y14 --- V DD ---

VDD42 Supply for cores and platform Y16 --- V DD ---

VDD43 Supply for cores and platform Y18 --- V DD ---

VDD44 Supply for cores and platform Y20 --- V DD ---

VDD45 Supply for cores and platform Y22 --- V DD ---

VDD46 Supply for cores and platform Y24 --- V DD ---

VDD47 Supply for cores and platform Y26 --- V DD ---

VDD48 Supply for cores and platform AA13 --- V DD ---

VDD49 Supply for cores and platform AA15 --- V DD ---

VDD50 Supply for cores and platform AA17 --- V DD ---

VDD51 Supply for cores and platform AA19 --- V DD ---

VDD52 Supply for cores and platform AA21 --- V DD ---

VDD53 Supply for cores and platform AA23 --- V DD ---

VDD54 Supply for cores and platform AA25 --- V DD ---

VDD55 Supply for cores and platform AB14 --- V DD ---

VDD56 Supply for cores and platform AB16 --- V DD ---

VDD57 Supply for cores and platform AB18 --- V DD ---

VDD58 Supply for cores and platform AB20 --- V DD ---

VDD59 Supply for cores and platform AB22 --- V DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 73 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

VDD60 Supply for cores and platform AB24 --- V DD ---

VDD61 Supply for cores and platform AB26 --- V DD ---

VDD62 Supply for cores and platform AC13 --- V DD ---

VDD63 Supply for cores and platform AC15 --- V DD ---

VDD64 Supply for cores and platform AC17 --- V DD ---

VDD65 Supply for cores and platform AC19 --- V DD ---

VDD66 Supply for cores and platform AC21 --- V DD ---

VDD67 Supply for cores and platform AC23 --- V DD ---

VDD68 Supply for cores and platform AC25 --- V DD ---

VDD69 Supply for cores and platform AD12 --- V DD ---

VDD70 Supply for cores and platform AD14 --- V DD ---

VDD71 Supply for cores and platform AD16 --- V DD ---

VDD72 Supply for cores and platform AD18 --- V DD ---

VDD73 Supply for cores and platform AD20 --- V DD ---

VDD74 Supply for cores and platform AD22 --- V DD ---

VDD75 Supply for cores and platform AD24 --- V DD ---

VDD76 Supply for cores and platform AD26 --- V DD ---

VDD77 Supply for cores and platform AE13 --- V DD ---

VDD78 Supply for cores and platform AE15 --- V DD ---

VDD79 Supply for cores and platform AE17 --- V DD ---

VDD80 Supply for cores and platform AE19 --- V DD ---

VDD81 Supply for cores and platform AE21 --- V DD ---

VDD82 Supply for cores and platform AE23 --- V DD ---

VDD83 Supply for cores and platform AE25 --- V DD ---

VDD84 Supply for cores and platform AF26 --- V DD ---

TA_BB_VDD Low Power Security Monitor J26 --- TA_BB_V DD ---

supply

SD3_SVDD1 SerDes3 core logic supply P14 --- SD3_SV DD ---

SD3_SVDD2 SerDes3 core logic supply P15 --- SD3_SV DD ---

SD3_SVDD3 SerDes3 core logic supply P16 --- SD3_SV DD ---

SD3_SVDD4 SerDes3 core logic supply P17 --- SD3_SV DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 74 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_SVDD5 SerDes3 core logic supply P18 --- SD3_SV DD ---

SD3_SVDD6 SerDes3 core logic supply P19 --- SD3_SV DD ---

SD3_SVDD7 SerDes3 core logic supply P20 --- SD3_SV DD ---

AVDD1 Platform PLL supply J23 --- AV DD ---

AVDD_SD3_PLLF SerDes3 Analog PLL fast L16 --- AV DD _SD3_PLLF ---

supply

AVDD_SD3_PLLS SerDes3 Analog PLL slow L19 --- AV DD_SD3_PLLS ---

supply

AVDD2 Core/platform PLL supply L23 --- AV DD ---

AVDD3 Core/platform PLL supply L24 --- AV DD ---

AVDD4 Core/platform PLL supply L25 --- AV DD ---

AVDD5 Core/platform PLL supply L26 --- AV DD ---

AVDD_D1 DDR PHY1 PLL supply T28 --- AV DD _D1 ---

AVDD_D2 DDR PHY2 PLL supply AC28 --- AV DD _D2 ---

AVDD_SD1_PLLS SerDes1 Analog PLL slow AJ16 --- AV DD _SD1_PLLS ---

supply

AVDD_SD1_PLLF SerDes1 Analog PLL slow AJ19 --- AV DD _SD1_PLLF ---

supply

AVDD_SD2_PLLF SerDes2 Analog PLL fast AJ22 --- AV DD _SD2_PLLF ---

supply

AVDD_SD2_PLLS SerDes2 Analog PLL fast AJ25 --- AV DD _SD2_PLLS ---

supply

USB_HVDD1 High voltage supply for High M12 --- USB_HV DD ---
Speed operation

USB_HVDD2 High voltage supply for High N11 --- USB_HV DD ---
Speed operation

USB_SDVDD1 Analog and digital high speed P11 --- USB_SDV DD ---
low voltage supply

USB_SDVDD2 Analog and digital high speed P12 --- USB_SDV DD ---
low voltage supply

USB_SVDD1 Analog and digital super M13 --- USB_SV DD ---

speed low voltage supply

USB_SVDD2 Analog and digital super N13 --- USB_SV DD ---

speed low voltage supply

SD_SVDD01 SerDes 1 and SerDes2 core AF12 --- SD_SV DD ---

logic supply

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 75 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD_SVDD02 SerDes 1 and SerDes2 core AF13 --- SD_SV DD ---

logic supply

SD_SVDD03 SerDes 1 and SerDes2 core AF14 --- SD_SV DD ---

logic supply

SD_SVDD04 SerDes 1 and SerDes2 core AF15 --- SD_SV DD ---

logic supply

SD_SVDD05 SerDes 1 and SerDes2 core AF16 --- SD_SV DD ---

logic supply

SD_SVDD06 SerDes 1 and SerDes2 core AF17 --- SD_SV DD ---

logic supply

SD_SVDD07 SerDes 1 and SerDes2 core AF18 --- SD_SV DD ---

logic supply

SD_SVDD08 SerDes 1 and SerDes2 core AF19 --- SD_SV DD ---

logic supply

SD_SVDD09 SerDes 1 and SerDes2 core AF20 --- SD_SV DD ---

logic supply

SD_SVDD10 SerDes 1 and SerDes2 core AF21 --- SD_SV DD ---

logic supply

SD_SVDD11 SerDes 1 and SerDes2 core AF22 --- SD_SV DD ---

logic supply

SD_SVDD12 SerDes 1 and SerDes2 core AF23 --- SD_SV DD ---

logic supply

SD_SVDD13 SerDes 1 and SerDes2 core AF24 --- SD_SV DD ---

logic supply

SD_SVDD14 SerDes 1 and SerDes2 core AF25 --- SD_SV DD ---

logic supply

SD_OVDD01 SerDes1 transceiver supply AH12 --- SD_OV DD ---

SD_OVDD02 SerDes1 transceiver supply AH13 --- SD_OV DD ---

SD_OVDD03 SerDes1 transceiver supply AH14 --- SD_OV DD ---

SD_OVDD04 SerDes1 transceiver supply AH15 --- SD_OV DD ---

SD_OVDD05 SerDes1 transceiver supply AH17 --- SD_OV DD ---

SD_OVDD06 SerDes1 transceiver supply AH18 --- SD_OV DD ---

SD_OVDD07 SerDes1 transceiver supply AH20 --- SD_OV DD ---

SD_OVDD08 SerDes1 transceiver supply AH21 --- SD_OV DD ---

SD_OVDD09 SerDes1 transceiver supply AH23 --- SD_OV DD ---

SD_OVDD10 SerDes1 transceiver supply AH24 --- SD_OV DD ---

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 76 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

SD3_OVDD1 SerDes3 transceiver supply M14 --- SD3_OV DD ---

SD3_OVDD2 SerDes3 transceiver supply M15 --- SD3_OV DD ---

SD3_OVDD3 SerDes3 transceiver supply M16 --- SD3_OV DD ---

SD3_OVDD4 SerDes3 transceiver supply M17 --- SD3_OV DD ---

SD3_OVDD5 SerDes3 transceiver supply M18 --- SD3_OV DD ---

SD3_OVDD6 SerDes3 transceiver supply M19 --- SD3_OV DD ---

SD3_OVDD7 SerDes3 transceiver supply M20 --- SD3_OV DD ---

SENSEVDD_CA VDD Sense pin J25 --- SENSEVDD_CA ---

SENSEVDD_CB VDD Sense pin AG27 --- SENSEVDD_CB ---

SENSEVDD_PL VDD Sense pin AG10 --- SENSEVDD_PL ---

No Connection Pins

NC_K11 No Connection K11 --- --- 10

NC_K22 No Connection K22 --- --- 10

NC_L8 No Connection L8 --- --- 10

NC_L9 No Connection L9 --- --- 10

NC_M5 No Connection M5 --- --- 10

NC_P28 No Connection P28 --- --- 10

NC_R5 No Connection R5 --- --- 10

NC_R6 No Connection R6 --- --- 10

NC_R7 No Connection R7 --- --- 10

NC_R8 No Connection R8 --- --- 10

NC_R9 No Connection R9 --- --- 10

NC_R27 No Connection R27 --- --- 10

NC_T2 No Connection T2 --- --- 10

NC_T4 No Connection T4 --- --- 10

NC_T5 No Connection T5 --- --- 10

NC_T7 No Connection T7 --- --- 10

NC_T8 No Connection T8 --- --- 10

NC_T9 No Connection T9 --- --- 10

NC_U1 No Connection U1 --- --- 10

NC_U2 No Connection U2 --- --- 10

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 77 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

NC_U3 No Connection U3 --- --- 10

NC_U5 No Connection U5 --- --- 10

NC_U6 No Connection U6 --- --- 10

NC_U7 No Connection U7 --- --- 10

NC_U9 No Connection U9 --- --- 10

NC_U27 No Connection U27 --- --- 10

NC_V1 No Connection V1 --- --- 10

NC_V2 No Connection V2 --- --- 10

NC_V3 No Connection V3 --- --- 10

NC_V4 No Connection V4 --- --- 10

NC_V5 No Connection V5 --- --- 10

NC_V7 No Connection V7 --- --- 10

NC_V8 No Connection V8 --- --- 10

NC_V9 No Connection V9 --- --- 10

NC_V28 No Connection V28 --- --- 10

NC_W1 No Connection W1 --- --- 10

NC_W2 No Connection W2 --- --- 10

NC_W3 No Connection W3 --- --- 10

NC_W5 No Connection W5 --- --- 10

NC_W6 No Connection W6 --- --- 10

NC_W7 No Connection W7 --- --- 10

NC_W9 No Connection W9 --- --- 10

NC_W27 No Connection W27 --- --- 10

NC_Y1 No Connection Y1 --- --- 10

NC_Y2 No Connection Y2 --- --- 10

NC_Y3 No Connection Y3 --- --- 10

NC_Y4 No Connection Y4 --- --- 10

NC_Y5 No Connection Y5 --- --- 10

NC_Y7 No Connection Y7 --- --- 10

NC_Y8 No Connection Y8 --- --- 10

NC_Y9 No Connection Y9 --- --- 10

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 78 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

NC_Y11 No Connection Y11 --- --- 10

NC_AA1 No Connection AA1 --- --- 10

NC_AA2 No Connection AA2 --- --- 10

NC_AA3 No Connection AA3 --- --- 10

NC_AA5 No Connection AA5 --- --- 10

NC_AA6 No Connection AA6 --- --- 10

NC_AA7 No Connection AA7 --- --- 10

NC_AA9 No Connection AA9 --- --- 10

NC_AA11 No Connection AA11 --- --- 10

NC_AA27 No Connection AA27 --- --- 10

NC_AB1 No Connection AB1 --- --- 10

NC_AB2 No Connection AB2 --- --- 10

NC_AB3 No Connection AB3 --- --- 10

NC_AB4 No Connection AB4 --- --- 10

NC_AB5 No Connection AB5 --- --- 10

NC_AB7 No Connection AB7 --- --- 10

NC_AB8 No Connection AB8 --- --- 10

NC_AB9 No Connection AB9 --- --- 10

NC_AB11 No Connection AB11 --- --- 10

NC_AB12 No Connection AB12 --- --- 10

NC_AC1 No Connection AC1 --- --- 10

NC_AC2 No Connection AC2 --- --- 10

NC_AC3 No Connection AC3 --- --- 10

NC_AC5 No Connection AC5 --- --- 10

NC_AC6 No Connection AC6 --- --- 10

NC_AC7 No Connection AC7 --- --- 10

NC_AC9 No Connection AC9 --- --- 10

NC_AC11 No Connection AC11 --- --- 10

NC_AC12 No Connection AC12 --- --- 10

NC_AC27 No Connection AC27 --- --- 10

NC_AD1 No Connection AD1 --- --- 10

Table continues on the next page...

Layerscape LX2160A, LX2120A, LX2080A Data Sheet, Rev. 3, 09/2021

Data Sheet: Technical Data 79 / 198
NXP Semiconductors
Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

NC_AD2 No Connection AD2 --- --- 10

NC_AD3 No Connection AD3 --- --- 10

NC_AD4 No Connection AD4 --- --- 10

NC_AD5 No Connection AD5 --- --- 10

NC_AD7 No Connection AD7 --- --- 10

NC_AD8 No Connection AD8 --- --- 10

NC_AD9 No Connection AD9 --- --- 10

NC_AD11 No Connection AD11 --- --- 10

NC_AD28 No Connection AD28 --- --- 10

NC_AE1 No Connection AE1 --- --- 10

NC_AE2 No Connection AE2 --- --- 10

NC_AE3 No Connection AE3 --- --- 10

NC_AE5 No Connection AE5 --- --- 10

NC_AE6 No Connection AE6 --- --- 10

NC_AE7 No Connection AE7 --- --- 10

NC_AE9 No Connection AE9 --- --- 10

NC_AE11 No Connection AE11 --- --- 10

NC_AE27 No Connection AE27 --- --- 10

NC_AF1 No Connection AF1 --- --- 10

NC_AF2 No Connection AF2 --- --- 10

NC_AF3 No Connection AF3 --- --- 10

NC_AF4 No Connection AF4 --- --- 10

NC_AF5 No Connection AF5 --- --- 10

NC_AF7 No Connection AF7 --- --- 10

NC_AF8 No Connection AF8 --- --- 10

NC_AF9 No Connection AF9 --- --- 10

NC_AF11 No Connection AF11 --- --- 10

NC_AF28 No Connection AF28 --- --- 10

NC_AG1 No Connection AG1 --- --- 10

NC_AG2 No Connection AG2 --- --- 10

NC_AG3 No Connection AG3 --- --- 10

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Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

NC_AG5 No Connection AG5 --- --- 10

NC_AG6 No Connection AG6 --- --- 10

NC_AG7 No Connection AG7 --- --- 10

NC_AG8 No Connection AG8 --- --- 10

NC_AG28 No Connection AG28 --- --- 10

NC_AH1 No Connection AH1 --- --- 10

NC_AH2 No Connection AH2 --- --- 10

NC_AH3 No Connection AH3 --- --- 10

NC_AH4 No Connection AH4 --- --- 10

NC_AH5 No Connection AH5 --- --- 10

NC_AH6 No Connection AH6 --- --- 10

NC_AH8 No Connection AH8 --- --- 10

NC_AH9 No Connection AH9 --- --- 10

NC_AH10 No Connection AH10 --- --- 10

NC_AJ1 No Connection AJ1 --- --- 10

NC_AJ2 No Connection AJ2 --- --- 10

NC_AJ3 No Connection AJ3 --- --- 10

NC_AJ4 No Connection AJ4 --- --- 10

NC_AJ6 No Connection AJ6 --- --- 10

NC_AJ7 No Connection AJ7 --- --- 10

NC_AJ8 No Connection AJ8 --- --- 10

NC_AJ9 No Connection AJ9 --- --- 10

NC_AK1 No Connection AK1 --- --- 10

NC_AK2 No Connection AK2 --- --- 10

NC_AK3 No Connection AK3 --- --- 10

NC_AK5 No Connection AK5 --- --- 10

NC_AK6 No Connection AK6 --- --- 10

NC_AK8 No Connection AK8 --- --- 10

NC_AL1 No Connection AL1 --- --- 10

NC_AL2 No Connection AL2 --- --- 10

NC_AL3 No Connection AL3 --- --- 10

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Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

NC_AL4 No Connection AL4 --- --- 10

NC_AL6 No Connection AL6 --- --- 10

NC_AL7 No Connection AL7 --- --- 10

NC_AL8 No Connection AL8 --- --- 10

NC_AL18 No Connection AL18 --- --- 10

NC_AM1 No Connection AM1 --- --- 10

NC_AM2 No Connection AM2 --- --- 10

NC_AM4 No Connection AM4 --- --- 10

NC_AM5 No Connection AM5 --- --- 10

NC_AM6 No Connection AM6 --- --- 10

NC_AM7 No Connection AM7 --- --- 10

NC_AN1 No Connection AN1 --- --- 10

NC_AN2 No Connection AN2 --- --- 10

NC_AN3 No Connection AN3 --- --- 10

NC_AN4 No Connection AN4 --- --- 10

NC_AN5 No Connection AN5 --- --- 10

NC_AN7 No Connection AN7 --- --- 10

NC_AP1 No Connection AP1 --- --- 10

NC_AP2 No Connection AP2 --- --- 10

NC_AP4 No Connection AP4 --- --- 10

NC_AP6 No Connection AP6 --- --- 10

NC_AP7 No Connection AP7 --- --- 10

NC_AR1 No Connection AR1 --- --- 10

NC_AR2 No Connection AR2 --- --- 10

NC_AR3 No Connection AR3 --- --- 10

NC_AR4 No Connection AR4 --- --- 10

NC_AR5 No Connection AR5 --- --- 10

NC_AR6 No Connection AR6 --- --- 10

NC_AR7 No Connection AR7 --- --- 10

NC_AT1 No Connection AT1 --- --- 10

NC_AT2 No Connection AT2 --- --- 10

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Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

NC_AT3 No Connection AT3 --- --- 10

NC_AT5 No Connection AT5 --- --- 10

NC_AT7 No Connection AT7 --- --- 10

NC_AT8 No Connection AT8 --- --- 10

NC_AU1 No Connection AU1 --- --- 10

NC_AU2 No Connection AU2 --- --- 10

NC_AU4 No Connection AU4 --- --- 10

NC_AU5 No Connection AU5 --- --- 10

NC_AU6 No Connection AU6 --- --- 10

NC_AU7 No Connection AU7 --- --- 10

NC_AV1 No Connection AV1 --- --- 10

NC_AV2 No Connection AV2 --- --- 10

NC_AV3 No Connection AV3 --- --- 10

NC_AV5 No Connection AV5 --- --- 10

NC_AV7 No Connection AV7 --- --- 10

NC_AW3 No Connection AW3 --- --- 10

NC_AW4 No Connection AW4 --- --- 10

NC_AW5 No Connection AW5 --- --- 10

NC_AW6 No Connection AW6 --- --- 10

NC_AW7 No Connection AW7 --- --- 10

1. Functionally, this pin is an output or an input, but structurally it is an I/O because it either sample configuration input
during reset, is a muxed pin, or has other manufacturing test functions. This pin will therefore be described as an I/O for
boundary scan.
2. This output is actively driven during reset rather than being tri-stated during reset.
3. MDIC is grounded through a 240 Ω precision 1% resistor. For either full or half driver strength calibration of DDR IOs,
use the same MDIC resistor value of 240 Ω. The memory controller register setting can be used to determine automatic
calibration is done to full or half drive strength. This pin is used for automatic calibration of the DDR4 IOs. The MDIC pin
must be connected to 240 Ω precision 1% resistors.
4. This pin is a power-on-reset (POR) configuration pin. It has a weak internal pull-up resistor that is enabled during POR
state only. The internal pull-up resistor allows the default value to be captured at POR de-assertion. This pull-up can
be overpowered by an external pull-down resistor in case a change in the default value is required. Refer to the Design
Checklist for details.
5. Recommend that a weak pull-up resistor be placed on this pin to the respective power supply. Refer to the Design
Checklist for details.

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Pin assignments

Table 2. Pinout list by bus (continued)

Signal Signal Description Package Pin Power Supply Notes

pin type
number

6. This pin is an open-drain signal.

7. This pin has a weak internal pull-up P-FET that is always enabled.
8. These are test signals for factory use only and must be pulled up (100 Ω to 1 kΩ) to the respective power supply for
normal operation.
9. This pin requires a 200 Ω ± 1% pull-up resistor to respective power-supply.
10. Do not connect. These pins should be left floating.
11. This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
12. These pins must be pulled to ground (GND).
13. This pin requires a 1.5 kΩ ± 1% pull-up resistor to respective power-supply.
14. These pins should be tied to ground if the diode is not utilized for temperature monitoring.
15. Attach 200 Ω ± 1% 100-ppm/C precision resistor-to-ground. Voltage range is between 0 to 250 mV.
16. Refer to the design checklist.
17. Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any
externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, an external
pull-up is required to drive this pin to a safe state during reset.
18. A 30.1 kΩ (±1%, ±100 ppm/⁰C) resistor is required between the USBn_VBUS and the 5 V supply.

Warning
See "Connection Recommendations"for additional details on properly connecting these pins for
specific applications.

2.2.1 DDR1 pins

See the DDR1 pins.

2.2.2 DDR2 pins

See the DDR2 pins.

2.2.3 I2C1 pins

See the I2C1 pins.

2.2.4 I2C2 pins

See the I2C2 pins.

2.2.5 I2C3 pins

See the I2C3 pins.

2.2.6 I2C4 pins

See the I2C4 pins.

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Pin assignments

2.2.7 I2C5 pins

See the I2C5 pins.

2.2.8 I2C6 pins

See the I2C6 pins.

2.2.9 I2C7 pins

See the I2C7 pins.

2.2.10 I2C8 pins

See the I2C8 pins.

2.2.11 XSPI1 pins

See the XSPI1 pins.

2.2.12 eSDHC1 pins

See the eSDHC1 pins.

2.2.13 eSDHC2 pins

See the eSDHC2 pins.

2.2.14 UART pins

See the UART pins.

2.2.15 Interrupt controller pins

See the Interrupt Controller pins.

2.2.16 Trust pins

See the Trust pins.

2.2.17 System control pins

See the system control pins.

2.2.18 Clocking pins

See the Clocking pins.

2.2.19 Debug pins

See the Debug pins.

2.2.20 DFT pins

See the DFT pins.

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Pin assignments

2.2.21 JTAG pins

See the JTAG pins.

2.2.22 Analog pins

See the Analog pins.

2.2.23 SerDes1 pins

See the SerDes1 pins.

2.2.24 SerDes2 pins

See the SerDes2 pins.

2.2.25 SerDes3 pins

See the SerDes3 pins.

2.2.26 USB PHY pins

See the USB PHY pins.

2.2.27 EC1 pins

See the EC1 pins.

2.2.28 EC2 pins

See the EC2 pins.

2.2.29 GPIO pins

See the GPIO pins.

2.2.30 FlexTimer pins

See the FlexTimer pins.

2.2.31 CAN pins

See the CAN pins.

2.2.32 Power-on-reset configuration pins

See the POR configuration pins.

2.2.33 SPI1 pins

See the SPI1 pins.

2.2.34 SPI2 pins

See the SPI2 pins.

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2.2.35 SPI3 pins

See the SPI3 pins.

2.2.36 IEEE 1588 pins

See the IEEE 1588 pins.

2.2.37 Power and ground pins

See the Power and Ground pins.

2.2.38 No connect pins

See the NC pins.

3 Electrical characteristics
This section describes the DC and AC electrical specifications for the chip. The chip is currently targeted to these specifications,
some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer
design specifications.

3.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.

3.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings

Table 3. Absolute maximum ratings 5

Characteristic Symbol Min Max Value Unit Notes

Core and platform supply voltage VDD -0.3 0.88 V 1

PLL supply voltage (core, AVDD, -0.3 1.98 V -

platform, DDR) AVDD_D1, AVDD_D2

SerDes analog PLL fast and PLL slow AVDD_SD1_PLLF, -0.3 0.99 V -
supply voltage AVDD_SD2_PLLF,
AVDD_SD3_PLLF,
AVDD_SD1_PLLS,
AVDD_SD2_PLLS,
AVDD_SD3_PLLS

SerDes 1 and SerDes 2 core SD_SVDD -0.3 0.99 V -

logic supply

SerDes 3 core logic supply SD3_SVDD -0.3 0.99 V -

SerDes 1 and SerDes 2 SD_OVDD -0.3 1.98 V -

transceiver supply

SerDes 3 transceiver supply SD3_OVDD -0.3 1.98 V -

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Table 3. Absolute maximum ratings 5 (continued)

Characteristic Symbol Min Max Value Unit Notes

SFP fuse programming TA_PROG_SFP -0.3 1.98 V -

Thermal monitor unit supply TH_VDD -0.3 1.98 V -

General I/O supply OVDD -0.3 1.98 V -

eSDHC1 supply (also includes some EVDD -0.3 1.8 V + 90 mV V -

GPIO1 and SPI1 pins)

DDR4 DRAM I/O voltage G1VDD, G2VDD -0.3 1.32 V -

USB PHY 3.3V high supply voltage USB_HVDD -0.3 3.63 V -

USB PHY analog and digital HS supply USB_SDVDD -0.3 0.88 V -

USB PHY analog and digital SS supply USB_SVDD -0.3 0.88 V -

Low power security monitor supply TA_BB_VDD -0.3 0.88 V -

Input voltage for DDR4 DRAM signals MVIN -0.3 GVDD + 0.3 V 2

Input voltage for general I/O signals and OVIN -0.3 OVDD + 0.3 V 3, 4
interfaces powered by OVDD

Input voltage for SerDes signals SVIN -0.4 SD_SVDD + 0.3 V 4

Input voltage for USB PHY 3.3 USB_HVIN -0.3 USB_HVDD + 0.3 V 4
HS signals

Input voltage for USB PHY SS signals USB_SVIN -0.3 USB_SVDD + 0.3 V 4

Input voltage for USBn_ID USB_IDIN -0.3 1.8 V

Input voltage for USBn_VBUS USB_VBUSIN -0.3 3.3 V

Input voltage for eSDHC1, GPIO1, and EVIN -0.3 EVDD + 0.3 V -
SPI1 signals powered by EVDD

Storage temperature range TSTG -55 150 °C 6

1. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. (M, O, S)VIN, and USBn_HVIN may overshoot/undershoot to a voltage and for a maximum duration as shown in the
Overshoot/undershoot voltage figure at the end of this section.

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Table 3. Absolute maximum ratings 5 (continued)

Characteristic Symbol Min Max Value Unit Notes

5. Functional operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional
operations at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
6. Not to exceed 1008 hours cumulative at 150°C.

3.1.2 Recommended Operating Conditions

This table provides the recommended operating conditions for this chip.

WARNING
The values shown are the recommended operating conditions and proper device operation outside these
conditions is not guaranteed.

Table 4. Recommended operating conditions 6

Parameter Symbol Min Typ Max Unit Notes

VID core and platform supply VDD 0.850 - 30 mV 0.850 0.850 + 30 mV V 1, 2, 3

voltage at boot

VID core and platform supply VDD VID - 30 mV VID VID + 30 mV V 1, 2, 3

voltage during normal operation

PLL supply voltage (core, AVDD, AVDD_D1, 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 4

platform, DDR) AVDD_D2

SerDes analog PLL fast and PLL AVDD_SD1_PLLF, 0.9 V - 30 mV 0.9 0.9 V + 50 mV V -
slow supply voltage AVDD_SD2_PLLF,
AVDD_SD3_PLLF,
AVDD_SD1_PLLS,
AVDD_SD2_PLLS,
AVDD_SD3_PLLS

SerDes 1 and SerDes 2 core SD_SVDD 0.9 V - 30 mV 0.9 0.9 V + 50 mV V -

logic supply

SerDes 3 core logic supply SD3_SVDD 0.9 V - 30 mV 0.9 0.9 V + 50 mV V -

SerDes 1 and SerDes 2 SD_OVDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

transceiver supply

SerDes 3 transceiver supply SD3_OVDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

SFP fuse programming TA_PROG_SFP 1.8 V - 90 mV 1.8 1.8 V + 90 mV V 5

Thermal monitor unit supply TH_VDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

General I/O supply OVDD 1.8 V - 90 mV 1.8 1.8 V + 90 mV V -

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Table 4. Recommended operating conditions 6 (continued)

Parameter Symbol Min Typ Max Unit Notes

eSDHC1 supply (also includes EVDD 1.8 V - 90 mV 1.8 V 1.8 V + 90 mV V -

some GPIO1 and SPI1 pins)

DDR4 DRAM I/O voltage G1VDD, G2VDD 1.2V - 60 mV 1.2 1.2 V + 60 mV V -

USB PHY 3.3V high USB_HVDD 3.3 - 165 mV 3.3 3.3 V + 165 mV V -
supply voltage

USB PHY analog and digital USB_SDVDD 0.8 V - 30 mV 0.8 0.8 V + 50 mV V -

HS supply

USB PHY analog and digital USB_SVDD 0.8 V - 30 mV 0.8 0.8 V + 50 mV V -

SS supply

Low power supply monitor when TA_BB_VDD VDD VDD VDD V -

connected to VDD supply

Low power supply monitor when TA_BB_VDD 0.8 V - 30 mV 0.8 0.8+50mV V -

powered by battery

Input voltage for DDR4 MVIN GND to V -

DRAM signals GnVDD

Input voltage for general I/O OVIN - GND to - V -

signals and interfaces powered OVDD
by OVDD

Input voltage for SerDes signals SVIN - -400 mV to - V -

+400 mV

Input voltage for USB PHY 3.3 USB_HVIN - GND to - V -

HS signals USB_HVDD

Input voltage for USB PHY SS USB_SVIN - GND to

signals USB_SVDD

Input voltage for eSDHC1, EVIN - GND to - V -

GPIO1, and SPI1 signals EVDD
powered by EVDD

Normal operating T A/TJ TA = 0 - TJ = 105 °C -

temperature range

Extended temperature range TA/TJ TA = -40 - TJ = 105 °C -

AEC-Q100 Grade 3 TA TA = -40 - TA = 85 °C 7, 8

temperature range

Secure boot fuse programming TA/TJ TA = 0 - TJ = 70 °C 5

operating temperature range

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Electrical characteristics

Table 4. Recommended operating conditions 6 (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
2. Operation at 0.88V is allowable for up to 25 ms at initial power on.
3. Voltage ID (VID) operating range is between 0.775 V to 0.85 V. It is highly recommended to select a PMBus style regulator
with a Vout range of at least 0.7 V to 0.9 V, with resolution of 12.5 mV or better.
4. AVDD, AVDD_D1, and AVDD_D2 are measured at the input to the filter and not at the pin of the device.
5. TA_PROG_SFP must be supplied 1.8V and the chip must operate in the specified fuse programming temperature range only
during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND, subject to the power
sequencing constraints shown in Power Sequencing.
6. See Figure 9.
7. Only available on automotive grade parts.
8. The TJ must not exceed 105°C. Proper thermal solution should be applied to meet this requirement.

See the Recommended operating conditions table for actual recommended core voltage. Voltage to the processor interface I/Os
are provided through separate sets of supply pins and must be provided at the voltages shown in the Recommended operating
conditions table. The input voltage threshold scales with respect to the associated I/O supply voltage. OVDD-based receivers
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential
receivers referenced by the internally generated VREF signal. The DDR DQS receivers cannot be operated in single-ended
fashion. The complement signal must be properly driven and cannot be grounded.
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

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Maximum overshoot

GVDD/OVDD/EVDD/SD_SVDD/USB_*VDD
VIH

GND

VIL

Minimum undershoot
Overshoot/undershoot period

Note:
The overshoot/undershoot period should be less than 10% of shortest possible toggling period of the input signal
or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot period, it should be
less than 10% of the SYSCLK period.

Figure 9. Overshoot/undershoot voltage for GVDD/OVDD/EVDD/SD_SVDD/USB_HVDD/USB_SVDD

3.1.3 Output drive capabilities

This chip provides information on the characteristics of the output driver strengths.

Table 5. Output drive capability 1, 2

Driver Type Minimum 1 Typ Maximum 2 Supply_Vol

tage

General I/O signals 30 45 60 OV DD =

1.8V

1. Minimum values reflect estimated numbers based on best-case processed device.

2. Maximum values reflect estimated numbers based on worst-case processed device.

3.2 General AC timing

This table provides AC timing specifications for the sections not covered under the specific interface sections.

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Table 6. General AC timing specifications

Parameter Symbol Min Max Unit Notes

Input signal rise and fall times tR/tF - 5 ns 1

1. Rise time refers to signal transitions from 10% to 90% of Supply; fall time refers to transitions from 90% to 10% of supply.

3.3 Power sequencing

For power up, the following sequence should be followed:
1. During VDD ramping, PORESET_B must be held low and TA_PROG_SFP must be grounded. All other power supplies
(GnVDD, OVDD, EVDD, USB_HVDD, USB_SVDD, USB_SDVDD, SD_SVDD, SD_OVDD, TA_BB_VDD, TH_VDD, AVDD (cores,
platform, DDR), and AVDD_SDm_PLLn) have no ordering requirement with respect to one another and with respect to
VDD. All supplies must be at their stable values within 400 ms.
2. Negate PORESET_B input as long as the required assertion/hold time has been met per the RESET initialization table.
3. For secure boot fuse programming, use the following steps:
a. After negation of PORESET_B, drive TA_PROG_SFP = 1.80 V after a required minimum delay per Table 7.
b. After fuse programming is completed, it is required to return TA_PROG_SFP = GND before the system is power
cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 7.
See Security fuse processor, for additional details.

NOTE
If using Trust Architecture Security Monitor battery backed features, prior to VDD ramping up to 0.5 V level, ensure
that SD_SVDD is properly ramped and DIFF_SYSCLK_P / DIFF_SYSCLK_N is running. The clock should have a
frequency of 100 MHz.

Warning
No activity other than that required for secure boot fuse programming is permitted while TA_PROG_SFP is driven
to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur
while TA_PROG_SFP = GND.

Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates.

This figure provides the TA_PROG_SFP timing diagram.

Fuse programming

TA_PROG_SFP 10% TA_PROG_SFP 10% TA_PROG_SFP

90% VDD
tTA_ROG_SFP_VDD
VDD

90% OVDD tTA_PROG_SFP_PROG 90% OVDD

PORESET_B
tTA_PROG_SFP_DELAY tTA_PROG_SFP_RST

NOTE: TA_PROG_SFP must be stable at 1.80 V prior to initiating fuse programming.

Figure 10. TA_PROG_SFP timing diagram

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This table provides information on the power-down and power-up sequence parameters for TA_PROG_SFP.

Table 7. TA_PROG_SFP timing 5

Driver type Min Max Unit Notes

tTA_PROG_SFP_DELAY 100 — SYSCLKs 1

tTA_PROG_SFP_PROG 0 — μs 2

tTA_PROG_SFP_VDD 0 — μs 3

tTA_PROG_SFP_RST 0 — μs 4

1. Delay required from the de-assertion of PORESET_B to driving TA_PROG_SFP ramp up. Delay measured from PORESET_B
deassertion at 90% OVDD to 10% TA_PROG_SFP ramp up.
2. Delay required from fuse programming finished to TA_PROG_SFP ramp down start. Fuse programming must complete while
TA_PROG_SFP is stable at 1.80 V. No activity other than that required for secure boot fuse programming is permitted while
TA_PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may
only occur while TA_PROG_SFP = GND. After fuse programming is completed, it is required to return TA_PROG_SFP = GND.
3. Delay required from TA_PROG_SFP ramp down complete to VDD ramp down start. TA_PROG_SFP must be grounded to
minimum 10% TA_PROG_SFP before VDD is at 90% VDD.
4. Delay required from TA_PROG_SFP ramp down complete to PORESET_B assertion. TA_PROG_SFP must be grounded to
minimum 10% TA_PROG_SFP before PORESET_B assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.

Warning
TA_PROG_SFP ramp up slew rate must not exceed 18,000V/s. Ramp down does not have a slew rate constraint.

3.4 Power-down requirements

The power-down cycle must complete such that power supply values are below 0.3 V before a new power-up cycle can be started.
If performing secure boot fuse programming per Power sequencing, it is required that TA_PROG_SFP = GND before the system
is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 7.

NOTE
All input signals, including I/Os that are configured as inputs, driven into the chip need to monotonically increase/
decrease through entire rise/fall durations.

3.5 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum
power-on ramp rate is required to avoid excess in-rush current.
This table provides the power supply ramp rate specifications.

Table 8. Power supply ramp rate

Parameter Min Max Unit Notes

Required ramp rate for all voltage supplies except those noted below — 25 V/ms 1, 2

Table continues on the next page...

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Table 8. Power supply ramp rate (continued)

Parameter Min Max Unit Notes

Required ramp rate for GnVDD and AVDD_Dn supplies — 5 V/ms 1, 2

Required ramp rate for TA_PROG_SFP supply — 18 V/ms 1, 2

Notes:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change
from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range (see Recommended Operating Conditions).

3.6 Power characteristics

This table shows the thermal VDD power at 85°C.

Table 9. Thermal VDD power at 85°C

A72 frequency Coherency Platform DDR data rate Power (W)

(MHz) domain frequency (MHz)
LX2160A LX2120A LX2080A
frequency (MHz)
(MHz)

2.2 GHz 1500 750 3200 26.9 24.4 21.8

2.0 GHz 1400 700 2900 20.4 18.0 15.7

1.8 GHz 1300 650 2600 19.1 17.0 14.8

Notes:
1. Thermal power assumes Dhrystone running with activity factor of 60% (on all cores) and executing DMA on the platform. VDD
must run at VID voltage level.

This table shows the estimated power dissipation on the TA_BB_VDD supply for the LX2160A at allowable voltage levels.

Table 10. TA_BB_VDD power dissipation

Supply Maximum Unit Notes

TA_BB_VDD (LX2xx0A off, 70°C) 36 uW 1

TA_BB_VDD (LX2xx0A off, 40°C) 5 uW 1

Notes:
1. When the device is off, TA_BB_VDD may be supplied by battery power to retain the Zeroizable Master Key and other trust
architecture state. Board should implement a PMIC, which switches TA_BB_VDD to battery when SoC powered down. See the
device reference manual trust architecture chapter for more information.

3.7 Input clocks

3.7.1 USB reference clock specifications

The reference clock of the USB PHY is the DIFF_SYSCLK_P/DIFF_SYSCLK_N. Refer to the Differential system clock
(DIFF_SYSCLK_P/DIFF_SYSCLK_N) timing specifications for the USB AC timing specifications.

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3.7.2 Gigabit Ethernet reference clock timing

This table provides the Ethernet gigabit reference clock DC electrical characteristics with OVDD = 1.8 V.

Table 11. EC_GTX_CLK125 DC electrical characteristics (OVDD = 1.8 V)1

Parameter Symbol Min Typical Max Unit Notes

Input high voltage VIH 0.7 x — — V 2

OVDD

Input low voltage VIL — — 0.3 x V 2

OVDD

Input capacitance CIN — — 6 pF —

Input current (VIN = 0 V or VIN = OVDD) IIN — — ± 50 µA 3

Notes:
1. For recommended operating conditions, see Recommended Operating Conditions.
2. The min VIL and max VIH values are based on the respective min and max VIN values found in Recommended
Operating Conditions.
3. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended Operating Conditions.

This table provides the Ethernet gigabit reference clock AC timing specifications.

Table 12. EC_GTX_CLK125 AC timing specifications 1

Parameter/Condition Symbol Min Typical Max Unit Notes

EC_GTX_CLK125 frequency fG125 125 - 100 ppm 125 125 + 100 MHz —
ppm

EC_GTX_CLK125 cycle time tG125 — 8 — ns —

EC_GTX_CLK125 rise and fall time tG125R/tG125F — — 0.75 ns 2

EC_GTX_CLK125 duty cycle tG125H/tG125 40 — 60 % 3

1000Base-T for RGMII

Notes:
1. At recommended operating conditions with OVDD = 1.8 V ± 90mV. See Recommended Operating Conditions.
2. Rise and fall times for EC_GTX_CLK125 are measured from 0.36 and 1.44 V for OVDD = 1.8 V.
3. See RGMII AC timing specifications for duty cycle for the 10Base-T and 100Base-T reference clocks. The frequency of
ECn_RX_CLK (input) should not exceed the frequency of EC_GTX_CLK125/ECn_TX_CLK (input) by more than 300 ppm.

3.7.3 DDR clock (DDRCLK)

This section provides the DDRCLK DC electrical characteristics and AC timing specifications.

3.7.3.1 DDRCLK DC electrical characteristics

This table provides the DDR clock (DDRCLK) DC electrical characteristics.

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Table 13. DDRCLK DC electrical characteristics3

Parameter Symbol Min Typical Max Unit Notes

Input high voltage VIH 0.7 x OVDD — — V 1

Input low voltage VIL — — 0.3 x OVDD V 1

Input capacitance CIN — 7 12 pF —

Input current (VIN= 0V or VIN = OVDD) IIN — — ± 50 μA 2

Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended
Operating Conditions.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended Operating Conditions.
3. At recommended operating conditions with OVDD = 1.8 V. See Recommended Operating Conditions.

3.7.3.2 DDRCLK AC timing specifications

This table provides the DDR clock (DDRCLK) AC timing specifications.

Table 14. DDRCLK AC timing specifications5

Parameter/Condition Symbol Min Typ Max Unit Notes

DDRCLK frequency fDDRCLK 100 MHz 1, 2

DDRCLK frequency offset FDDRCLK_OFFSET -300.0 — 300.0 ppm

DDRCLK duty cycle tKHK/tDDRCLK 42.5 50 57.5 % 2

DDRCLK slew rate — 1.0 — 10 V/ns 3

DDRCLK peak period jitter — — — ± 150 ps 4

Notes:
1. Caution: The memory controller complex PLL multiplier/ratio (RCW[MEM_PLL_RAT]) must be chosen such that the resulting
DDR data rate does not exceed its respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.25 x OVDD to 0.75 x OVDD.
4. Peak period jitter is calculated according to the JEDEC standard expression 8.22 * RMS jitter.
5. At recommended operating conditions with OVDD = 1.8V. See Recommended Operating Conditions.

3.7.4 Differential system clock (DIFF_SYSCLK_P/DIFF_SYSCLK_N) timing specifications

The differential system clocking mode requires an on-board oscillator to provide reference clock input to the differential system
clock pair (DIFF_SYSCLK_P/DIFF_SYSCLK_N).
This differential clock pair can be configured to provide the clock to core, platform, and USB PLLs.
This figure shows a receiver reference diagram of the differential system clock.

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50 Ω

DIFF_SYSCLK_P

Input
amp

DIFF_SYSCLK_N

50 Ω

Figure 11. DIFF_SYSCLK_P/DIFF_SYSCLK_N receiver

This section provides the differential system clock DC and AC timing specifications.

3.7.4.1 Differential system clock DC electrical characteristics

For DC electrical characteristics, see DC-level requirement for SerDes reference clocks.
The differential system clock receiver's power supply voltage requirements (SD3_SVDD) are specified in Recommended
Operating Conditions.

3.7.4.2 Differential system clock AC timing specifications

This table provides the differential system clock AC timing specificiatons.
For additional AC timing specifications, see SerDes reference clocks AC timing specifications.

Table 15. Differential System Clock AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Reference clock frequency fSYSCLK - 100 - MHz -

Reference clock frequency- FREF_OFFSET -300.0 - 300.0 ppm -

offset

Reference clock random JRMSREF_CLK - - 2.6 ps 1, 2

jitter (RMS)

Reference clock cycle-to- DJREF_CLK - - 150.0 ps 3

cycle jitter

Reference clock duty cycle tKHK/tSYSCLK 40 - 60 % -

1. 1.5 MHz to Nyquist frequency. For example, for 100 MHz reference clock, the Nyquist frequency is 50 MHz.
2. The peak-to-peak Rj specification is calculated at 14.069 times the RJRMS for 10-12 BER.
3. DJ across all frequencies.

3.7.5 Other input clocks

A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block
diagram. For information about the input clock requirements of functional modules sourced external of the chip, see the specific
interface section.

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3.8 Reset initialization timing specifications

This table provides the RESET initialization timing specifications.

Table 16. RESET initialization timing specifications

Parameter Min Max Unit Notes

Required assertion time of PORESET_B after 1.0 - ms 1

SYSCLK/DIFF_SYSCLK and all power rails
are stable

Required input assertion time of HRESET_B 32.0 - SYSCLKs 2, 3

Maximum rise/fall time of HRESET_B - 10.0 SYSCLK 4

Maximum rise/fall time of PORESET_B - 1 SYSCLK 4

Input setup time for POR configs with respect 4.0 - SYSCLKs 2
to negation of PORESET_B

Input hold time for all POR configs with 2.0 - SYSCLKs 2
respect to negation of PORESET_B

Maximum valid-to-high impedance time for - 5.0 SYSCLKs 2

actively driven POR configs with respect to
negation of PORESET_B

1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
2. The DIFF_SYSCLK is the primary clock input for the chip.
3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The
device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequence of HRESET_B deassertion is
documented in the reference manual's "Power-on Reset Sequence" section.
4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

3.9 Battery-backed security monitor and tamper detect

This section describes the DC and AC electrical characteristics for the battery-backed security monitor interface, which includes
the TA_BB_TMP_DETECT_B pin. It also describes the DC electrical characteristics for the TA_TMP_DETECT_B pin.

3.9.1 Battery-backed security monitor and tamper detect DC electrical characteristics

This table provides the DC electrical characteristics for the battery-backed security monitor interface (TA_BB_TMP_DETECT_B)
operating at TA_BB_V DD.

Table 17. Battery-backed security monitor interface DC electrical characteristics (TA_BB_V DD = VID) 1

Parameter Symbol Min Typ Max Unit Notes

Input high voltage V IH 0.75 x V 2, 4

TA_BB_VDD

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Table 17. Battery-backed security monitor interface DC electrical characteristics (TA_BB_V DD = VID) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

Input low voltage V IL - 0.30 x V 2

TA_BB_VDD

Input current (V IN = 0V or V IN = I IN - - 50.0 μA 3

TA_BB_V DD)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max TA_BB_V IN values found in Recommended
Operating Conditions.
3. The symbol TA_BB_V DD represents the recommended operating voltage of the supply referenced in Recommended
Operating Conditions.
4. If the signal falls below VIH, it can cause a false trigger.

This table provides the DC electrical characteristics for the tamper detect security monitor (TA_TMP_DETECT_B) operating
at OVDD.

Table 18. Tamper detect monitor interface DC electrical characteristics (OVDD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Input high voltage V IH 0.7 x OVDD V 2, 4

Input low voltage V IL - 0.3 x OVDD V 2

Input current (VIN = 0V or VIN I IN - - 50.0 μA 3

= OVIN)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the recommended operating voltage of the supply referenced in Recommended
Operating Conditions.
4. If the signal falls below VIH, it can cause a false trigger.

3.9.2 Battery-backed security monitor AC timing specifications

This table provides the AC timing specifications for the battery-backed security monitor interface.

Table 19. Battery-backed security monitor interface AC timing specifications

Parameter Symbol Min Max Unit Notes

TA_BB_TMP_DETECT_B t TMP 100.0 - ns 1

1. TA_BB_TMP_DETECT_B is asynchronous to any clock.

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3.10 DDR4 SDRAM controller

This section describes the DC and AC electrical specifications for the DDR4 SDRAM controller interface. Note that the required
GVDD(typ) voltage is 1.2 V when interfacing to DDR4 SDRAM.

NOTE
When operating at a DDR data rate of 2600 MT/s or higher, only one dual-ranked module per memory controller
is supported.

3.10.1 DDR4 SDRAM controller DC electrical characteristics

This table provides the recommended opearting conditions for the DDR SDRAM controller when interfacing to DDR4 SDRAM.

Table 20. DDR4 SDRAM interface DC electrical characteristics (GV DD = 1.2V) 1, 6, 7

Parameter Symbol Min Max Unit Notes

Input high voltage V IH VREF + 0.085 — V 2, 3

Input low voltage V IL — VREF - 0.085 V 2, 3

I/O leakage current IIN/I OZ -50 50 μA 4, 5

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
3. Internal VREF is trained.
4. Refer to IBIS model for the complete output IV curve characteristics.
5. Output leakage is measured with all outputs diabled, 0 V ≤ V OUT ≤ GV DD. Applies to each pin.
6. GV DD is expected to be within 60 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's voltage
supply may or may not be from the same source. GV DD min = 1.14 V, GV DD max = 1.26 V, and GV DD typ = 1.2 V.
7. VTT and VREFCA are applied directly to the DRAM device. Both VTT and VREFCA voltages must track GV DD/2.

3.10.2 DDR4 SDRAM controller AC timing specifications

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM.

Table 21. DDR4 SDRAM interface input AC timing specifications

Parameter Symbol Min Max Unit Notes

AC input low voltage V ILAC - VREF - 0.085 V Internal VREF is

trained.

AC input high voltage V IHAC VREF + 0.085 - V Internal VREF is

trained.

This table provides the input AC timing specifications for the DDR controller when interfacing to DDR4 SDRAM.

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Table 22. DDR4 SDRAM interface input AC timing specifications 3

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS-MDQ/MECC t CISKEW - - ps -

Data Rate of 1300 MT/s in DDR4 -125.0 125.0 1

Data Rate of 1600 MT/s in DDR4 -112.0 112.0 1

Data Rate of 1800 MT/s in DDR4 -93.0 93.0 1

Data Rate of 2100 MT/s in DDR4 -82.0 82.0 1

Data Rate of 2400 MT/s in DDR4 -78.0 78.0 1

Data Rate of 2600 MT/s in DDR4 -74.0 74.0 1

Data Rate of 2900 MT/s in DDR4 -69.0 69.0 1

Data Rate of 3200 MT/s in DDR4 -65.0 65.0 1

Tolerated Skew for MDQS-MDQ/MECC t DISKEW - - ps -

Data Rate of 1300 MT/s in DDR4 -250.0 250.0 2

Data Rate of 1600 MT/s in DDR4 -200.0 200.0 2

Data Rate of 1800 MT/s in DDR4 -175.0 175.0 2

Data Rate of 2100 MT/s in DDR4 -152.0 152.0 2

Data Rate of 2400 MT/s in DDR4 -130.0 130.0 2

Data Rate of 2600 MT/s in DDR4 -114.0 114.0 2

Data Rate of 2900 MT/s in DDR4 -102.0 102.0 2

Data Rate of 3200 MT/s in DDR4 -92.0 92.0 2, 3

1. t CISKEW represents the amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be
captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t DISKEW. This can be
determined by the following equation: t DISKEW = +/-(T / 4 - abs(t CISKEW)), where T is the clock period and abs(t CISKEW) is the
absolute value of t CISKEW.
3. See Figure 12.

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MCK[n]_B
MCK[n]
tMCK

MDQS[n]

tDISKEW

MDQ[x] D0 D1

tDISKEW
tDISKEW

Figure 12. DDR4 SDRAM interface input timing diagram

This table contains the output AC timing targets for the DDR4 SDRAM interface.

Table 23. DDR4 SDRAM interface output AC timing specifications 6

Parameter Symbol Min Max Unit Notes

MCK[n] cycle time t MCK 625.0 1500.0 ps 1

ADDR/CMD/CNTL output setup with t DDKHAS - - ps -

respect to MCK

Data Rate of 1300 MT/s in DDR4 606.0 - 3, 4

Data Rate of 1600 MT/s in DDR4 495.0 - 3, 4

Data Rate of 1800 MT/s in DDR4 410.0 - 3, 4

Data Rate of 2100 MT/s in DDR4 350.0 - 3, 4

Data Rate of 2400 MT/s in DDR4 321.0 - 3, 4

Data Rate of 2600 MT/s in DDR4 289.0 - 3, 4

Data Rate of 2900 MT/s in DDR4 263.0 - 3, 4

Data Rate of 3200 MT/s in DDR4 210.0 - 3, 4

ADDR/CMD/CNTL output hold with t DDKHAX - - ps -

respect to MCK

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Table 23. DDR4 SDRAM interface output AC timing specifications 6 (continued)

Parameter Symbol Min Max Unit Notes

Data Rate of 1300 MT/s in DDR4 606.0 - 3, 4

Data Rate of 1600 MT/s in DDR4 495.0 - 3, 4

Data Rate of 1800 MT/s in DDR4 390.0 - 3, 4

Data Rate of 2100 MT/s in DDR4 350.0 - 3, 4

Data Rate of 2400 MT/s in DDR4 321.0 - 3, 4

Data Rate of 2600 MT/s in DDR4 289.0 - 3, 4

Data Rate of 2900 MT/s in DDR4 263.0 - 3, 4

Data Rate of 3200 MT/s in DDR4 210.0 - 3, 4

MDQ/MECC/MDM output data eye t DDKXDEYE - - ps -

Data Rate of 1300 MT/s in DDR4 500.0 - 4, 5

Data Rate of 1600 MT/s in DDR4 400.0 - 4, 5

Data Rate of 1800 MT/s in DDR4 350.0 - 4, 5

Data Rate of 2100 MT/s in DDR4 320.0 - 4, 5

Data Rate of 2400 MT/s in DDR4 280.0 - 4, 5

Data Rate of 2600 MT/s in DDR4 250.0 - 4, 5

Data Rate of 2900 MT/s in DDR4 225.0 - 4, 5

Data Rate of 3200 MT/s in DDR4 205.0 - 4, 5

MDQS preamble t DDKHMP 0.9 * t MCK - ps 4

MDQS postamble t DDKHME 0.4 * t MCK 0.6 * t MCK ps 4

1. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
2. See Figure 12.
3. ADDR/CMD/CNTL includes all DDR SDRAM output signals except MCK/MCK_B, and MDQ/MECC/MDM/MDQS/MDQS_B.
4. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs
and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from
the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
setup (S) or output valid time.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.

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Table 23. DDR4 SDRAM interface output AC timing specifications 6 (continued)

Parameter Symbol Min Max Unit Notes

6. See Figure 13.

MCK_B

MCK
tMCK

tDDKHAS

tDDKHAX

ADDR/CMD Write A0 NOOP

tDDKHMP

MDQS[n]

tDDKHDS tDDKHME
tDDKLDS

MDQ[x] D0 D1

tDDKLDX
tDDKHDX

Figure 13. DDR4 SDRAM interface output timing diagram

3.11 Universal asynchronous receiver/transmitter (UART)

3.11.1 UART DC electrical characteristics

This table provides the DC electrical characteristics for the UART interface.

Table 24. UART DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (V IN = 0V or V IN = OV DD) I IN - ±50 μA 3

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Table 24. UART DC electrical characteristics (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

Output high voltage (I OH = -0.5 mA) V OH 1.35 - V -

Output low voltage (I OL = 0.5 mA) V OL - 0.45 V -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.11.2 UART AC timing specifications

This table provides the AC timing specifications for the UART interface.

Table 25. UART AC timing specifications

Parameter Symbol Min Max Unit Notes

Baud rate baud 300.0 921600.0 bits/se 1, 2

c

1. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
2. The actual attainable baud rate is limited by the latency of interrupt processing.

3.12 Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.

3.12.1 eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 26. eSDHC DC electrical characteristics (EVDD/OVDD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x EVDD/OVDD - V 2

Input low voltage VIL - 0.3 x EVDD/OVDD V 2

Input/output leakage current IIN/IOZ - -250/+50 μA -

Output high voltage (IOH = -2mA at EVDD/ VOH EVDD/OVDD - 0.45 - V -

OVDD min)

Output low voltage (IOL = 2mA at EVDD/ VOL - 0.45 V -

OVDD min)

1. For recommended operating conditions, see Recommended Operating Conditions.

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Table 26. eSDHC DC electrical characteristics (EVDD/OVDD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

2. The min VIL and max VIH values are based on the respective min and max EVIN/OVIN values found in Recommended
Operating Conditions.

3.12.2 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in the eSDHC clock input timing diagram.

Table 27. eSDHC AC timing specifications (full-speed mode) 1, 3, 5

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency SD/SDIO f SHSCK 0.0 25.0 MHz 1, 2, 3

SDHC_CLK frequency eMMC f SHSCK 0.0 26.0 MHz 1, 2, 3

SDHC_CLK clock low time t SHSCKL 10.0 - ns 3

SDHC_CLK clock high time t SHSCKH 10.0 - ns 3

SDHC_CLK clock rise and fall times t SHSCKR/t - 3.0 ns 3

SHSCKF

Input setup times (SDHC_CMD, t SHSIVKH 2.5 - ns 3, 4

SDHC_DATx to SDHC_CLK)

Input hold times (SDHC_CMD, t SHSIXKH 2.5 - ns 3

SDHC_DATx to SDHC_CLK)

Output hold time (SDHC_CLK to t SHSKHOX -3.0 - ns 3

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to t SHSKHOV - 3.0 ns 3

SDHC_CMD, SDHC_DATx valid)

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. In full-speed mode, the clock frequency value can be 0-25MHz for an SD/SDIO card and 0-26MHz for an MMC card.
3. C CARD ≤ 10 pF, (1 card), and C L = C BUS + C HOST + C CARD ≤ 40 pF.
4. SDHC_SYNC_OUT/IN loop back is recommended to compensate the clock delay. In case the SDHC_SYNC_OUT/IN
loopback is not used, to satisfy setup timing, one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD,
and SDHC_DATx should not exceed 1ns for any high-speed MMC card. For any high-speed or default speed mode SD card, the
one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns.
5. See Figure 19.

This table provides the eSDHC AC timing specifications as defined in the eSDHC clock input timing diagram.

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Table 28. eSDHC AC timing specifications (high-speed mode) 1, 3, 5, 6, 7

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency SD/SDIO f SHSCK 0.0 50.0 MHz 1, 2, 3

SDHC_CLK frequency eMMC f SHSCK 0.0 52.0 MHz 1, 2, 3

SDHC_CLK clock low time t SHSCKL 7.0 - ns 3

SDHC_CLK clock high time t SHSCKH 7.0 - ns 3

SDHC_CLK clock rise and fall times t SHSCKR/t - 3.0 ns 3

SHSCKF

Input setup times (SDHC_CMD, t SHSIVKH 2.5 - ns 3, 4

SDHC_DATx to SDHC_CLK)

Input hold times (SDHC_CMD, t SHSIXKH 2.5 - ns 3

SDHC_DATx to SDHC_CLK)

Output hold time (SDHC_CLK to t SHSKHOX -3.0 - ns 3

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to t SHSKHOV - 3.0 ns 3

SDHC_CMD, SDHC_DATx valid)

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. In high-speed mode, the clock frequency value can be 0-50MHz for an SD/SDIO card and 0-52MHz for an MMC card.
3. C CARD ≤ 10 pF, (1 card), and C L = C BUS + C HOST + C CARD ≤ 40 pF.
4. SDHC_SYNC_OUT/IN loop back is recommended to compensate the clock delay. In case the SDHC_SYNC_OUT/IN
loopback is not used, to satisfy setup timing, one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD,
and SDHC_DATx should not exceed 1ns for any high-speed MMC card. For any high-speed or default speed mode SD card, the
one-way board-routing delay between host and card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed 1.5ns.
5. See Figure 19.
6. See Figure 14.
7. See Figure 15.

This figure provides the input AC timing diagram for high-speed mode.

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NXP Semiconductors
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VM VM VM VM

SDHC_CLK
t SHSIVKH t SHSIXKH

SDHC_DAT/SDHC_CMD
inputs

VM = Midpoint Voltage (Respective supply / 2)

Figure 14. eSDHC high-speed mode input AC timing diagram

This figure provides the output AC timing diagram for high-speed mode.

VM VM VM VM

SDHC_CLK

SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
outputs

t SHSKHOV tSHSKHOX

VM = Midpoint Voltage (Respective supply / 2)

Figure 15. eSDHC high-speed mode output AC timing diagram

This table provides the eSDHC AC timing specifications for SDR50 mode on devices with a voltage translator.

Table 29. eSDHC AC timing specifications (SDR50 mode with voltage translator) 2, 3, 4

Parameter Symbol Min Max Unit Notes

SDHC_CLK clock frequency f SHSCK 0.0 100.0 MHz -

SDHC_CLK rise and fall times t SHSCKR/t - 2.0 ns 1

SHSCKF

Table continues on the next page...

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NXP Semiconductors
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Table 29. eSDHC AC timing specifications (SDR50 mode with voltage translator) 2, 3, 4 (continued)

Parameter Symbol Min Max Unit Notes

SDHC_CLK duty cycle t SHSCK 47.0 53.0 % -

Input setup times (SDHC_CMD, t SHSIVKH 1.9 - ns 1, 5, 6

SDHC_DATx to SDHC_CLK_SYNC_IN)

Input hold times (SDHC_CMD, t SHSIXKH 0.7 - ns 1, 5, 6

SDHC_DATx to SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to t SHSKHOX 1.6 - ns 1, 5, 6

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to t SHSKHOV - 5.7 ns 1, 5, 6

SDHC_CMD, SDHC_DATx valid)

1. C CARD ≤ 10 pF, (1 card), and CL = C BUS + C HOST + C CARD ≤ 30 pF.

2. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. See Figure 20.
4. See Figure 21.
5. Voltage translator with board skew: -0.8 ns to 0.8 ns
6. The voltage translator parameters are based on:
• Channel-to-channel skew is min -0.5 ns, max +0.5 ns.
• CLK_Feedback to DAT/CMD delay is min -0.5 ns, max +0.5 ns.

This table provides the SDHC1 and SDHC2 AC timing specifications for DDR50 and DDR (3.3V) mode with voltage translator.

Table 30. SDHC1 and SDHC2 AC timing specifications (DDR50 and DDR (3.3V) mode with voltage translator) 3, 4, 5, 6

Parameter Symbol Min Max Unit Notes

SDHC_CLK duty cycle t SHSCK 47.0 53.0 % -

SDHC_CLK frequency f SHCK - - MHz -

SD/SDIO DDR50 mode - 50.0 1

eMMC DDR mode - 50.0 2

SDHC_CLK rise and fall times t SHCKR/t - - ns -

SHCKF
SD/SDIO DDR50 mode - 4.0 1

eMMC DDR mode - 2.0 2

Table continues on the next page...

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Table 30. SDHC1 and SDHC2 AC timing specifications (DDR50 and DDR (3.3V) mode with voltage translator) 3, 4, 5, 6
(continued)

Parameter Symbol Min Max Unit Notes

Input setup times (SDHC_DATx t SHDIVKH - - ns -

to SDHC_CLK_SYNC_IN)

SD/SDIO DDR50 mode 1.6 - 1, 7, 9

eMMC DDR mode 1.6 - 2, 7, 9

Input hold times (SDHC_DATx t SHDIXKH 0.7 - ns 1, 7, 9

to SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to t SHDKHOX - - ns -

SDHC_DATx valid)

SD/SDIO DDR50 mode 2.2 - 1, 7, 9

eMMC DDR mode 3.9 - 2, 7, 9

Output delay time (SDHC_CLK to t SHDKHOV - - ns -

SDHC_DATx valid)

SD/SDIO DDR50 mode - 5.6 1, 7, 9

eMMC DDR mode - 6.1 2, 7, 9

Input setup time (SDHC_CMD t SHCIVKH - - ns -

to SDHC_CLK_SYNC_IN)

SD/SDIO DDR50 mode 4.8 - 1, 8, 9

eMMC DDR mode 4.5 - 2, 8, 9

Input hold time (SDHC_CMD t SHCIXKH 0.7 - ns 1, 7, 9

to SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to t SHCKHOX - - ns -

SDHC_CMD valid)

SD/SDIO DDR50 mode 2.2 - 1, 7, 9

eMMC DDR mode 4.4 - 2, 7, 9

Output delay time (SDHC_CLK to t SHCKHOV - - ns -

SDHC_CMD valid)

SD/SDIO DDR50 mode - 12.6 1, 7, 9

eMMC DDR mode - 15.3 2, 7, 9

1. C CARD ≤ 10pF, (1 card).

Table continues on the next page...

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Table 30. SDHC1 and SDHC2 AC timing specifications (DDR50 and DDR (3.3V) mode with voltage translator) 3, 4, 5, 6
(continued)

Parameter Symbol Min Max Unit Notes

2. C L = C BUS + C HOST + C CARD ≤ 20 pF for MMC, ≤ 25pF for Input Data of DDR50, ≤ 30pF for Input CMD of DDR50.
3. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
4. See Figure 22.
5. See Figure 23.
6. Assumes no skew between CLK to and CLK_SYNC_OUT
7. Voltage translator with board skew: -0.8 ns to 0.8 ns.
8. Voltage translator with board skew: -0.8 ns to 0.9 ns.
9. The voltage translator parameters are based on:
• Channel-to-channel skew is min -0.5 ns, max +0.5 ns.
• CLK_Feedback to DAT/CMD delay is min -0.5 ns, max +0.5 ns.

This table provides the SDHC1 and SDHC2 AC timing specifications for the DDR (1.8V) mode without voltage translator.

Table 31. SDHC1 and SDHC2 AC timing specifications (DDR (1.8V) mode without voltage translator) 1, 2, 3, 4

Parameter Symbol Min Max Unit Notes

SDHC_CLK duty cycle t SHSCK 47.0 53.0 % -

SDHC_CLK frequency f SHCK 50.0 MHz

SDHC_CLK rise and fall times t SHCKR/t 2.0 ns

SHCKF

Skew between t SHSKEW

SDHC_CLK_SYNC_OUT and
SDHC_CLK

SDHC1 -0.6 0.1 ns

SDHC2 -0.2 0.2 ns

Input setup times (SDHC_DATx t SHDIVKH 1.6 ns 5

to SDHC_CLK_SYNC_IN)

Input hold times (SDHC_DATx t SHDIXKH 0.7 ns 5

to SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to t SHDKHOX 3.4 ns 5

SDHC_DATx valid)

Output delay time (SDHC_CLK to t SHDKHOV 6.1 ns 5

SDHC_DATx valid)

Table continues on the next page...

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NXP Semiconductors
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Table 31. SDHC1 and SDHC2 AC timing specifications (DDR (1.8V) mode without voltage translator) 1, 2, 3, 4 (continued)

Parameter Symbol Min Max Unit Notes

Input setup time (SDHC_CMD t SHCIVKH 4.5 ns 5

to SDHC_CLK_SYNC_IN)

Input hold time (SDHC_CMD to t SHCIXKH 0.7 ns 5

SDHC_CLK_SYNC_IN)

Output hold time (SDHC_CLK to t SHCKHOX 3.9 ns 5

SDHC_CMD valid)

Output delay time (SDHC_CLK to t SHCKHOV 15.3 ns 5

SDHC_CMD valid)

1. C L = C BUS + C HOST + C CARD ≤ 20 pF for MMC, ≤ 25pF for Input Data of DDR50, ≤ 30pF for Input CMD of DDR50.
2. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. See Figure 22.
4. See Figure 23.
5. Board skew: -0.2 to 0.2 ns

This table provides the eSDHC AC timing specifications for SDR104/eMMC HS200 mode.

Table 32. eSDHC AC timing specifications (SDR104/HS200 mode) 2, 3

Parameter Symbol Min Max Unit Notes

SDHC_CLK duty cycle t SHSCK 47.0 53.0 % -

SDHC_CLK frequency f SHCK - - MHz -

SD/SDIO SDR104 mode - 208.0 -

eMMC HS200 mode - 200.0 -

SDHC_CLK rise and fall times t SHCKR/t - 1.0 ns 1

SHCKF

Output hold time (SDHC_CLK to T SHKHOX - - ns -

SDHC_CMD, SDHC_DATx valid)

SD/SDIO SDR104 mode 1.58 - 1

eMMC HS200 mode 1.6 - 1

Output delay time (SDHC_CLK to T SHKHOV - - ns -

SDHC_CMD, SDHC_DATx valid)

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 32. eSDHC AC timing specifications (SDR104/HS200 mode) 2, 3 (continued)

Parameter Symbol Min Max Unit Notes

SD/SDIO SDR104 mode - 2.9 1

eMMC HS200 mode - 2.95 1

Input data window (UI) t SHIDV - - Unit -

interva
SD/SDIO SDR104 mode 0.5 - l 1

eMMC HS200 mode 0.475 - 1

1. C L = C BUS + C HOST + C CARD ≤ 15pF.

2. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. See Figure 16.

This figure provides the eSDHC SDR104/HS200 mode timing diagram.

T
SHCK

SDHC_CLK

T
SHIDV

SDHC_CMD/
DATA
SDHC_DAT input

T
SHKHOV

SDHC_CMD/SDHC_CMD_DIR
DATA DATA
SDHC_DAT/SDHC_DATn_DIR
output

T
SHKHOX

Figure 16. eSDHC SDR104/HS200 mode timing diagram

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NXP Semiconductors
Electrical characteristics

This table provides the eSDHC AC timing specifications for eMMC HS400 mode.

Table 33. eSDHC AC timing specifications (HS400 mode) 2, 3, 4, 5

Parameter Symbol Min Max Unit Notes

SDHC_CLK frequency f SHCK - 200.0 MHz -

Output hold time (SDHC_CLK to T SHKHOX 0.75 - ns 1

SDHC_CMD, SDHC_DATx valid)

Output delay time (SDHC_CLK to T SHKHOV - 1.75 ns 1

SDHC_CMD, SDHC_DATx valid)

Data valid skew to DQS T SHRQV - 0.45 ns 1

Data hold skew to DQS T SHRQHX - 0.45 ns 1

Command valid skew to DQS T - 0.45 ns 1

SHRQV_CMD

Command hold skew to DQS T - 0.45 ns 1

SHRQHX_CM
D

DQS pulse width T SHDSPWS 1.97 - ns 1

Duty cycle distortion t SHSCK_DIS 0.0 0.3 ns 1

1. C L = C BUS + C HOST + C CARD ≤ 15pF.

2. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t SHKHOX symbolizes eSDHC highspeed
mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state
(X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a
particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. See Figure 17.
4. See Figure 18.
5. For HS400 without enhanced strobe (DQS) command, see Figure 16.

This figure provides the eSDHC HS400 mode input timing diagram.

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NXP Semiconductors
Electrical characteristics

Data Strobe
tSHDSPW tSHDSPW
VT

TSHRQV
TSHRQHX TSHRQV TSHRQHX

VIH
DAT[7:0]
Input
VIL

TSHRQV_CMD TSHRQHX_CMD

VIH
CMD
Input
VIL

Figure 17. eSDHC HS400 mode input timing diagram

This figure provides the eSDHC HS400 mode output timing diagram.

Tclk

SDHC_CLK

SDHC_DAT/SDHC_DATn_DIR TSHKHOV TSHKHOV

output

TSHKHOX TSHKHOX

Figure 18. eSDHC HS400 mode output timing diagram

This figure provides the eSDHC clock input timing diagram.

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NXP Semiconductors
Electrical characteristics

eSDHC
external clock
operational mode VM VM VM

tSHSCKL tSHSCKH
tSHSCK

tSHSCKR tSHSCKF
VM = Midpoint voltage (Respective supply / 2)

Figure 19. eSDHC clock input timing diagram

This figure provides the eSDHC input AC timing diagram for SDR50 mode.

T CLK

SDHC_CLK_SYNC_IN

TSHSIVKH TSHSIXKH

SDHC_CMD/
SDHC_DAT
input

Figure 20. eSDHC SDR50 mode input AC timing diagram

This figure provides the eSDHC output timing diagram for SDR50 mode.

T
CLK

SD_CLK

T
SHSKHOV

SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output

T
SHSKHOX

Figure 21. eSDHC SDR50 mode output timing diagram

This figure provides the eSDHC DDR50/DDR mode input AC timing diagram.

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NXP Semiconductors
Electrical characteristics

T SHCK

SDHC_CLK_SYNC_IN

T T
SHDIVKH SHDIXKH

SDHC_DAT
input

T T
SHCIVKH SHCIXKH

SDHC_CMD
input

Figure 22. eSDHC DDR50/DDR mode input AC timing diagram

This figure provides the eSDHC DDR50/DDR mode output AC timing diagram.

T SHCK

SDHC_CLK

T
SHDKHOV

SDHC_DAT/
SDHC_DATn_DIR
output

T
SHDKHOX
T
SHCKHOV

SDHC_CMD/
SD_CMD_DIR
output

T
SHCKHOX

Figure 23. eSDHC DDR50/DDR mode output AC timing diagram

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NXP Semiconductors
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3.13 Ethernet interface (EMI, RGMII, and IEEE Std 1588™)

This section describes the DC and AC electrical characteristics for the EMI, RGMII, and IEEE Std 1588 interfaces.

3.13.1 Ethernet management interface (EMI)

This section describes the electrical characteristics for the Ethernet management interface (EMI) interface.
™
The EMI1 and EMI2 interface timings are compatible with IEEE Std 802.3 clauses 22 and 45, respectively.

3.13.1.1 EMI DC electrical characteristics

This table provides the EMI DC electrical characteristics.

Table 34. EMI DC electrical characteristics (OVDD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN = 0 or VIN = OVIN) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V -

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended
Operating Conditions.
3. The symbol OVIN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.13.1.2 EMI AC timing specifications

This table provides the EMI AC timing specifications.

Table 35. EMI AC timing specifications 4, 5, 6

Parameter Symbol Min Max Unit Notes

MDC frequency f MDC - 5.0 MHz 1

MDC clock pulse width high t MDCH 80.0 - ns -

MDC to MDIO delay t MDKHDX Y x t enet_clk - 3 Y x t enet_clk + 3 ns 2, 3

MDIO to MDC setup time t MDDVKH 8.0 - ns -

MDIO to MDC hold time t MDDXKH 0.0 - ns -

1. This parameter is dependent on the Ethernet clock frequency. The MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock EC_MDC.

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 35. EMI AC timing specifications 4, 5, 6 (continued)

Parameter Symbol Min Max Unit Notes

2. t enet_clk is the Ethernet clock period x 2.

3. MDIO timing is configurable by programming the EMDIO_CFG register fields. The default value of Y = 5. Y is the value
determined by EMDIO_CFG[NEG], EMDIO_CFG[MDIO_HOLD], and MDIO[EHOLD]. The easiest way is to program NEG=1,
then MDIO is driven at negative edge of MDC, satisfying both setup and hold time requirement of Ethernet PHY.
4. The symbols used for timing specifications follow these patterns: t (first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t MDKHDX symbolizes management data timing
(MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, t MDDVKH
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the
tMDC clock reference (K) going to the high (H) state or setup time.
5. Assumes a maximum load of 338 pF.
6. See Figure 24.

This figure shows the Ethernet management interface timing diagram.

tMDC

MDC

tMDCH

MDIO
(Input)

tMDDVKH

tMDDXKH

MDIO
(Output)

tMDKHDX

Figure 24. Ethernet management interface timing diagram

3.13.2 Reduced media-independent interface (RGMII)

3.13.2.1 RGMII DC electrical characteristics

This table provides the DC electrical characteristics for the RGMII interface.

Table 36. RGMII DC electrical characteristics (OVDD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

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Electrical characteristics

Table 36. RGMII DC electrical characteristics (OVDD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

Input low voltage VIL - 0.3 x OVDD V 2

Input current (VIN=0 or VIN = OVIN) IIN - ±50 μA 3

Output high voltage (OVDD = min, IOH = VOH 1.35 - V 3

-0.5 mA)

Output low voltage (OVDD = min, IOL = VOL - 0.4 V 3

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended
Operating Conditions.
3. The symbol OVDD represents the recommended operating voltage of the supply referenced in Recommended
Operating Conditions.

3.13.2.2 RGMII AC timing specifications

This table provides the RGMII AC timing specifications.

Table 37. RGMII AC timing specifications 7, 8

Parameter Symbol Min Typ Max Unit Notes

Data to clock output skew t -500.0 0.0 500.0 ps 1

(at transmitter) SKRGT_TX

Data to clock input skew t 1.0 - 2.6 ns 2

(at receiver) SKRGT_RX

Clock period duration t RGT 7.2 8.0 8.8 ns 3

Duty cycle for 10BASE-T t RGTH/t 40.0 50.0 60.0 % 3, 4

and 100BASE-TX RGT

Duty cycle for Gigabit t RGTH/t 45.0 50.0 55.0 % -

RGT

Rise time (20%-80%) OV DD t RGTR - - 0.75 ns 5, 6

= 1.8V

Fall time (20%-80%) OV DD = 1.8V t RGTF - - 0.75 ns 5, 6

1. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300 ppm.
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,
additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, t RGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

Table continues on the next page...

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NXP Semiconductors
Electrical characteristics

Table 37. RGMII AC timing specifications 7, 8 (continued)

Parameter Symbol Min Typ Max Unit Notes

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains
as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Applies to inputs and outputs.
6. The system/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
7. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing.
Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing
skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
8. See Figure 25.

NOTE: NXP guarantees timings generated from the MAC. Board designers must ensure delays needed at the PHY or the MAC.
This figure shows the RGMII AC timing and multiplexing diagrams.

tRGT
tRGTH
GTX_CLK
(At MAC, output)
tS KRGT_TX tS KRGT_TX
TXD[8:5][3:0] TXD[8:5]
TXD[3:0] TXD[7:4]
TXD[7:4][3:0]
(At MAC, output)

TX_CTL TXD[4] TXD[9]

(At MAC, output) TXEN TXERR
P HY e quiva le nt to tS KRGT_RX P HY e quiva le nt to tS KRGT_RX

TX_CLK
(At P HY, input)

tRGT
tRGTH
RX_CLK
(At P HY, output)

RXD[8:5][3:0] RXD[8:5]
RXD[7:4][3:0] RXD[3:0] RXD[7:4]
(At P HY, output) P HY e quiva le nt to tS KRGT_TX P HY e quiva le nt to tS KRGT_TX

RX_CTL RXD[4] RXD[9]

RXDV RXERR
(At P HY, output)
tS KRGT_RX tS KRGT_RX
RX_CLK
(At MAC, input)

Figure 25. RGMII AC timing and multiplexing diagrams

3.13.3 IEEE 1588

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3.13.3.1 IEEE 1588 DC electrical characteristics

This table provides the IEEE 1588 DC electrical characteristics.

Table 38. IEEE 1588 DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (V IN = 0 or V IN = OV DD) I IN - ±50 μA 3

Output high voltage (OV DD = min, I OH = V OH 1.35 - V -

-0.5 mA)

Output low voltage (OV DD = min, I OL = V OL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.13.3.2 IEEE 1588 AC timing specifications

This table provides the AC timing specifications for the IEEE 1588 interface.

Table 39. IEEE 1588 AC timing specifications 2, 3

Parameter Symbol Min Typ Max Unit Notes

TSEC_1588_CLK_IN clock period t 1588CLK 6.0 - ns -

TSEC_1588_CLK_IN duty cycle t 40.0 50.0 60.0 % -

T1588CLKH
/t T1588CLK

TSEC_1588_CLK_IN peak-to- t - - 250.0 ps -

peak jitter T1588CLKI
NJ

Rise time TSEC_1588_CLK_IN t 1.0 - 2.0 ns -

(20% to 80%) T1588CLKI
NR

Fall time TSEC_1588_CLK_IN t 1.0 - 2.0 ns -

(80% to 20%) T1588CLKI
NF

TSEC_1588_CLK_OUT t 2 x t 1588CLK - - ns -
clock period T1588CLKO
UT

Table continues on the next page...

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Table 39. IEEE 1588 AC timing specifications 2, 3 (continued)

Parameter Symbol Min Typ Max Unit Notes

TSEC_1588_CLK_OUT t 30.0 50.0 70.0 % -

duty cycle T1588CLKO
TH/t
T1588CLKO
UT

TSEC_1588_PULSE_OUT1/2, t T1588OV 0.5 - 4.0 ns -

TSEC_1588_ALARM_OUT1/2

TSEC_1588_TRIG_IN1/2 t 2 x t 1588CLK - - ns 1
pulse width T1588TRIG
H

1. This needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
2. See Figure 26.
3. See Figure 27.

This figure shows the data and command output AC timing diagram.

tT1588CLKOUT
tT1588CLKOUTH

TSEC_1588_CLK_OUT

tT1588OV

TSEC_1588_PULSE_OUT1/2
TSEC_1588_ALARM_OUT1/2

Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.
Otherwise, it is counted starting at the falling edge.

Figure 26. IEEE 1588 output AC timing

This figure shows the data and command input AC timing diagram.

tT1588CLK

TSEC_1588_CLK_IN tT1588CLKH

TSEC_1588_TRIG_IN1/2

tT1588TRIGH

Figure 27. IEEE 1588 input AC timing

3.14 General purpose input/output (GPIO)

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3.14.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for the GPIO interface.

Table 40. GPIO DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (V IN = 0V or V IN= OV DD) I IN - ±50 μA 3

Output high voltage (OV DD = min, I OH = V OH 1.35 - V -

-0.5 mA)

Output low voltage (OV DD = min, I OL = V OL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.14.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.

Table 41. GPIO AC timing specifications 2

Parameter Symbol Min Max Unit Notes

GPIO inputs-minimum pulse width t PIWID 20.0 - ns 1

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs must be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least t PIWID ns to ensure proper operation.
2. See Figure 28.

The figure below provides the AC test load for the GPIO.

Output Z0= 50 Ω Respective

supply / 2
RL = 50 Ω

Figure 28. GPIO AC test load

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3.15 Flextimer interface

3.15.1 Flextimer DC electrical characteristics

This table provides the DC electrical characteristics for the Flextimer interface.

Table 42. Flextimer DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (V IN = 0V or V IN= OV DD) I IN - ±50 μA 3

Output high voltage (OV DD = min, I OH = V OH 1.35 - V -

-0.5 mA)

Output low voltage (OV DD = min, I OL = V OL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.15.2 Flextimer AC timing specifications

This table provides the Flextimer input and output AC timing specifications.

Table 43. Flextimer AC timing specifications 2

Parameter Symbol Min Max Unit Notes

Flextimer inputs-minimum pulse width t PIWID 20.0 - ns 1

1. Flextimer inputs and outputs are asynchronous to any visible clock. Flextimer outputs must be synchronized before use by
any external synchronous logic. Flextimer inputs are required to be valid for at least t PIWID ns to ensure proper operation.
2. See Figure 29.

The figure below provides the AC test load for the Flextimer.

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Output Z0= 50 Ω Respective

supply / 2
RL = 50 Ω

Figure 29. Flextimer AC test load

3.16 Generic interrupt controller (GIC)

3.16.1 GIC DC electrical characteristics

This table provides the DC electrical characteristics for the GIC interface.

Table 44. GIC DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (V IN = 0V or V IN= OV DD) I IN - ±50 μA 3

Output high voltage (OV DD = min, I OH = V OH 1.35 - V -

-0.5 mA)

Output low voltage (OV DD = min, I OL = V OL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.16.2 GIC AC timing specifications

This table provides the GIC input and output AC timing specifications.

Table 45. GIC AC timing specifications

Parameter Symbol Min Max Unit Notes

GIC inputs-minimum pulse width t PIWID 3.0 - SYSCLKs 1

1. GIC inputs and outputs are asynchronous to any visible clock. GIC outputs must be synchronized before use by any external
synchronous logic. GIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge
triggered mode.

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3.17 I2C

3.17.1 I2C DC electrical characteristics

This table provides the DC electrical characteristics for the I2C interface.

Table 46. I2C DC electrical characteristics (OVDD = 1.8V)1

Parameter Symbol Min Max Unit Notes

Input high voltage VIH 0.7 x OVDD - V 2

Input low voltage VIL - 0.3 x OVDD V 2

Output low voltage (OVDD = min, IOL = 2 VOL 0.0 0.36 V -

mA, OVDD ≤ 2V)

Pulse width of spikes that must be tI2KHKL 0.0 50.0 ns 3

suppressed by the input filter

Input current each I/O pin (input voltage II - ±50 μA 4

is between 0.1 x OVDD (min) and 0.9 x
OVDD (max))

Capacitance for each I/O pin CI - 10.0 pF -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min VIL and max VIH values are based on the respective min and max OVIN values found in Recommended
Operating Conditions.
3. See the chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if the supply is switched off.

3.17.2 I2C AC timing specifications

This table provides the AC timing specifications for the I2C interface.

Table 47. I2C AC timing specifications 5, 6, 7

Parameter Symbol Standard Mode Fast Mode Unit Notes

Min Max Min Max

Max. Frequency fI2C 100 - 400.0 kHz -

Low period of the SCL clock tI2CL 4.7 1.3 - μs -

High period of the SCL clock tI2CH 4 0.6 - μs -

Setup time for a repeated tI2SVKH 4.7 0.6 - μs -

START condition

Hold time (repeated) START tI2SXKL 4 0.6 - μs -

condition

Table continues on the next page...

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Table 47. I2C AC timing specifications 5, 6, 7 (continued)

Parameter Symbol Standard Mode Fast Mode Unit Notes

Min Max Min Max

Setup time tI2DVKH 250 100.0 - ns 1

Input hold time tI2DXKL 0.0 0.0 - μs 2

Master output delay time tI2OVKL 3.45 0.9 μs 3

Input setup time for STOP tI2PVKH 4 - 0.6 - μs -

condition

Bus free time between a tI2KHDX 4.7 1.3 - μs -

STOP and START condition

Capacitive load for each bus Cb 400.0 - 400.0 pF 4

line

1. A Fast-mode I2C-bus device can be used in a Standard-modeI2C-bus system, but the requirement of Setup time of 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line max rise time + data
Setup Time = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
2. A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling
edge of I2Cx_SCL.
3. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. Cb = Total capacitance of one bus line in pF
5. The symbols used for timing specifications herein follow these patterns: t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time.
6. See Figure 30.
7. See Figure 31.

This figure shows the AC test load for the I2C.

Output Z0= 50 Ω OVDD/2

RL = 50 Ω

Figure 30. I2C AC test load

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This figure shows the AC timing diagram for the I2C bus.

SDA

tI2DVKH tI2KHKL tI2KHDX

tI2CL tI2SXKL
SCL

tI2CH tI2SVKH tI2PVKH

tI2SXKL
tI2DXKL, tI2OVKL
S Sr P S

Figure 31. I2C bus AC timing diagram

3.18 JTAG
This section describes the DC and AC electrical specifications for the JTAG (IEEE 1149.1) interface.

3.18.1 JTAG DC electrical characteristics

This table provides the DC electrical characteristics for the JTAG (IEEE 1149.1) interface.

Table 48. JTAG DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 1.2 - V 2

Input low voltage V IL - 0.6 V 2

Input current (V IN = 0V or V IN = OV DD) I IN - -100/+50 μA 3

Output high voltage (OV DD = min, I OH = V OH 1.35 - V -

-0.5 mA)

Output low voltage (OV DD = min, I OL = V OL - 0.4 V -

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.18.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 32, Figure 33, Figure 34, and Figure 35.

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Table 49. JTAG AC timing specifications 3, 4, 5, 6, 7

Parameter Symbol Min Max Unit Notes

JTAG external clock frequency F JTG 0 25 MHz -

of operation

JTAG external clock cycle time t JTG 40 - ns -

JTAG external clock pulse width t JTKHKL 20 - ns -

measured at 1.4 V

JTAG external clock rise and fall times t JTGR/t JTGF 0.0 2.0 ns -

TRST_B assert time t TRST 25.0 - ns 1

Input setup times t JTDVKH 6 - ns -

Input hold times t JTDXKH 10.0 - ns -

Output valid times: boundary-scan data t JTKLDV - 20.0 ns 2

Output valid times: TDO t JTKLDV - 14 ns 2

Output hold times t JTKLDX 0.0 - ns 2

1. TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
2. All outputs are measured from the midpoint voltage of the falling edge of t TCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be
added for trace lengths, vias, and connectors in the system.
3. The symbols used for timing specifications follow these patterns: t(first two letters of functional block)(signal)(state)(reference)
(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t JTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to
the time data input signals (D) reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
4. See Figure 32.
5. See Figure 33.
6. See Figure 34.
7. See Figure 35.

This figure shows the AC test load for TDO and the boundary-scan outputs of the device.

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Output Z0= 50 Ω OVDD/2

RL = 50 Ω

Figure 32. AC test load for the JTAG interface

This figure shows the JTAG clock input timing diagram.

VM VM VM
JTAG external clock
tJTGR
tJTKHKL
tJTGF
tJTG

VM = Midpoint voltage (OVDD/2)

Figure 33. JTAG clock input timing diagram

This figure shows the TRST_B timing diagram.

TRST_B

VM VM

tTRST

VM = Midpoint voltage (OVDD/2)

Figure 34. TRST_B timing diagram

This figure shows the boundary-scan timing diagram.

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JTAG External Clock

VM VM

tJTDVKH

tJTDXKH

Boundary Data Inputs Input Data Valid

tJTKLDV
tJTKLDX

Boundary Data Outputs Output Data Valid

VM = Midpoint Voltage (OVDD/2)

Figure 35. Boundary-scan timing diagram

3.19 Flex serial peripheral interface (FlexSPI)

3.19.1 FlexSPI DC electrical characteristics

This table provides the DC electrical characteristics for the FlexSPI interface.

Table 50. FlexSPI DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (0V ≤ V IN ≤ OV DD) I IN - ±50 μA 3

Output high voltage (I OH = -100 μA) V OH 0.85xOV DD - V -

Output low voltage (I OL = 100 μA) V OL - 0.15xOV DD V -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.19.2 FlexSPI AC timing specifications

This table provides the FlexSPI timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

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Table 51. SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0 2, 3, 4

Parameter Symbol Min Max Unit Notes

Clock frequency F SCK - 100.0 MHz -

Duty cycle T LOW/T 45 55 % -

HIGH

CS output hold time t FSKHOX2 FLSHxyCR1[TCSH] - ns 1, 5

* T - 0.15

CS output delay t FSKHOV2 ((FLSHxyCR1[TCS - ns 1, 5

S]+ 0.5) * T) - 5.15

Setup time for incoming data- t FSIVKH 2.4 - ns 5

without DQS

Hold time for incoming data without DQS t FSIXKH 1.05 - ns -

Output data delay t FSKHOV 2.35 ns -

Output data hold t FSKHOX -1.35 - ns -

1. Refer the FLSHxyCR1 QorIQ LX2160ARM for more details, where x: A or B, y: 1 or 2

2. See Figure 37.
3. See Figure 38.
4. See Figure 39.
5. T = FlexSPI clock period

This table provides the FlexSPI timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] =0x1 or 0x2

Table 52. SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x1 or 0x2 2, 3, 4

Parameter Symbol Min Max Unit Notes

Clock frequency F SCK - 100.0 MHz -

Duty cycle T LOW/T 45 55 % -

HIGH

CS output hold time t FSKHOX2 FLSHxyCR1[TCSH] - ns 1, 5

* T - 0.15

CS output delay t FSKHOV2 ((FLSHxyCR1[TCS - ns 1, 5

S] + 0.5) * T) - 5.15

Setup time for incoming data- t FSIVKH 2.4 - ns -

without DQS

Hold time for incoming data without DQS t FSIXKH 1.05 - ns -

Table continues on the next page...

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Table 52. SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x1 or 0x2 2, 3, 4 (continued)

Parameter Symbol Min Max Unit Notes

Output data delay t FSKHOV 2.35 ns -

Output data hold t FSKHOX -1.35 - ns -

1. Refer the FLSHxyCR1 QorIQ LX2160ARM for more details, where x: A or B, y: 1 or 2

2. See Figure 37.
3. See Figure 38.
4. See Figure 39.
5. T = FlexSPI clock period

This table provides the FlexSPI timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] =0x1 or 0x2.

Table 53. DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x1, or 0x2 4, 5, 6

Parameter Symbol Min Max Unit Notes

Clock frequency F SCK - 75 MHz -

Duty cycle T LOW/T 47 53 % -

HIGH

CS output hold time t FSKHOX2 ((FLSHxyCR1[TCS - ns 1, 7

H]+ 0.5) * T/2) - 0.15

CS output delay t FSKHOV2 ((FLSHxyCR1[TCS - ns 1, 7

S]+ 0.5) * T/2) - 5.15

Data Valid Window t FSIDVW 0.3 - UI 2, 3

Output data delay t FSKHOV/ - 3.94 ns -

tFSKLOV

Output data hold t FSKHOX/ 2.8 for Rev 1.0 - ns -

tFSKLOX
3.0 for Rev 2.0

1. Refer the FLSHxyCR1 QorIQ LX2160ARM for more details, where x: A or B, y: 1 or 2

2. For DDR, Unit Internval (UI) is half of period. For example, 5 ns for 100 MHz
3. See "Data Learning Feature" section in QorIQ LXxxxxARM for details
4. See Figure 37.
5. See Figure 38.
6. See Figure 40.
7. T = FlexSPI clock period

This table provides the FlexSPI timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] =0x3.

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Table 54. DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 2, 3, 4, 5

Parameter Symbol Min Typ Max Unit Notes

Clock frequency F SCK - - 200.0 MHz -

Duty cycle T LOW/T 45 - 55 % -

HIGH

CS output hold time t FSKHOX2 ((FLSHxyCR1[T - - ns 1, 6

CSH]+ 0.5) * T/2)
- 0.15

CS output delay t FSKHOV2 ((FLSHxyCR1[T - - ns 1, 6

CSH]+ 0.5) * T/2)
- 5.15

DQS to data skew t FSIVKH/ - 0.6 ns 7

tFSIVKL

DQS to data hold skew t FSIIVKH/ - 0.9 ns 7

tFSIIVKL

Output data delay t FSKHOV/ - - 1.7 ns -

tFSKLOV

Output data hold t FSKHOX/ 0.8 - - ns -

tFSKLOX

1. Refer the FLSHxyCR1 QorIQ LX2160ARM for more details, where x: A or B, y: 1 or 2

2. See Figure 37.
3. See Figure 38.
4. See Figure 40.
5. See Figure 36.
6. T = FlexSPI clock period
7. When DLLxCR = 0x0000_1100, where x: A or B.

This figure shows the FlexSPI data input timing in DDR mode with an external DQS.

XSPI_A_SCK
XSPI_B_SCK

XSPI_A_DQS
XSPI_B_DQS
tFSIVKH tFSIVKL tFSIIVKH
tFSIIVKLSL

Input Data

Figure 36. FlexSPI input AC timing-DDR mode with an external DQS

This figure shows the AC test load for the FlexSPI interface.

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Output Z0= 50 Ω Respective

supply / 2
RL = 50 Ω

Figure 37. AC test load for FlexSPI

This figure shows the FlexSPI clock input timing diagram.

t HIGH

FlexSPI clock

t LOW

Figure 38. FlexSPI clock input timing diagram

This figure shows the FlexSPI AC timing diagram for SDR mode.

XSPI_A_SCK
XSPI_B_SCK
tFSIXKH
tFSIVKH
Input Signals:

tFSKHOX
tFSKHOV
Output Signals:

tFSKHOV2 tFSKHOX2
XSPI_A_CS0
XSPI_A_CS1
XSPI_B_CS0
XSPI_B_CS1

Figure 39. FlexSPI SDR mode AC timing diagram

This figure shows the FlexSPI AC timing diagram for DDR mode 1 and 2.

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XSPI_A_SCK
XSPI_B_SCK
tFSIDVW

Input Signals:

tFSIDVW tFSKHOV
tFSKLOX
Output Signals:

tFSKLOV
tFSKHOV2 tFSKHOX tFSKHOX2
XSPI_A_CS0_B
XSPI_A_CS1_B
XSPI_B_CS0_B
XSPI_B_CS1_B

Figure 40. FlexSPI DDR mode 1 and 2 AC timing diagram

3.20 Serial peripheral interface (SPI)

3.20.1 SPI DC electrical characteristics

This table provides the DC electrical characteristics for the SPI interface when operating with a single master device.

Table 55. SPI DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OV DD - V 2

Input low voltage V IL - 0.3 x OV DD V 2

Input current (V IN = 0V or V IN = OV DD) I IN - ±50 μA 3

Output high voltage (I OH = -100 μA) V OH 0.85xOV DD - V -

Output low voltage (I OL = 100 μA) V OL - 0.15xOV DD V -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.20.2 SPI AC timing specifications

This table provides the SPI timing specifications when operating with a single master device.

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Table 56. SPI AC timing specifications 6, 7

Parameter Symbol Min Max Unit Notes

SCK cycle time t SCK t SYS * 2 - ns 1

SCK clock pulse width t SDC 40.0 60.0 % -

CS to SCK delay t CSC tp*2 - 1.85 - ns 2, 3, 4

After SCK delay t ASC tp*2 + 0.06 - ns 2, 5, 4

Data setup time for inputs t NIIVKH 9.0 - ns 2

Data hold time for inputs t NIIXKH 0.0 - ns 2

Data valid (after SCK edge) for outputs t NIKHOV - 5.0 ns 2

Data hold time for outputs t NIKHOX 0.0 - ns 2

1. t SYS = 10 ns
2. Master mode
3. Refer the CTARx register in QorIQ LX2160ARM for more details. The tCSC = tp * (Delay Scaler Value) * CTARx[PCSSCK] -
1.85, where the Delay Scaler Value comes from Table Delay Scaler Encoding. For example, the tCSC = tp * 4 * 3 - 1.85 when
CTARx[PCSSCK] = 0b01, CTARx[CSSCK]=0b0001
4. tp is the input clock period for the SPI controller.
5. Refer the CTARx register in QorIQ LX2160ARM for more details. The tASC = tp * (Delay Scaler Value) * CTARx[PASC] +
0.06, where the Delay Scaler Value comes from Table Delay Scaler Encoding. For example, the tASC = tp * 8 * 3 + 0.06 when
CTARx[PASC] = 0b01, CTARx[ASC]=0b0010
6. See Figure 41.
7. See Figure 42.

This figure shows the SPI timing master when CPHA = 0.

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tCSC tASC

CSx

t SDC
t SCK

SCK Output
(CPOL = 0) t SDC

SCK Output
(CPOL = 1)

t NIIXKH
t NIIVKH

SIN First Data Data Last Data

t NIKHOX
t NIKHOV

SOUT

First Data Data Last Data

Figure 41. SPI timing master, CPHA = 0

This figure shows the SPI timing master when CPHA = 1.

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CSx

SCK Output
(CPOL = 0)
tNIIXKH

SCK Output
(CPOL = 1)

tNIIVKH

SIN First Data Data Last Data

t NIKHOX
t NIKHOV
SOUT

First Data Data Last Data

Figure 42. SPI timing master, CPHA = 1

3.21 Universal serial bus 3.0 (USB)

This section describes the specification for the on-chip Super Speed (SS) USB 3.0 PHY signals. For High Speed (HS), Full
Speed (FS) , and Low Speed (LS) specifications of the USB PHY signals, see Chapter 7 in the Universal Serial Bus Revision 2.0
Specification for more information.

3.21.1 USB 3.0 DC electrical characteristics

This table provides the USB 3.0 transmitter DC electrical characteristics at the package pins.

Table 57. USB 3.0 transmitter DC electrical characteristics (USB_HVDD = 3.3V, USB_SVDD = 0.8V) 1

Parameter Symbol Min Typ Max Unit

Differential output voltage V tx-diff-pp 800.0 1000.0 1200.0 mV p-p

Low power differential output voltage V tx-diff-pp- 400.0 - 1200.0 mV p-p

low

Transmit de-emphasis V tx-de-ratio 3.0 - 4.0 dB

Differential impedance Z diffTX 72.0 100.0 120.0 Ω

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Table 57. USB 3.0 transmitter DC electrical characteristics (USB_HVDD = 3.3V, USB_SVDD = 0.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit

Transmit common mode impedance R TX-DC 18.0 - 30.0 Ω

Absolute DC common mode voltage T TX-CM-DC- - - 200.0 mV

between U1 and U0 ACTIVEIDLE-
DELTA

DC electrical idle differential V TX-IDLE- 0.0 - 10.0 mV

output voltage DIFF-DC

1. For recommended operating conditions, see Recommended Operating Conditions.

This table provides the USB 3.0 receiver DC electrical characteristics at the receiver package pins.

Table 58. USB 3.0 receiver DC electrical characteristics (USB_HVDD = 3.3V, USB_SVDD = 0.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential receiver R RX-DIFF- 72.0 100.0 120.0 Ω -

input impedance DC

Receiver DC common R RX-DC 18.0 - 30.0 Ω -

mode impedance

DC input CM input impedance for Z RX-HIGH- 25000.0 - - Ω -

V > 0 during reset or power down IMP-DC

LFPS detect threshold V TRX- 100.0 - 300.0 mV 2

IDLE-DET-
DC-DIFFpp

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Below the minimum is noise. Must wake up above the maximum.

3.21.2 USB 3.0 AC timing specifications

This table provides the USB 3.0 transmitter AC timing specifications at package pins.

Table 59. USB 3.0 transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Speed f USB - 5.0 - Gb/s -

Transmitter eye T TX-EYE 0.625 - - UI -

Unit Interval UI 199.94 200.0 200.06 ps 1

AC coupling capacitor AC CAP 75.0 - 200.0 nF -

1. UI does not account for SSC-caused variations.

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This table provides the USB 3.0 receiver AC timing specifications at the receiver package pins.

Table 60. USB 3.0 receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 199.94 200.0 200.06 ps 1

1. UI does not account for SSC-caused variations.

This table provides the key LFPS electrical specifications at the transmitter.

Table 61. LFPS electrical specifications at the transmitter 2

Parameter Symbol Min Max Unit Notes

Period t Period 20.0 100.0 ns -

Peak-to-peak differential amplitude V tx-diff-pp-lfps 800.0 1200.0 mV -

Rise/fall time t rise/fall - 4.0 ns 1

Duty cycle DC LFPS 40.0 60.0 % 1, 2

1. Measured at compliance TP1. See the Transmit normative setup figure below for details.
2. See Figure 43.

This figure shows the transmit normative setup with reference channel as per USB 3.0 specifications.

Measurement Tool SMP Reference Test Channel Reference Cable DUT

TP1

Figure 43. Transmit normative setup

3.22 Controller Automatic Network interface (CAN)

3.22.1 CAN DC electrical characteristics

This table provides the DC electrical characteristics for CAN-FD pins operating at OV DD = 1.8 V.

Table 62. DC electrical characteristics for CAN-FD (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Input high voltage V IH 0.7 x OVDD - V 2

Input low voltage V IL - 0.3 x OVDD V 2

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Table 62. DC electrical characteristics for CAN-FD (OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Max Unit Notes

Input current (VIN = 0 V or VIN= OV DD) I IN - ±50 μA 3

Output high voltage (OV DD = min, IOH = V OH 1.35 - V -

-0.5 mA)

Output low voltage (OV DD = min, IOL = V OL - 0.4 V -

-0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The min V IL and max V IH values are based on the respective min and max OV IN values found in Recommended
Operating Conditions.
3. The symbol OV IN represents the input voltage of the supply referenced in Recommended Operating Conditions.

3.22.2 CAN AC electrical characteristics

This table provides the CAN-FD AC timing specifications.

Table 63. CAN-FD AC timing specifications 1

Parameter Min Max Unit

Baud rate 10.0 8000.0 kbps

1. See Figure 44.

This figure provides the CAN-FD AC test load.

Output Z0= 50 Ω OVDD/2

RL = 50 Ω

Figure 44. FlexCAN AC test load

3.23 High-speed serial interfaces (HSSI)

The chip features a Serializer/Deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The
SerDes interface can be used for PCI Express, SGMII, 1000Base-KX, USXGMII, XFI, SFI, 10GBase-KR, 25G-AUI, XLAUI,
40GBase-KR, 50GAUI-2, CAUI-4, and serial ATA (SATA) data transfers.
This section describes the most common portion of the SerDes DC electrical specifications: the DC requirement for SerDes
reference clocks. The SerDes data lane's transmitter (Tx) and receiver (Rx) reference circuits are also described.

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3.23.1 Signal terms definitions

The SerDes uses differential signaling to transfer data across the serial link. This section defines the terms that are used in the
description and specification of differential signals.
This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure
shows the waveform for either a transmitter output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N).
Each signal swings between A volts and B volts where A > B.

SD_TXn_P or
SD_RXn_P
A Volts

Vcm= (A + B)/2

SD_TXn_N or
SD_RXn_N
B Volts

Differential swing, VID orVOD = A - B

Differential peak voltage, VDIFFp = |A - B|
Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown)

Figure 45. Differential voltage definitions for transmitter or receiver

Using this waveform, the definitions are as described in the following list. To simplify the illustration, the definitions assume that
the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment:

Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N, SD_RXn_P and
SD_RXn_N each have a peak-to-peak swing of A - B volts. This is also referred to as each signal
wire's single-ended swing.

Differential Output The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the
Voltage, VOD (or two complementary output voltages: VSD_TX n_P - VSD_TXn_N. The VOD value can be either positive or
Differential Output negative.
Swing)

Differential Input The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
Voltage, V ID (or complementary input voltages: VSD_RXn_P- VSD_RXn_N. The VID value can be either positive or negative.
Differential Input
Swing)

Differential Peak The peak value of the differential transmitter output signal or the differential receiver input signal is
Voltage, V DIFFp defined as the differential peak voltage, VDIFFp = |A - B| volts.

Differential Peak-to- Because the differential output signal of the transmitter and the differential input signal of the receiver
Peak, V DIFFp-p each range from A - B to -(A - B) volts, the peak-to-peak value of the differential transmitter output
signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p =
2 x VDIFFp = 2 x |(A - B)| volts, which is twice the differential swing in amplitude, or twice the differential
peak. For example, the output differential peak-to-peak voltage can also be calculated as VTX-DIFFp-p =
2 x |VOD|.

Differential The differential waveform is constructed by subtracting the inverting signal (SD_TXn_N, for example)
Waveform from the non-inverting signal (SD_TXn_P, for example) within a differential pair. There is only one
signal trace curve in a differential waveform. The voltage represented in the differential waveform is
not referenced to ground. See Figure 50 as an example for differential waveform.

Common Mode The common mode voltage is equal to half of the sum of the voltages between each conductor of
Voltage, V cm a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn_P
+ VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complementary output

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voltages within a differential pair. In a system, the common mode voltage may often differ from one
component's output to the other's input. It may be different between the receiver input and driver
output circuits within the same component. It is also referred to as the DC offset on some occasions.

To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common
mode voltage of 2.25 V and outputs, TD and TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage
swing of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the
differential signaling environment is fully symmetrical in this example, the transmitter output's differential swing (VOD) has the
same amplitude as each signal's single-ended swing. The differential output signal ranges between 500 mV and -500 mV. In
other words, VOD is 500 mV in one phase and -500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The
peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

3.23.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the
corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_PLLF_REF_CLK_P/SD1_PLLF_REF_CLK_N
and SD1_PLLS_REF_CLK_P/SD1_PLLS_REF_CLK_N for SerDes 1, SD2_PLLF_REF_CLK_P/SD2_PLLF_REF_CLK_N and
SD2_PLLS_REF_CLK_P/SD2_PLLS_REF_CLK_N for SerDes 2, and SD3_PLLF_REF_CLK_P/SD3_PLLF_REF_CLK_N and
SD3_PLLS_REF_CLK_P/SD3_PLLS_REF_CLK_N for SerDes 3.
SerDes 1-3 may be used for various combinations of the following IP blocks based on the RCW Configuration
field SRDS_PRTCLn:
• SerDes 1: SGMII, PCIe, USXGMII/XFI/SFI, 100GE, 50GE, 40GE, 25GE
• SerDes 2: SGMII, PCIe, USXGMII/XFI/SFI, SATA
• SerDes 3: PCIe
The following sections describe the SerDes reference clock requirements and provide application information.

3.23.2.1 SerDes spread-spectrum clock source recommendations

SDn_PLLm_REF_CLK_P and SDn_PLLm_REF_CLK_N are designed to work with spread-spectrum clocking for the PCI Express
protocol only with the spreading specification defined in Table 64. When using spread-spectrum clocking for PCI Express, both
ends of the link partners should use the same reference clock. For best results, a source without significant unintended modulation
must be used.
The SerDes transmitter does not support spread-spectrum clocking for the SATA protocol. The SerDes receiver does support
spread-spectrum clocking on receive, which means the SerDes receiver can receive data correctly from a SATA serial link partner
using spread-spectrum clocking.
Spread-spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread-spectrum-
supported protocols. For example, if spread-spectrum clocking is desired on a SerDes reference clock for the PCI Express
protocol and the same reference clock is used for any other protocol, such as SATA or SGMII because of the SerDes lane usage
mapping option, spread-spectrum clocking cannot be used at all.
This table provides the source recommendations for SerDes spread-spectrum clocking.

Table 64. SerDes spread-spectrum clock source recommendations 1

Parameter Min Max Unit Notes

Frequency modulation 30 33 kHz —

Frequency spread +0 -0.5 % 2

Notes:
1. At recommended operating conditions. See Recommended Operating Conditions.

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Table 64. SerDes spread-spectrum clock source recommendations 1 (continued)

Parameter Min Max Unit Notes

2. Only down-spreading is allowed.

3.23.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

50 Ω

SDn_REF_CLKn_P

Input
amp

SDn_REF_CLKn_N

50 Ω

Figure 46. Receiver of SerDes reference clocks

3.23.2.3 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the
clock driver chip and SerDes reference clock inputs, as described below.
Differential mode:
• The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-to-peak (or between
200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended
swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
• For an external DC-coupled connection, as described in SerDes reference clock receiver characteristics, the maximum
average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400
mV. Figure 47 shows the SerDes reference clock input requirement for DC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_PLLm_REF_CLK_P Vmax < 800mV

100 mV < Vcm < 400 mV

SDn_PLLm_REF_CLK_N Vmin > 0 V

Figure 47. Differential reference clock input DC requirements (external DC-coupled)

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• For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the
external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in
different common mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode
voltage set to SD_GND. Each signal wire of the differential inputs is allowed to swing below and above the common mode
voltage (SD_GND). Figure 48 shows the SerDes reference clock input requirement for AC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_PLLm_REF_CLK_P Vmax < Vcm + 400 mV

Vcm

SDn_PLLm_REF_CLK_N Vmin > Vcm - 400 mV

Figure 48. Differential reference clock input DC requirements (external AC-coupled)

Single-ended mode:
• The reference clock can also be single-ended. The SDn_PLLm_REF_CLK_P input amplitude (single-ended swing) must be
between 400 mV and 800 mV peak-to-peak (from VMIN to VMAX) with SDn_PLLm_REF_CLK_N either left unconnected or tied
to ground.
• The SDn_PLLm_REF_CLK_P input average voltage must be between 200 and 400 mV. Figure 49 shows the SerDes
reference clock input requirement for single-ended signaling mode.
• To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally.
For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase
(SDn_PLLm_REF_CLK_N) through the same source impedance as the clock input (SDn_PLLm_REF_CLK_P) in use.

400 mV < SD_REF_CLKn input amplitude < 800 mV

SDn_PLLm_REF_CLK_P

0V

SDn_PLLm_REF_CLK_N

Figure 49. Single-ended reference clock input DC requirements

3.23.2.4 SerDes reference clocks AC timing specifications

For protocols with data rates up to 5 Gb/s where there is not reference clock jitter specification (ex: SGMII), use the PCIe 2.5G
clock jitter requirements.
For protocols with data rates greater than 5 Gb/s and less than 8 Gb/s where there is no reference clock jitter specification, use
the PCIe 5G clock jitter requirements.
For protocols with data rates greater than 8 Gb/s and less than 16 Gb/s where there is no reference clock jitter specification (ex:
XLAUI, USXGMII-10.31.25G), use the PCIe 8G or XFI clock jitter requirements.
For protocols with data rates greater than 16 Gb/s where there is no reference clock jitter specification (ex: CAUI-4/50GAUI-2/25G-
AUI use the PCIe 16G clock jitter requirements).

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Use the protocol’s reference clock frequency tolerance specification (ex: +/-100 ppm for SGMII/USXGMII/XFI/SFI/10GBaseKR/
1000Base-KX/XLAUI/CAUI-4/50GAUI-2/25G-AUI and +/-300 ppm for PCIe).
This table defines the AC requirements for SerDes reference clocks for PCI Express. SerDes reference clocks need to be verified
by the customer’s application design.

Table 65. SDn_PLLm_REF_CLK_P and SDn_PLLm_REF_CLK_N input clock requirements for PCI Express

Parameter Symbol Min Typ Max Unit Note

s

SDn_PLLm_REF_CLK_P/ tCLK_REF - 100/125 - MHz -

SDn_PLLm_REF_CLK_N
frequency range

SDn_PLLm_REF_CLK_P/ tCLK_TOL -300.0 - 300.0 ppm 1

SDn_PLLm_REF_CLK_N clock
frequency tolerance

SDn_PLLm_REF_CLK_P/ tCLK_DUTY 40.0 50.0 60.0 % 2

SDn_PLLm_REF_CLK_N
reference clock duty cycle

PCIe 2.5G tCLK_DJ - - 42.0 ps P-P 3, 4

SDn_PLLm_REF_CLK_P/
SDn_PLLm_REF_CLK_N max
deterministic peak-to-peak jitter at
10 -6 BER

PCIe 2.5G tCLK_TJ - - 86.0 ps P-P 3, 4

SDn_PLLm_REF_CLK_P/
SDn_PLLm_REF_CLK_N total
reference clock jitter at 10 -6 BER

PCIe 5G tREFCLK- - - 3.0 ps RMS 5

SDn_PLLm_REF_CLK_P/ LF-RMS
SDn_PLLm_REF_CLK_N 10 kHz
to 1.5 MHz RMS jitter

PCIe 5G tREFCLK- - - 3.1 ps RMS 5

SDn_PLLm_REF_CLK_P/ HF-RMS
SDn_PLLm_REF_CLK_N > 1.5
MHz to Nyquist RMS jitter

PCIe 8G tREFCLK- - - 1.0 ps RMS 6

SDn_PLLm_REF_CLK_P/ RMS-DC
SDn_PLLm_REF_CLK_N RMS
reference clock jitter

SDn_PLLm_REF_CLK_P/ tCLKRR/ 0.6 - 4.0 V/ns 7, 8

SDn_PLLm_REF_CLK_N rising/ tCLKFR
falling edge rate

Differential input high voltage VIH 150.0 - - mV 2

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Table 65. SDn_PLLm_REF_CLK_P and SDn_PLLm_REF_CLK_N input clock requirements for PCI Express (continued)

Parameter Symbol Min Typ Max Unit Note

s

Differential input low voltage VIL - - -150.0 mV 2

Rising edge rate Rise-Fall - - 20.0 % 9, 10,

(SDn_PLLm_REF_CLK_P) to matching 11
falling edge rate
(SDn_PLLm_REF_CLK_N)
matching

1. For PCI Express (2.5, 5, and 8 GT/s).

2. Measurement taken from differential waveform.
3. Limits from PCI Express CEM Rev 2.0.
4. For PCI Express 2.5 GT/s
5. For PCI Express 5 GT/s
6. For PCI Express 8 GT/s
7. Measured from -150 mV to +150 mV on the differential waveform (derived from SDn_PLLm_REF_CLK_P minus
SDn_PLLm_REF_CLK_N). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing.
8. See Figure 50.
9. Measurement taken from single-ended waveform.
10. Matching applies to rising edge for SDn_PLLm_REF_CLK_P and falling edge rate for SDn_PLLm_REF_CLK_N. It is
measured using a +/- 75 mV window centered on the median cross point where SDn_PLLm_REF_CLK_P rising meets
SDn_PLLm_REF_CLK_N falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope
uses for the edge rate calculations. The rise edge rate of SDn_PLLm_REF_CLK_P must be compared to the fall edge rate of
SDn_PLLm_REF_CLK_N, the maximum allowed difference should not exceed 20% of the slowest edge rate.
11. See Figure 51.

This figure shows the differential measurement points for rise and fall time.

Rise-edge rate Fall-edge rate

VIH = + 150 mV

0.0 V

VIL = - 150 mV

SDn_PLLm_REF_CLK_P
SDn_PLLm_REF_CLK_N

Figure 50. Differential measurement points for rise and fall time

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This figure shows the single-ended measurement points for rise and fall time matching.

SDn_PLLm_REF_CLK_N SDn_PLLm_REF_CLK_N
TFALL TRISE

VCROSS MEDIAN + 75 mV

VCROSS MEDIAN VCROSS MEDIAN

VCROSS MEDIAN - 75 mV

SDn_PLLm_REF_CLK_P SDn_PLLm_REF_CLK_P

Figure 51. Single-ended measurement points for rise and fall time matching

This table defines the AC requirements for SerDes reference clocks for XFI, SFI, XLAUI, and CAUI-4/50GAUI-2/25G-AUI. SerDes
reference clocks need to be verified by the customer’s application design.

Table 66. SDn_PLLm_REF_CLK_P and SDn_PLLm_REF_CLK_N input clock requirements for XFI, SFI, XLAUI, and
CAUI-4/50GAUI-2/25G-AUI

Parameter Symbol Min Typ Max Unit Note

s

Frequency range tCLK_REF - 156.25/ - SFI -

161.1328125 MHz

Clock frequency tolerance tCLK_TOL -100.0 - 100.0 ppm -

Reference clock duty cycle tCLK_DUTY 40.0 50.0 60.0 % 1

Single side band noise at 1 kHz at 1 kHz - - -85.0 dBC/Hz 2

Single side band noise at 10 kHz at 10 kHz - - -108.0 dBC/Hz 2

Single side band noise at 100 kHz at 100 - - -128.0 dBC/Hz 2

kHz

Single side band noise at 1 MHz at 1 MHz - - -138.0 dBC/Hz 2

Single side band noise at 10 MHz at 10 - - -138.0 dBC/Hz 2

MHz

Random jitter (1.2 MHz to 15 MHz) tCLK_RJ - - 0.8 ps -

Total reference clock jitter at 10 -12 tCLK_TJ - - 11.0 ps -

BER (1.2 MHz to 15 MHz)

Spurious noise (1.2 MHz to NA - - -75.0 dBC -

15 MHz)

1. Measurement taken from differential waveform.

2. Per XFP specification, Rev 4.5, the Module Jitter Generation spec at XFI optical output is 10mUI (RMS) and 100 mUI (p-p).
In the CDR mode, the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.

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3.23.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane's transmitter and receiver.

SDn_TXn_P SDn_RXn_P

50 Ω
Transmitter 100 Ω Receiver

SDn_TXn_N SDn_RXn_N 50 Ω

Figure 52. SerDes transmitter and receiver reference circuits

The DC and AC specifications of the SerDes data lanes are defined in each interface protocol section below based on the
application usage:
• PCI Express
• SATA
• SGMII
• USXGMII
• XFI
• SFI
• 10GBase-KR
• CAUI-4, 50GAUI-2, 25G-AUI
• XLAUI
• 40GBase-KR
Note that an external AC-coupling capacitor is required for the above serial transmission protocols with the capacitor value defined
in the specification of each protocol section.

3.23.4 PCI Express

3.23.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 ppm of each other at all times. This is specified
to allow bit rate clock sources with a ±300 ppm tolerance.

3.23.4.2 PCI Express clocking requirements for SDn_PLLF_REF_CLK and SDn_PLLS_REF_CLK

SerDes 1/2/3 SD[1:3]_PLLF_REF_CLK/SD[1:3]_PLLF_REF_CLK_B and SD[1:3]_PLLS_REF_CLK/SD[1:3]_PLLS_REF_CLK_B
may be used for various SerDes PCI Express configurations based on the RCW Configuration field SRDS_PRTCL. PCI Express
is supported on SerDes 1, 2, and 3.
For more information on these specifications, see SerDes reference clocks.

3.23.4.3 PCI Express DC electrical characteristics

This section describes the PCI Express DC physical layer transmitter specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s.
This table defines the PCI Express 1.0 (2.5 GT/s) DC electrical characteristics for the differential output at all transmitters. The
parameters are specified at the component pins.

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Electrical characteristics

Table 67. PCI Express 1.0 (2.5 GT/s) differential transmitter output DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak V TX- 800.0 1000.0 1200.0 mV 2

output voltage DIFFP-P

De-emphasized differential output V TX-DE- 3.0 3.5 4.0 dB 3

voltage (ratio) RATIO

DC differential Z TX-DIFF- 80.0 100.0 120.0 Ω 4

transmitter impedance DC

Transmitter DC impedance Z TX-DC 40.0 50.0 60.0 Ω 5

1. For recommended operating conditions, see Recommended Operating Conditions.

2. V TX_DIFFp-p = 2 x | V TX-D+ - V TX-D- |
3. Ratio of V TX-DIFFp-p of the second and following bits after a transition divided by the V TX-DIFFp-p of the first bit after a transition.
4. Transmitter DC differential mode low impedance
5. Required transmitter D+ as well as D- DC Impedance during all states.

This table defines the DC electrical characteristics for the PCI Express 1.0 (2.5 GT/s) differential input at all receivers. The
parameters are specified at the component pins.

Table 68. PCI Express 1.0 (2.5 GT/s) differential receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak voltage V RX- 175.0 1000.0 1200.0 mV 2, 3

DIFFP-P

DC differential input impedance Z RX-DIFF- 80.0 100.0 120.0 Ω 4, 5

DC

DC input impedance Z RX-DC 40.0 50.0 60.0 Ω 6, 3, 5

Powered down DC Z RX-HIGH- 50.0 - - kΩ 7, 8

input impedance IMP-DC

Electrical idle detect threshold V RX-IDLE- 65.0 - 175.0 mV 9, 3

DET-DIFFp-
p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. V RX_DIFFp-p = 2 x | V RX-D+ - V RX-D- |
3. Measured at the package pins with a test load of 50Ω to GND on each pin.
4. Receiver DC differential mode impedance.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all configured lanes on a port.
6. Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).

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Electrical characteristics

Table 68. PCI Express 1.0 (2.5 GT/s) differential receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1
(continued)

Parameter Symbol Min Typ Max Unit Notes

7. Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
8. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300mV above the receiver ground.
9. V RX-IDLE-DET-DIFFp-p = 2 x | V RX-D+ - V RX-D- |

This table defines the PCI Express 2.0 (5 GT/s) DC electrical characteristics for the differential output at all transmitters. The
parameters are specified at the component pins.

Table 69. PCI Express 2.0 (5 GT/s) differential transmitter output DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak V TX- 800.0 1000.0 1200.0 mV 2

output voltage DIFFP-P

Low power differential peak-peak V TX- 400.0 500.0 1200.0 mV 2

output voltage DIFFP-P-
LOW

De-emphasized differential output V TX-DE- 3.0 3.5 4.0 dB 3

voltage (ratio) RATIO-3.5d
B

De-emphasized differential output V TX-DE- 5.5 6.0 6.5 dB 3

voltage (ratio) RATIO-6.0d
B

DC differential Z TX-DIFF- 80.0 100.0 120.0 Ω 4

transmitter impedance DC

Transmitter DC impedance Z TX-DC 40.0 50.0 60.0 Ω 5

1. For recommended operating conditions, see Recommended Operating Conditions.

2. V TX_DIFFp-p = 2 x | V TX-D+ - V TX-D- |
3. Ratio of V TX-DIFFp-p of the second and following bits after a transition divided by the V TX-DIFFp-p of the first bit after a transition.
4. Transmitter DC differential mode low impedance
5. Required transmitter D+ as well as D- DC Impedance during all states.

This table defines the DC electrical characteristics for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The
parameters are specified at the component pins.

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Electrical characteristics

Table 70. PCI Express 2.0 (5 GT/s) differential receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential peak-to-peak voltage V RX- 120.0 1000.0 1200.0 mV 2, 3

DIFFP-P

DC differential input impedance Z RX-DIFF- 80.0 100.0 120.0 Ω 4, 5

DC

DC input impedance Z RX-DC 40.0 50.0 60.0 Ω 6, 3, 5

Powered down DC Z RX-HIGH- 50.0 - - kΩ 7, 8

input impedance IMP-DC

Electrical idle detect threshold V RX-IDLE- 65.0 - 175.0 mV 9, 3

DET-DIFFp-
p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. V RX_DIFFp-p = 2 x | V RX-D+ - V RX-D- |
3. Measured at the package pins with a test load of 50Ω to GND on each pin.
4. Receiver DC differential mode impedance.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all configured lanes on a port.
6. Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).
7. Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
8. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300mV above the receiver ground.
9. V RX-IDLE-DET-DIFFp-p = 2 x | V RX-D+ - V RX-D- |

This table defines the PCI Express 3.0 (8 GT/s) DC electrical characteristics for the differential output at all transmitters. The
parameters are specified at the component pins.

Table 71. PCI Express 3.0 (8 GT/s) differential transmitter output DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Full swing transmitter voltage with V TX-FS- 800.0 - 1300.0 mVp- 2

no TX Eq NO-EQ p

Reduced swing transmitter V TX-RS- 400.0 - 1300.0 mV 2

voltage with no TX Eq NO-EQ

De-emphasized differential output V TX-DE- 3.0 3.5 4.0 dB 3

voltage (ratio) RATIO-3.5d
B

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Electrical characteristics

Table 71. PCI Express 3.0 (8 GT/s) differential transmitter output DC electrical characteristics (SD_OV DD = 1.8V) 1
(continued)

Parameter Symbol Min Typ Max Unit Notes

De-emphasized differential output V TX-DE- 5.5 6.0 6.5 dB 3

voltage (ratio) RATIO-6.0d
B

Minimum swing during EIEOS for V TX- 250.0 - - mVp- 4

full swing EIEOS-FS p

Minimum swing during EIEOS for V TX- 232.0 - - mVp- 4

reduced swing EIEOS-RS p

DC differential Z TX-DIFF- 80.0 100.0 120.0 Ω 5

transmitter impedance DC

Transmitter DC impedance Z TX-DC 40.0 50.0 60.0 Ω 6

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage measurements for V TX-FS-NO-EQ and V TX-RS-NO-EQ are made using the 64-zeroes/64-ones pattern in the
compliance pattern.
3. Ratio of V TX-DIFFp-p of the second and following bits after a transition divided by the V TX-DIFFp-p of the first bit after a transition.
4. Voltage limits comprehend both full swing and reduced swing modes. The transmitter must reject any changes that would
violate this specification. The maximum level is covered in the V TX-FS-NO-EQ measurement which represents the maximum
peak voltage the transmitter can drive. The V TX-EIEOS-FS and V TX-EIEOS-RS voltage limits are imposed to guarantee the EIEOS
threshold of 175 mV P-P at the receiver pin. This parameter is measured using the actual EIEOS pattern that is part of the
compliance pattern and then removing the ISI contribution of the breakout channel.
5. Transmitter DC differential mode low impedance
6. Required transmitter D+ as well as D- DC Impedance during all states.

This table defines the DC electrical characteristics for the PCI Express 3.0 (8 GT/s) differential input at all receivers. The
parameters are specified at the component pins.

Table 72. PCI Express 3.0 (8 GT/s) differential receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

DC differential input impedance Z RX-DIFF- 80.0 100.0 120.0 Ω 2, 3

DC

DC input impedance Z RX-DC 40.0 50.0 60.0 Ω 4, 5, 3

Powered down DC Z RX-HIGH- 50.0 - - kΩ 6, 7

input impedance IMP-DC

Electrical idle detect threshold V RX-IDLE- 65.0 - 175.0 mV 8, 5

DET-DIFFp-
p

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Electrical characteristics

Table 72. PCI Express 3.0 (8 GT/s) differential receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1
(continued)

Parameter Symbol Min Typ Max Unit Notes

Generator launch voltage V RX- - 800.0 - mV 9

LAUNCH-8
G

Eye height (-20dB channel) V RX- 25.0 - - mV 10

SV-8G

Eye height (-12dB channel) V RX- 50.0 - - mV 10

SV-8G

Eye height (-3dB channel) V RX- 200.0 - - mV 10

SV-8G

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Receiver DC differential mode impedance.
3. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all configured lanes on a port.
4. Required receiver D+ as well as D- DC impedance (50 ± 20% tolerance).
5. Measured at the package pins with a test load of 50Ω to GND on each pin.
6. Required receiver D+ as well as D- DC impedance when the receiver terminations do not have power.
7. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300mV above the receiver ground.
8. V RX-IDLE-DET-DIFFp-p = 2 x | V RX-D+ - V RX-D- |
9. Measured at TP1 per PCI Express base specification Rev 3.0.
10. Measured at TP2 per PCI Express base specification Rev 3.0. V RX-SV-8G is tested at three different voltages to ensure the
receiver device under test is capable of equalizing over a range of channel loss profiles. In the parameter names, "SV" refers
to stressed voltage. V RX-SV-8G is referenced to TP2P and is obtained after post-processing data is captured at TP2.

3.23.4.4 PCI Express AC timing specifications

This section describes the PCI Express AC physical layer transmitter specifications for 2.5 GT/s, 5 GT/s, and 8 GT/s.
This table defines the PCI Express 1.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters
are specified at the component pins. The ACtiming specifications do not include RefClk jitter.

Table 73. PCI Express 1.0 (2.5 GT/s) differential transmitter output AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 399.88 400.0 400.12 ps 1

Minimum transmitter eye width T TX-EYE 0.75 - - UI 2, 3, 4, 5

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Electrical characteristics

Table 73. PCI Express 1.0 (2.5 GT/s) differential transmitter output AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

Maximum time between the jitter T TX-EYE- - - 0.125 UI 6, 3, 4, 5

median and maximum deviation MEDIAN-to-
from the median MAX-
JITTER

AC coupling capacitor C TX 75.0 - 200.0 nF 7, 8

1. Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. The maximum transmitter jitter can be derived as T TX-MAX-JITTER = 1 -T TX-EYE = 0.25 UI. Does not include spread-spectrum
or REFCLK jitter. Includes devices random jitter at 10 -12.
3. Specified at the measurement point into a timing and voltage test load and measured over any 250 consecutive
transmitter Uis.
4. A T TX-EYE - 0.75 UI provides for a a total sum of deterministic and random jitter budget of T TX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter Uis. The T TX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as
the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal
as opposed to the averaged time value.
5. See Figure 53.
6. Jiiter is defined as the measurement variation of the crossing points (V TX-DIFFp-p = 0 V) in relation to a recovered transmitter UI.
A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI.
7. All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting
component itself.
8. The chip's SerDes transmitter does not have C TX built-in. An external AC coupling capacitor is required.

This table defines the AC timing specifications for the PCI Express 1.0 (2.5 GT/s) differential input at all receivers. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 74. PCI Express 1.0 (2.5 GT/s) differential receiver input AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 399.88 400.0 400.12 ps 1

Minimum receiver eye width T RX-EYE 0.4 - - UI 2, 3, 4

Maximum time between the jitter T RX-EYE- - - 0.3 UI 3, 4, 5

median and maximum deviation MEDIAN-to-
from the median MAX-
JITTER

1. Each UI is 400 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as T RX-MAX-JITTER
= 1 - T RX-EYE = 0.6 UI.

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Table 74. PCI Express 1.0 (2.5 GT/s) differential receiver input AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

3. Jitter is defined as the measurement variation of the crossing points (V RX-DIFFp-p = 0 V) in relation to a recovered transmitter UI.
A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI.
4. A T RX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The T RX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter median describes the
point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If
the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
5. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and
simulated data.

This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 75. PCI Express 2.0 (5 GT/s) differential transmitter output AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 199.94 200.0 200.06 ps 1

Minimum transmitter eye width T TX-EYE 0.75 - - UI 2, 3, 4, 5

Transmitter deterministic jitter > T TX-HF- - - 0.15 UI -

1.5 MHz DJ-DD

Transmitter RMS jitter < 1.5 MHz T TX-LF- - 3.0 - ps 6

RMS

AC coupling capacitor C TX 75.0 - 200.0 nF 7, 8

1. Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
2. The maximum transmitter jitter can be derived as T TX-MAX-JITTER = 1 -T TX-EYE = 0.25 UI. Does not include spread-spectrum
or REFCLK jitter. Includes devices random jitter at 10 -12.
3. Specified at the measurement point into a timing and voltage test load and measured over any 250 consecutive
transmitter Uis.
4. A T TX-EYE - 0.75 UI provides for a a total sum of deterministic and random jitter budget of T TX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter Uis. The T TX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as
the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal
as opposed to the averaged time value.
5. See Figure 53.
6. Reference input clock RMS jitter (< 1.5 MHz) at pin < 1 ps.

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Electrical characteristics

Table 75. PCI Express 2.0 (5 GT/s) differential transmitter output AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

7. All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting
component itself.
8. The chip's SerDes transmitter does not have C TX built-in. An external AC coupling capacitor is required.

This table defines the AC timing specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 76. PCI Express 2.0 (5 GT/s) differential receiver input AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 199.4 200.0 200.06 ps 1

Max receiver inherent timing error T RX-TJ-CC - - 0.4 UI -

Max receiver inherent T RX-DJ- - - 0.3 UI -

deterministic timing error DD-CC

1. Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.

This table defines the PCI Express 3.0 (8 GT/s) AC specifications for the differential output at all transmitters. The parameters are
specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 77. PCI Express 3.0 (8 GT/s) differential transmitter output AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 124.9625 125.0 125.0375 ps 1

AC coupling capacitor C TX 176.0 - 265.0 nF 2, 3

Transmitter uncorrelated total jitter T TX-UTJ - - 31.25 ps p- -

p

Transmitter uncorrelated T TX-UDJ- - - 12.0 ps p- -

deterministic jitter DD p

Total uncorrelated pulse width T TX-UPW- - - 24.0 ps p- 4, 5

jitter (PWJ) TJ p

Deterministic data dependent jitter T TX-UPW- - - 10.0 ps p- 4, 5

(DjDD) uncorrelated pulse width DJDD p
jitter (PWJ)

Data-dependent jitter T TX-DDJ - - 18.0 ps p- 4, 5, 6

p

1. Each UI is 125 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.

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Electrical characteristics

Table 77. PCI Express 3.0 (8 GT/s) differential transmitter output AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

2. All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting
component itself.
3. The chip's SerDes transmitter does not have C TX built-in. An external AC coupling capacitor is required.
4. Measured with optimized preset value after de-embedding to transmitter pin.
5. PWJ parameters shall be measured after data-dependent jitter (DDJ) separation.
6. The AC specifications do not include Refclk jitter

This table defines the AC timing specifications for the PCI Express 3.0 (8 GT/s) differential input at all receivers. The parameters
are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 78. PCI Express 3.0 (8 GT/s) differential receiver input AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 124.9625 125.0 125.0375 ps 1, 2

Eye width at TP2P T RX- 0.3 - 0.35 UI 2

SV-8G

Differential mode interference V RX-SV- 14.0 - - mV 3

DIFF-8G

Sinusoidal jitter at 100 MHz T RX-SV- - - 0.1 UI p-p 4, 5

SJ-8G

Random jitter T RX-SV- - - 2.0 ps 6, 5

RJ-8G RMS

1. Each UI is 125 ps ± 300 ppm. UI does not account for spreadspectrum clock dictated variations.
2. T RX-SV is referenced to TP2P and is obtained after post-processing data is captured at TP2. T RX-SV includes the effects of
applying the behavioral receiver model and receiver behavioral equalization.
3. Frequency = 2.1GHz. V RX-SV-DIFF-8G voltage may need to be adjusted over a wide range for the different loss
calibration channels.
4. Fixed at 100 MHz. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency.
5. See Figure 54.
6. Random jitter spectrally flat before filtering. Random jitter (Rj) is applied over the following range: The low frequency limit may
be between 1.5 and 10 MHz, and the upper limit is 1.0 GHz. Rj may be adjusted to meet the 0.3 UI value for T RX-SV-8G.

The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure. Note that the allowance
of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may
benefit from D+ and D- not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state
where the measurement point is located, the measurement point is assumed to be the D+ and Dpackage pins.

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Electrical characteristics

D + package pin

C = CTX

Transmitter
silicon
+ package

C = CTX

D - package pin
R = 50 Ω R = 50 Ω

Figure 53. Test and measurement load

This figure shows the swept sinusoidal jitter mask.

Figure 54. Swept sinusoidal jitter mask

3.23.5 Serial ATA (SATA)

3.23.5.1 SATA DC electrical characteristics

This table provides the differential transmitter output DC characteristics for the SATAinterface at Gen1i/1m or 1.5
Gbits/s transmission.

Table 79. SATA Gen 1i/1m 1.5G transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential V 400.0 500.0 600.0 mV Terminated by

output voltage SATA_TXDI p-p a 50Ω load.
FF

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Electrical characteristics

Table 79. SATA Gen 1i/1m 1.5G transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential Z 85.0 100.0 115.0 Ω DC

pair impedance SATA_TXDI impedance.
FFIM

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Terminated by a 50Ω load.
3. DC impedance.

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface.

Table 80. SATA Gen 1i/1m 1.5G receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage V 240.0 500.0 600.0 mV 2

SATA_RXDI p-p
FF

Differential receiver Z 85.0 100.0 115.0 Ω 3

input impedance SATA_RXS
EIM

OOB signal detection threshold V 50.0 120.0 240.0 mV -

SATA_OOB p-p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage relative to common of either signal comprising a differential pair.
3. DC impedance.

This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i/2m or 3.0
Gbits/s transmission.

Table 81. SATA Gen 2i/2m 3G transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential V 400.0 - 700.0 mV Terminated by

output voltage SATA_TXDI p-p a 50Ω load.
FF

Transmitter differential Z 85.0 100.0 115.0 Ω DC

pair impedance SATA_TXDI impedance.
FFIM

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Terminated by a 50Ω load.
3. DC impedance.

This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.

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Table 82. SATA Gen 2i/2m 3G receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage V 240.0 - 750.0 mV 2

SATA_RXDI p-p
FF

Differential receiver Z 85.0 100.0 115.0 Ω 3

input impedance SATA_RXS
EIM

OOB signal detection threshold V 75.0 120.0 240.0 mV -

SATA_OOB p-p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage relative to common of either signal comprising a differential pair.
3. DC impedance.

This table provides the differential transmitter output DC characteristics for the SATA interface at Gen 3i transmission.

Table 83. SATA Gen 3i transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Transmitter differential V 240.0 - 900.0 mV Terminated by

output voltage SATA_TXDI p-p a 50Ω load.
FF

Transmitter differential Z 85.0 100.0 115.0 Ω DC

pair impedance SATA_TXDI impedance.
FFIM

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Terminated by a 50Ω load.
3. DC impedance.

This table provides the Gen 3i differential receiver input DC characteristics for the SATAinterface.

Table 84. SATA Gen 3i receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential input voltage V 240.0 - 1000.0 mV 2

SATA_RXDI p-p
FF

Differential receiver Z 85.0 100.0 115.0 Ω 3

input impedance SATA_RXS
EIM

Table continues on the next page...

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Table 84. SATA Gen 3i receiver input DC electrical characteristics (SD_SV DD = 0.9V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

OOB signal detection threshold V 75.0 120.0 200.0 mV -

SATA_OOB p-p

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Voltage relative to common of either signal comprising a differential pair.
3. DC impedance.

3.23.5.2 SATA AC timing specifications

This table provides the AC requirements for the SATA reference clock. These requirements must be guaranteed by the customer’s
application design.

Table 85. SATA reference clock input requirements

Parameter Symbol Min Typ Max Unit Notes

SDn_REF_CLKn_P/ t CLK_REF - 100 / 125 - MHz 1

SDn_REF_CLKn_N
frequency range

SDn_REF_CLK z_P/ t CLK_TOL -350.0 - 350.0 ppm -

SDn_REF_CLKn_N
frequency tolerance

SDn_REF_CLKn_P/ t 40 50 60 % 2
SDn_REF_CLKn_N reference CLK_DUTY
clock duty cycle

SDn_REF_CLKn_P/ t CLK_CJ - - 100.0 ps 3

SDn_REF_CLKn_N cycle-to-
cycle clock jitter (period jitter)

SDn_REF_CLKn_P/ t CLK_PJ -50.0 - 50.0 - 3, 4, 5

SDn_REF_CLKn_N total
reference clock jitter,
phase jitter (peak-to-peak)

1. Caution: Only 100 MHz and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.
2. Measurement taken from differential waveform.
3. At RefClk input.
4. In a frequency band from 150 kHz to 15 MHz at BER of 10 -12.
5. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 1i/1m or 1.5 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.

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Table 86. Gen 1i/1m 1.5 G transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 666.4333 666.6667 670.2333 - -

Channel speed t - 1.5 - Gbps -

CH_SPEED

Total jitter, data-data 5 UI U - - 0.355 UI p-p 1

SATA_TXTJ
5UI

Total jitter, data-data 250 UI U - - 0.47 UI p-p 1

SATA_TXTJ
250UI

Deterministic jitter, data-data 5 UI U - - 0.175 UI p-p 1

SATA_TXDJ
5UI

Deterministic jitter, data-data U - - 0.22 UI p-p 1

250 UI SATA_TXDJ
250UI

1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern.

This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing
specifications do not include RefClk jitter.

Table 87. Gen 1i/1m 1.5 G receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 666.4333 666.6667 670.2333 - -

Total jitter, data-data 5 UI U - - 0.43 UI p-p Measured at

SATA_RXTJ the receiver.
5UI

Total jitter, data-data 250 UI U - - 0.6 UI p-p Measured at

SATA_RXTJ the receiver.
250UI

Deterministic jitter, data-data 5 UI U - - 0.25 UI p-p Measured at

SATA_RXDJ the receiver.
5UI

Deterministic jitter, data-data U - - 0.35 UI p-p Measured at

250 UI SATA_RXDJ the receiver.
250UI

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 2i/2m or 3.0 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.

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Table 88. Gen 2i/2m 3 G transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 333.2167 333.3333 335.1167 - -

Channel speed t - 3.0 - Gbps -

CH_SPEED

Total jitter, f C3DB = f BAUD ÷ 500 U - - 0.37 UI p-p 1

SATA_TXTJ
fB/500

Total jitter, f C3DB = f BAUD ÷ 1667 U - - 0.55 UI p-p 1

SATA_TXTJ
fB/1667

Deterministic jitter, f C3DB = f BAUD U - - 0.19 UI p-p 1

÷ 500 SATA_TXTJ
fB/500

Deterministic jitter, f C3DB = f BAUD U - - 0.35 UI p-p 1

÷ 1667 SATA_TXTJ
fB/1667

1. Measured at transmitter output pins peak-to-peak phase variation; random data pattern.

This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i/2m or 3.0 Gbits/s
transmission. The AC timing specifications do not include RefClk jitter.

Table 89. Gen 2i/2m 3 G receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI 333.2167 333.3333 335.1167 - -

Total jitter, f C3DB = f BAUD ÷ 500 U - - 0.6 UI p-p Measured at

SATA_RXTJ the receiver.
fB/500

Total jitter, f C3DB = f BAUD ÷ 1667 U - - 0.65 UI p-p Measured at

SATA_RXTJ the receiver.
fB/1667

Deterministic jitter, f C3DB = f BAUD U - - 0.42 UI p-p Measured at

÷ 500 SATA_RXTJ the receiver.
fB/500

Deterministic jitter, f C3DB = f BAUD U - - 0.35 UI p-p Measured at

÷ 1667 SATA_RXTJ the receiver.
fB/1667

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen 3i transmission. The AC
timing specifications do not include RefClk jitter.

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Table 90. Gen 3i transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Unit Interval UI 166.6083 167.6667 167.5583 -

Channel speed t CH_SPEED - 6.0 - Gbps

Total jitter before and after compliance J T - - 0.52 UI p-p

interconnect channel

Random jitter before compliance JR - - 0.18 UI p-p

interconnect channel

This table provides the differential receiver input AC characteristics for the SATA interface at Gen 3i transmission The AC timing
specifications do not include RefClk jitter.

Table 91. Gen 3i receiver AC timing specifications

Parameter Symbol Min Typ Max Unit

Unit Interval UI 166.6083 167.6667 167.5583 -

Total jitter before and after compliance J T - - 0.6 UI p-p

interconnect channel

Random jitter before compliance JR - - 0.18 UI p-p

interconnect channel

3.23.6 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in 4-wire AC-coupled
SGMII serial link connection example, where CTX is the external (on board) AC-coupled capacitor. Each SerDes transmitter
differential pair features 100-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die
termination to XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in SerDes transmitter and receiver
reference circuits.

3.23.6.1 SGMII DC electrical characteristics

This table describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N), as shown in the SGMII transmitter DC measurement circuit
figure below.

Table 92. SGMII DC transmitter electrical characteristics (SD_OVDD = 1.8V) 1, 12, 13

Parameter Symbol Min Typ Max Unit Notes

Output high voltage VOH - - 1.5 x |VOD|-max mV 2

Output low voltage VOL |VOD|-min/2 - - mV 2

Output differential voltage |VOD| 320.0 500.0 725.0 mV 3, 4, 5

Output differential voltage |VOD| 293.8 459.0 665.6 mV 3, 4, 6

Table continues on the next page...

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Table 92. SGMII DC transmitter electrical characteristics (SD_OVDD = 1.8V) 1, 12, 13 (continued)

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage |VOD| 266.9 417.0 604.7 mV 3, 4, 7

Output differential voltage |VOD| 240.6 376.0 545.2 mV 3, 4, 8

Output differential voltage |VOD| 213.1 333.0 482.9 mV 3, 4, 9

Output differential voltage |VOD| 186.9 292.0 423.4 mV 3, 4, 10

Output differential voltage |VOD| 160.0 250.0 362.5 mV 3, 4, 11

Output impedance (differential) RO 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. This does not align to DC-coupled SGMII.
3. |VOD| = |VSD_TXn_P - VSD_TXn_N|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x |VOD|.
4. The |VOD| value shown in Typ column is based on the condition of SD_OVDD-Typ, no common mode offset variation. SerDes
transmitter is terminated with 100-Ω differential load between SDn_TXn_P and SDn_TXn_N.
5. LNmTECR0[EQ_AMP_RED]=0b000000
6. LNmTECR0[EQ_AMP_RED]=0b000001
7. LNmTECR0[EQ_AMP_RED]=0b000011
8. LNmTECR0[EQ_AMP_RED]=0b000010
9. LNmTECR0[EQ_AMP_RED]=0b000110 (default)
10. LNmTECR0[EQ_AMP_RED]=0b000111
11. LNmTECR0[EQ_AMP_RED]=0b010000
12. See Figure 55.
13. See Figure 56.

This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.

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SDn_TXn_P SDn_RXn_P
CTX

50 Ω

Transmitter 100 Ω Receiver

CTX
SDn_TXn_N SDn_RXn_N
50 Ω

SGMII
SerDes Interface
SDn_RXn_P SDn_TXn_P
CTX

50 Ω

Receiver Transmitter
100 Ω

CTX
SDn_RXn_N SDn_TXn_N
50 Ω

Figure 55. 4-wire AC-coupled SGMII serial link connection example

This figure shows the SGMII transmitter DC measurement circuit.

SGMII
SerDes Interface

SDn_TXn_P

50 Ω

Transmitter 100 Ω VOD

50 Ω

SDn_TXn_N

Figure 56. SGMII transmitter DC measurement circuit

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This table lists the SGMII DC receiver electrical characteristics. Source synchronousclocking is not supported. Clock is recovered
from the data.

Table 93. SGMII DC receiver electrical characteristics (SD_SVDD = 0.9V) 1

Parameter Symbol Min Max Unit Notes

DC input voltage range VIN N/A N/A - 2

Input differential voltage (default) VRX_DIFFp-p 100.0 1200.0 mV 3, 5

Input differential voltage VRX_DIFFp-p 175.0 1200.0 mV 3, 6

Loss of signal threshold (default) VLOS 30.0 100.0 mV 4, 5

Loss of signal threshold VLOS 65.0 175.0 mV 4, 6

Receiver differential input impedance ZRX_DIFF 80.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Input must be externally AC coupled.
3. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
4. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express.
5. LNmRGCR1[DATA_LOST_TH_SEL] = 001
6. LNmRGCR1[DATA_LOST_TH_SEL] = 100

3.23.6.2 SGMII AC timing specifications

This table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing
specifications do not include RefClk jitter.

Table 94. SGMII transmitter AC timing specifications 4

Parameter Symbol Min Typ Max Unit Notes

Deterministic jitter JD - - 0.17 UI p-p -

Total jitter JT - - 0.35 UI p-p 1

Unit interval: 1.25 GBaud (SGMII) UI 800-100ppm 800.0 800+100ppm ps 2

AC coupling capacitor C TX 10.0 - 200.0 nF 3

1. See Figure 58.

2. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter output.
4. See Figure 57.

Transmitter and receiver AC characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N) or at the
receiver inputs (SDn_RXn_P and SDn_RXn_N) respectively, as shown in this figure.

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D + package pin

C = CTX

Transmitter
silicon
+ package

C = CTX

D - package pin
R = 50 Ω R = 50 Ω

Figure 57. SGMII AC test/measurement load

This table provides the SGMII receiver AC timing specifications. TheAC timing specifications do not include RefClk jitter. Source
synchronous clocking is notsupported. Clock is recovered from the data.

Table 95. SGMII receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Deterministic jitter tolerance JD - - 0.37 UI p-p 1

Combined deterministic and J DR - - 0.55 UI p-p 1

random jitter tolerance

Total jitter tolerance JT - - 0.65 UI p-p 1, 2, 3

Unit interval: 1.25 GBaud (SGMII) UI 800-100ppm 800.0 800+100ppm ps 1

Bit error ratio BER - - 10 -12 - -

1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of the Single-frequency sinusoidal jitter limits
figure shown below. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise,
crosstalk and other variable system effects.
3. See Figure 58.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of this figure.

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8.5 UI p-p

Sinuosidal
Jitter 20 dB/dec
Amplitude

0.10 UI p-p

baud/142000 Frequency baud/1667 20 MHz

Figure 58. Single-frequency sinusoidal jitter limits

3.23.7 XFI

3.23.7.1 XFI DC electrical characteristics

This table defines the XFI transmitter DC electrical characteristics.

Table 96. XFI transmitter DC electrical characteristics (SD_OVDD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage VTX-DIFF 360.0 - 770.0 mV 2

De-emphasized differential output VTX-DE- 0.6 1.1 1.6 dB 3

voltage (ratio at 1.14dB) RATIO-1.14
dB

De-emphasized differential output VTX-DE- 3.0 3.5 4.0 dB 4

voltage (ratio at 3.5dB) RATIO-3.5d
B

De-emphasized differential output VTX-DE- 4.1 4.6 5.1 dB 5

voltage (ratio at 4.66dB) RATIO-4.66
dB

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Table 96. XFI transmitter DC electrical characteristics (SD_OVDD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

De-emphasized differential output VTX-DE- 5.5 6.0 6.5 dB 6

voltage (ratio at 6.0dB) RATIO-6.0d
B

De-emphasized differential output VTX-DE- 9.0 9.5 10.0 dB 7

voltage (ratio at 9.5dB) RATIO-9.5d
B

Differential resistance TRD 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. LNmTECR0[EQ_AMP_RED]= 000111
3. LNmTECR0[EQ_POST1Q]= 00011
4. LNmTECR0[EQ_POST1Q]= 01000
5. LNmTECR0[EQ_POST1Q]= 01010
6. LNmTECR0[EQ_POST1Q]= 01100
7. LNmTECR0[EQ_POST1Q]= 10000

This table defines the XFI receiver DC electrical characteristics.

Table 97. XFI receiver DC electrical characteristics (SD_SVDD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential resistance RRD 80.0 100.0 120.0 Ω -

Input differential voltage VRX-DIFF 110.0 - 1050.0 mV 2

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Measured at receiver.

3.23.7.2 XFI AC timing specifications

This table defines the XFI transmitter AC timing specifications. RefClk jitter is not included.

Table 98. XFI transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Transmitter baud Rate TBAUD 10.3125-100ppm 10.3125 10.3125+100ppm Gb/s

Unit Interval UI - 96.96 - ps

Deterministic jitter DJ - - 0.15 UI p-p

Total jitter tolerance TJ - - 0.3 UI p-p

This table defines the XFI receiver AC timing specifications. RefClk jitter is not included.

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Table 99. XFI receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI - 96.96 - ps -

Receiver baud rate RBAUD 10.3125-100pp 10.3125 10.3125+100pp Gb/s -

m m

Total non-EQJ jitter TNON-EQJ - - 0.45 UI p-p 1

Total jitter tolerance TJ - - 0.65 UI p-p 1, 2

1. The total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distortion (DCD), Periodic Jitter (PJ), and Inter-Symbol
Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), and periodic jitter (PJ). Non-EQJ
jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under test.
It can exhibit a wide spectrum. Non - EQJ = TJ - ISI = RJ + DCD + PJ.
2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The
channel crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude will be required for
performance optimization.
3. See Figure 59.

This figure shows the sinusoidal jitter tolerance of XFI receiver.

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1.13x 0.2 + 0.1 , f in MHz

f
Sinuosidal Jitter Tolerance (UIp-p)

-20 dB/Dec

0.17

0.05

0.04 4 8 27.2 80

Frequency (MHz)

Figure 59. XFI host receiver input sinusoidal jitter tolerance

3.23.8 SFI
This section presents the SFI+ specifications at data rate 10.3125Gb/s.

3.23.8.1 SFI DC electrical characteristics

This table defines the SFI+ transmitter DC electrical characteristics.

Table 100. SFI+ host transmitter DC electrical characteristics (SD_OVDD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage VTX-DIFF 190 - 700 mVp-p 2

De-emphasized differential output VTX-DE- 0.6 1.1 1.6 dB 3

voltage (ratio at 1.14dB) RATIO-1.14
dB

De-emphasized differential output VTX-DE- 3 3.5 4 dB 4

voltage (ratio at 3.5dB) RATIO-3.5d
B

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Table 100. SFI+ host transmitter DC electrical characteristics (SD_OVDD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

De-emphasized differential output VTX-DE- 4.1 4.6 5.1 dB 5

voltage (ratio at 4.66dB) RATIO-4.66
dB

De-emphasized differential output VTX-DE- 5.5 6.0 6.5 dB 6

voltage (ratio at 6.0dB) RATIO-6.0d
B

De-emphasized differential output VTX-DE- 9 9.5 10 dB 7

voltage (ratio at 9.5dB) RATIO-9.5d
B

Differential resistance TRD 80 100 120 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. LNmTECR0[EQ_AMP_RED]= 000111
3. LNmTECR0[EQ_POST1Q]= 00011
4. LNmTECR0[EQ_POST1Q]= 01000
5. LNmTECR0[EQ_POST1Q]= 01010
6. LNmTECR0[EQ_POST1Q]= 01100
7. LNmTECR0[EQ_POST1Q]= 10000

This table defines the SFI+ host receiver DC electrical characteristics.

Table 101. SFI+ host receiver DC electrical characteristics (SD_SVDD = 0.9V) 1

Parameter Symbol Min Typ Max Unit Notes

Differential resistance RRD 80 120 Ω -

Input differential voltage VRX-DIFF 300 - 850 mVp-p -

1. For recommended operating conditions, see Recommended Operating Conditions.

3.23.8.2 SFI AC timing specifications

This table defines the SFI+ host transmitter AC timing specifications.

Table 102. SFI+ host transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Transmitter baud Rate TBAUD 10.3125-100ppm 10.3125 10.3125+100ppm Gb/s

Unit Interval UI - 96.96 - ps

Data dependent jitter DDJ - - 0.1 UI p-p

Table continues on the next page...

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Table 102. SFI+ host transmitter AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit

Data dependent pulse width shrinkage DDPWS 0.055 UI p-p

Uncorrelated jitter UJ 0.023 UI

(RMS)

Total jitter tolerance TJ - - 0.28 UI p-p

1. Duty cycle distortion (DCD) and Pulse Width Shrinkage (DDPWS) are components of DDJ. DDJ is the range (max-min) of the
timing variations.
2. The AC specifications do not include Refclk jitter.

This table defines the SFI+ host receiver AC timing specifications.

Table 103. SFI+ host receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Unit Interval UI - 96.96 - ps -

Receiver baud rate RBAUD 10.3125-100pp 10.3125 10.3125+100pp Gb/s -

m m

99% jitter J2 0.42 1

Pulse width shrinkage jitter DDPWS - - 0.3 UI p-p 2

Total jitter TJ - - 0.7 UI p-p

1. The 99% jitter is per SFF-8431 Rev4.1 and includes sinusoidal jitter, per Figure 60.
2. In practice the test implementer may trade DDPWS with other pulse width shrinkage from the sinusoidal interferer per
SFF-8431 Rev4.1.
3. The SFI total channel Link Budget when measured with Host Compliance board is 9.0 dB @5.5GHz. The channel
loss including connector measured with Host Compliance board @ 5.5GHz is 6.5dB. The penalty for reflections and other
impairments is 2.5dB. Manual tuning of TX Equalization and amplitude will be required for performance optimization.
4. The AC specifications do not include Refclk jitter.

This figure shows the sinusoidal jitter tolerance of SFI receiver.

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Figure 60. SFI+ SR and LR host receiver input datacom sinusoidal jitter tolerance

3.23.9 SFP+ direct attach copper

SFP+ direct attach copper is supported for passive copper cable compliant per SFF-8472.

3.23.9.1 SFP+ direct attach copper DC electrical characteristics

The SFP+ host supporting direct attach cables must meet transmitter output DC specifications in Table 100 at reference point B
per SFF-8472. In addition, the SFP+ host transmitter must meet the specifications in the table below.
This table defines the SFP+ host transmitter output DC specifications.

Table 104. SFP+ host transmitter output DC electrical characteristics at B for Cu (SD_OVDD = 1.8V) 1

Parameters - B Symbol Min Typ Max Unit

Voltage modulation amplitude (p-p) VMA 300 mV

Transmitter Qsq Qsq 63.1

Output AC common mode voltage 12.0 mV

(RMS)

Host output TWDPc TWDPc 10.7 dBe

1. For recommended operating conditions, see Recommended Operating Conditions.

2. Qsq = 1/RN if the one level and zero level noises are identical. RN is relative noise per SFF-8472.
3. Host electrical output measured with LRM 14 taps FFE and 5 taps DFE Equalizer with PRBS9 for copper direct attach stressor.
4. The TWDPc is the host transmitter penalty for copper cable stressor.

The SFP+ host supporting direct attach cables must meet the receiver output DC specifications in Table 101.

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3.23.9.2 SFP+ direct attach AC timing specifications

The SFP+ host supporting direct attach cables must meet the transmitter output AC specifications in Table 102 at reference point
B per SFF-8472.
The SFP+ host supporting direct attach cables must meet the AC specifications in Table 103 in at reference point B per SFF-8472.
In addition, the SFP+ host receiver must meet required 1×10-12 BER when tested with the stressed signal described per SFF-847.

3.23.10 1000Base-KX

3.23.10.1 1000Base-KX DC electrical characteristics

This table describes the 1000Base-KX SerDes transmitter DC specification at TP1 per IEEE Std 802.3-2015. Transmitter DC
characteristics are measured at the transmitter outputs (SDn_TXn_P and SDn_TXn_N).

Table 105. 1000Base-KX transmitter DC electrical characteristics (SD_OVDD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage VTX-DIFFp- 800.0 - 1600.0 mV 2

p

Differential resistance TRD 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. SRDSxLNmTECR0[EQ_AMP_RED]=00_0000

This tableprovides the 1000Base-KX receiver DC timing specifications.

Table 106. 1000Base-KX receiver DC electrical characteristics (SD_SVDD = 0.9V) 1

Parameter Symbol Min Max Unit

Input differential voltage VRX-DIFFp-p - 1600.0 mV

Differential resistance TRDIN 80.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.23.10.2 1000Base-KX AC timing specifications

This table defines the 1000Base-KX transmitter AC timing specifications.

Table 107. 1000Base-KX transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Baud rate TBAUD 1.25-100ppm 1.25 1.25+100ppm Gb/s -

Uncorrelated high probability jitter/ TUHPJ / - - 0.15 UI p-p -

Random Jitter TRJ

Deterministic jitter tolerance TDJ - - 0.1 UI p-p -

Total jitter tolerance TTJ - - 0.25 UI p-p 1

Table continues on the next page...

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Table 107. 1000Base-KX transmitter AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

1. Total jitter is specified at a BER of 10 -12.

This table defines the 1000Base-KX receiver AC timing specifications.

Table 108. 1000Base-KX receiver AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

Baud rate RBAUD 1.25-100ppm 1.25 1.25+100ppm Gb/s -

Total jitter tolerance RTJ - - Per IEEE UI p-p 1

802.3ap-clause
70.

Random jitter RRJ - - 0.15 UI p-p 2

Sinusoidal jitter (maximum) RSJ-max - - 0.1 UI p-p 1

1. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE
Std 802.3ap-2007.
2. Random jitter is specified at a BER of 10 -12.

3.23.11 10GBase-KR

3.23.11.1 10GBase-KR clocking requirements for SDn_REF_CLKn and SDn_REF_CLKn_B

Only SerDes 1 and SerDes 2 may be used for SerDes 10GBase-KR configurations based on the RCW Configuration
field SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks .

3.23.11.2 10GBase-KR DC electrical characteristics

This table defines the 10GBase-KR transmitter DC electrical characteristics.

Table 109. 10GBase-KR transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit Notes

Output differential voltage V TX-DIFF 800.0 - 1200.0 mV 2

De-emphasized differential output V TX-DE- 0.6 1.1 1.6 dB 3

voltage (ratio at 1.14dB) RATIO-1.14
dB

De-emphasized differential output V TX-DE- 3.0 3.5 4.0 dB 4

voltage (ratio at 3.5dB) RATIO-3.5d
B

Table continues on the next page...

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Table 109. 10GBase-KR transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1 (continued)

Parameter Symbol Min Typ Max Unit Notes

De-emphasized differential output V TX-DE- 4.1 4.6 5.1 dB 5

voltage (ratio at 4.66dB) RATIO-4.66
dB

De-emphasized differential output V TX-DE- 5.5 6.0 6.5 dB 6

voltage (ratio at 6.0dB) RATIO-6.0d
B

De-emphasized differential output V TX-DE- 9.0 9.5 10.0 dB 7

voltage (ratio at 9.5dB) RATIO-9.5d
B

Differential resistance T RD 80.0 100.0 120.0 Ω -

1. For recommended operating conditions, see Recommended Operating Conditions.

2. LNmTECR0[EQ_AMP_RED]= 000000
3. LNmTECR0[EQ_POST1Q]= 00011
4. LNmTECR0[EQ_POST1Q]= 01000
5. LNmTECR0[EQ_POST1Q]= 01010
6. LNmTECR0[EQ_POST1Q]= 01100
7. LNmTECR0[EQ_POST1Q]= 10000

This table defines the 10GBase-KR receiver DC electrical characteristics.

Table 110. 10GBase-KR receiver DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Max Unit

Input differential voltage V RX-DIFF - 1200.0 mV

Differential resistance R RD 80.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.23.11.3 10GBase-KR AC timing specifications

This table defines the 10GBase-KR transmitter AC timing specifications. RefClk jitter is not included.

Table 111. 10GBase-KR transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Transmitter baud rate T BAUD 10.3125 - 100 ppm 10.3125 10.3125 + 100 ppm GBd

Deterministic jitter T_DJ - - 0.15 UI p-p

Total jitter T_TJ - - 0.3 UI p-p

This table defines the 10GBase-KR receiver AC timing specifications. RefClk jitter is not included.

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Table 112. 10GBase-KR receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Receiver baud rate R BAUD 10.3125 - 100 10.3125 10.3125 + 100 GBd -
ppm ppm

Total jitter TJ - - 1.0 UI p-p 1, 2

Random jitter RJ - - 0.13 UI p-p 1

Sinusoidal jitter, maximum S J-max - - 0.115 UI p-p 1

Duty cycle distortion D CD - - 0.035 UI p-p 1

1. The AC specifications do not include Refclk jitter.

2. The total applied Jitter Tj = ISI + Rj + DCD + Sj-max, where ISI is jitter due to frequency dependent loss.
3. TX equalization and amplitude tuning is through software for performance optimization, as in NXP provided SDKs.

3.23.12 CAUI-4, 50GAUI-2, and 25G-AUI interface

The IEEE Std 802.3-2015. 100 Gb/s Attachment Unit Interface (CAUI-4) is intended for use as a chip-to-chip or a chip-to-module
interface. The four-lane version (CAUI-4) in Annex 83D and Annex 83E supports 100GbE. Each lane operates at 25.78125
GBaud. 50GAUI-2 supports 50GbE (2 lanes, each running @ 25.78125 GBaud) and 25G-AUI supports 25GbE (single lane @
25.78125 GBaud) .

3.23.12.1 CAUI-4/50GAUI-2/25G-AUI DC electrical characteristics

This table defines the CAUI-4/50GAUI-2/25G-AUI transmitter DC electrical characteristics.

Table 113. CAUI-4/50GAUI-2/25G-AUI transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit

Differential peak-to-peak output voltage V TX-DIFF 1200.0 mV

Differential peak-to-peak output voltage V TX-DIS- 0.0 - 30.0 mV

transmitter disabled DIFF

DC common mode voltage V CM 0.0 - 1.9 V

Output waveform steady state voltage Vf 0.4 - 0.6 V

Output waveforem linear fit pulse peak V P(k) 0.71 * V f - - V

Differential resistance Z TX-DIFF-DC 80.0 100.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

This table defines the CAUI-4/50GAUI-2/25G-AUI receiver DC electrical characteristics.

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Table 114. CAUI-4/50GAUI-2/25G-AUI receiver DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Max Unit

Differential resistance Z RX-DIFF-DC 80.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.23.12.2 CAUI-4/50GAUI-2/25G-AUI AC timing characteristics

This table defines the CAUI-4/50GAUI-2/25G-AUI transmitter AC timing specifications.

Table 115. CAUI-4/50GAUI-2/25G-AUI transmitter AC timing specifications 1, 2

Parameter Symbol Min Typ Max Unit

Transmitter baud Rate T BAUD 25.78125-100ppm 25.78125 25.78125+100ppm Gb/s

AC common mode output voltage RMS V CM - - 0.012 V

Bounded uncorrelated jitter T BUJ 0.1 UI p-p

Even-odd jitter T EOJ - - 0.035 UI

Total uncorrelated jitter T TU J - - 0.26 UI p-p

Signal-to-noise-and-distortion ratio SINAD 27.0 - - dB

1. See Figure 61.

2. See Figure 62.

This figure shows the applied sinusoidal jitter tolerance of the CAUI-4/50GAUI-2/25G-AUI receiver.

Figure 61. CAUI-4/50GAUI-2/25G-AUI receiver applied sinusoidal jitter

This figure provides the ISI channel loss profile.

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Figure 62. CAUI-4/50GAUI-2/25G-AUI chip-to-chip channel insertion

3.23.13 USXGMII interface (USXGMII)

3.23.13.1 USXGMII DC electrical characteristics

This table defines the 10G-SXGMII transmitter DC electrical characteristics.

Table 116. 10G-SXGMII transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit

Output differential voltage V TX-DIFF 800.0 - 1200.0 mV

De-emphasized differential output V TX-DE- 0.6 1.1 1.6 dB

voltage (ratio at 1.14dB) RATIO-1.14dB

De-emphasized differential output V TX-DE- 3.0 3.5 4.0 dB

voltage (ratio at 3.5dB) RATIO-3.5dB

De-emphasized differential output V TX-DE- 4.1 4.6 5.1 dB

voltage (ratio at 4.66dB) RATIO-4.66dB

De-emphasized differential output V TX-DE- 5.5 6.0 6.5 dB

voltage (ratio at 6.0dB) RATIO-6.0dB

De-emphasized differential output V TX-DE- 9.0 9.5 10.0 dB

voltage (ratio at 9.5dB) RATIO-9.5dB

Differential resistance T RD 80.0 100.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

This table defines the 10G-SXGMIIreceiver DC electrical characteristics.

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Table 117. 10G-SXGMII receiver DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Max Unit

Input differential voltage V RX-DIFF - 1200.0 mV

Differential resistance R RD 80.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

3.23.13.2 USXGMII AC timing characteristics

This table defines the 10G-SXGMIItransmitter AC timing specifications. RefClk jitter is not included.

Table 118. 10G-SXGMII transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Transmitter baud rate T BAUD 10.3125 - 100 ppm 10.3125 10.3125 + 100 ppm GBd

Uncorrelated high probability jitter/ T UHPJ/T RJ - - 0.15 UI p-p

Random Jitter

Deterministic jitter DJ - - 0.15 UI p-p

Total jitter TJ - - 0.3 UI p-p

This table defines the 10G-SXGMIIreceiver AC timing specifications. RefClk jitter is not included.

Table 119. 10G-SXGMII receiver AC timing specifications 3

Parameter Symbol Min Typ Max Unit Notes

Receiver baud rate R BAUD 10.3125 - 100 10.3125 10.3125 + 100 GBd -
ppm ppm

Total jitter TJ - - 1.0 UI p-p 1, 2

Random jitter RJ - - 0.13 UI p-p 1

Sinusoidal jitter, maximum S J-max - - 0.115 UI p-p 1

Duty cycle distortion D CD - - 0.035 UI p-p 1

1. The AC specifications do not include Refclk jitter.

2. The total applied Jitter Tj = ISI + Rj + DCD + Sj-max, where ISI is jitter due to frequency dependent loss.
3. TX equalization and amplitude tuning is through software for performance optimization, as in NXP provided SDKs.

3.23.14 XLAUI interface (XLAUI)

The XLAUI standard achieves 40 Gbps with four 10.3125 Gbps lanes.

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3.23.14.1 XLAUI DC electrical characteristics

This table defines the XLAUI transmitter DC electrical characteristics. The parameters are specified at the transmitter compliance
point per IEEE Std 802.3-2015.

Table 120. XLAUI transmitter DC electrical characteristics (SD_OV DD = 1.8V) 1

Parameter Symbol Min Typ Max Unit

Differential peak-to-peak output voltage V TX-DIFF 760.0 mV p-

p

De-emphasis 4.4 - 7.0 dB

Differential resistance Z TX-DIFF-DC 80.0 100.0 120.0 Ω

1. For recommended operating conditions, see Recommended Operating Conditions.

This table defines the XLAUI receiver DC electrical characteristics. The parameters are specified per IEEE 802.3-2015.

Table 121. XLAUI receiver DC electrical characteristics (SD_SV DD = 0.9V) 1

Parameter Symbol Min Typ Max Unit

Differential input voltage V IN 85.0 850.0 mV p-

p

Differential receive input impedance V IN 80.0 100.0 120.0 Ohm

1. For recommended operating conditions, see Recommended Operating Conditions.

3.23.14.2 XLAUI AC timing characteristics

This table defines the XLAUItransmitter AC timing specifications.The parameters are specified per IEEE 802.3-2015. The AC
timing specifications do not include RefClk jitter.

Table 122. XLAUI transmitter AC timing specifications

Parameter Symbol Min Typ Max Unit

Deterministic jitter eye mask (far end) JD 0.17 UI p-p

Total jitter eye mask (far end) JT - - 0.32 UI p-p

Transmitter baud rate T BAUD 10.3125-100ppm 10.3125 10.3125+100ppm Gb/s

This table defines the XLAUIreceiver AC timing specifications.The parameters are specified per IEEE 802.3-2015. The AC timing
specifications do not include RefClk jitter.

Table 123. XLAUI receiver AC timing specifications

Parameter Symbol Min Typ Max Unit

Input AC common-mode 20.0 - - RMS

voltage tolerance

Table continues on the next page...

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Table 123. XLAUI receiver AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit

Deterministic jitter tolerance JD 0.42 UI p-p

Total jitter tolerance JT 0.62 - UI p-p

Bit error ratio BER - 10 -12 - -

Receiver baud rate R BAUD 10.3125-100ppm 10.3125 10.3125+100ppm Gb/s

3.23.15 SerDes Recovered Clock Outputs

The RCLK[0:1] pins provide the recovered clocks from SerDes lanes running Ethernet protocols (SGMII 1G, XFI, USXGMII,
CAUI-4, 50GAUI-2, 25G-AUI, and XLAUI) on SerDes 1 and SerDes 2.

3.23.15.1 SerDes 1 and 2 receive recovered clocks DC electrical characteristics

This table provides the DC electrical characteristics for the recovered clock output.

Table 124. RCLK DC electrical characteristics (OV DD = 1.8V) 1

Parameter Symbol Min Max Unit Notes

Output high voltage (OV DD = min, I OH = V OH 1.35 - V 2

-0.5 mA)

Output low voltage (OV DD = min, I OL = V OL - 0.4 V 2

0.5 mA)

1. For recommended operating conditions, see Recommended Operating Conditions.

2. The symbol OV DD represents the recommended operating voltage of the supply referenced in Recommended
Operating Conditions.

3.23.15.2 SerDes 1 and 2 receive recovered clocks AC timing characteristics

This table provides the AC electrical characteristics of the recovered clock output.

Table 125. RCLK AC timing specifications

Parameter Symbol Min Typ Max Unit Notes

RCLK frequency f RCLK 0.0 - 161.1328125 MHz -

RCLK pulse width t RCLKPW 40.0 50.0 60.0 % -

LP filter < 1 MHz TJpk-pk - - 30 ps 1

RCLK peak-to-peak jitter DJpk-pk - - 10 ps

1. Values listed for RCLK peak-to-peak jitter represent the jitter generation limits without any input data jitter or input PLL
reference clock jitter. It is recommended that system designers use RCLK with an external jitter cleaning PLL when intending
to use RCLK as a reference clock for the system. Jitter calculations for such a system should include the quoted RCLK

Table continues on the next page...

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Hardware design considerations

Table 125. RCLK AC timing specifications (continued)

Parameter Symbol Min Typ Max Unit Notes

peak-to-peak jitter, the system’s SerDes PLL reference clock jitter, and the system’s receiver input data jitter. Determination of
both the SerDes PLL reference clock peak-to-peak jitter and the receiver peak-to-peak input data jitter should include the use
of a low pass filter with a bandwidth of 1 MHz with a roll off of at least 20 dB per decade.

4 Hardware design considerations

4.1 Clock ranges

This table provides the clocking specifications for the processor core, coherency domain, platform, memory, and DCE.

Table 126. Processor, platform, and memory clocking specifications

Characteristic Maximum processor core frequency Unit Notes

1800 MHz 2000 MHz 2200 MHz

Min Max Min Max Min Max

Core cluster group PLL frequency 700 1800 700 2000 700 2200 MHz

Core frequency 175 1800 175 2000 175 2200 MHz 1

Coherency Domain frequency 1000 1300 1000 1400 1000 1500 MHz

Platform clock frequency 500 650 500 700 500 750 MHz 1

Memory bus clock frequency 650 1300 650 1450 650 1600 MHz 1, 2

Decompression/compression 300 400 300 450 300 450 MHz

acceleration engine (DCE) frequency

Notes:
1. Caution: The coherency domain clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the
resulting SYSCLK frequency, core frequency, coherency domain and platform clock frequency do not exceed their respective
maximum or minimum operating frequencies.
2. The memory bus clock speed is half the DDR4 data rate.

4.2 Platform clock requirements for Ethernet

This table shows the minimum platform clock frequency required to run Ethernet at different speeds.

Table 127. Platform clocking restrictions

Ethernet Speed Platform clock requirement

10G 516 MHz

25G 645 MHz

40G 261 MHz

50G 350 MHz

100G 652 MHz

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Thermal

4.3 Power supply design

For additional details on the power supply design, see the applicable chip design checklist.

4.3.1 Voltage ID (VID) controllable supply

To guarantee performance and power specifications, a specific method of selecting the optimum voltage-level must be
implemented when the chip is used. As part of the chip's boot process, software must read the VID efuse values stored in the Fuse
Status register (FUSESR) and then configure the external voltage regulator based on this information. This method requires a
point of load voltage regulator for each chip.

NOTE
During the power-on reset process, the fuse values are read and stored in the FUSESR. It is expected that the
chip's boot code reads the FUSESR value very early in the boot sequence and updates the regulator accordingly.

The default voltage regulator setting that is safe for the system to boot is the recommended operating VDD at boot of 0.850 V. It is
highly recommended to select a regulator with a Vout range of at least 0.7 V to 0.9 V, with a resolution of 12.5 mV or better, when
implementing a VID solution.
The table below lists the valid VID efuse values that will be programmed at the factory for this chip.

Table 128. Fuse Status Register (DCFG_CCSR_FUSESR)

Binary value of DA_V / DA_ALT_V VDD voltage

00000 default (0.850 V)

00010 0.775 V

10000 0.800 V

10010 0.825 V

10100 0.850 V

All other values Reserved

For additional information on VID, see the chip reference manual.

5 Thermal
This table shows the thermal rating for the chip.

Table 129. Package thermal characteristics

Rating Board Symbol Value Unit Notes

Junction to case thermal resistance RΘJC 0.15 °C/W 1

Notes:
1. Junction-to-Case thermal resistance is determined using an isothermal cold plate heat extraction through the top side of the
package. Case temperature is the surface temperature at the package lid’s geometric centre.

5.1 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local
NXP sales office.

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Package information

5.2 Temperature diode

The chip has temperature diodes that can be used to monitor its temperature by using an external temperature monitoring device
(such as NXP SA56004x).
The following are the specifications of the chip's on-board temperature diodes:
Operating range: 14 - 240 μA
The ideality factor over temperature range 85C⁰ to 105C⁰, n = 1.022 ± 0.003, with approximate error +/- 1.5 C⁰ and approximate
error under +/- 3 C⁰ for temperature range 0 C⁰ to 85C⁰ and 105 C⁰ to 125C⁰.

5.3 Thermal management information

This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for air-cooled
applications. Proper thermal control design is primarily dependent on the system-level design-the heat sink, airflow, and thermal
interface material.
The recommended attachment method to the heat sink is illustrated in Figure 63. The heat sink should be attached to the
printed-circuit board with the spring force centered over the lid. This spring force should not exceed 47 pounds force (209 Newton).

FC-PBGA package (with lid)

Heat sink

Heat sink clip

Adhesive or
Die lid
thermal interface material

Die

Lid adhesive

Printed circuit-board

Figure 63. Package exploded, cross-sectional view-FC-PBGA (w/ Lid)

The system board designer can choose between several types of heat sinks to place on the device. There are several
commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat
sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method,
assembly, and cost.

5.3.1 Thermal interface materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The
performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is
generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by means
of a spring clip attachment to the printed-circuit board (see Figure 63).
The system board designer can choose among several types of commercially available thermal interface materials.

6 Package information

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Package information

6.1 Package parameters for the FC-PBGA

The package parameters are as provided in the following list.
• Package: #I/O 1517, 40 mm x 40 mm, lidded FCBGA
• Substrate: #3-2-3, stack up, 600μm core thickness
• Pitch: 1 mm
• Ball Diameter (typical): 0.6 mm
• Solder Balls: 96.5% Sn, 3% Ag, 0.5% Cu
• Module height: 3.21 mm (minimum), 3.36 mm (typical), 3.51 mm (maximum)
• Case outline number: 98ASA01023D

6.2 Mechanical dimensions of the FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the chip.

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Package information

Figure 64. Mechanical dimensions of the FC-PBGA

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Security fuse processor

7 Security fuse processor

This chip implements the QorIQ platform's trust architecture, supporting capabilities such as secure boot. Use of the trust
architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the trust
architecture and SFP can be found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.80 V to the TA_PROG_SFP pin per Power sequencing. TA_PROG_SFP
should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All
other times TA_PROG_SFP should be connected to GND. The sequencing requirements for raising and lowering TA_PROG_SFP
are shown in Figure 10. To ensure device reliability, fuse programming must be performed within the recommended fuse
programming temperature range per Recommended Operating Conditions.

NOTE
Users not implementing the QorIQ platform's trust architecture features should connect TA_PROG_SFP to GND.

8 Ordering information
Contact your local NXP sales office or regional marketing team for order information.

8.1 Part numbering nomenclature

This table provides the NXP Layerscape platform part numbering nomenclature.

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Ordering information

Table 130. Part numbering nomenclature

Prototype

Family

Number of Cores

Derivative

Temp Range

Options

Package Type

CPU Frequency, DDR Data Rate

Revision
Indicator

P= LX2 = 08 = 8 0 = first P = Prototype C = SEC, CAN- 7 = 1826 = 1800 B = Rev 2.0

Prototype 16FFC FD enabled 40x40mm MHz, 2600
12 = 12 S = Standard (0
FC PBGA MT/s
Blank = to 105C) E = SEC
16 = 16 pb-free
Production enabled, CAN 2029 = 2000
X = Extended C4/C5
2.0b enabled MHz, 2900
(-40 to 105C)
(no CAN-FD MT/s
support)
2232 = 2200
N = SEC MHz, 3200
disabled, CAN MT/s
2.0b enabled
(no CAN-FD
support)

This table provides the NXP Layerscape platform automotive part numbering nomenclature.

Table 131. Automotive part numbering nomenclature

Prototype
Family

Number of Cores

Derivative

Temp, Qual

Options

Package Type

CPU Frequency, DDR Data Rate

Revision
Indicator

P= LX2 = 08 = 8 0 = first C = AEC-Q100 C = SEC 7= 1826 = 1800 B = Rev 2.0

Prototype 16FFC grade 3 enabled, CAN- 40x40mm MHz, 2600
12 = 12
FD enabled FC PBGA MT/s
Blank =
16 = 16 pb-free
Production A = SEC 2029 = 2000
C4/C5
disabled, CAN- MHz, 2900
FD enabled MT/s
2232 = 2200
MHz, 3200
MT/s

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NXP Semiconductors
Revision history

8.2 Part marking

Parts are marked as in the example shown in this figure.

NXP
LX2160XXXXXXXXXX
AWLYYWW

MMMMM CCCCC
YWWLAZ

FC-PBGA
Legend:
LX2160XXXXXXXXXX is the part marking on the die.
AWLYYWW is the test traceability code.
MMMMM is the mask number.
CCCCC is the country code.
YWWLAZ is the assembly traceability code.

Figure 65. Part marking for FC-PBGA chip

9 Revision history
This table summarizes revisions to this document.

Table 132. Revision history

Revision Date Description

3 09/2021 Updated I2C AC timing specifications.

2 06/2021 • Changed the ADD/CMD/CNTL output setup and hold times for 3200 MT/s from 241.0 ps to
210.0 ps in Table 22.
• Added Battery-backed security monitor and tamper detect DC electrical characteristics.
• Added SFP+ direct attach copper.
• Updated Figure 17 to show VIH/VIL instead of VOH/VOL and CMD/DATA input instead of
CMD/DATA output.
• Updated note 4 in Table 92.
• In the Pinout list:
— Added note 16 to D1_MRESET_B and D2_MRESET_B.
— Added 1% precision to notes 9 and 13.

Table continues on the next page...

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NXP Semiconductors
Revision history

Table 132. Revision history (continued)

Revision Date Description

— Changed note 12 to 10 for NC_AK1.

— Changed the Power Supply column for AVDD_Dx and AVDD_SDn_PLLF/S from AVDD
to AVDD_Dx and AVDD_SDn_PLLF/S.
• Updated figure "DDR4 SDRAM interface output timing diagram" in DDR4 SDRAM controller
AC timing specifications.

1 12/2020 • Added automotive to the list of applications in Introduction.

• Added the temperature range for automotive grade parts in Recommended Operating
Conditions.
• In the Part numbering nomenclature:
— Added Table 131.
— Updated Table 130.
• Removed the "Orderable part numbers addressed by this document" section.
• Changed the parameter "Required assertion time of PORESET_B" to "Required assertion
time of PORESET_B after SYSCLK/DIFF_SYSCLK and all power rails are stable” in Reset
initialization timing specifications.
• Changed OVDD to SD_SVDD in the note in Power sequencing.
• Renamed CAUI-2 to 50GAUI-2 throughout the document.
• Changed the test traceability code from ATWLYYWW to AWLYYWW in Part marking .

0 07/2020 Initial public release

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Date of release: 09/2021

Document identifier: LX2160A