Behavioral Code for 1x4 Demultiplexer: Testbench for Behavioral Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity demux_1_4_behav is entity tb_demux_1_4_behav is

port (a: in std_logic; end tb_demux_1_4_behav;
s: in std_logic_vector(1 downto 0);
z: out std_logic_vector(3 downto 0):="0000"); architecture testbench of tb_demux_1_4_behav is
end demux_1_4_behav; component demux_1_4_behav is
port (a: in std_logic;
architecture behavioural of demux_1_4_behav is s: in std_logic_vector(1 downto 0);
begin z: out std_logic_vector(3 downto 0));
behave : process(a, s) end component;
begin
if (s="00") then z(0)<=a; signal a: std_logic;
elsif (s="01") then z(1)<=a; signal s: std_logic_vector(1 downto 0);
elsif (s="10") then z(2)<=a; signal z: std_logic_vector(3 downto 0):="0000";
elsif (s="11") then z(3)<=a;
else null; begin
end if ; H1: demux_1_4_behav port map(a=>a, s=>s,
end process; z=>z);
end behavioural; process begin
a<= '1';
s <= "00";
wait for 10 ns;
s <= "01";
wait for 10 ns;
s <= "10";
wait for 10 ns;
s <= "11";
wait for 10 ns;
end process;
end testbench;

Waveform:

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Structural Code for 1x4 Demultiplexer: Testbench for Structural Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity demux_1_4_struct is entity tb_demux_1_4_struct is

port(a: in std_logic; end tb_demux_1_4_struct;
s: in std_logic_vector(1 downto 0);
z: out std_logic_vector(3 downto 0)); architecture testbench of tb_demux_1_4_struct is
end entity demux_1_4_struct; component demux_1_4_struct is
port(a: in std_logic;
architecture structural of demux_1_4_struct is s: in std_logic_vector(1 downto 0);
component not_gate is z: out std_logic_vector(3 downto 0));
port (m: in std_logic; o: out std_logic); end component;
end component;
signal a: std_logic:='0';
component and_3_gate is signal s: std_logic_vector(1 downto 0):="00";
port(l, m, n: in std_logic; o: out std_logic); signal z: std_logic_vector(3 downto 0);
end component; begin
H1: demux_1_4_struct port map(a=>a, s=>s,
signal sbar_0, sbar_1: std_logic; z=>z);
s(0) <= not s(0) after 10 ns;
begin s(1) <= not s(1) after 20 ns;
N1: not_gate port map(s(0), sbar_0); a <= not a after 40 ns;
N2: not_gate port map(s(1), sbar_1); end testbench;

A1: and_3_gate port map(a, sbar_0, sbar_1,

z(0));
A2: and_3_gate port map(a, s(0), sbar_1, z(1));
A3: and_3_gate port map(a, sbar_0, s(1), z(2));
A4: and_3_gate port map(a, s(0), s(1), z(3));

end architecture structural;

Waveform:

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Dataflow Code for 1x4 Demultiplexer: Testbench for Dataflow Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity demux_1_4_dataf is entity tb_demux_1_4_dataf is

port (a: in std_logic; end tb_demux_1_4_dataf;
s: in std_logic_vector(1 downto 0);
z: out std_logic_vector(3 downto 0)); architecture testbench of tb_demux_1_4_dataf is
end demux_1_4_dataf; component demux_1_4_dataf is
port (a: in std_logic;
architecture dataflow of demux_1_4_dataf is s: in std_logic_vector(1 downto 0);
begin z: out std_logic_vector(3 downto 0));
with s select end component;
z <=("000" & a) when "00",
("00" & a & "0") when "01", signal a: std_logic;
("0" & a & "00") when "10", signal s: std_logic_vector(1 downto 0);
(a & "000") when others; signal z: std_logic_vector(3 downto 0);
end dataflow;
begin
H1: demux_1_4_dataf port map(a=>a, s=>s, z=>z);
process begin
a<= '1';
s <= "00";
wait for 10 ns;
s <= "01";
wait for 10 ns;
s <= "10";
wait for 10 ns;
s <= "11";
wait for 10 ns;
end process;
end testbench;

Waveform:

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